WO2015058581A1 - 薄膜晶体管及其制备方法、阵列基板、显示器 - Google Patents

薄膜晶体管及其制备方法、阵列基板、显示器 Download PDF

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WO2015058581A1
WO2015058581A1 PCT/CN2014/084932 CN2014084932W WO2015058581A1 WO 2015058581 A1 WO2015058581 A1 WO 2015058581A1 CN 2014084932 W CN2014084932 W CN 2014084932W WO 2015058581 A1 WO2015058581 A1 WO 2015058581A1
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active layer
layer
metal
thin film
film transistor
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PCT/CN2014/084932
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English (en)
French (fr)
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黄常刚
张振宇
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US14/436,953 priority Critical patent/US9929277B2/en
Publication of WO2015058581A1 publication Critical patent/WO2015058581A1/zh

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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display. Background technique
  • TFT thin film transistor
  • the active layer of the thin film transistor is required to have a carrier mobility of 1.0 cm 2 /Vs or more.
  • the carrier mobility of amorphous silicon TFTs is difficult to meet the driving needs of large-size displays.
  • a thin film transistor includes: a gate, a gate insulating layer, an active layer, a source and a drain.
  • the active layer includes a first active layer and a second active layer, and the first active layer is disposed on a side close to the gate insulating layer, and the second active layer is disposed adjacent to the source The pole and drain sides.
  • the carrier mobility of the first active layer is greater than the carrier mobility of the second active layer.
  • the first active layer includes an oxynitride semiconductor active layer
  • the second active layer package The metal-doped oxynitride semiconductor active layer is included.
  • the thickness of the first active layer is 1.0 to 1.8 times the thickness of the second active layer.
  • the metal element used for the metal doping includes at least one metal element of aluminum, gallium, germanium, indium, tin, and antimony.
  • the metal doping has a total doping concentration of 0.1 to 10%.
  • the thin film transistor further includes an etch barrier layer disposed over the active layer corresponding to a gap between the source and the drain.
  • an array substrate includes a thin film transistor as described above, and a pixel electrode electrically connected to a drain of the thin film transistor.
  • the array substrate further includes a common electrode.
  • a display is provided.
  • the display includes an array substrate as described above.
  • a method of fabricating a thin film transistor includes: forming a gate, a gate insulating layer, an active layer, a source, and a drain on a substrate.
  • Forming the active layer on the substrate includes: forming a first active layer and a second active layer on the substrate, wherein the first active layer is adjacent to a side of the gate insulating layer, the second active layer Close to the source and drain sides.
  • the carrier mobility of the first active layer is greater than the carrier mobility of the second active layer.
  • the first active layer includes an oxynitride semiconductor active layer
  • the second active layer includes a metal-doped oxynitride semiconductor active layer
  • the thickness of the first active layer is 1.0 1.8 times the thickness of the second active layer.
  • the metal-doped metal element includes at least one metal element of aluminum, gallium, germanium, indium, tin, and antimony.
  • the metal doping has a total doping concentration of 0.1 to 10%.
  • forming the active layer, the source, and the drain on the substrate by a patterning process include:
  • the forming a metal-doped oxynitride film includes: forming the metal-doped oxynitride film by a sputtering method.
  • the method further includes forming an etch barrier layer formed over the active layer corresponding to a gap between the source and the drain;
  • Forming the active layer, the etch stop layer, the source, and the drain on the substrate include:
  • the source and the drain are formed.
  • the forming a metal-doped oxynitride film comprises: forming the metal-doped oxynitride film by a sputtering method.
  • FIG. 1 is a schematic structural view of a bottom-gate thin film transistor according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram 2 of a bottom-gate thin film transistor according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a top-gate thin film transistor according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram 1 of an array substrate according to an embodiment of the present invention
  • FIG. 6 is a schematic structural view 2 of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a preparation process of a bottom gate type thin film transistor according to an embodiment of the present invention
  • 13 to 19 are schematic diagrams showing a preparation process of a bottom gate type thin film transistor according to an embodiment of the present invention.
  • the embodiment of the present invention provides a thin film transistor, as shown in FIG. 1, including: a gate 200, a gate insulating layer 201, an active layer 300, a source 401, and a drain 402; wherein the active layer 300 includes a first active layer 301 and a second active layer 302, and the first active layer 301 is disposed adjacent to a side of the gate insulating layer 201, and the second active layer 302 is disposed adjacent to the source 401 and the drain 402 side; and, the carrier mobility of the first active layer 301 is greater than the carrier mobility of the second active layer 302.
  • the active layer 300 is not limited to the above two layers, and may be two or more layers as long as the source and drain electrodes 401 and 401 are ensured along the gate insulating layer 201.
  • the carrier mobility of each constituent layer of the active layer 300 may be sequentially decreased, but the layers constituting the active layer 300 are not as good as possible, and the basic performance of the thin film transistor is ensured.
  • the thin film transistor is kept at a high on-state current and the leakage current of the thin film transistor is lowered.
  • the active layer 300 in order not to increase the overall thickness of the active layer 300, the active layer 300 includes only the first active layer 301 and the second active layer 302 as an example. However, embodiments of the invention are not limited thereto.
  • the present invention has been described by taking the bottom gate type of the thin film transistor as an example in the embodiment of the present invention, it should be understood by those skilled in the art that the first The source layer 301 and the second active layer 302 are applied to a top gate type thin film transistor or other structural thin film transistor, which is not limited herein.
  • Embodiments of the present invention provide a thin film transistor including the first active layer 301 and the second active layer 302 having different carrier mobility, which are relatively high in two carrier mobility.
  • the first active layer 301 having a high carrier mobility is disposed on a side close to the gate insulating layer 201, and the thin film transistor can maintain a high on state when the thin film transistor is applied to a display.
  • the second active layer 302 having a relatively small carrier mobility is disposed adjacent to the source 401 and the drain 402,
  • the leakage current of the thin film transistor can be reduced; therefore, the thin film transistor can reduce the leakage current of the thin film transistor while maintaining a high on-state current, thereby satisfying the large-size display while maintaining the reliability of the thin film transistor. demand.
  • the first active layer 301 includes a NOx oxide semiconductor active layer
  • the second active layer 302 includes a metal-doped oxynitride semiconductor active layer; that is, the first active layer
  • the material of the layer 301 is a nitrogen oxide
  • the material of the second active layer 302 is a metal-doped nitrogen oxide.
  • the thickness of the first active layer 301 is 1.0 to 1.8 times the thickness of the second active layer 302. Since the second active layer 302 is close to the thickness of the first active layer 301, the electrical properties of the second active layer 302 and the first active layer 301 can be ensured as a whole. The difference in performance is small.
  • the metal element used for the metal doping includes at least one metal element of aluminum (Al), gallium (Ga), germanium (Ge), indium (In), tin (Sn), and bismuth (Bi).
  • the metal doping has a total doping concentration of 0.1 to 10%. It can be avoided that when the doping concentration is too high, it is difficult for the doping element to enter the structure of the oxynitride (ZnON) or to form other impurities.
  • the nitrogen atom is easily fixed from the nitrogen oxide semiconductor. Leaving out creates a vacancy, called the nitrogen vacancy, which results in a certain number of hole carriers due to the generation of the nitrogen vacancies. A certain number of nitrogen vacancies will produce a corresponding number of hole carriers, which will attract the electron carriers in the nitrogen oxide semiconductor to generate a certain direction of motion due to the attraction of the Coulomb force. Further, the mobility of carriers in the oxynitride semiconductor is increased. Therefore, the first active layer 301 has a higher carrier mobility.
  • M includes at least one metal element of Al, Ga, Ge, In, Sn, Bi, that is, the bonding strength of the chemical bond formed by the metal-doped metal atom and the nitrogen atom is greater than the atomic and nitrogen atoms.
  • the Zn-N bond energy between the nitrogen atoms makes it difficult to escape from the fixed position in the metal-doped oxynitride semiconductor, thereby suppressing the generation of the nitrogen vacancies; due to the number of nitrogen vacancies There is a decrease, and correspondingly, the number of carriers in the metal-doped oxynitride semiconductor is reduced, thereby reducing the metal-doped nitriding semiconductor carrier mobility. Therefore, the second active layer 302 has a lower carrier mobility than the first active layer 301.
  • the thin film transistor further includes an etch stop layer 500, and the etch stop layer 500 is disposed at the corresponding to the gap between the source 401 and the drain 402. Above the active layer 300.
  • the active layer 300 in the embodiment of the present invention includes the first active layer 301 formed by the oxynitride semiconductor and the second active layer 302 formed by the metal-doped oxynitride semiconductor,
  • the materials of an active layer 301 and the second active layer 302 are both metal oxynitrides, and when the active layer is exposed, it easily reacts with oxygen or water vapor in the air, thereby causing characteristics of the thin film transistor. A change has occurred. Therefore, in the embodiment of the present invention, for example, the thin film transistor further includes an etch stop layer 500, and the etch stop layer 500 is disposed at the active corresponding to the gap between the source 401 and the drain 402. Above layer 300. The etch stop layer 500 is also used to avoid affecting the active layer 300 when the metal layer on the active layer 300 is etched in a subsequent process.
  • the etch stop layer 500 may also be a structure as shown in FIG. That is, the etch stop layer 500 is disposed above the active layer 300 corresponding to the gap between the source 401 and the drain 402, and the area of the etch stop layer 500 is slightly larger than the The area of the gap between the source 401 and the drain 402.
  • the embodiment of the present invention does not limit the material used for the etch stop layer 500, so as to protect the active layer 300 from being affected during the subsequent metal layer formed by etching.
  • the material of the etch barrier layer 500 may be, for example, a dense silicon nitride, silicon oxide, silicon oxynitride or the like.
  • the embodiment of the present invention provides a bottom gate thin film transistor, as shown in FIG. 2, comprising: a gate 200, a gate insulating layer 201, an active layer 300, a source 401, and a drain 402; wherein, the active
  • the layer 300 includes a first active layer 301 formed by a nitrogen oxide semiconductor and a nitrogen-oxygen co-doped by gallium and aluminum.
  • the thin film transistor further includes an etch barrier layer 500 disposed over the second active layer 302 corresponding to a gap between the source 401 and the drain 402.
  • the thickness of the first active layer 301 formed by the oxynitride semiconductor is 1.5 times the thickness of the second active layer 302 formed by a gallium-aluminum co-doped oxynitride semiconductor; and the gallium The total concentration of aluminum co-doping is 8%.
  • the material of the second active layer 302 is a gallium-aluminum co-doped oxynitride semiconductor, wherein the bond energies of Ga-N and A1-N are greater than the bond energy of the Zn-N,
  • the nitrogen atom is difficult to be separated from the fixed position in the oxynitride semiconductor in which the gallium and aluminum are co-doped, thereby suppressing the generation of the nitrogen vacancy; since the number of the nitrogen vacancies is reduced, correspondingly The number of carriers in the oxynitride semiconductor co-doped with gallium and aluminum is reduced, thereby reducing the carrier mobility of the oxynitride semiconductor which is co-doped by the gallium and aluminum. Therefore, the second active layer 302 has a lower carrier mobility than the first active layer 301.
  • the first active layer 301 having a higher carrier mobility is disposed adjacent to the gate insulating layer
  • the bottom gate type thin film transistor when the bottom gate type thin film transistor is applied to a display, the bottom gate type thin film transistor can maintain a high on-state current, thereby significantly improving the response speed of pixels in the display;
  • the second active layer 302 having a small carrier mobility is disposed over the first active layer 301, that is, near the sides of the source 401 and the drain 402, and the thin film transistor can be lowered Leakage current; therefore, the bottom-gate thin film transistor can reduce the leakage current of the bottom-gate thin film transistor while maintaining a high on-state current, thereby satisfying the large while maintaining the reliability of the bottom-gate thin film transistor The need for a size display.
  • the embodiment of the present invention provides a top gate thin film transistor, as shown in FIG. 4, comprising: a source 401 and a drain 402, an active layer 300, a gate insulating layer 201, and a gate 200, which are sequentially disposed on a substrate 100.
  • the active layer 300 includes a first active layer 301 formed of a oxynitride semiconductor and a second active layer 302 formed of a ytterbium-doped oxynitride semiconductor, and the second active layer 302 is disposed.
  • the first active layer 301 is disposed over the second active layer 302.
  • the thickness of the first active layer 301 formed by the oxynitride semiconductor is ⁇ -doped nitrogen
  • the second active layer 302 formed of the oxidized semiconductor has the same thickness; and the total concentration of the erbium doping is 2.0%.
  • the material of the second active layer 302 is an erbium-doped oxynitride semiconductor, wherein the bond energy of Ge-N is greater than the bond energy of the Zn-N, making the nitrogen atom difficult to be doped from the ruthenium
  • the fixed position in the hetero-nitrogen oxide semiconductor is detached, thereby reducing the carrier mobility of the ytterbium-doped oxynitride semiconductor. Therefore, the second active layer 302 has a lower carrier mobility than the first active layer 301.
  • the second active layer 302 having a smaller carrier mobility is disposed over the source 401 and the drain 402, which can reduce leakage current of the thin film transistor; and at the same time, have higher carrier mobility
  • the first active layer 301 is disposed over the second active layer 302, that is, near the side of the gate insulating layer 201, and can be maintained when the top gate thin film transistor is applied to a display.
  • the top gate thin film transistor has a higher on-state current, thereby significantly increasing the response speed of the pixel in the display; therefore, the top gate thin film transistor can reduce the leakage current of the top gate thin film transistor While maintaining a high on-state current, the demand for a large-sized display can be satisfied while maintaining the reliability of the top-gate thin film transistor.
  • the embodiment of the present invention further provides an array substrate, as shown in FIG. 5, comprising the above-mentioned thin film transistor, and a pixel electrode 600 electrically connected to the drain 402 of the thin film transistor.
  • the array substrate provided by the embodiment of the present invention can be applied to a liquid crystal display device of an advanced super-dimensional field conversion type, a twisted nematic type or the like.
  • the core technical characteristics of the advanced super-dimensional field conversion technology are described as follows: The electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer form a multi-dimensional electric field, so that the slit electrode in the liquid crystal cell All of the aligned liquid crystal molecules directly above the electrode can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • the advanced super-dimensional field conversion technology can improve the picture quality of the TFT liquid crystal display panel, and has the advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no squeezing water ripple.
  • the array substrate further includes a common electrode 700.
  • FIG. 6 only schematically shows the case where the common electrode 700 is on and the pixel electrode 600 is below.
  • the array substrate may also be the common electrode 700 under and the pixel electrode 600 on.
  • the common electrode 700 located in the upper layer may be formed as a strip electrode including a plurality of electrical connections. At this time, the common electrode 700 is included.
  • the structure of the slit or the comb structure, the pixel electrode 600 located in the lower layer is formed into a flat plate type.
  • the embodiment of the present invention is not limited thereto, and the pixel electrode 600 located in the lower layer may also be a strip electrode including a plurality of electrical connections.
  • the common electrode 700 is on, and the pixel electrode 600 is on, the upper pixel electrode is in a slit shape, and the lower common electrode may be a plate electrode or a slit electrode.
  • the embodiment of the invention further provides a display comprising the array substrate described above.
  • the display may specifically be a product or component having any display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the embodiment of the present invention further provides a method for fabricating a thin film transistor, comprising: forming a gate 200, a gate insulating layer 201, an active layer 300, a source 401, and a drain 402 on a substrate 100;
  • the forming the active layer 300 on the substrate 100 includes: forming a first active layer 301 and a second active layer 302 on the substrate 100, and the first active layer 301 is adjacent to the gate insulating layer 201 a side, the second active layer 302 is adjacent to the source 401 and the drain 402 side; and, the carrier mobility of the first active layer 301 is greater than that of the second active layer 302 Carrier mobility.
  • the first active layer 301 includes an oxynitride semiconductor active layer
  • the second active layer 302 includes a metal-doped oxynitride semiconductor active layer.
  • the thickness of the first active layer 301 is 1.0 to 1.8 times the thickness of the second active layer 302.
  • the metal element used for the metal doping includes at least one metal element of aluminum (Al), gallium (Ga), germanium (Ge), indium (In), tin (Sn), and bismuth (Bi).
  • the metal doping has a total doping concentration of 0.1 to 10%.
  • the active layer 300, the source 401, and the drain 402 described above may be formed by one patterning process.
  • a NOx film, a metal-doped oxynitride film, and a metal film are sequentially formed on the substrate 100, and a photoresist layer is formed on the metal film; and a half-order mask or a gray-scale mask is used.
  • Forming, exposing, developing, and etching the substrate on which the photoresist is formed to form the first active layer 301 of the oxynitride semiconductor, and the metal doped oxynitride semiconductor The second active layer 302, and the source 401 and the drain 402 are described.
  • the film formed by the sputtering method has the advantages of uniform film formation, smooth surface, controllable film thickness, controllable doping concentration, and the like; therefore, the metal-doped nitrogen oxide film can be formed by magnetron sputtering.
  • Exposing the substrate on which the photoresist layer is formed with a half-order mask or a gray-scale mask After the light, the development, and the etching, the forming the first active layer 301, the second active layer 302, and the source 401 and the drain 402 may be:
  • ⁇ After exposing and developing the substrate on which the photoresist layer is formed by using a half-order mask or a gray-scale mask, forming a completely retained portion of the photoresist, a semi-retained portion of the photoresist, and completely removing the photoresist a portion of the photoresist that is completely reserved corresponds to the source 401 and the drain 402 to be formed, and the semi-reserved portion of the photoresist corresponds to between the source 401 and the drain 402 to be formed. In the gap, the completely removed portion of the photoresist corresponds to other regions.
  • the oxynitride film, the metal-doped oxynitride film, and the metal thin film of the completely removed portion of the photoresist are removed by an etching process, and the first active layer 301 and the second active layer are formed.
  • the photoresist of the semi-retained portion of the photoresist is removed by an ashing process, and the exposed metal thin film is removed by an etching process to form the source 401 and the drain 402.
  • the first active layer 301, the second active layer 302, and the source 401 and the drain 402 can be formed by one patterning process, which can reduce the number of patterning processes, thereby reducing the cost.
  • the thin film transistor may also be a top gate type thin film transistor.
  • the method includes forming on the substrate 100 by a first patterning process.
  • the source electrode 401 and the drain electrode 402 are further formed on the source electrode 401 and the drain electrode 402 by a second patterning process, and the active layer 300 includes a region formed by a nitrogen oxide semiconductor.
  • a gate insulating layer 201 and a gate electrode 200 are formed.
  • the method further includes forming an etch stop layer 500, the etch stop layer 500 forming the active corresponding to a gap between the source 401 and the drain 402, as shown in FIG. Above layer 300.
  • the etch stop layer 500 may also refer to FIG.
  • forming the active layer 300, the etch stop layer 500, the source 401 and the drain 402 on the substrate include:
  • a metal thin film is formed on the substrate 100 on which the active layer 300 and the etch stop layer 500 are formed, and the photoresist layer is formed on the metal thin film; After the substrate 100 on which the photoresist layer is formed is exposed, developed, and etched, the source electrode 401 and the drain electrode 402 are formed.
  • the film formed by the sputtering method has the advantages of uniform film formation, smooth surface, controllable film thickness, controllable doping concentration, and the like; therefore, the metal-doped nitrogen oxide film can be formed by magnetron sputtering.
  • Example three Two specific examples are provided below to describe in detail the preparation method of the above thin film transistor.
  • Example three Two specific examples are provided below to describe in detail the preparation method of the above thin film transistor.
  • the method for fabricating the above thin film transistor is described in detail by taking a bottom gate type thin film transistor as an example.
  • the method includes the following steps:
  • a metal thin film is formed on the substrate 100, and a gate electrode 200 is formed on the substrate 100 by one patterning process.
  • a copper elemental metal film having a thickness of 1000 7000 A can be prepared on a glass substrate by a magnetron sputtering method. Then, a patterning process such as exposure, development, etching, and peeling is performed by a common mask, and the gate electrode 200 is formed in a certain region of the substrate 100, and a gate line, a gate line lead, or the like is also formed.
  • a gate insulating layer 201 is formed on the substrate on which step S01 is completed.
  • a gate insulating film having a thickness of about 1000 6000 A may be deposited on the substrate on which the gate electrode 200 is formed by chemical vapor deposition, and the material of the gate insulating film is usually silicon nitride or silicon oxide. And silicon oxynitride.
  • step S03 sequentially forming a nitrogen oxide film 301a on the substrate on which step S02 is completed,
  • the gallium and aluminum are commonly doped with the oxynitride film 302a and the metal thin film 400, and a photoresist layer 800 is formed on the metal thin film.
  • a nitrogen oxide film 301a having a thickness of about 100 8000 A and a gallium or aluminum co-doped oxynitride film 302a having a thickness of about 100 8000 A may be deposited on the substrate by magnetron sputtering; and then on the substrate.
  • a molybdenum metal film 400 having a thickness of about 1000 7000 A is deposited, and a photoresist layer 800 is coated on the molybdenum metal film 400.
  • the photoresist completely remaining portion 801 corresponds to the source 401 and the drain 402 to be formed, and the photoresist half-retaining portion 802 corresponds to a gap between the source 401 and the drain 402 to be formed.
  • the photoresist completely removed portion 803 corresponds to other regions.
  • a conventional reticle refers to a device having a specific pattern of a light-shielding metal layer formed on a transparent substrate material to effect selective exposure of the photoresist layer 800.
  • the area covered by the light shielding metal layer is completely opaque, and the area not covered by the light shielding metal layer is completely transparent; the photoresist layer 800 is exposed through the common mask, due to ultraviolet The light cannot be irradiated to a portion of the photoresist layer 800 corresponding to the completely opaque portion of the normal reticle, thereby forming the photoresist completely remaining portion 801 after development, and the completely transparent portion of the normal reticle
  • the corresponding photoresist layer 800 forms a photoresist completely removed portion 803 after development; thus, when etching the photoresist-covered film, the photoresist completely retains the film covered by the portion 801 Both are retained, and the film covered by the photoresist completely removed portion 803 is completely etched away to form at least one pattern layer having a specific pattern.
  • the patterns of the at least one pattern layer are the same; and when it is required to obtain at least two pattern layers of different patterns by one patterning process, the half-level mask is needed. 900.
  • the half-order mask 900 is compared with the conventional mask, and the half-step mask 900 includes a translucent portion in addition to the fully opaque portion 901 and the completely transparent portion 903. 902; that is: the half-order mask 900 is formed on certain areas of the transparent substrate material.
  • An opaque light-shielding metal layer forms a semi-transmissive light-shielding metal layer in other regions, and no other light-shielding metal layer is formed in other regions; wherein the semi-transmissive light-shielding metal layer has a thickness smaller than the completely opaque metal layer The thickness of the light-shielding metal layer; in addition, the transmittance of the semi-transmissive light-shielding metal layer to ultraviolet light can be changed by adjusting the thickness of the semi-transmissive light-shielding metal layer.
  • the working principle of the half-order mask 900 is as follows: By controlling the thickness of the light-shielding metal layer at different regions on the half-stage mask 900, the intensity of transmitted light in different regions during exposure is Differently, after the photoresist layer 800 is selectively exposed and developed, a photolithography corresponding to the completely opaque portion 901, the translucent portion 902, and the completely transparent portion 903 of the half-order mask 900 is formed. The glue completely remains portion 801, the photoresist half-retained portion 802, and the photoresist completely removed portion 803.
  • the film covered by the photoresist completely remaining portion 801 and the photoresist half-retaining portion 802 are retained, and thereafter, since the thickness of the photoresist completely remains portion 801 More than the thickness of the photoresist half-retaining portion 802, after the photoresist of the photoresist half-retaining portion 802 is ashed, the photoresist of the photoresist completely remaining portion 801 still exists, so that The exposed portions of the film are selectively etched to obtain at least two patterned layers of different patterns.
  • the principle of the gray-scale mask is similar to the principle of the half-order mask 900, and is not described herein again. Only the difference between the gray-scale mask and the half-order mask 900 is Description:
  • the translucent portion 902 of the half-order mask is formed by forming a semi-transparent light-shielding metal layer having a relatively thin thickness on the transparent substrate material, that is, adjusting the ultraviolet layer by controlling the thickness of the metal layer.
  • the transmittance of light so that the exposure amount of the photoresist corresponding to the portion is different from the exposure amount of other regions; and the translucent portion of the gray scale mask is formed by forming a narrow strip-shaped slit structure
  • an optical phenomenon such as scattering or diffraction occurs, so that the exposure amount of the photoresist corresponding to the portion is different from the exposure amount of the other regions.
  • the photoresist layer 800 referred to in all the embodiments of the present invention is a positive adhesive, that is, in the half-order mask 900, the corresponding region of the photoresist completely removed portion 803 is a fully exposed region.
  • the corresponding region of the photoresist half-retaining portion 802 is a half-exposure region corresponding to the translucent portion 902 of the half-order mask 900, the light
  • the area corresponding to the fully-retained portion 801 is an unexposed area corresponding to the fully opaque portion 901 of the half-order mask 900.
  • the embodiment of the present invention is not limited thereto, and the photoresist layer 800 may also be a negative glue. 505.
  • the active layer 300 includes the first active layer 301 formed near the oxynitride semiconductor of the gate insulating layer 201, and a metal doped oxynitride semiconductor formed over the first active layer 301
  • the photoresist 800 of the photoresist semi-retaining portion 802 is removed by an ashing process, and the exposed metal film 400 is removed by an etching process to form the source electrode 401. And the drain 402.
  • the method for fabricating the above thin film transistor is described in detail by taking a bottom gate type thin film transistor as an example.
  • the method includes the following steps:
  • a metal thin film is formed on the substrate 100, and a gate electrode 200 is formed on the substrate 100 by a patterning process.
  • a copper elemental metal film having a thickness of 1000 7000 A can be prepared on a glass substrate by a magnetron sputtering method. Then, a patterning process such as exposure, development, etching, and peeling is performed by a common mask, and the gate electrode 200 is formed in a certain region of the substrate 100, and a gate line, a gate line lead, or the like is also formed.
  • a gate insulating layer 201 is formed on the substrate on which step S11 is completed.
  • a gate insulating film having a thickness of about 1000 6000 A may be deposited on the substrate on which the gate electrode 200 is formed by chemical vapor deposition, and the material of the gate insulating film is usually silicon nitride or silicon oxide. And silicon oxynitride.
  • an oxynitride film 301a, an indium-doped oxynitride film 302a, and an etch barrier film 500a are sequentially formed on the substrate on which step S12 is completed, and the etch barrier film 500a is formed on the substrate.
  • a photoresist layer 800 is formed thereon.
  • a nitrogen oxide film 301a having a thickness of about 100 8000 A and an indium-doped oxynitride film 302a having a thickness of about 100 8000 A may be deposited on the substrate by magnetron sputtering;
  • a silicon nitride etch barrier film 500a having a thickness of about 500 3000 A is deposited on the substrate, and a photoresist layer 800 is coated on the silicon nitride etch barrier film 500a.
  • a photoresist completely remaining portion 801 and a photoresist semi-retained portion 802 are formed.
  • the portion 803 is completely removed with the photoresist.
  • the photoresist completely remaining portion 801 corresponds to the etch stop layer 500 to be formed, and the photoresist half-retaining portion 802 does not cover the active layer 300 corresponding to the etch stop layer 500 to be formed. In part, the photoresist completely removed portion 803 corresponds to other regions.
  • the active layer 300 is formed.
  • the active layer 300 includes the first active layer 301 formed near the oxynitride semiconductor of the gate insulating layer 201, and a metal doped oxynitride semiconductor formed over the first active layer 301
  • the photoresist 800 of the photoresist semi-retained portion 802 is removed by an ashing process, and the exposed etch barrier film 500a is removed by an etching process to form the The barrier layer 500 is etched.
  • the photoresist 800 of the photoresist completely remaining portion 801 is removed by a lift-off process.
  • a molybdenum metal film 400 having a thickness of about 100 7000A is formed on the substrate on which step S16 is completed, and a photoresist layer 800 is formed on the molybdenum metal film 400.
  • the photoresist completely remaining portion 801 corresponds to the source 401 and the drain 402 to be formed, and the photoresist completely removed portion 803 corresponds to a gap between the source 401 and the drain 402 to be formed and Other areas.
  • the molybdenum metal film 400 corresponding to the photoresist completely removed portion 803 is removed by an etching process to form the source electrode 401 and the drain electrode 402.
  • a protective layer exposing the drain 402 may be sequentially formed, and a pixel electrode connected to the drain 402 through the via hole is formed to be formed.
  • a passivation layer and a common electrode may be sequentially formed over the pixel electrode.

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Abstract

一种薄膜晶体管及其制备方法、阵列基板、显示器。该薄膜晶体管包括：栅极（200）、栅绝缘层（201）、有源层（300）、源极（401）和漏极（402）、所述有源层（300）包括第一有源层（301）和第二有源层（302），且所述第一有源层（301）设置在靠近所述栅绝缘层（201）一侧，所述第二有源层（302）设置在靠近所述源极（401）和漏极（402）一侧。所述第一有源层（301）的载流子迀移率大于所述第二有源层（302）的载流子迀移率。通过这种设置，所述薄膜晶体管可在包括高开态电流的同时降低所述薄膜晶体管的漏电流。

Description

薄膜晶体管及其制备方法、 阵列基板、 显示器 技术领域
本发明的实施例涉及一种薄膜晶体管及其制备方法、阵列基板、显示器。 背景技术
目前， 随着显示器尺寸不断地增大， 驱动电路的频率不断地提高， 需要 具有更高载流子迁移率的薄膜晶体管作为显示器中像素单元的开关。 传统的 薄膜晶体管 （TFT ) 釆用非晶硅材料作为有源层， 其载流子迁移率仅为 0.5cm2/V-so 对于尺寸超过 80 英寸的大尺寸显示器而言， 其驱动频率达到 120Hz, 相对应的， 则需要薄膜晶体管的有源层具有 1.0cm2/V.s 以上的载流 子迁移率。 显然， 非晶硅 TFT的载流子迁移率很难满足大尺寸显示器的驱动 需要。 因此， 人们将研究目光转向具有高载流子迁移率的金属氧化物半导体 有源层； 在众多可作为有源层的金属氧化物半导体中， 氮氧化辞（ZnON ) 由于其较高的载流子迁移率（可大于 100cm2/V.s ) 、 低廉的原料成本， 较为 简单的制作工艺， 使得 TFT具有较高的开态电流， 可显著提高像素的响应速 度， 从而更好地满足大尺寸显示器的需求， 因此备受人们的关注。
然而， 由于氮氧化辞（ZnON )有源层的载流子迁移率是传统非晶硅有 源层载流子迁移率的 200倍以上，过高的载流子迁移率将导致 TFT的漏电流 增大， 影响 TFT的工作特性， 降低该 TFT阵列基板的可靠性， 从而影响该 显示器的显示品质。 发明内容
根据本发明的实施例，提供一种薄膜晶体管。该薄膜晶体管包括： 栅极、 栅绝缘层、有源层、 源极和漏极。 所述有源层包括第一有源层和第二有源层， 且所述第一有源层设置在靠近所述栅绝缘层一侧， 所述第二有源层设置在靠 近所述源极和漏极一侧。 所述第一有源层的载流子迁移率大于所述第二有源 层的载流子迁移率。
例如， 所述第一有源层包括氮氧化辞半导体有源层， 所述第二有源层包 括金属掺杂氮氧化辞半导体有源层。
例如， 所述第一有源层的厚度是所述第二有源层的厚度的 1.0~1.8倍。 例如， 用于所述金属掺杂的金属元素包括铝、 镓、 锗、 铟、 锡、 铋中至 少一种金属元素。
例如， 所述金属掺杂的掺杂总浓度为 0.1~10%。
例如， 所述薄膜晶体管还包括刻蚀阻挡层， 所述刻蚀阻挡层设置在与所 述源极和所述漏极之间的间隙对应的所述有源层上方。
根据本发明的实施例， 提供一种阵列基板。 该阵列基板包括如上所述的 薄膜晶体管， 以及与所述薄膜晶体管的漏极电连接的像素电极。
例如， 所述阵列基板还包括公共电极。
根据本发明的实施例， 提供一种显示器。 该显示器包括如上所述的阵列 基板。
根据本发明的实施例， 提供一种薄膜晶体管的制备方法。 该方法包括： 在基板上形成栅极、 栅绝缘层、 有源层、 源极和漏极。 所述在基板上形成有 源层包括： 在基板上形成第一有源层和第二有源层， 且所述第有源层靠近所 述栅绝缘层一侧， 所述第二有源层靠近所述源极和漏极一侧。 所述第一有源 层的载流子迁移率大于所述第二有源层的载流子迁移率。
例如， 所述第一有源层包括氮氧化辞半导体有源层， 所述第二有源层包 括金属掺杂氮氧化辞半导体有源层。
例如， 所述第一有源层的厚度是所述第二有源层的厚度的 1.0 1.8倍。 例如， 所述金属掺杂的金属元素包括铝、 镓、 锗、 铟、 锡、 铋中至少一 种金属元素。
例如， 所述金属掺杂的掺杂总浓度为 0.1~10%。
例如， 通过一次构图工艺在所述基板上形成所述有源层、 所述源极和所 述漏极， 包括：
在所述基板上依次形成氮氧化辞薄膜、 金属掺杂氮氧化辞薄膜、 以及金 属薄膜， 并在所述金属薄膜上形成光刻胶层；
釆用半阶掩膜板或灰阶掩膜板对形成有所述光刻胶层的基板进行曝光、 显影、 刻蚀后， 形成所述氮氧化辞半导体有源层、 所述金属掺杂氮氧化辞半 导体有源层、 以及所述源极和所述漏极。 例如， 所述形成金属掺杂氮氧化辞薄膜包括： 通过溅射法形成所述金属 掺杂氮氧化辞薄膜。
例如， 所述方法还包括形成刻蚀阻挡层， 所述刻蚀阻挡层形成在与所述 源极和所述漏极之间的间隙对应的所述有源层上方；
在所述基板上形成所述有源层、所述刻蚀阻挡层、所述源极和所述漏极， 包括：
在所述基板上依次形成氮氧化辞薄膜、 金属掺杂氮氧化辞薄膜以及刻蚀 阻挡层薄膜， 并在所述刻蚀阻挡层薄膜上形成光刻胶层；
釆用半阶掩膜板或灰阶掩膜板对形成有所述光刻胶层的基板进行曝光、 显影、 刻蚀后， 形成所述氮氧化辞半导体有源层、 所述金属掺杂氮氧化辞半 导体有源层、 以及所述刻蚀阻挡层；
在形成有所述有源层以及所述刻蚀阻挡层的基板上形成金属薄膜， 并在 所述金属薄膜上形成所述光刻胶层；
釆用普通掩膜板对形成有所述光刻胶层的基板进行曝光、显影、刻蚀后， 形成所述源极和所述漏极。
例如， 所述形成金属掺杂氮氧化辞薄膜包括： 通过溅射法形成所述金属 掺杂氮氧化辞薄膜。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例提供的一种底栅型薄膜晶体管结构示意图一； 图 2为本发明实施例提供的一种底栅型薄膜晶体管结构示意图二； 图 3为本发明实施例提供的一种底栅型薄膜晶体管结构示意图三； 图 4为本发明实施例提供的一种顶栅型薄膜晶体管结构示意图； 图 5为本发明实施例提供的一种阵列基板结构示意图一；
图 6为本发明实施例提供的一种阵列基板结构示意图二；
图 Ί〜\2 为本发明实施例提供的一种底栅型薄膜晶体管的制备过程示意 图； 图 13~19为本发明实施例提供的一种底栅型薄膜晶体管的制备过程示意 图。 具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图， 对本发明实施例的技术方案进行清楚、 完整地描述。 显然， 所描述的实施例 是本发明的一部分实施例， 而不是全部的实施例。 基于所描述的本发明的实 施例， 本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实 施例， 都属于本发明保护的范围。
本发明实施例提供了一种薄膜晶体管， 如图 1所示， 包括： 栅极 200、 栅绝缘层 201、 有源层 300、 源极 401和漏极 402; 其中， 所述有源层 300包 括第一有源层 301和第二有源层 302， 且所述第一有源层 301设置在靠近所 述栅绝缘层 201一侧， 所述第二有源层 302设置在靠近所述源极 401和漏极 402一侧； 并且， 所述第一有源层 301的载流子迁移率大于所述第二有源层 302的载流子迁移率。
需要说明的是， 第一， 本领域技术人员应该明白， 所述有源层 300并不 限于上述两层，也可以为两层以上，只要保证沿栅绝缘层 201到所述源极 401 和漏极 402的方向， 有源层 300的各组成层的载流子迁移率依次递减即可， 但是构成所述有源层 300的各层也并不是越多越好， 在保证薄膜晶体管的基 本性能的同时， 使所述薄膜晶体管保持高开态电流并降低所述薄膜晶体管的 漏电流即可。
本发明实施例中， 为了不增加所述有源层 300的整体厚度， 均釆用所述 有源层 300仅包括所述第一有源层 301和第二有源层 302为例进行说明， 但 本发明实施例并不限于此。
第二， 尽管在本发明实施例中， 以底栅型的所述薄膜晶体管为例对本发 明进行了说明， 然而本领域的技术人员应当明白， 在本发明实中也可以将所 述第一有源层 301和所述第二有源层 302应用于顶栅型的薄膜晶体管或其他 结构薄膜晶体管， 在此不做限定。
本发明实施例提供了一种薄膜晶体管， 包括不同载流子迁移率的所述第 一有源层 301和所述第二有源层 302， 由于两种载流子迁移率中具有相对较 高载流子迁移率的所述第一有源层 301设置在靠近所述栅绝缘层 201一侧， 当所述薄膜晶体管应用于显示器时， 便可以保持所述薄膜晶体管具有较高的 开态电流， 从而显著提高所述显示器中的像素的响应速度； 同时， 具有相对 较小载流子迁移率的所述第二有源层 302设置在靠近所述源极 401 和漏极 402 一侧， 可以降低所述薄膜晶体管的漏电流； 因此， 所述薄膜晶体管可在 保持高开态电流的同时降低所述薄膜晶体管的漏电流， 从而在保持所述薄膜 晶体管可靠性的同时满足大尺寸显示器的需求。
例如， 所述第一有源层 301 包括氮氧化辞（ZnON )半导体有源层， 所 述第二有源层 302包括金属掺杂氮氧化辞半导体有源层； 即： 所述第一有源 层 301的材料为氮氧化辞，所述第二有源层 302的材料为金属掺杂氮氧化辞。
例如， 所述第一有源层 301 的厚度是所述第二有源层 302 的厚度的 1.0~1.8倍。 由于所述第二有源层 302与所述第一有源层 301的厚度相近， 可 以保证所述第二有源层 302与所述第一有源层 301作为一个整体时， 二者的 电学性能差异较小。
例如，用于所述金属掺杂的金属元素包括铝（ A1 )、镓（ Ga )、锗（ Ge )、 铟（In ) 、 锡（Sn ) 、 铋（Bi ) 中至少一种金属元素。
例如， 所述金属掺杂的掺杂总浓度为 0.1~10%。 可避免当掺杂浓度过高 时， 使得所述掺杂元素难以进入所述氮氧化辞（ZnON ) 的结构中， 或者形 成其他杂质。
这里， 在氮氧化辞半导体形成的所述第一有源层 301中， 由于辞原子与 氮原子之间的 Zn-N键能较小， 氮原子容易从所述氮氧化辞半导体中的固定 位置脱离出而产生一个空缺， 称为氮空位， 由于所述氮空位的产生， 使得产 生一定数量的空穴载流子。一定数量的氮空位将产生相应数量的空穴载流子， 由于库伦力的吸引， 所述空穴载流子将会吸引所述氮氧化辞半导体中的电子 载流子产生一定方向的运动， 进而使得所述氮氧化辞半导体中载流子的迁移 率增大。 因此， 所述第一有源层 301具有较高的载流子迁移率。
在此基础上， 在所述金属掺杂氮氧化辞半导体形成的所述第二有源层 302中，由于所述金属掺杂的金属元素的原子与氮原子之间的 M-N键能较大， 其中 M包括 Al、 Ga、 Ge、 In、 Sn、 Bi中至少一种金属元素， 即所述金属掺 杂的金属原子与氮原子形成的化学键的结合强度均大于所述辞原子与氮原子 之间的 Zn-N键能， 使得所述氮原子难以从所述金属掺杂的氮氧化辞半导体 中的固定位置脱离出， 从而抑制了所述氮空位的产生； 由于所述氮空位的数 量有所减少， 相应的， 使得所述金属掺杂的氮氧化辞半导体中的载流子数量 有所减少，从而减小了所述金属掺杂的氮氧化辞半导体载流子迁移率。 因此， 所述第二有源层 302具有与所述第一有源层 301相比较低的载流子迁移率。
例如， 如图 2和图 3所示， 所述薄膜晶体管还包括刻蚀阻挡层 500， 所 述刻蚀阻挡层 500设置在与所述源极 401和漏极 402之间的间隙对应的所述 有源层 300上方。
这里， 由于本发明实施例中的所述有源层 300包括氮氧化辞半导体形成 的第一有源层 301和金属掺杂氮氧化辞半导体形成的第二有源层 302， 即构 成所述第一有源层 301和所述第二有源层 302的物质均为金属氮氧化物， 当 所述有源层暴露在外时容易与空气中的氧气或水汽反应， 从而导致所述薄膜 晶体管的特性发生变化。 因此， 本发明实施例中， 例如所述薄膜晶体管还包 括刻蚀阻挡层 500， 所述刻蚀阻挡层 500设置在与所述源极 401和漏极 402 之间的间隙对应的所述有源层 300上方。 所述刻蚀阻挡层 500还用于避免在 后续工艺中刻蚀所述有源层 300上的金属层时对所述有源层 300造成影响。
此外， 为了避免在后续工艺中刻蚀所述源极 401和漏极 402之间的间隙 时对所述有源层的影响， 所述刻蚀阻挡层 500还可以是如图 3所示的结构， 即所述刻蚀阻挡层 500设置在与所述源极 401和漏极 402之间的间隙对应的 所述有源层 300上方， 且所述刻蚀阻挡层 500的面积略敖大于所述源极 401 和漏极 402之间的间隙面积。
需要说明的是， 本发明实施例不对所述刻蚀阻挡层 500釆用的材料加以 限制， 以能够起到保护所述有源层 300在刻蚀后续形成的金属层过程中不被 影响这一目的为准， 所述刻蚀阻挡层 500釆用的材料例如可以是致密的氮化 硅、 氧化硅、 氮氧化硅等材料。
下面提供两个示例， 以详细描述根据本发明实施例的薄膜晶体管。
示例一
本发明实施例提供了一种底栅型薄膜晶体管， 参考图 2所示， 包括： 栅 极 200、 栅绝缘层 201、 有源层 300、 源极 401和漏极 402; 其中， 所述有源 层 300包括氮氧化辞半导体形成的第一有源层 301和镓、 铝共同掺杂的氮氧 化辞半导体形成的第二有源层 302， 且所述第一有源层 301设置在所述栅绝 缘层 201之上， 所述第二有源层 302设置在所述第一有源层 301之上； 所述 薄膜晶体管还包括刻蚀阻挡层 500， 所述刻蚀阻挡层 500设置在与所述源极 401和漏极 402之间的间隙对应的所述第二有源层 302上方。
其中， 氮氧化辞半导体形成的所述第一有源层 301的厚度是镓、 铝共同 掺杂的氮氧化辞半导体形成的所述第二有源层 302厚度的 1.5倍； 并且， 所 述镓、 铝共同掺杂的总浓度为 8%。
由于所述第二有源层 302的材料为镓、 铝共同掺杂的氮氧化辞半导体， 其中， Ga-N及 A1-N的键能均大于所述 Zn-N的键能， 使得所述氮原子难以 从所述镓、 铝共同掺杂的氮氧化辞半导体中的固定位置脱离出， 从而抑制了 所述氮空位的产生； 由于所述氮空位的数量有所减少，相应的，使得所述镓、 铝共同掺杂的氮氧化辞半导体中的载流子数量有所减少，从而减小了所述镓、 铝共同掺杂的氮氧化辞半导体载流子迁移率。 因此， 所述第二有源层 302具 有与所述第一有源层 301相比较低的载流子迁移率。
具有较高载流子迁移率的所述第一有源层 301设置在靠近所述栅绝缘层
201 一侧， 当所述底栅型薄膜晶体管应用于显示器时， 便可以保持所述底栅 型薄膜晶体管具有较高的开态电流， 从而显著提高所述显示器中的像素的响 应速度； 同时， 具有较小载流子迁移率的所述第二有源层 302设置在所述第 一有源层 301之上， 即靠近所述源极 401和漏极 402一侧， 可以降低所述薄 膜晶体管的漏电流； 因此， 所述底栅型薄膜晶体管可在保持高开态电流的同 时降低所述底栅型薄膜晶体管的漏电流， 从而在保持所述底栅型薄膜晶体管 可靠性的同时满足大尺寸显示器的需求。
示例二
本发明实施例提供了一种顶栅型薄膜晶体管， 参考图 4所示， 包括： 依 次设置在基板 100上的源极 401和漏极 402、 有源层 300、 栅绝缘层 201、 栅 极 200; 其中， 所述有源层 300包括氮氧化辞半导体形成的第一有源层 301 和锗掺杂的氮氧化辞半导体形成的第二有源层 302， 且所述第二有源层 302 设置在所述源极 401和漏极 402之上， 所述第一有源层 301设置在所述第二 有源层 302之上。
其中， 氮氧化辞半导体形成的所述第一有源层 301的厚度与锗掺杂的氮 氧化辞半导体形成的所述第二有源层 302的厚度相同； 并且， 所述锗掺杂的 总浓度为 2.0%。
由于所述第二有源层 302的材料为锗掺杂的氮氧化辞半导体，其中， Ge-N 的键能大于所述 Zn-N的键能， 使得所述氮原子难以从所述锗掺杂的氮氧化 辞半导体中的固定位置脱离出， 从而减小了所述锗掺杂的氮氧化辞半导体的 载流子迁移率。 因此， 所述第二有源层 302具有与所述第一有源层 301相比 较低的载流子迁移率。
具有较小载流子迁移率的所述第二有源层 302设置在所述源极 401和漏 极 402之上， 可以降低所述薄膜晶体管的漏电流； 同时， 具有较高载流子迁 移率的所述第一有源层 301设置在所述第二有源层 302之上， 即靠近所述栅 绝缘层 201—侧， 当所述顶栅型薄膜晶体管应用于显示器时， 便可以保持所 述顶栅型薄膜晶体管具有较高的开态电流， 从而显著提高所述显示器中的像 素的响应速度； 因此， 所述顶栅型薄膜晶体管可在降低所述顶栅型薄膜晶体 管的漏电流的同时保持高开态电流， 从而在保持所述顶栅型薄膜晶体管可靠 性的同时满足大尺寸显示器的需求。
本发明实施例还提供了一种阵列基板， 如图 5所示， 包括以上所述的薄 膜晶体管， 以及与所述薄膜晶体管的漏极 402电连接的像素电极 600。
本发明实施例提供的阵列基板可以适用于高级超维场转换型、 扭曲向列 型等类型的液晶显示装置。 高级超维场转换技术的核心技术特性描述为： 通 过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产 生的电场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方所有取向液晶 分子都能够产生旋转， 从而提高了液晶工作效率并增大了透光效率。 高级超 维场转换技术可以提高 TFT液晶显示面板的画面品质， 具有高分辨率、 高透 过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波纹等优点。
因此， 如图 6所示， 所述阵列基板还包括公共电极 700。
这里， 附图 6仅示意性的画出了公共电极 700在上， 像素电极 600在下 的情况， 当然， 所述阵列基板还可以是公共电极 700在下， 像素电极 600在 上。
当所述公共电极 700在上， 像素电极 600在下时， 位于上层的所述公共 电极 700可以做成包含多个电连接的条形电极， 此时， 公共电极 700为含有 狭缝的结构或梳状结构， 位于下层的像素电极 600做成平板型。 但本发明实 施例并不限于此， 位于下层的像素电极 600也可以为包含多个电连接的条形 电极。 同理， 所述公共电极 700在下， 像素电极 600在上的情况， 在上的像 素电极为狭缝状， 在下的公共电极可以是板状电极， 也可以是狭缝状电极。
本发明实施例又提供了一种显示器， 包括以上所述的阵列基板。
所述显示器具体可以是液晶显示器、 液晶电视、 数码相框、 手机、 平板 电脑等具有任何显示功能的产品或者部件。
针对上述薄膜晶体管， 本发明实施例还提供了一种薄膜晶体管的制备方 法， 包括： 在基板 100上形成栅极 200、栅绝缘层 201、有源层 300、 源极 401 和漏极 402; 其中， 所述在基板 100上形成有源层 300包括： 在基板 100上 形成第一有源层 301和第二有源层 302， 且所述第一层有源层 301靠近所述 栅绝缘层 201—侧，所述第二有源层 302靠近所述源极 401和漏极 402一侧； 并且， 所述第一有源层 301的载流子迁移率大于所述第二有源层 302的载流 子迁移率。
例如， 所述第一有源层 301包括氮氧化辞半导体有源层， 所述第二有源 层 302包括金属掺杂氮氧化辞半导体有源层。
例如， 所述第一有源层 301 的厚度是所述第二有源层 302 的厚度的 1.0~1.8倍。
例如，用于所述金属掺杂的金属元素包括铝（ A1 )、镓（ Ga )、锗（ Ge ) 、 铟（In ) 、 锡（Sn ) 、 铋（Bi ) 中至少一种金属元素。
例如， 所述金属掺杂的掺杂总浓度为 0.1~10%。
例如， 上述的有源层 300、 所述源极 401和漏极 402可以通过一次构图 工艺形成。 首先， 在基板 100上依次形成氮氧化辞薄膜、 金属掺杂氮氧化辞 薄膜、 以及金属薄膜， 并在所述金属薄膜上形成光刻胶层； 釆用半阶掩膜板 或灰阶掩膜板对形成有所述光刻胶的所述基板进行曝光、 显影、 刻蚀后， 形 成所述氮氧化辞半导体的所述第一有源层 301、 所述金属掺杂氮氧化辞半导 体的所述第二有源层 302、 以及所述源极 401和漏极 402。
溅射法形成的薄膜具有成膜均勾， 表面平整， 膜厚可控， 掺杂浓度可控 等优点； 因此， 可通过磁控溅射法形成所述金属掺杂氮氧化辞薄膜。
釆用半阶掩膜板或灰阶掩膜板对形成有所述光刻胶层的所述基板进行曝 光、 显影、 刻蚀后， 形成所述第一有源层 301、 所述第二有源层 302、 以及所 述源极 401和漏极 402可以为：
釆用半阶掩膜板或灰阶掩膜板对形成有所述光刻胶层的基板进行曝光、 显影后， 形成光刻胶完全保留部分、 光刻胶半保留部分和光刻胶完全去除部 分； 其中， 所述光刻胶完全保留部分对应待形成的所述源极 401和漏极 402， 所述光刻胶半保留部分对应待形成的所述源极 401和漏极 402之间的间隙， 所述光刻胶完全去除部分对应其他区域。
然后， 釆用刻蚀工艺去除所述光刻胶完全去除部分的氮氧化辞薄膜、 金 属掺杂氮氧化辞薄膜、 以及金属薄膜， 形成包括第一有源层 301和所述第二 有源层 302的有源层。
釆用灰化工艺去除所述光刻胶半保留部分的光刻胶， 釆用刻蚀工艺去除 露出的所述金属薄膜， 形成所述源极 401和漏极 402。
最后釆用剥离工艺去除所述光刻胶完全保留部分的光刻胶。
这样可以通过一次构图工艺， 便可形成所述第一有源层 301、 所述第二 有源层 302、 以及所述源极 401和漏极 402， 可以减少构图工艺的次数，从而 降低成本。
此处， 如图 4所示， 所述薄膜晶体管也可以是顶栅型薄膜晶体管， 当所 述薄膜晶体管为顶栅型时， 所述方法包括通过第一次构图工艺在所述基板 100上形成所述源极 401和漏极 402，再通过第二次构图工艺在所述源极 401 和漏极 402上形成所述有源层 300， 所述有源层 300包括氮氧化辞半导体形 成的所述第一有源层 301、 所述金属掺杂氮氧化辞半导体形成的所述第二有 源层 302， 所述第二有源层 302靠近所述源极 401和漏极 402; 然后，依次形 成栅绝缘层 201和栅极 200。
例如， 所述方法还包括形成刻蚀阻挡层 500， 参考如图 2所示， 所述刻 蚀阻挡层 500形成在与所述源极 401和漏极 402之间的间隙对应的所述有源 层 300上方。
此处， 为了避免在后续工艺中刻蚀所述源极 401和漏极 402之间的间隙 时对所述有源层的影响，所述刻蚀阻挡层 500还可以参考如图 3所示的结构， 即所述刻蚀阻挡层 500设置在与所述源极 401和漏极 402之间的间隙对应的 所述有源层 300上方， 且所述刻蚀阻挡层 500的面积略敖大于所述源极 401 和漏极 402之间的间隙面积。
在此基础上， 在所述基板上形成所述有源层 300、 所述刻蚀阻挡层 500、 所述源极 401和所述漏极 402包括：
在所述基板 100上依次形成氮氧化辞薄膜、 金属掺杂氮氧化辞薄膜以及 刻蚀阻挡层薄膜， 并在所述刻蚀阻挡层薄膜上形成光刻胶层； 釆用半阶掩膜 板或灰阶掩膜板对形成有所述光刻胶层的基板进行曝光、 显影、 刻蚀后， 形 成所述氮氧化辞半导体有源层、 所述金属掺杂氮氧化辞半导体有源层、 以及 所述刻蚀阻挡层 500。
进一步的，在形成有所述有源层 300以及所述刻蚀阻挡层 500的基板 100 上形成金属薄膜， 并在所述金属薄膜上形成所述光刻胶层； 釆用普通掩膜板 对形成有所述光刻胶层的基板 100进行曝光、 显影、 刻蚀后， 形成所述源极 401和所述漏极 402。
溅射法形成的薄膜具有成膜均勾， 表面平整， 膜厚可控， 掺杂浓度可控 等优点； 因此， 可通过磁控溅射法形成所述金属掺杂氮氧化辞薄膜。
下面提供 2个具体的示例，用以详细描述上述的薄膜晶体管的制备方法。 示例三
以底栅型薄膜晶体管为例来详细描述上述薄膜晶体管的制备方法， 在所 述底栅型薄膜晶体管不包括所述刻蚀阻挡层 500的情况下， 该方法包括如下 步骤：
S01、 如图 7所示， 在所述基板 100上形成金属薄膜， 通过一次构图工 艺处理， 在所述基板 100上形成栅极 200。
例如， 可以使用磁控溅射方法， 在玻璃基板上制备厚度在 1000 7000A 的铜单质金属薄膜。 然后通过普通掩膜板进行曝光、 显影、 刻蚀、 剥离等构 图工艺处理， 在所述基板 100的一定区域形成所述栅极 200， 同时还形成栅 线、 栅线引线等。
S02、 如图 8所示， 在完成步骤 S01的基板上形成栅绝缘层 201。
例如， 可以利用化学气相沉积法在形成有所述栅极 200的基板上沉积厚 度约为 1000 6000A的栅绝缘层薄膜， 所述栅绝缘层薄膜的材料通常是氮化 硅， 也可以使用氧化硅和氮氧化硅。
S03、如图 9所示，在完成步骤 S02的基板上依次形成氮氧化辞薄膜 301a、 镓、 铝共同掺杂氮氧化辞薄膜 302a、 以及金属薄膜 400， 并在所述金属薄膜 上形成光刻胶层 800。
例如，可以利用磁控溅射法在上述基板上沉积厚度约为 100 8000A的氮 氧化辞薄膜 301a和厚度约为 100 8000A 的镓、 铝共同掺杂氮氧化辞薄膜 302a; 然后再在上述基板上沉积厚度约为 1000 7000A的钼金属薄膜 400，并 在所述钼金属薄膜 400上涂覆光刻胶层 800。
S04、 如图 10所示， 釆用半阶掩膜板 900对形成有所述光刻胶层 800的 基板进行曝光、 显影后， 形成光刻胶完全保留部分 801、 光刻胶半保留部分
802和光刻胶完全去除部分 803。
所述光刻胶完全保留部分 801对应待形成的所述源极 401和漏极 402， 所述光刻胶半保留部分 802对应待形成的所述源极 401和漏极 402之间的间 隙， 所述光刻胶完全去除部分 803对应其他区域。
此处， 首先对普通掩模板的工作原理加以说明， 以便更好地理解半阶掩 模板 900的工作原理：
普通掩模板是指在透明衬底材料上形成的具有特定图形的遮光金属层， 以便实现所述光刻胶层 800选择性曝光的一种装置。 其中， 所述遮光金属层 覆盖的区域是完全不透明的， 而没有被所述遮光金属层覆盖的区域是完全透 明的； 通过所述普通掩模板对所述光刻胶层 800进行曝光， 由于紫外光无法 照射到与所述普通掩模板的完全不透明部分对应的部分光刻胶层 800， 从而 在显影后形成了所述光刻胶完全保留部分 801， 而与所述普通掩模板的完全 透明部分对应的光刻胶层 800，在显影后形成了光刻胶完全去除部分 803 ;这 样一来， 在刻蚀所述光刻胶覆盖的薄膜时， 所述光刻胶完全保留部分 801覆 盖的薄膜均会被保留， 而所述光刻胶完全去除部分 803覆盖的薄膜均会被完 全刻蚀去除， 从而形成具有特定图案的至少一层图案层。
通过釆用所述普通掩模板， 上述的至少一层图案层的图案均相同； 而当 需要通过一次构图工艺得到不同图案的至少两层图案层时， 就需要釆用所述 半阶掩膜板 900。
参考图 10所示， 所述半阶掩膜板 900与所述普通掩膜板相比， 所述半 阶掩膜板 900除包括完全不透明部分 901和完全透明部分 903外， 还包括半 透明部分 902; 即： 半阶掩膜板 900是指在透明衬底材料上在某些区域形成 不透光的遮光金属层， 在另外一些区域形成半透光的遮光金属层， 其他区域 不形成任何遮光金属层； 其中， 所述半透光的遮光金属层的厚度小于所述完 全不透光的遮光金属层的厚度； 此外， 可以通过调节所述半透光的遮光金属 层的厚度来改变所述半透光的遮光金属层对紫外光的透过率。
基于上述描述， 所述半阶掩膜板 900工作原理说明如下： 通过控制所述 半阶掩膜板 900上不同区域处遮光金属层的厚度， 使曝光时在不同区域的透 过光的强度有所不同， 从而使光刻胶层 800进行有选择性的曝光、 显影后， 形成与所述半阶掩膜板 900的完全不透明部分 901、 半透明部分 902以及完 全透明部分 903分别对应的光刻胶完全保留部分 801、光刻胶半保留部分 802、 光刻胶完全去除部分 803。 这样以来， 在第一次刻蚀时， 所述光刻胶完全保 留部分 801和所述光刻胶半保留部分 802覆盖的薄膜均会被保留， 此后， 由 于光刻胶完全保留部分 801的厚度大于所述光刻胶半保留部分 802的厚度， 当把所述光刻胶半保留部分 802的光刻胶灰化掉后，光刻胶完全保留部分 801 的光刻胶还存在， 这样便可以对露出部分的薄膜进行有选择的刻蚀， 从而可 以得到不同图案的至少两层图案层。
所述灰阶掩膜板的原理与所述半阶掩膜板 900的原理类似， 此处不再赘 述， 仅对所述灰阶掩膜板与所述半阶掩膜板 900不同之处加以说明： 所述半 阶掩膜板的半透明部分 902， 是通过在所述透明衬底材料上形成厚度相对较 薄的半透光的遮光金属层， 即， 通过控制金属层的厚度来调节紫外光的透过 率， 从而使与该部分对应的光刻胶的曝光量与其他区域的曝光量不同； 而所 述灰阶掩模板的半透明部分， 是通过制作一些窄条形的狭缝结构， 当紫外光 通过狭缝结构时， 发生散射、 衍射等光学现象， 从而使与该部分对应的所述 光刻胶的曝光量与其他区域的曝光量不同。
本发明所有实施例中所指的所述光刻胶层 800均为正性胶， 即所述半阶 掩膜板 900中， 所述光刻胶完全去除部分 803对应的区域为完全曝光区域， 对应所述半阶掩膜板 900的完全透明部分 903; 所述光刻胶半保留部分 802 对应的区域为半曝光区域， 对应所述半阶掩膜板 900的半透明部分 902， 所 述光刻胶完全保留部分 801对应的区域为不曝光区域， 对应所述半阶掩膜板 900 的完全不透明部分 901。 然而， 本发明实施例并不局限于此， 光刻胶层 800也可以为负性胶。 505、 如图 11所示， 釆用刻蚀工艺去除与所述光刻胶完全去除部分 803 对应的氮氧化辞薄膜 301a、 镓、 铝共同掺杂氮氧化辞薄膜 302a、 以及金属薄 膜 400， 形成有源层 300。
所述有源层 300包括靠近所述栅绝缘层 201的氮氧化辞半导体形成的所 述第一有源层 301、 以及位于所述第一有源层 301上方的金属掺杂氮氧化辞 半导体形成的所述第二有源层 302。
506、 如图 12所示， 釆用灰化工艺去除所述光刻胶半保留部分 802的光 刻胶 800， 并釆用刻蚀工艺去除露出的所述金属薄膜 400， 形成所述源极 401 和所述漏极 402。
S07、 通过剥离工艺去除所述光刻胶完全保留部分 801 的光刻胶， 形成 参考图 1所述的薄膜晶体管。
示例四
以底栅型薄膜晶体管为例来详细描述上述薄膜晶体管的制备方法， 在所 述底栅型薄膜晶体管包括所述刻蚀阻挡层 500的情况下， 该方法包括如下步 骤：
511、 参考图 7所示， 在基板 100上形成金属薄膜， 通过一次构图工艺 处理， 在所述基板 100上形成栅极 200。
例如， 可以使用磁控溅射方法， 在玻璃基板上制备厚度在 1000 7000A 的铜单质金属薄膜。 然后通过普通掩膜板进行曝光、 显影、 刻蚀、 剥离等构 图工艺处理， 在所述基板 100的一定区域形成所述栅极 200， 同时还形成栅 线、 栅线引线等。
512、 参考图 8所示， 在完成步骤 S11的基板上形成栅绝缘层 201。
例如， 可以利用化学气相沉积法在形成有所述栅极 200的基板上沉积厚 度约为 1000 6000A的栅绝缘层薄膜， 所述栅绝缘层薄膜的材料通常是氮化 硅， 也可以使用氧化硅和氮氧化硅。
513、 如图 13 所示， 在完成步骤 S12 的基板上依次形成氮氧化辞薄膜 301a, 铟掺杂氮氧化辞薄膜 302a、 以及刻蚀阻挡层薄膜 500a， 并在所述刻蚀 阻挡层薄膜 500a上形成光刻胶层 800。
例如，可以利用磁控溅射法在上述基板上沉积厚度约为 100 8000A的氮 氧化辞薄膜 301a和厚度约为 100 8000A的铟掺杂氮氧化辞薄膜 302a; 然后 再在上述基板上沉积厚度约为 500 3000A的氮化硅刻蚀阻挡层薄膜 500a，并 在所述氮化硅刻蚀阻挡层薄膜 500a上涂覆光刻胶层 800。
514、 如图 14所示， 釆用半阶掩膜板 900对形成有所述光刻胶层 800的 基板进行曝光、 显影后， 形成光刻胶完全保留部分 801、 光刻胶半保留部分 802和光刻胶完全去除部分 803。
所述光刻胶完全保留部分 801对应待形成的所述刻蚀阻挡层 500， 所述 光刻胶半保留部分 802对应待形成的所述刻蚀阻挡层 500没有覆盖住所述有 源层 300的部分， 所述光刻胶完全去除部分 803对应其他区域。
515、 如图 15所示， 釆用刻蚀工艺去除与所述光刻胶完全去除部分 803 对应的氮氧化辞薄膜 301a、 镓、 铝共同掺杂氮氧化辞薄膜 302a以及刻蚀阻 挡层薄膜 500a， 形成有源层 300。
所述有源层 300包括靠近所述栅绝缘层 201的氮氧化辞半导体形成的所 述第一有源层 301、 以及位于所述第一有源层 301上方的金属掺杂氮氧化辞 半导体形成的所述第二有源层 302。
S16、 如图 16所示， 釆用灰化工艺去除所述光刻胶半保留部分 802的光 刻胶 800， 并釆用刻蚀工艺去除露出的所述刻蚀阻挡层薄膜 500a， 形成所述 刻蚀阻挡层 500。
然后， 通过剥离工艺去除所述光刻胶完全保留部分 801的光刻胶 800。
517、如图 17所示，在完成步骤 S16的基板上形成厚度约为 100 7000A 的钼金属薄膜 400， 并在所述钼金属薄膜 400上形成光刻胶层 800。
518、 如图 18所示， 釆用普通掩膜板 1000对形成有所述光刻胶层 800 的基板进行曝光、 显影后， 形成所述光刻胶完全保留部分 801和所述光刻胶 完全去除部分 803。
所述光刻胶完全保留部分 801对应待形成的所述源极 401和漏极 402, 所述光刻胶完全去除部分 803对应待形成的所述源极 401和漏极 402之间的 间隙及其它区域。
519、 如图 19所示， 釆用刻蚀工艺去除与所述光刻胶完全去除部分 803 对应的钼金属薄膜 400， 形成所述源极 401和所述漏极 402。
520、 通过剥离工艺去除所述光刻胶完全保留部分 801 的光刻胶， 形成 参考图 2所述的薄膜晶体管。 此外， 在上述步骤 S01-S07或者步骤 S11-S20的基础上， 还可以依次形 成露出所述漏极 402的保护层， 通过所述过孔与所述漏极 402连接的像素电 极， 从而制备形成阵列基板。 当然还可以在所述像素电极上方依次形成钝化 层和公共电极。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。
本申请要求于 2013年 10月 21 日递交的第 201310495817.6号中国专利 申请的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的 一部分。

Claims

权利要求书
1、 一种薄膜晶体管， 包括： 栅极、 栅绝缘层、 有源层、 源极和漏极， 其 中
所述有源层包括第一有源层和第二有源层， 且所述第一有源层设置在靠 近所述栅绝缘层一侧， 所述第二有源层设置在靠近所述源极和漏极一侧； 并 且
所述第一有源层的载流子迁移率大于所述第二有源层的载流子迁移率。
2、根据权利要求 1所述的薄膜晶体管，其中所述第一有源层包括氮氧化 辞半导体有源层， 所述第二有源层包括金属掺杂氮氧化辞半导体有源层。
3、根据权利要求 2所述的薄膜晶体管，其中所述第一有源层的厚度是所 述第二有源层的厚度的 1.0~1.8倍。
4、根据权利要求 2-3任一项所述的薄膜晶体管， 其中用于所述金属掺杂 的金属元素包括铝、 镓、 锗、 铟、 锡、 铋中至少一种金属元素。
5、根据权利要求 2-4任一项所述的薄膜晶体管， 其中所述金属掺杂的掺 杂总浓度为 0.1~10%。
6、根据权利要求 1所述的薄膜晶体管，其中所述薄膜晶体管还包括刻蚀 阻挡层， 所述刻蚀阻挡层设置在与所述源极和所述漏极之间的间隙对应的所 述有源层上方。
7、 一种阵列基板， 包括权利要求 1至 6任一项所述的薄膜晶体管， 以及 与所述薄膜晶体管的漏极电连接的像素电极。
8、根据权利要求 7所述的阵列基板，其中所述阵列基板还包括公共电极。
9、 一种显示器， 包括权利要求 7或 8所述的阵列基板。
10、 一种薄膜晶体管的制备方法， 包括： 在基板上形成栅极、栅绝缘层、 有源层、 源极和漏极； 其中所述在基板上形成有源层包括：
在基板上形成第一有源层和第二有源层， 且所述第有源层靠近所述栅绝 缘层一侧， 所述第二有源层靠近所述源极和漏极一侧；
其中所述第一有源层的载流子迁移率大于所述第二有源层的载流子迁移 率。
11、根据权利要求 10所述的方法，其中所述第一有源层包括氮氧化辞半 导体有源层， 所述第二有源层包括金属掺杂氮氧化辞半导体有源层。
12、根据权利要求 11所述的方法，其中所述第一有源层的厚度是所述第 二有源层的厚度的 1.0~1.8倍。
13、 根据权利要求 11-12任一项所述的方法， 其中所述金属掺杂的金属 元素包括铝、 镓、 锗、 铟、 锡、 铋中至少一种金属元素。
14、 根据权利要求 11-13任一项所述的薄膜晶体管， 其中所述金属掺杂 的掺杂总浓度为 0.1~10%。
15、根据权利要求 11所述的方法，其中通过一次构图工艺在所述基板上 形成所述有源层、 所述源极和所述漏极， 包括：
在所述基板上依次形成氮氧化辞薄膜、 金属掺杂氮氧化辞薄膜、 以及金 属薄膜， 并在所述金属薄膜上形成光刻胶层；
釆用半阶掩膜板或灰阶掩膜板对形成有所述光刻胶层的基板进行曝光、 显影、 刻蚀后， 形成所述氮氧化辞半导体有源层、 所述金属掺杂氮氧化辞半 导体有源层、 以及所述源极和所述漏极。
16、根据权利要求 15所述的方法，其中所述形成金属掺杂氮氧化辞薄膜 包括： 通过溅射法形成所述金属掺杂氮氧化辞薄膜。
17、根据权利要求 11所述的方法，其中所述方法还包括形成刻蚀阻挡层， 所述刻蚀阻挡层形成在与所述源极和所述漏极之间的间隙对应的所述有源层 上方；
在所述基板上形成所述有源层、所述刻蚀阻挡层、所述源极和所述漏极， 包括：
在所述基板上依次形成氮氧化辞薄膜、 金属掺杂氮氧化辞薄膜以及刻蚀 阻挡层薄膜， 并在所述刻蚀阻挡层薄膜上形成光刻胶层；
釆用半阶掩膜板或灰阶掩膜板对形成有所述光刻胶层的基板进行曝光、 显影、 刻蚀后， 形成所述氮氧化辞半导体有源层、 所述金属掺杂氮氧化辞半 导体有源层、 以及所述刻蚀阻挡层；
在形成有所述有源层以及所述刻蚀阻挡层的基板上形成金属薄膜， 并在 所述金属薄膜上形成所述光刻胶层；
釆用普通掩膜板对形成有所述光刻胶层的基板进行曝光、显影、刻蚀后， 形成所述源极和所述漏极。
18、根据权利要求 17所述的方法，其中所述形成金属掺杂氮氧化辞薄膜 包括： 通过溅射法形成所述金属掺杂氮氧化辞薄膜。
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