WO2011111781A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2011111781A1 WO2011111781A1 PCT/JP2011/055658 JP2011055658W WO2011111781A1 WO 2011111781 A1 WO2011111781 A1 WO 2011111781A1 JP 2011055658 W JP2011055658 W JP 2011055658W WO 2011111781 A1 WO2011111781 A1 WO 2011111781A1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01—ELECTRIC ELEMENTS
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Definitions
- the present invention relates to a semiconductor device, and more particularly, to a semiconductor device including an oxide semiconductor TFT.
- the present invention also relates to a method for manufacturing such a semiconductor device.
- An active matrix substrate used for a liquid crystal display device or the like includes a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel.
- a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel.
- TFT thin film transistor
- amorphous silicon TFT a TFT having an amorphous silicon film as an active layer
- polycrystalline silicon TFT a TFT having a polycrystalline silicon film as an active layer
- the polycrystalline silicon TFT Since the mobility of electrons and holes in the polycrystalline silicon film is higher than that of the amorphous silicon film, the polycrystalline silicon TFT has a higher on-current than the amorphous silicon TFT and can operate at high speed. Therefore, when an active matrix substrate is formed using a polycrystalline silicon TFT, the polycrystalline silicon TFT can be used not only as a switching element but also in a peripheral circuit such as a driver. Therefore, there is an advantage that part or all of peripheral circuits such as a driver and the display portion can be integrally formed on the same substrate. Further, there is an advantage that the pixel capacity of a liquid crystal display device or the like can be charged with a shorter switching time.
- the polycrystalline silicon TFT is mainly used for medium-sized and small-sized liquid crystal display devices.
- the amorphous silicon TFT is preferably used for an active matrix substrate of a device that requires a large area. Despite having a lower on-current than polycrystalline silicon TFTs, amorphous silicon TFTs are used in many active matrix substrates of liquid crystal televisions.
- liquid crystal display devices such as liquid crystal televisions are strongly required to have high image quality and low power consumption in addition to an increase in size, and it is difficult for amorphous silicon TFTs to sufficiently meet such requirements.
- liquid crystal display devices are strongly required to have a high performance such as a driver monolithic substrate for narrow frame and cost reduction, and a built-in touch panel function. It is difficult to fully meet the requirements.
- Patent Documents 1 and 2 propose forming an active layer of a TFT using an oxide semiconductor film such as zinc oxide.
- a TFT is called an “oxide semiconductor TFT”.
- An oxide semiconductor has higher mobility than amorphous silicon. For this reason, the oxide semiconductor TFT can operate at a higher speed than the amorphous silicon TFT.
- the oxide semiconductor film is formed by a simpler process than the polycrystalline silicon film, the oxide semiconductor film can be applied to a device that requires a large area.
- the oxide semiconductor film may be easily damaged in the manufacturing process, and the transistor characteristics may be deteriorated.
- dry etching using a halogen gas such as a fluorine gas or a chlorine gas is generally performed when the source / drain electrodes are formed by patterning.
- a halogen gas such as a fluorine gas or a chlorine gas
- the oxide semiconductor film is exposed to a halogen plasma, so that oxygen is detached from the oxide semiconductor film, and thus the characteristics deteriorate (for example, the off characteristics deteriorate due to the low resistance of the channel). Will occur.
- Patent Documents 1 and 2 propose that an insulating film (channel protective film) functioning as an etch stop is formed on the channel region of an active layer formed from an oxide semiconductor. Yes.
- FIG. 14 shows a cross-sectional structure of a conventional oxide semiconductor TFT 10A having a channel protective film.
- the oxide semiconductor TFT 10A includes a substrate 1, a gate electrode 11 provided on the substrate 1, a gate insulating layer 12 covering the gate electrode 11, an oxide semiconductor layer 13 formed on the gate insulating layer 12, an oxide semiconductor TFT 13A.
- a channel protective film 30 formed on the channel region of the physical semiconductor layer 13 and a source electrode 14 and a drain electrode 15 provided on the oxide semiconductor layer 13 are provided.
- the source electrode 14 and the drain electrode 15 are each electrically connected to the oxide semiconductor layer 13.
- Patent Document 1 describes that an amorphous oxide insulator film is used as the channel protective film 30.
- Patent Document 2 describes using a silicon nitride film as the channel protective film 30.
- the channel region of the oxide semiconductor layer 13 is formed by the channel protective film 30. Protected. Therefore, damage to the channel region of the oxide semiconductor layer 13 can be prevented.
- the present invention has been made in view of the above problems, and its object is to reduce damage to an oxide semiconductor layer in a manufacturing process of an oxide semiconductor TFT having a bottom gate / top contact structure, and to improve throughput. It is in suppressing the decrease.
- a semiconductor device includes a substrate, a gate electrode provided on the substrate, a gate insulating layer formed on the gate electrode, a channel region formed on the gate insulating layer, and the channel region.
- An oxide semiconductor layer having a source region and a drain region located on both sides of the source region, a source electrode electrically connected to the source region, a drain electrode electrically connected to the drain region, and the source
- a metal compound layer located between and in contact with the oxide semiconductor layer, the metal compound layer comprising a metal element contained in the source electrode and the drain electrode. It is an insulator layer or a semiconductor layer formed from a compound of the same metal element as at least one of them.
- the thickness of the metal compound layer is smaller than the thickness of the source electrode and the drain electrode.
- the metal compound layer has a thickness of 1 nm to 50 nm.
- the metal compound layer has a thickness of 1 nm or more and 5 nm or less.
- the metal compound layer is a metal oxide layer.
- the method of manufacturing a semiconductor device includes a step (A) of forming a gate electrode on a substrate, a step (B) of forming a gate insulating layer so as to cover the gate electrode, and an oxidation on the gate insulating layer.
- a method of manufacturing a semiconductor device comprising: a step (C) of forming a physical semiconductor layer; and a step (D) of providing a source electrode and a drain electrode electrically connected to the oxide semiconductor layer
- the step (D) includes a step (D-1) of forming a metal film so as to cover the oxide semiconductor layer, and a step of forming the source electrode and the drain electrode by patterning the metal film (D- 2), and in the patterning in the step (D-2), a portion of the metal film located on a region to be a channel region of the oxide semiconductor layer has the source electrode and
- the step (D-2) is a photoresist layer that covers a part of the metal film, and is a first layer that overlaps a region to be a source region and a drain region of the oxide semiconductor layer.
- the photoresist layer is a second portion that overlaps a region that becomes a channel region of the oxide semiconductor layer, and the first portion Is implemented to have a thinner second portion.
- the step (D-2-1) includes an exposure step using a multi-tone mask.
- the metal compound layer formed in the step (E) is an insulator layer or a semiconductor layer.
- the metal compound layer has a thickness of 1 nm to 50 nm.
- the metal compound layer has a thickness of 1 nm or more and 5 nm or less.
- a metal oxide layer is formed as the metal compound layer by oxidizing the conductor film in the step (E).
- the present invention it is possible to reduce damage to the oxide semiconductor layer in the manufacturing process of an oxide semiconductor TFT having a bottom gate / top contact structure and to suppress a decrease in throughput.
- FIG. 2 is a diagram schematically showing a cross-sectional structure of a TFT substrate 100 in a preferred embodiment of the present invention, and is a cross-sectional view taken along line 2A-2A ′ in FIG. It is sectional drawing which shows typically the thin-film transistor 10 with which the TFT substrate 100 in suitable embodiment of this invention is provided.
- FIGS. 5A to 5D are process cross-sectional views for explaining a manufacturing method of the TFT substrate 100.
- FIGS. FIGS. 5A to 5D are process cross-sectional views for explaining a manufacturing method of the TFT substrate 100.
- FIGS. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of TFT substrate 100.
- FIG. It is a graph which shows the gate voltage-drain current (Vg-Id) characteristic of the thin-film transistor 10B of a comparative example.
- 3 is a graph showing gate voltage-drain current (Vg-Id) characteristics of the thin film transistor 10 of Example 1.
- 6 is a graph showing the gate voltage-drain current (Vg-Id) characteristics of the thin film transistor 10 of Example 2.
- 3 is a graph showing gate voltage-drain current (Vg-Id) characteristics of the thin film transistor 10 of Example 1.
- 6 is a graph showing the gate voltage-drain current (Vg-Id) characteristics of the thin film transistor 10 of Example 2. It is sectional drawing which shows typically the TFT substrate 100 in suitable embodiment of this invention.
- a semiconductor device includes a thin film transistor (oxide semiconductor TFT) having an active layer formed of an oxide semiconductor.
- the semiconductor device according to the present invention only needs to include at least one oxide semiconductor TFT, and widely includes various substrates, various display devices, and various electronic devices including such a TFT.
- an active matrix substrate (TFT substrate) for a liquid crystal display device will be described as an example.
- FIG. 1 is a plan view schematically showing a region corresponding to one pixel of the TFT substrate 100
- FIG. 2 is a cross-sectional view taken along line 2A-2A 'in FIG.
- the TFT substrate 100 includes an insulating substrate (typically a transparent substrate) 1, a gate wiring (scanning wiring) 2 and a source wiring (signals) provided on the substrate 1. Wiring) 3, a thin film transistor 10 electrically connected to the gate wiring 2 and the source wiring 3, and a pixel electrode 4 electrically connected to the thin film transistor 10.
- the gate wiring 2 is formed to extend in the row direction, whereas the source wiring 3 is formed to extend in the column direction.
- the thin film transistor 10 is supplied with a scanning signal from the gate line 2 and supplied with a display signal from the source line 3.
- the TFT substrate 100 further includes an auxiliary capacitance line 5 for forming the auxiliary capacitance Cs.
- FIG. 3 is a cross-sectional view schematically showing the thin film transistor 10 in an enlarged manner.
- the thin film transistor 10 includes a gate electrode 11 provided on the substrate 1, a gate insulating layer 12 formed on the gate electrode 11, an oxide semiconductor layer 13 formed on the gate insulating layer 12, and an oxide semiconductor layer. 13 has a source electrode 14 and a drain electrode 15 electrically connected to 13.
- the source electrode 14 and the drain electrode 15 are in contact with the upper surface of the oxide semiconductor layer 13.
- a region 13 s in contact with the source electrode 14 is referred to as a “source region”
- a region 13 d in contact with the drain electrode 15 is referred to as a “drain region”.
- a region 13c of the oxide semiconductor layer 13 that overlaps with the gate electrode 11 and is located between the source region 13s and the drain region 13d is referred to as a “channel region”. That is, the oxide semiconductor layer 13 includes a channel region 13c and a source region 13s and a drain region 13d that are located on both sides of the channel region 13c, respectively.
- the source electrode 14 and the drain electrode 15 are each an oxide semiconductor layer. 13 source regions 13s and drain regions 13d are electrically connected.
- the thin film transistor 10 in the present embodiment further includes a metal compound layer 16 that is located between the source electrode 14 and the drain electrode 15 and provided on and in contact with the oxide semiconductor layer 13.
- the metal compound layer 16 is an insulator layer or a semiconductor layer.
- the metal compound layer 16 is formed by using a part of a metal film (hereinafter also referred to as “source metal film”) for forming the source electrode 14 and the drain electrode 15. Specifically, the metal compound layer 16 leaves a portion located on the channel region when the source electrode 14 and the drain electrode 15 are formed by patterning the source metal film. It is formed by chemically reacting a body membrane) to remove it from a conductor. Therefore, the metal compound layer 16 is a compound of the same metal element as at least one of the metal elements (one or a plurality of types) contained in the source electrode 14 and the drain electrode 15 (not necessarily all types as described later). Formed from.
- source metal film a metal film
- the first interlayer insulating layer 6 and the second interlayer insulating layer 7 are provided so as to cover the thin film transistor 100 having the above-described structure.
- the first interlayer insulating layer 6 and the second interlayer insulating layer 7 are stacked in this order from the lower side.
- a pixel electrode 4 is provided on the second interlayer insulating layer 7.
- An opening 8 is formed at a position of the first interlayer insulating layer 6 and the second interlayer insulating layer 7 that overlaps the auxiliary capacitance wiring 5.
- the drain electrode 15 extends to the opening 8, and the pixel electrode 4 is connected to the drain electrode 15 in the opening 8.
- the TFT substrate 100 in this embodiment includes the metal compound layer 16 located between the source electrode 14 and the drain electrode 15 (that is, on the channel region 13c of the oxide semiconductor layer 13). Therefore, when the source electrode 14 and the drain electrode 15 are formed by patterning (for example, using dry etching), the oxide semiconductor layer 13 is protected by a portion that becomes the metal compound layer 16 of the source metal film. Therefore, damage to the oxide semiconductor layer 13 in the manufacturing process is reduced. Further, since it is not necessary to deposit a new film or pattern the film in order to form the metal compound layer 16, compared with the structure in which the channel protective film 30 as shown in FIG. 14 is provided. , Improve throughput.
- the thickness of the metal compound layer 16 is preferably smaller than the thickness of the source electrode 14 and the drain electrode 15 as shown in FIGS. If the metal compound layer 16 is thinner than the source electrode 14 and the drain electrode 15, it is easy to prevent a conductor portion from remaining when the metal compound layer 16 is formed by chemically reacting a part of the source metal film. Become.
- the thickness of the source electrode 14 and the drain electrode 15 is typically 100 nm or more and 500 nm or less.
- the thickness of the metal compound layer 16 is preferably 1 nm or more and 50 nm or less. If the thickness of the metal compound layer 16 exceeds 50 nm, it may be difficult to leave no conductor portion depending on the type of chemical reaction used. If the thickness of the metal compound layer 16 is less than 1 nm, the channel region 13c may be exposed due to variations in etching, and in that case, the oxide semiconductor layer 13 is damaged.
- the metal compound layer 16 may be formed of any compound as long as it is an insulator or a semiconductor.
- the metal compound layer 16 is a metal oxide layer formed of a metal oxide, the oxygen vacancy is recovered by oxygen contained in the metal oxide layer when the oxygen vacancy occurs in the oxide semiconductor layer 13. Therefore, there is an advantage that oxygen vacancies in the oxide semiconductor layer 13 can be reduced.
- FIGS. 4 to 6 are process cross-sectional views for explaining the manufacturing method of the TFT substrate 100.
- FIG. 4 to 6 are process cross-sectional views for explaining the manufacturing method of the TFT substrate 100.
- a gate electrode 11 is formed on a substrate (for example, a glass substrate) 1.
- the gate wiring 2 (not shown in FIG. 4A) and the auxiliary capacitance wiring 5 are also formed at the same time.
- the gate electrode 11, the gate wiring 2 and the auxiliary capacitance wiring 5 can be formed by forming a metal film (conductor film) on the substrate 1 by sputtering or the like and then patterning the metal film by photolithography. .
- a Ti / Al / Ti film, an Al / Ti film, and a Cu / Ti film are used as the metal film (gate metal film) that becomes the gate electrode 11, the gate wiring 2, and the auxiliary capacitance wiring 5.
- the thicknesses of the gate electrode 11, the gate wiring 2 and the auxiliary capacitance wiring 5 are, for example, 100 nm or more and 500 nm or less.
- a gate insulating layer 12 is formed so as to cover the gate electrode 11 and the like.
- the gate insulating layer 12 can be formed using, for example, a CVD method.
- an oxide film such as a SiO 2 film is used as the gate insulating layer 12
- oxygen vacancies in the oxide semiconductor layer 13 can be reduced.
- the same advantage can be obtained when stacking is performed in such an order that the oxide film is in contact with the oxide semiconductor layer 13.
- the thickness of the gate insulating layer 12 is, for example, not less than 200 nm and not more than 500 nm.
- an oxide semiconductor layer 13 is formed on the gate insulating layer 12.
- the oxide semiconductor layer 13 is typically formed from an amorphous oxide.
- Examples of the material of the oxide semiconductor layer 13 include a Zn—O based semiconductor (ZnO), an In—Ga—Zn—O based semiconductor (IGZO), an In—Zn—O based semiconductor (IZO), and a Zn—Ti—O.
- ZTO system semiconductor
- the oxide semiconductor layer 13 can be formed as follows. First, an IGZO film having a thickness of 30 nm to 300 nm, for example, is formed on the gate insulating layer 12 by sputtering. Next, a photoresist layer covering a predetermined region of the IGZO film is formed by photolithography. Subsequently, the portion of the IGZO film that is not covered with the photoresist layer is removed by wet etching. Thereafter, the photoresist layer is peeled off. In this way, an island-shaped oxide semiconductor layer 13 is obtained.
- a source electrode 14 and a drain electrode 15 that are electrically connected to the oxide semiconductor layer 13 are provided, and then a metal compound positioned between the source electrode 14 and the drain electrode 15 is provided.
- Layer 16 is formed.
- a metal film (source metal film) 20 is formed so as to cover the oxide semiconductor layer 13.
- the metal film 20 is deposited by sputtering, for example.
- a Ti / Al / Ti film, an Al / Ti film, a Cu / Ti film, an Al film, a Cu film, and a Mo film are used as the metal film 20, for example, a Ti / Al / Ti film, an Al / Ti film, a Cu / Ti film, an Al film, a Cu film, and a Mo film are used.
- the thickness of the metal film 20 is, for example, not less than 100 nm and not more than 500 nm.
- the source electrode 14 and the drain electrode 15 are formed by patterning the metal film 20. At this time, the source wiring 3 is also formed. The patterning in this step is performed so that a portion of the metal film 20 located on the region to be the channel region 13c of the oxide semiconductor layer 13 remains as a conductor film thinner than the source electrode 14 and the drain electrode 15. Executed.
- a photoresist layer 21 covering a part of the metal film 20 is formed.
- the photoresist layer 21 includes a first portion 21a that overlaps a region that becomes the source region 13s and the drain region 13d of the oxide semiconductor layer 13, and a second portion that overlaps a region that becomes the channel region 13c of the oxide semiconductor layer 13. 21b.
- the second portion 21b is thinner than the first portion 21a. That is, the photoresist layer 21 has a distribution in its thickness.
- Such a photoresist layer 21 can be formed by performing an exposure process using a multi-tone mask. By performing multi-tone exposure using the multi-tone mask, the intermediately exposed region becomes the second portion 21b.
- a gray-tone mask or a half-tone mask can be used as the multi-tone mask.
- the gray tone mask is formed with a slit below the resolution of the exposure machine, and intermediate exposure is realized by blocking a part of the light by the slit.
- intermediate exposure is realized by using a semi-transmissive film.
- the source electrode 14 and the drain electrode 15 are formed by etching (for example, dry etching) the metal film 20 using the photoresist layer 21 as a mask.
- the portion of the metal film 20 covered with the second portion 21b (thinner than the other portion) of the photoresist layer 21 is light-etched, so that the channel region of the oxide semiconductor layer 13 A conductor film 20 ′ thinner than the source electrode 14 and the drain electrode 15 remains on 13c.
- the thickness of the conductor film 20 ' is not less than 1 nm and not more than 50 nm.
- a metal compound layer 16 located between the source electrode 14 and the drain electrode 15 is formed by chemically reacting the conductor film 20 '.
- a metal oxide layer is formed as the metal compound layer 16 by oxidizing the conductor film 20 ′.
- the metal film (source metal film) 20 is an Al film, a Cu film, or a Mo film
- the metal compound layer 16 becomes an aluminum oxide layer, a copper (II) oxide layer, and a molybdenum oxide layer, respectively.
- the metal film 20 is a laminated film based on a Ti layer such as a Ti / Al / Ti film, an Al / Ti film, or a Cu / Ti film, and the conductor film 20 ′ is a Ti film ( In other words, when etching is performed (only the base layer remains as the conductor film 20 ′), the metal compound layer 16 becomes a titanium oxide layer.
- the metal compound layer 16 is made of the same metal element as the metal element (one or more kinds) contained in the source electrode 14 and the drain electrode 15. Formed from compounds.
- the metal compound layer 16 is made of the same metal element as a part of the plurality of types of metal elements included in the source electrode 14 and the drain electrode 15. It may be formed from a compound.
- Various known methods can be used as the oxidation method. For example, oxygen gas, nitrogen gas, or laughing gas plasma may be used, hydrogen peroxide water may be used, or an anodic oxidation method may be used.
- the conductor film 20 ′ is oxidized to form a metal oxide layer as the metal compound layer 16.
- the metal compound layer 16 may be any compound as long as it is an insulator or a semiconductor. It may be formed from. In this way, the thin film transistor 10 is obtained.
- the first interlayer insulating layer 6 and the second interlayer insulating layer 7 are formed in this order so as to cover the thin film transistor 10.
- the first interlayer insulating layer 6 is, for example, a SiO 2 film, a SiN x film, or a spin-on-glass (SOG) film.
- the second interlayer insulating layer 7 is, for example, an acrylate-based photosensitive resin film.
- an opening 8 for exposing the surface of the drain electrode 15 is formed in the first interlayer insulating layer 6 and the second interlayer insulating layer 7, an opening 8 for exposing the surface of the drain electrode 15 is formed.
- the three layers of the metal compound layer 16, the first interlayer insulating layer 6, and the second interlayer insulating layer 7 function as a protective layer for protecting the thin film transistor 10, but the three layers are not necessarily used as the protective layer. There is no need to provide it.
- the thin film transistor 10 can be protected only by the metal compound layer 16.
- the pixel electrode 4 is formed so as to be in contact with the exposed surface of the drain electrode 15.
- the pixel electrode 4 can be formed by depositing a conductor film on the second interlayer insulating layer 7 and in the opening 8 by sputtering and then patterning the conductor film by photolithography.
- a material of the pixel electrode 4 for example, ITO can be used. In this way, the TFT substrate 100 is completed.
- the oxide semiconductor is formed by the conductor film 20 ′ located on the channel region 13c. Since the layer 13 is protected, damage to the oxide semiconductor layer 13 is reduced.
- the conductor film 20 ′ is a part of the metal film (source metal film) 20 that becomes the source electrode 14 and the drain electrode 15, a new film is laminated in order to form the conductor film 20 ′. do not have to. Therefore, the manufacturing method of this embodiment has many advantages compared to the manufacturing method in the case of providing the channel protective film 30 as shown in FIG.
- an advantage that the throughput is improved is obtained as compared with the case where the channel protective film 30 (for example, SiO 2 film) is formed by the sputtering method, and the case where the channel protective film 30 is formed by the CVD method is obtained.
- the advantage is that no process is required.
- the number of masks used may be the same as that in the case of manufacturing a conventional channel etch structure (a structure without the channel protective film 30). For this reason, the manufacturing method of the present embodiment is simplified in comparison with the manufacturing method in the case where the channel protective film 30 is provided, so that the advantage of improving the throughput can be obtained also in this respect.
- wet etching can be used in the step of forming the source electrode 14 and the drain electrode 15. This is because the presence of the conductor film 20 ′ prevents the oxide semiconductor layer 13 from being directly immersed in the etching solution.
- the source metal film is a Cu / Ti film
- the Cu layer is wet etched and then the Ti layer is dry etched.
- the source metal film The Cu / Ti film as the (metal film) 20 can be wet etched together.
- the conductor film 20 ′ that protects the oxide semiconductor layer 13 is turned into a metal compound layer 16 that is an insulator layer or a semiconductor layer by a chemical reaction in a subsequent step (step shown in FIG. 5D).
- the step of patterning the metal film 20 is performed so that the conductor film 20 ′ is thinner than the source electrode 14 and the drain electrode 15. Therefore, it is easy to prevent the conductor portion from remaining when the metal compound layer 16 is formed.
- the thickness of the metal compound layer 16 is more preferably 1 nm or more and 5 nm or less for the reason described below.
- the metal film 20 to be the source electrode 14 and the drain electrode 15 is formed (step shown in FIG. 5A)
- a reduction reaction may occur in the oxide semiconductor layer 13 and metal may be deposited in the channel region 13c.
- Such a leak path due to metal causes variations in transistor characteristics.
- the oxide semiconductor layer 13 can also be oxidized in the step of oxidizing the conductor film 20 ′. In addition, it is possible to reduce a leak path caused by metal deposited in the channel region 13c. Therefore, variation in transistor characteristics can be reduced.
- the oxide semiconductor TFT (pixel TFT) 10 provided in each pixel as a switching element, but also a part or all of TFTs (circuit TFTs) for peripheral circuits such as drivers are TFTs. It may be formed on the substrate 100 (monolithic).
- the peripheral circuit is formed in a region (referred to as a “frame region”) other than a region including a plurality of pixels (referred to as a “display region”) on the TFT substrate.
- the oxide semiconductor TFT uses an oxide semiconductor layer having a high mobility (for example, 10 cm 2 / Vs or more) as an active layer. Therefore, the oxide semiconductor TFT can be used not only as a pixel TFT but also as a circuit TFT. Preferably used.
- a thin film transistor 10 having the structure shown in FIG. 3 (that is, having a metal compound layer 16) was produced. While the thickness of the metal compound layer 16 of the thin film transistor 10 of Example 1 is more than 5 nm and 50 nm or less, the thickness of the metal compound layer 16 of the thin film transistor 10 of Example 2 is 1 nm or more and 5 nm or less.
- the manufacturing method is as described with reference to FIG.
- a thin film transistor 10B having the structure shown in FIG. 15 was produced.
- the thin film transistor 10B is different from the thin film transistor 10 shown in FIG. 3 or the thin film transistor 10A shown in FIG. 14 in that neither the metal compound layer 16 nor the channel protective film 30 is provided.
- the thin film transistors 10 of Examples 1 and 2 and the thin film transistor 10B of the comparative example have the same configuration (material, thickness, size, etc. of each layer) except for the presence or absence of the metal compound layer 16.
- Vg-Id gate voltage-drain current
- the drain current was almost constant regardless of the magnitude of the gate voltage, and the transistor characteristics (on / off characteristics) were not obtained. This is because the oxide semiconductor layer 13 is damaged (more specifically, partly reduced) by halogen plasma or the like used when dry etching the source metal film, and excessive carriers are generated. (In other words, the resistance of the channel is reduced).
- the thin film transistors 10 of the first and second embodiments clear transistor characteristics (on / off characteristics) can be obtained, and the threshold voltage can be controlled within an appropriate range. Met. This is because when the source metal film 20 is dry-etched, the oxide semiconductor layer 13 is not directly exposed to the etching atmosphere, and generation of excessive carriers can be prevented.
- the Vg-Id characteristics varied. This is because when the metal film (source metal film) 20 is formed, a reduction reaction occurs in the oxide semiconductor layer 13, metal is deposited in the channel region 13 c, and a leak path is generated.
- FIG. 12 shows the structure of the TFT substrate 100 manufactured in this example.
- the drain electrode 15 extends to a position where it overlaps the auxiliary capacitance line 5, and the pixel electrode 4 is connected to the drain electrode 15 at a position where it overlaps the auxiliary capacity line 5.
- the drain electrode 15 does not extend to a position that overlaps the auxiliary capacitance line 5, and the pixel electrode 4 does not overlap the auxiliary capacitance line 5. It is connected to the.
- FIG. 13 shows the manufacturing method of this example and the conventional manufacturing method.
- a detailed flowchart of the conventional manufacturing method is shown in the center of FIG. 13, and a detailed flowchart of the manufacturing method of this example is shown on the right side of FIG. Further, on the left side of FIG. 13, there is shown a flowchart summarizing the conventional manufacturing method and the manufacturing method of this example (which does not strictly match the manufacturing method of this example as will be described later).
- FIG. 13 shows a Cu / Ti film as a gate metal film, a SiO 2 film as a gate insulating layer 12, an IGZO film as an oxide semiconductor layer 13, a Cu / Ti film as a source metal film (metal film) 20, and a first interlayer insulation.
- An example in which a SiO 2 film is used as the layer 6 and a photosensitive resin film is used as the second interlayer insulating layer 7 is shown.
- a Cu / Ti film is deposited on the substrate 1 as a gate metal film, and then a photoresist layer covering a part of the Cu / Ti film is formed. Subsequently, the Cu / Ti film is patterned by wet etching using the photoresist layer as a mask, and then the photoresist layer is peeled off. In this way, the gate electrode 11, the gate wiring, and the auxiliary capacitance wiring are formed.
- an SiO 2 film as the gate insulating layer 12 and an IGZO film as the oxide semiconductor film are deposited.
- an island-shaped oxide semiconductor layer 13 is formed by patterning the oxide semiconductor film. Specifically, first, a photoresist layer covering a part of the IGZO film is formed, then wet etching is performed using this photoresist layer as a mask, and then the photoresist layer is peeled off.
- a Cu / Ti film is deposited as a source metal film, and then a photoresist layer covering a part of the Cu / Ti film is formed. Subsequently, using this photoresist layer as a mask, the Cu layer is patterned by wet etching, the Ti layer is patterned by dry etching, and then the photoresist layer is peeled off. In this way, the source electrode 14, the drain electrode 15, and the source wiring are formed.
- a SiO 2 film is deposited as a first interlayer insulating layer, and a photosensitive resin film is deposited in this order as a second interlayer insulating layer. Subsequently, the photosensitive resin film is exposed and developed to thereby form a photosensitive resin film. An opening is formed in a part. Thereafter, an opening is also formed in the SiO 2 film by performing dry etching using the photosensitive resin film as a mask.
- an amorphous ITO film is deposited, and then a photoresist layer covering a part of the amorphous ITO film is formed.
- the amorphous ITO film is patterned by wet etching using this photoresist layer as a mask, and then the photoresist layer is peeled off. In this way, a pixel electrode is formed.
- a Cu / Ti film is deposited on the substrate 1 as a gate metal film, and then a photoresist layer covering a part of the Cu / Ti film is formed. Subsequently, the Cu / Ti film is patterned by wet etching using the photoresist layer as a mask, and then the photoresist layer is peeled off. In this way, the gate electrode 11, the gate wiring 2 and the auxiliary capacitance wiring 5 are formed.
- an SiO 2 film as the gate insulating layer 12 and an IGZO film as the oxide semiconductor film are deposited.
- a Cu / Ti film is deposited as the source metal film 20, and then a photoresist layer covering a part of the Cu / Ti film is formed.
- a photoresist layer covering a part of the Cu / Ti film is formed.
- multi-tone exposure using a multi-tone mask is performed.
- the Cu layer is patterned by wet etching and the Ti layer is patterned by dry etching, whereby the source electrode 14, the drain electrode 15, and the source wiring 3 are formed.
- a portion of the source metal film 20 located on the channel region 13c remains as a conductor film 20 'thinner than other portions.
- the island-shaped oxide semiconductor layer 13 is formed by patterning the IGZO film by wet etching (for example, using oxalic acid). Thereafter, oxidation treatment is performed to oxidize the conductor film 20 ′ on the channel region 13 c, thereby forming a titanium oxide layer as the metal compound layer 16.
- the oxide semiconductor layer 13 is also oxidized at this time. Subsequently, the photoresist layer is peeled off.
- a SiO 2 film is deposited as the first interlayer insulating layer 6 and a photosensitive resin film is deposited in this order as the second interlayer insulating layer 7, and then the photosensitive resin film is exposed and developed to perform photosensitive resin.
- An opening is formed in a part of the film. Thereafter, an opening is also formed in the SiO 2 film by performing dry etching using the photosensitive resin film as a mask.
- an amorphous ITO film is deposited, and then a photoresist layer covering a part of the amorphous ITO film is formed.
- the amorphous ITO film is patterned by wet etching using this photoresist layer as a mask, and then the photoresist layer is peeled off. In this way, the pixel electrode 4 is formed.
- a photomask is used in four steps (steps M1 'to M4' shown in FIG. 13), so that a total of four photomasks are necessary. That is, one less mask is required compared with the conventional manufacturing method.
- the tact time for forming the source / drain is increased by the wet etching and the oxidation treatment, but the oxide semiconductor film is patterned in an island shape prior to the deposition of the source metal film 20. Therefore, the overall throughput is improved.
- the TFT substrate 100 for a liquid crystal display device has been exemplified, but the present invention is also suitably used for an active matrix substrate for an organic EL display device and an active matrix substrate for an inorganic EL display device.
- the present invention relates to a circuit substrate such as an active matrix substrate, a liquid crystal display device, a display device such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device, an imaging device such as an image sensor device, an image input device, and a fingerprint.
- a circuit substrate such as an active matrix substrate, a liquid crystal display device, a display device such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device, an imaging device such as an image sensor device, an image input device, and a fingerprint.
- EL organic electroluminescence
- the present invention can be widely applied to an apparatus including a thin film transistor such as an electronic apparatus such as a reading apparatus. In particular, it can be suitably applied to large liquid crystal display devices and the like.
- Substrate 2 Gate wiring (scanning wiring) 3 Source wiring (signal wiring) 4 pixel electrode 5 auxiliary capacitance wiring 6 first interlayer insulating layer 7 second interlayer insulating layer 8 opening 10 thin film transistor (oxide semiconductor TFT) DESCRIPTION OF SYMBOLS 11 Gate electrode 12 Gate insulating layer 13 Oxide semiconductor layer 13s Source region 13d Drain region 13c Channel region 14 Source electrode 15 Drain electrode 16 Metal compound layer 20 Metal film (source metal film) 20 'Conductor film 21 Photoresist layer 21a First portion of photoresist layer 21b Second portion of photoresist layer 100 TFT substrate (active matrix substrate)
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Abstract
Description
本実施形態におけるTFT基板100の薄膜トランジスタ10および従来の構造を有する薄膜トランジスタ(いずれも酸化物半導体TFTである)を実際に作製し、そのトランジスタ特性を測定した結果を説明する。
本実施形態における製造方法を4枚マスクプロセスとして実行する例を説明する。比較のために、図15に示した構造を有する薄膜トランジスタ10Bを備えたTFT基板を製造する従来の方法も説明する。
2 ゲート配線(走査配線)
3 ソース配線(信号配線)
4 画素電極
5 補助容量配線
6 第1層間絶縁層
7 第2層間絶縁層
8 開口部
10 薄膜トランジスタ(酸化物半導体TFT)
11 ゲート電極
12 ゲート絶縁層
13 酸化物半導体層
13s ソース領域
13d ドレイン領域
13c チャネル領域
14 ソース電極
15 ドレイン電極
16 金属化合物層
20 金属膜(ソースメタル膜)
20’ 導電体膜
21 フォトレジスト層
21a フォトレジスト層の第1の部分
21b フォトレジスト層の第2の部分
100 TFT基板(アクティブマトリクス基板)
Claims (13)
- 基板と、
前記基板上に設けられたゲート電極と、
前記ゲート電極上に形成されたゲート絶縁層と、
前記ゲート絶縁層上に形成され、チャネル領域と、前記チャネル領域の両側にそれぞれ位置するソース領域およびドレイン領域とを有する酸化物半導体層と、
前記ソース領域に電気的に接続されたソース電極と、
前記ドレイン領域に電気的に接続されたドレイン電極と、
前記ソース電極および前記ドレイン電極の間に位置し、前記酸化物半導体層上に接して設けられた金属化合物層と、
を備え、
前記金属化合物層は、前記ソース電極および前記ドレイン電極に含まれる金属元素のうちの少なくとも1種と同じ金属元素の化合物から形成された絶縁体層または半導体層である半導体装置。 - 前記金属化合物層の厚さは、前記ソース電極および前記ドレイン電極の厚さよりも小さい請求項1に記載の半導体装置。
- 前記金属化合物層の厚さは、1nm以上50nm以下である請求項1または2に記載の半導体装置。
- 前記金属化合物層の厚さは、1nm以上5nm以下である請求項3に記載の半導体装置。
- 前記金属化合物層は、金属酸化物層である請求項1から4のいずれかに記載の半導体装置。
- 基板上にゲート電極を形成する工程(A)と、
前記ゲート電極を覆うようにゲート絶縁層を形成する工程(B)と、
前記ゲート絶縁層上に酸化物半導体層を形成する工程(C)と、
前記酸化物半導体層に電気的に接続されたソース電極およびドレイン電極を設ける工程(D)と、を包含する半導体装置の製造方法であって、
前記工程(D)は、前記酸化物半導体層を覆うように金属膜を形成する工程(D-1)と、
前記金属膜をパターニングすることによって前記ソース電極および前記ドレイン電極を形成する工程(D-2)と、を含み、
前記工程(D-2)におけるパターニングは、前記金属膜のうちの、前記酸化物半導体層のチャネル領域となる領域上に位置する部分が、前記ソース電極および前記ドレイン電極よりも薄い導電体膜として残存するように実行され、
前記導電体膜を化学反応させることにより、前記ソース電極および前記ドレイン電極の間に位置する金属化合物層を形成する工程(E)をさらに包含する半導体装置の製造方法。 - 前記工程(D-2)は、
前記金属膜の一部を覆うフォトレジスト層であって、前記酸化物半導体層のソース領域およびドレイン領域となる領域に重なる第1の部分を有するフォトレジスト層を形成する工程(D-2-1)と、
前記フォトレジスト層をマスクとして用いて前記金属膜をエッチングする工程(D-2-2)と、を含む請求項6に記載の半導体装置の製造方法。 - 前記工程(D-2-1)は、前記フォトレジスト層が、前記酸化物半導体層のチャネル領域となる領域に重なる第2の部分であって、前記第1の部分よりも薄い第2の部分を有するように実行される請求項7に記載の半導体装置の製造方法。
- 前記工程(D-2-1)は、多階調マスクを用いた露光工程を含む請求項8に記載の半導体装置の製造方法。
- 前記工程(E)において形成される前記金属化合物層は、絶縁体層または半導体層である請求項6から9のいずれかに記載の半導体装置の製造方法。
- 前記金属化合物層の厚さは、1nm以上50nm以下である請求項6から10に記載の半導体装置の製造方法。
- 前記金属化合物層の厚さは、1nm以上5nm以下である請求項11に記載の半導体装置の製造方法。
- 前記工程(E)において、前記導電体膜を酸化させることによって前記金属化合物層として金属酸化物層が形成される請求項6から12のいずれかに記載の半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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KR1020127026342A KR101280649B1 (ko) | 2010-03-11 | 2011-03-10 | 반도체 장치 및 그 제조 방법 |
CN201180013422.7A CN102812555B (zh) | 2010-03-11 | 2011-03-10 | 半导体装置及其制造方法 |
JP2012504516A JP5209146B2 (ja) | 2010-03-11 | 2011-03-10 | 半導体装置およびその製造方法 |
EP11753439A EP2546884A1 (en) | 2010-03-11 | 2011-03-10 | Semiconductor device and method for manufacturing the same |
US13/583,311 US20130037807A1 (en) | 2010-03-11 | 2011-03-10 | Semiconductor device and method for manufacturing the same |
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CN103247532A (zh) * | 2012-02-14 | 2013-08-14 | 群康科技(深圳)有限公司 | 薄膜晶体管及其制作方法及显示器 |
EP2709159A1 (en) * | 2012-09-17 | 2014-03-19 | Boe Technology Group Co. Ltd. | Fabricating method of thin film transistor, fabricating method of array substrate and display device |
JP2016146501A (ja) * | 2013-05-14 | 2016-08-12 | エルジー ディスプレイ カンパニー リミテッド | 酸化物薄膜トランジスタ及びその製造方法 |
JP2017037341A (ja) * | 2016-10-27 | 2017-02-16 | 株式会社半導体エネルギー研究所 | 表示装置 |
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- 2011-03-10 US US13/583,311 patent/US20130037807A1/en not_active Abandoned
- 2011-03-10 WO PCT/JP2011/055658 patent/WO2011111781A1/ja active Application Filing
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Also Published As
Publication number | Publication date |
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US20130037807A1 (en) | 2013-02-14 |
KR20130030255A (ko) | 2013-03-26 |
JPWO2011111781A1 (ja) | 2013-06-27 |
CN102812555A (zh) | 2012-12-05 |
KR101280649B1 (ko) | 2013-07-01 |
JP5209146B2 (ja) | 2013-06-12 |
EP2546884A1 (en) | 2013-01-16 |
CN102812555B (zh) | 2013-07-24 |
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