WO2015010606A1 - 绝缘栅双极晶体管及其制造方法 - Google Patents

绝缘栅双极晶体管及其制造方法 Download PDF

Info

Publication number
WO2015010606A1
WO2015010606A1 PCT/CN2014/082730 CN2014082730W WO2015010606A1 WO 2015010606 A1 WO2015010606 A1 WO 2015010606A1 CN 2014082730 W CN2014082730 W CN 2014082730W WO 2015010606 A1 WO2015010606 A1 WO 2015010606A1
Authority
WO
WIPO (PCT)
Prior art keywords
type
region
insulated gate
semiconductor layer
layer
Prior art date
Application number
PCT/CN2014/082730
Other languages
English (en)
French (fr)
Inventor
钟圣荣
邓小社
王根毅
周东飞
Original Assignee
无锡华润上华半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润上华半导体有限公司 filed Critical 无锡华润上华半导体有限公司
Priority to US14/902,517 priority Critical patent/US9954074B2/en
Publication of WO2015010606A1 publication Critical patent/WO2015010606A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Definitions

  • the present invention relates to the field of semiconductor design and manufacturing technology, and in particular to an insulated gate bipolar transistor (Insulated Gate) Bipolar Transistor, referred to as IGBT) and its manufacturing method.
  • IGBT Insulated Gate Bipolar Transistor
  • IGBT is made of BJT (Bipolar Junction Transistor) Composite fully-regulated voltage-driven power semiconductor device composed of MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor), combining high input impedance of MOSFET and low on-state voltage of BJT
  • MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • IGBT generally needs to solve the following technical problems: First, under high temperature conditions, the IGBT leakage current is too large or even increased continuously and cannot be stabilized. After the normal temperature is restored, the breakdown voltage is reduced or even a short circuit occurs (ie, the IGBT's withstand voltage reliability problem)
  • the second problem in order to improve the performance of the IGBT as much as possible, it is necessary to continuously reduce its on-resistance. For high-voltage IGBTs, it affects the forward voltage drop Vce(on). Mainly JFET (Junction Field-effect) Transistor, junction field effect transistor) area equivalent resistance RJ and drift area equivalent resistance RD, therefore, to minimize these two parts of resistance is an important consideration for high power IGBT design.
  • ⁇ Q is the effective movable charge and Q f is the surface charge of the substrate.
  • ⁇ is the effective movable charge and Q f is the surface charge of the substrate. The larger the ⁇ , the greater the influence of the movable charge, and the worse the device withstand voltage reliability, and vice versa.
  • the technical method for solving this problem mainly starts from two aspects: on the one hand, minimizing the factors that introduce the movable charge in the chip manufacturing process and the packaging process, such as using special surface passivation technology or packaging with high reliability synthetic resin, Reducing the introduction of external charges and water vapor and other contaminants, which has a significant effect on reducing leakage current of devices at high temperatures, but this method requires high packaging technology and high process cost; on the other hand, special design structure is used to strengthen the chip. It shields the movable charge by itself, thereby improving the leakage performance of the device under high temperature and high stress conditions.
  • a SIPS (Semi-Insulating Polycrystalline Silicon) structure is used, which is connected to the main junction by one end of the semi-insulating film resistor and connected at one end.
  • an electric field will be generated at both ends of the semi-insulating resistor, and the electric field can shield the influence of the movable electric charge on the electric field of the terminal surface, thereby improving the breakdown performance of the device after testing under high temperature and high pressure conditions.
  • the semi-insulating film is generally formed by doping oxygen or nitrogen to polysilicon, and the resistivity is required to be between 10 7 and 10 10 .
  • the structure of the SIPOS is complicated, and the film resistance must be precisely controlled according to the design;
  • the semi-insulating resistor is directly connected between the high voltage and the ground. Under normal operating conditions, non-negligible power consumption will occur.
  • the thin film resistor has a high temperature coefficient and also has certain stability problems.
  • the prior art mainly starts from reducing the JFET region resistance RJ and the drift region resistance RD.
  • the JFET region resistance RJ there are currently three main methods: first, increase the carrier concentration at the JFET region, reduce the JFET resistance, but this method requires an increase in the process steps and the effect is not very obvious; second, the use of trench gate Instead of the planar gate structure, the JFET region in the planar gate is removed. This method directly removes the resistor of the JFET, effectively increasing the current density of the device, and is widely used in low voltage IGBTs, but this method is manufactured. The process is complicated, and the morphology and process control of the trench gate have a great influence on the reliability of the IGBT. It is not commonly used in high voltage IGBTs. Third, the carrier storage layer is added under the Pbody region to improve the carriers.
  • the drift region resistance RD it is mainly achieved by reducing the thickness of the drift region.
  • PT-IGBT Non-punch-through insulated gate bipolar transistor NPT-
  • FS-IGBT field-stop insulated gate bipolar transistor
  • the main difference between the three is the different substrate PN junction structure and different drift region thickness.
  • PT-IGBT and NPT-IGBT FS-IGBT has the thinnest thickness, and its forward conduction voltage drop is significantly reduced.
  • This structure has been widely used in IGBT products.
  • semiconductor wafer sizes continue to increase, the price of wafer devices, process complexity, and high fragmentation rates severely limit the performance of IGBTs (especially low voltage IGBTs).
  • An insulated gate bipolar transistor comprising: a first conductivity type semiconductor substrate having a first major surface and a second major surface, wherein the semiconductor substrate includes a cell region and is located outside the cell region a terminal protection region; a first semiconductor layer of a first conductivity type formed on a first main surface side of the semiconductor substrate, wherein a doping concentration of the first semiconductor layer is higher than a doping of the semiconductor substrate a high impurity concentration; an insulated gate transistor unit formed on a first main surface side of the first semiconductor layer in the original cell region, wherein the insulated gate transistor unit is formed with a first conductivity type when turned on The channel.
  • the method further includes: a protection terminal formed on a first main surface side of the first semiconductor layer in the termination protection region.
  • the method further includes: a second semiconductor layer of a second conductivity type formed on a second main surface side of the semiconductor substrate; and a first semiconductor layer formed with the insulated gate transistor unit a first main electrode formed on the first main surface; a second main electrode formed on the second semiconductor layer.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the insulated gate transistor unit is an N-channel MOSFET unit
  • the substrate is an N-type semiconductor substrate
  • the first semiconductor layer is an N+ type semiconductor layer
  • the second semiconductor layer is a P+ type collector layer
  • the first main electrode is an emitter
  • the second main The electrode is a collector.
  • the N-channel MOSFET cell includes: a selectively formed P-type base region from a first main face of the N+ type semiconductor layer in the cell region; a surface of the base region having a selectively formed N+ active region in the P-type base region; a P+ active region formed from a surface of the P-type base region inside the N+ active region toward the P-type base region; a first main surface of the edge portion of the P-type base region and a gate oxide layer formed on the first main surface of the N+ type semiconductor layer in the original cell region where the P-type base region is not formed; a polysilicon gate electrode formed on an upper surface of the layer; a dielectric layer covering the exposed surface of the gate oxide layer and the polysilicon gate electrode; wherein a first main electrode is formed on an outer side of the dielectric layer and is adjacent to the N+ active region The P+ active area is electrically contacted.
  • the protection terminal includes a P-type field limiting ring region formed on a first main surface side of the first semiconductor layer in the terminal protection region and located above the P-type field limiting ring region a metal field plate in electrical contact with the P-type field limiting ring region.
  • a method of fabricating an insulated gate bipolar transistor comprising: preparing a semiconductor substrate of a first conductivity type having a first major surface and a second major surface, wherein the semiconductor substrate includes a cell region and is located Terminal protection area outside the original cell area;
  • first semiconductor layer of a first conductivity type on a first major surface side of the semiconductor substrate, wherein a doping concentration of the first semiconductor layer is higher than a doping concentration of the semiconductor substrate;
  • the first main surface side of the first semiconductor layer of the region forms an insulated gate type transistor cell, wherein when the insulated gate transistor unit is turned on, it is formed with a channel of a first conductivity type.
  • the method further includes forming a protection terminal on a first major surface side of the first semiconductor layer in the termination protection region.
  • the method further includes: forming a first main electrode on a first main surface of the first semiconductor layer on which the insulated gate transistor unit is formed; from a second main surface of the semiconductor substrate Thinning the semiconductor substrate after the formation of the insulated gate transistor unit; forming a second semiconductor layer of a second conductivity type in the second main surface of the thinned semiconductor substrate; in the second A second main electrode that is in electrical contact with the second semiconductor layer is formed on the semiconductor layer.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the insulated gate transistor unit is an N-channel MOSFET unit
  • the substrate is an N-type semiconductor substrate
  • the first semiconductor layer is an N+ type semiconductor layer
  • the second semiconductor layer is a P+ type collector layer
  • the first main electrode is an emitter
  • the second main The electrode is a collector.
  • the process of forming the N+ type semiconductor layer includes: forming a pre-oxygen layer on a first main surface of the N-type semiconductor substrate; and transmitting the pre-oxygen layer in the N-
  • the first main surface side of the type semiconductor substrate is subjected to N-type impurity implantation to form an N+ layer; and the high temperature push well forms the N+ type semiconductor layer.
  • the pre-oxygen layer has a thickness of 1000 ⁇ to 3000 ⁇
  • the N-type impurity has an implantation dose of 2e11 to 1e13 cm -2 and an energy of 60 KEV to 120 KEV.
  • the protection terminal includes a P-type field limiting ring region formed on a first main surface side of the first semiconductor layer in the terminal protection region and located above the P-type field limiting ring region a metal field plate electrically contacting the P-type field limiting ring region
  • the N-channel MOSFET unit comprising: selectively formed from a first main surface of the N+ type semiconductor layer in the cell region a P-type base region; a selectively formed N+ active region from the surface of the P-type base region to the P-type base region; from the surface of the P-type base region inside the N+ active region to the P-type base region a P+ active region formed; a gate formed from a first main surface of an edge portion of the P-type base region and a first main surface of the N+ type semiconductor layer in the original cell region where a P-type base region is not formed a polar oxide layer; a polysilicon gate electrode formed on an upper surface of the gate oxide layer; a dielectric layer covering the exposed surface of the gate oxide
  • the first semiconductor layer of the first conductivity type is formed on the first main surface side of the semiconductor substrate of the first conductivity type, and the first semiconductor
  • the doping concentration in the layer is higher than the doping concentration in the semiconductor substrate; the insulated gate transistor unit and the protective terminal are formed on the first main surface side of the first semiconductor layer.
  • the first semiconductor layer acts as a carrier storage layer in the cell region, so that the forward voltage drop of the insulated gate bipolar transistor in the present invention can be reduced; at the same time, the impurity concentration on the surface of the protection terminal is improved, and the concentration is lowered.
  • the influence of the movable charge on protecting the electric field of the surface of the terminal thereby improving the withstand voltage reliability of the insulated gate bipolar transistor in the present invention.
  • FIG. 1 is a longitudinal cross-sectional view showing a portion of an insulated gate bipolar transistor in one embodiment
  • FIG. 2 to 12 are longitudinal cross-sectional views showing respective manufacturing processes of the insulated gate bipolar transistor of FIG. 1 in one embodiment
  • FIG. 13 is a flow chart of a method of fabricating the insulated gate bipolar transistor of FIG. 1 in one embodiment.
  • one embodiment or “an embodiment” as used herein refers to a particular feature, structure, or characteristic that can be included in at least one implementation of the invention.
  • the insulated gate bipolar transistor includes: a first conductive type semiconductor substrate 1 having a first main surface 1S1 and a second main surface 1S2, wherein the semiconductor substrate 1 includes a cell region 2, located in the original a terminal protection region 4 outside the cell region 2 and a transition region 3 between the cell region 2 and the terminal protection region 4; a first conductive layer formed on the first main surface 1S1 side of the semiconductor substrate 1 a first semiconductor layer 5 of a type, wherein a doping concentration of the first semiconductor layer 5 is higher than a doping concentration of the semiconductor substrate 1; and a first semiconductor layer 5 formed in the cell region 2
  • the insulated gate bipolar transistor further includes: a first main electrode 12 formed on a first main surface 1S1 of the first semiconductor layer 5 on which the insulated gate transistor unit is formed; and a second semiconductor layer 6 The second main electrode 13 is formed thereon.
  • the structure of the insulated gate bipolar transistor of the present invention will be specifically described below with reference to FIG. 1 taking the first conductivity type as N-type and the second conductivity type as P-type as an example.
  • the first conductivity type semiconductor substrate 1 is an N-type semiconductor substrate (also referred to as an N-layer).
  • the first semiconductor layer 5 of the first conductivity type formed on the first main surface 1S1 side of the semiconductor substrate 1 is an N+ type semiconductor layer (or referred to as a FaceN+ layer).
  • the protection terminal is a field limiting ring plus field plate terminal structure, and includes: selectively performing P-type impurity doping to form the P-type impurity from the first main surface 1S1 of the terminal protection area 4 to the N+-type semiconductor layer 5
  • a P-type field limiting ring region 7 also referred to as a field limiting ring structure
  • the protection terminal further includes a field formed from a first main surface of the edge portion of the P-type field limiting ring region 7 and a first main surface of the terminal protection region 4 where the P-type field limiting ring region 7 is not formed.
  • the oxide layer 210 and the dielectric layer 400 formed on the upper surface of the field oxide layer 210. It is easy to think that the protection terminal can also be other protection terminal structures in the prior art, such as a field limiting ring termination structure.
  • the insulated gate transistor unit is a MOSFET having a channel of a first conductivity type (here, an N-type channel).
  • the N-channel MOSFET is DMOS (Double-diffused Metal Oxide a semiconductor, double-diffused MOS) MOSFET comprising: a P-body region formed from a first main surface 1S1 of the cell region 2 to a selected diffused P-type impurity in the N+ type semiconductor layer 5 ( Or referred to as a P-base region 8; an N+ active region (or referred to as an N+ emitter region) formed from the surface of the P-body region 8 to the P-body region 8 with selective diffusion of a high concentration of N-type impurities.
  • DMOS Double-diffused Metal Oxide a semiconductor, double-diffused MOS MOSFET comprising: a P-body region formed from a first main surface 1S1 of the cell region 2 to a selected diffused P-type impurity in the N+ type semiconductor layer
  • a P+ active region 10 formed by diffusing a high concentration of P-type impurities from the surface of the P-body region 8 inside the N+ active region 9 into the P-body region 8; from the P-body region 8 a first main surface of the edge portion and a gate oxide layer (abbreviated as gate oxide layer) 220 formed on the first main surface of the original cell region 2 where the P-body region 8 is not formed; on the gate oxide layer 220
  • the second semiconductor layer 6 of the second conductivity type is a P+ layer formed by injecting a P-type impurity into the N-type semiconductor substrate 1 from the second main surface 1S2. (Or called P+ collector layer).
  • the portion of the N-type semiconductor substrate 1 located between the P+ collector layer 6 and the N+ type semiconductor layer 5 is an N-type drift region 11.
  • the insulated gate bipolar transistor of FIG. 1 further includes: a first main electrode (in this embodiment, an emitter) 12 formed on the first main surface 1S1 of the cell region 2 to cover the dielectric layer 400, the first The main electrode 12 is in electrical contact with the N+ active region 9 and the P+ active region 10; a second main electrode (collector in the present embodiment) 13 formed on the second semiconductor layer 6, the first The two main electrodes 13 are in electrical contact with the second semiconductor layer 6; and the first passivation layer covering the first main electrode 8, the field oxide layer 400 and the metal field plate 500 for protecting the surface of the chip from external ions 600 and a second passivation layer 700.
  • a first main electrode in this embodiment, an emitter
  • the insulated gate bipolar transistor of the present invention shown in FIG. 1 forms an N+ type semiconductor layer 5 on the first main surface 1S1 side of the N-type semiconductor substrate 1, due to the N+ type semiconductor layer 5
  • the doping concentration is higher than the doping concentration of the semiconductor substrate 1, and the insulated gate type transistor cell is formed based on the N+ type semiconductor layer 5, and therefore, the N+ type semiconductor layer 5 functions as a carrier storage layer in the cell region 2.
  • the insulated gate bipolar transistor of FIG. 1 is forward-conducting, holes injected from the P+ collector layer 6 of the second main surface 1S2 into the N-type drift region 11 are formed by the N+ semiconductor layer 5 in the middle of diffusion thereof.
  • the barrier of the barrier causes the minority carrier holes to accumulate near the interface of the P-body region 8 and the N+ type semiconductor layer 5, and according to the principle of electrical neutrality, the carrier concentration in the region is greatly increased, thereby reducing the present The forward voltage drop of an insulated gate bipolar transistor in the invention.
  • the impurity concentration of the surface of the protective terminal can be increased (ie, increased)
  • the charge Q f of the surface of the protection terminal is large, and the formula (1) of the background art is referred to, thereby reducing the influence of the movable charge on the electric field on the surface of the protection terminal, thereby improving the withstand voltage reliability of the device.
  • the insulated gate transistor cell is a MOSFET of a DMOS structure, and in other embodiments, it may also be a trench MOSFET or a V-shaped MOSFET.
  • FIG. 13 is a flow chart of a method 800 of fabricating the insulated gate bipolar transistor of FIG. 1 in one embodiment.
  • the method of manufacture 800 includes the following operations.
  • Step 810 preparing a semiconductor substrate 1 of a first conductivity type having a first main surface 1S1 and a second main surface 1S2, wherein the semiconductor substrate 1 includes a cell region 2 and is located outside the cell region 2 Terminal protection zone 4.
  • Step 820 forming a first semiconductor layer 5 of a first conductivity type on a side of the first main surface 1S1 of the semiconductor substrate 1, wherein a doping concentration of the first semiconductor layer 5 is higher than a doping of the semiconductor substrate 1. Miscellaneous concentration.
  • Step 830 forming a protection terminal on the first main surface 1S1 side of the first semiconductor layer 5 in the terminal protection region 4, and forming a first main surface 1S1 side of the first semiconductor layer 5 in the original cell region 2 Insulated gate transistor unit.
  • Step 840 forming a first main electrode 12 on the first main surface 1S1 of the cell region 2 forming the insulated gate transistor unit;
  • Step 850 thinning the semiconductor substrate 1 after the formation of the insulated gate transistor unit from the second main surface of the semiconductor substrate 1 to meet a predetermined thickness requirement.
  • Step 860 forming a second semiconductor layer 6 of the second conductivity type into the semiconductor substrate 1 from the second main surface 1S2 of the thinned semiconductor substrate 1.
  • Step 870 forming a second main electrode 13 in electrical contact with the second semiconductor layer 6 on the second main surface 1S2 of the semiconductor substrate 1 after the second semiconductor layer 6 is formed.
  • the manufacturing method includes the following steps:
  • Step one preparing an N-type semiconductor substrate 1 having a first main surface 1S1 and a second main surface 1S2.
  • Step 2 as shown in FIG. 2, a pre-oxygen layer 200 is formed on the first main surface 1S1 of the N-type semiconductor substrate 1, and the pre-oxygen layer may have a thickness of 1000 ⁇ to 3000 ⁇ .
  • Step 3 N-type impurity implantation is performed on the first main surface side of the N-type semiconductor substrate 1 through the pre-oxygen layer 200 to form an N+ layer 130.
  • the implantation dose of the N-type impurity may be 2e11 ⁇ 1e13cm -2 , and the energy may be 60KEV ⁇ 120KEV.
  • Step four as shown in FIG. 3, a high temperature push well forms the N+ type semiconductor layer 5, and then a field oxide layer 210 is formed on the pre-oxygen layer 200.
  • the N+ type conductor layer 5 can be formed by pushing the well in an aerobic environment at 1100 ° C to 1200 ° C while growing 6000. ⁇ ⁇ 20000 ⁇ field oxygen layer 210.
  • the formed N+ type conductor layer 5 may have a sheet resistance of 100 ohm/sp to 6000 ohm/sp.
  • the second to fourth steps are the formation process of the N+ type conductor layer 5.
  • Step 5 selectively etching the field oxide layer 210 to etch the implantation window of the P-type field limiting ring region 7, and self-etching the implantation window to the N+ type semiconductor P-type diffusion is performed in layer 5 to form P-type region 140.
  • a Ring (lithographic) lithography plate can be used to etch the injection window of the P-type field limiting ring region 7 on the field oxide layer 210 through steps of coating, exposing, wet etching, and de-glue.
  • the high temperature push trap forms a P-type field limiting ring region 7.
  • the P-type field limiting ring region 7 is formed by pushing the trap in an aerobic environment at 1100 ° C to 1200 ° C.
  • the formed P-type field limiting ring region 7 may have a sheet resistance of 10 ohm/sp to 1200 ohm/sp.
  • Step 7 as shown in FIG. 6, a gate oxide layer 220 is formed on the first main surface 1S1 of the cell region 2, and polysilicon is deposited on the gate oxide layer 220 and the field oxide layer 210.
  • Gate layer 300 Specifically, an Active (active area) lithography plate is used to thermally grow a layer 800 on the first main surface 1S1 of the cell region 2 through steps of coating, exposure, wet etching, and stripping. ⁇ ⁇ 1200 ⁇ gate oxide layer 220, depositing 6000 ⁇ ⁇ 12000 on the upper surface of the gate oxide layer 220 and the field oxide layer 210 ⁇ polysilicon and doped to form a polysilicon gate layer 300.
  • Step 8 as shown in FIG. 7, the polysilicon gate layer 300 of the upper surface of the field oxide layer 210 is removed, and the implantation window of the P-body region 8 is selectively etched on the polysilicon gate layer 300.
  • the implantation window is etched from the etched P-type diffusion into the N+ type conductor layer 5 to form a P-type region 150.
  • a poly (polysilicon) lithography plate is used to selectively etch the injection window of the P-body region 8 on the polysilicon gate layer 300 through steps of coating, exposure, dry etching, and de-glue.
  • P-type impurities having a dose of 1e13 to 1e15 cm -2 and an energy of 60 KEV to 120 KEV are implanted from the window to form a P-type region 150 in the N + -type semiconductor layer 5.
  • Step IX as shown in FIG. 8, the high temperature push-bonding forms the P-body region 8, and the N+ active region is formed by selectively diffusing a high concentration of N-type impurities from the surface of the P-body region 8 into the P-body region 8. (or N+ emitter) 9.
  • the Pbody region 8 is formed by the 1100 ° C to 1200 ° CN 2 (nitrogen) environment, and the selected implant dose from the surface of the P-body region 8 to the P-body region 8 is 5e14. ⁇ 1e16cm -2 , N-type impurity with energy of 60KEV ⁇ 120KEV, activated by high temperature annealing at 800 °C ⁇ 1000 °C to form N+ active region (or N+ emitter)9.
  • Step 10 as shown in FIG. 9, a P+ active region 10 is formed in the P-body region 8 from the surface of the P-body region 8 inside the N+ active region 9, and in the N+ type semiconductor layer 5
  • a dielectric layer 400 is formed on a main surface 1S1. Specifically, an oxide layer is deposited, and Spacer etching and silicon etching are performed on the entire device, boron implantation is performed, P+ active region 10 is formed, and BPSG (borophosphosilicate glass, boro-phospho-silicate-) is deposited at 8000A to 16000A. Glass, BPSG), reflowed at 850 ° C to 950 ° C to form a dielectric layer 400.
  • BPSG borophosphosilicate glass, boro-phospho-silicate-
  • Step 11 As shown in FIG. 10, a contact hole shorting the N+ active region 9 and the P+ active region 10 is etched in the original cell region 2 by photolithography and etching, in the terminal protection region 4 Etching a contact hole connecting the P-type field limiting ring region 7; forming a metal layer covering the dielectric layer 400 on the first main surface of the N+ type semiconductor layer 5; selectively etching by photolithography and etching Departing to form an overlying dielectric layer 400 in the cell region 2 and electrically connecting the N+ active region 9 and the P+ active region 10, and forming a partial covering dielectric layer 400 in the terminal protection region 4 and electrically The metal field plate 500 of the P-type field limiting ring region 7 is connected.
  • a Cont (contact hole) lithography plate is used to sequentially perform hole etching, sputtering metal, and etching a metal layer using a Metal lithography plate to form a metal emitter 12 and a metal field plate 500.
  • the fifth to eleventh steps are processes of forming the protection terminal, the insulated gate transistor unit, and the emitter 12.
  • Step 12 as shown in FIG. 11, the passivation layers 600 and 700 are sequentially deposited on the metal emitter 12 and the metal field plate 500, and the PAD (pad) for extracting the gate electrode 300 and the emitter 12 is left. Area (not shown). Specifically, the lithographic plates of PAD1 (pad 1) and PAD2 (pad 2) are successively subjected to steps of coating, exposing, degumming, annealing and curing at 380 ° C to 450 ° C to form passivation layers 600 and 700. Step 12 may also be specifically implemented by other means, for example, by chemical vapor deposition, a passivation layer 600 for protecting the surface of the chip from external ions is sequentially deposited on the metal emitter 12 and the metal field plate 500.
  • a photosensitive Polyimide having a thickness of 4 um to 18 um can be used as the passivation layer of the device.
  • Step 13 the thickness of the N-type semiconductor substrate 1 is thinned by the back surface thinning process, and is formed on the second main surface 1S2 side of the thinned N-type semiconductor substrate 1.
  • the N-type semiconductor substrate 1 can be back-thinned and thinned to a desired thickness, and the second main surface 1S2 of the self-thinned N-type semiconductor substrate 1 is implanted at a dose of 5e12 to 1e15 cm . 2
  • the NPT type insulated gate bipolar transistor of Fig. 1 can be manufactured.
  • a person skilled in the art can also make various changes or substitutions according to the spirit of the above manufacturing method.
  • the high temperature push in step three and the high temperature push in step five can be combined and the high temperature push process in step five.
  • Steps 5 to 11 are processes of generating an insulated gate type transistor unit, a protection terminal, and an emitter 12 on the first main surface 1S1 side of the N + -type semiconductor layer 5, if the insulated gate type transistor is another type of MOSFET, or
  • the protection terminal is a P-type field limiting ring and other protection terminal structures, and the manufacturing steps also need to be changed accordingly.
  • the first main surface 1S1 side of the first conductive type semiconductor substrate 1 is formed by adding one ion implantation.
  • a first semiconductor layer 5 of a conductivity type, and a doping concentration in the first semiconductor layer 5 is higher than a doping concentration in the semiconductor substrate 1.
  • the first semiconductor layer 5 acts as a carrier storage layer in the cell region 3, so that the forward voltage drop of the insulated gate bipolar transistor in the present invention can be reduced; and the impurity concentration on the surface of the protective terminal is improved, The influence of the movable charge on the electric field on the surface of the protection terminal is lowered, thereby improving the withstand voltage reliability of the insulated gate bipolar transistor in the present invention.
  • the method can realize the carrier storage layer structure without adding a lithography plate, and has the advantages of low cost and precise control.
  • the first conductivity type is N-type
  • the second conductivity type is P-type.
  • the first conductivity type may be P-type.
  • the second conductivity type is N-type, in which case a P-type semiconductor substrate 1 is used, the first semiconductor layer 5 is a P+ semiconductor layer, the insulated gate transistor is a P-channel MOSFET unit, and the second main electrode 13 is an emitter, and the first main electrode 12 is a collector.
  • the specific structure and principle are similar to those of the above-mentioned insulated gate bipolar transistor, and are not described here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种绝缘栅双极晶体管及其制造方法，其中绝缘栅双极晶体管包括：具有第一主面（1S1）和第二主面（1S2）的第一导电类型半导体衬底（1），其中，半导体衬底（1）包括原胞区（2）和位于原胞区外侧的终端保护区（4）；形成于半导体衬底（1）的第一主面侧的第一导电类型的第一半导体层（5），其中第一半导体层（5）的掺杂浓度高于半导体衬底（1）的掺杂浓度；形成于原胞区内的第一半导体层（5）的第一主面侧的绝缘栅型晶体管单元，其中，绝缘栅型晶体管单元导通时，其形成有第一导电类型的沟道。与现有技术相比，其不仅可以提高绝缘栅双极晶体管的耐压可靠性，而且还可以降低绝缘栅双极晶体管的正向导通压降。

Description

绝缘栅双极晶体管及其制造方法
【技术领域】
本发明涉及半导体设计及制造技术领域，特别涉及一种绝缘栅双极晶体管（Insulated Gate Bipolar Transistor，简称IGBT）及其制造方法。
【背景技术】
IGBT是由BJT （Bipolar Junction Transistor，双极结型晶体管） 和MOSFET（Metal-Oxide-Semiconductor-Field-Effect-Transistor，金属氧化物半导体场效应晶体管）组成的复合全控型电压驱动式功率半导体器件，兼有MOSFET的高输入阻抗和BJT的低导通压降两方面的优点，具有工作频率高，控制电路简单，电流密度高，通态压低等特点，广泛应用于功率控制领域。
IGBT普遍需要解决以下技术问题：第一，在高温条件下，IGBT漏电流偏大甚至出现持续增大不能稳定，恢复常温后击穿电压降低甚至出现短路的现象（即IGBT的耐压可靠性问题）；第二个问题，为了尽可能的提高IGBT的性能，需要不断的降低其导通电阻，对于高压IGBT来说，影响正向导通压降Vce(on) 的主要是JFET(Junction Field-effect Transistor，结型场效应晶体管)区域等效电阻RJ和漂移区等效电阻RD，因此，尽量降低这两部分电阻是大功率IGBT设计的重要考虑因素。
针对第一个技术问题：
一般认为，该问题主要是由器件内部和外部引入的可动电荷引起的。实际工作中，可动电荷在外部应力条件下移动，将会改变原来稳定的表面电场，从而使的耐压发生改变，甚至出现漏电流增大的问题。为了定量表征外界电荷对终端表面电场的影响，定义影响因子：
α=ΔQ/(ΔQ+Qf) （1）
其中，ΔQ为有效可动电荷，Qf为衬底表面电荷。α越大表征可动电荷影响越大，器件耐压可靠性越差，反之亦然。
解决该问题的技术方法主要从两个方面出发：一方面，尽量减少芯片制造过程和封装过程引入可动电荷的因素，比如采用特殊的表面钝化技术或采用高可靠性合成树脂进行封装，以降低外部电荷及水汽等沾污的引入，这对降低高温下器件漏电流具有显著的效果，但是该方法对封装技术要求很高且工艺成本较高；另一方面，采用特殊设计结构以加强芯片本身对可动电荷的屏蔽作用，从而改善器件在高温高压应力条件下的漏电表现，比如，采用SIPOS（Semi-Insulating Polycrystalline silicon）结构，它是利用半绝缘薄膜电阻一端连接主结，一端连接截止环，在高压反偏条件下，半绝缘电阻两端将会产生电场，该电场能够屏蔽可动电荷对终端表面电场的影响，从而改善器件在高温高压条件下测试后的击穿表现。半绝缘薄膜一般是通过对多晶硅进行掺氧或氮形成的，电阻率要求在107~1010之间，因此，采用SIPOS结构，工艺过程复杂，薄膜电阻质量必须根据设计精确控制；该结构采用半绝缘电阻直接跨接在高压和地之间，正常工作条件下将会产生不可忽略的功耗；同时，薄膜电阻具有较高的温度系数，也存在一定的稳定性问题。
针对第二个技术问题：
为了降低器件正向导通压降，现有技术主要从降低JFET区电阻RJ和漂移区电阻RD出发。
针对JFET区域电阻RJ，目前主要有三类方法：第一、增加JFET区域处载流子浓度，降低JFET电阻，但这种方法需要增加工艺步骤且效果不是非常明显；第二、使用采用沟槽栅代替平面栅结构，将平面栅中的JFET区域去除，这种方法直接去除了JFET这部分电阻，有效地增大了器件的电流密度，在低压IGBT中得到了广泛地应用，但是这种方法制造工艺复杂，且沟槽栅的形貌及工艺控制对IGBT的可靠性具有很大的影响，在高压IGBT中并不常用；第三、在Pbody区域下增加载流子存储层，提高载流子浓度，降低正向导通压降，但这种方法需要增加工艺步骤且效果不是非常明显；第四、通过增加平面栅的尺寸来降低JFET电阻，这种方法会降低器件的电流密度和击穿电压，需要优化设计。
针对漂移区电阻RD，主要通过降低漂移区厚度来实现。迄今为止，主要有穿通型绝缘栅双极晶体管PT- IGBT、 非穿通型绝缘栅双极晶体管NPT- IGBT和场截止型绝缘栅双极晶体管FS-IGBT三种结构，三者之间的主要差异是不同的衬底PN结结构和不同的漂移区厚度。相对PT-IGBT和NPT-IGBT来讲，FS-IGBT具有最薄的厚度，其正向导通压降得到明显的下降，该结构在IGBT产品中得到了广泛的应用。然而，随着半导体晶圆尺寸的不断提高，薄片设备的价格、工艺复杂程度以及很高的碎片率严重的限制了IGBT（特别是低压IGBT）性能的不断提升。
因此，有必要提供一种改进的技术方案来克服上述问题。
【发明内容】
基于此，有必要提供一种绝缘栅双极晶体管及其制造方法，其不仅可以提高该绝缘栅双极晶体管的耐压可靠性，而且还可以降低该绝缘栅双极晶体管的正向导通压降。
一种绝缘栅双极晶体管，其包括：具有第一主面和第二主面的第一导电类型的半导体衬底，其中，所述半导体衬底包括原胞区和位于所述原胞区外侧的终端保护区；形成于所述半导体衬底的第一主面侧的第一导电类型的第一半导体层，其中，所述第一半导体层的掺杂浓度高于所述半导体衬底的掺杂浓度高；形成于所述原胞区内的第一半导体层的第一主面侧的绝缘栅型晶体管单元，其中，所述绝缘栅型晶体管单元导通时，其形成有第一导电类型的沟道。
在其中一个实施例中，其还包括：形成于所述终端保护区内的第一半导体层的第一主面侧的保护终端。
在其中一个实施例中，其还包括：在所述半导体衬底的第二主面侧形成的第二导电类型的第二半导体层；在形成有所述绝缘栅型晶体管单元的第一半导体层的第一主面上形成的第一主电极；在所述第二半导体层上形成的第二主电极。
在其中一个实施例中，所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型半导体衬底，所述第一半导体层为N+型半导体层，所述第二半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极。
在其中一个实施例中，所述N型沟道MOSFET单元包括：自所述原胞区内的N+型半导体层的第一主面向内有选择的形成的P型基区；自所述P型基区的表面向该P型基区内有选择的形成的N+有源区；自所述N+有源区内侧的P型基区表面向该P型基区内形成的P+有源区；自所述P型基区的边缘部分的第一主面和所述原胞区内的N+型半导体层的未形成P型基区的第一主面上形成的栅极氧化层；在栅极氧化层的上表面上形成的多晶硅栅电极；覆盖栅极氧化层和多晶硅栅电极露出表面的介质层；其中，第一主电极形成于所述介质层的外侧并与所述N+有源区和所述P+有源区电性接触。
在其中一个实施例中，所述保护终端包括形成于所述终端保护区内的第一半导体层的第一主面侧的P型场限环区以及位于所述P型场限环区上方并与所述P型场限环区电性接触的金属场板。
一种绝缘栅双极晶体管的制造方法，其包括：制备具有第一主面和第二主面的第一导电类型的半导体衬底，其中，所述半导体衬底包括原胞区和位于所述原胞区外侧的终端保护区；
在所述半导体衬底的第一主面侧形成第一导电类型的第一半导体层，其中，所述第一半导体层的掺杂浓度高于半导体衬底的掺杂浓度；在所述原胞区的第一半导体层的第一主面侧形成绝缘栅型晶体管单元，其中，所述绝缘栅型晶体管单元导通时，其形成有第一导电类型的沟道。
在其中一个实施例中，其还包括：在所述终端保护区内的第一半导体层的第一主面侧形成保护终端。
在其中一个实施例中，其还包括：在形成有所述绝缘栅型晶体管单元的第一半导体层的第一主面上形成第一主电极；从所述半导体衬底的第二主面起减薄该绝缘栅型晶体管单元形成后的半导体衬底；自减薄后的半导体衬底的第二主面向所述半导体衬底内形成第二导电类型的第二半导体层；在所述第二半导体层上形成与第二半导体层电性接触的第二主电极。
在其中一个实施例中，所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型半导体衬底，所述第一半导体层为N+型半导体层，所述第二半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极。
在其中一个实施例中，形成所述N+型半导体层的过程包括：在所述N-型半导体衬底的第一主面上形成预氧层；透过所述预氧层在所述N-型半导体衬底的第一主面侧进行N型杂质注入以形成N+层；和高温推阱形成所述N+型半导体层。
在其中一个实施例中，所述预氧层的厚度为1000Å~3000 Å，所述N型杂质的注入剂量2e11~1e13cm-2，能量为60KEV~120KEV。
在其中一个实施例中，所述保护终端包括形成于所述终端保护区内的第一半导体层的第一主面侧的P型场限环区以及位于所述P型场限环区上方并与所述P型场限环区电性接触的金属场板，所述N型沟道MOSFET单元包括：自所述原胞区内的N+型半导体层的第一主面向内有选择的形成的P型基区；自P型基区的表面向该P型基区内有选择的形成的N+有源区；自所述N+有源区内侧的P型基区表面向该P型基区内形成的P+有源区；自所述P型基区的边缘部分的第一主面和所述原胞区内的N+型半导体层的未形成P型基区的第一主面上形成的栅极氧化层；在栅极氧化层的上表面上形成的多晶硅栅电极；覆盖栅极氧化层和多晶硅栅电极露出表面的介质层；其中，第一主电极形成于所述介质层的外侧并与所述N+有源区和所述P+有源区电性接触。
与现有技术相比，上述绝缘栅双极晶体管及其制造方法，在第一导电类型的半导体衬底的第一主面侧形成第一导电类型的第一半导体层，且所述第一半导体层中的掺杂浓度高于所述半导体衬底中的掺杂浓度；绝缘栅型晶体管单元和保护终端形成于第一半导体层的第一主面侧。这样，所述第一半导体层在原胞区中充当载流子存储层，从而可以降低本发明中的绝缘栅双极晶体管的正向导通压降；同时提高了保护终端表面的杂质浓度，降低了可动电荷对保护终端表面电场的影响，从而提高本发明中的绝缘栅双极晶体管的耐压可靠性。
【附图说明】
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。其中：
图1为一个实施例中的绝缘栅双极晶体管的一部分的纵剖面图；
图2至图12为图1中的绝缘栅双极晶体管在一个具体实施例中的各个制造工序的纵剖面图；
图13为图1中的绝缘栅双极晶体管的制造方法在一个实施例中的流程图。
【具体实施方式】
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。
此处所称的“一个实施例”或“实施例”是指可包含于本发明至少一个实现方式中的特定特征、结构或特性。在本说明书中不同地方出现的“在一个实施例中”并非均指同一个实施例，也不是单独的或选择性的与其他实施例互相排斥的实施例。
请参考图1所示，其为一个实施例中的绝缘栅双极晶体管的一部分的纵剖面图。所述绝缘栅双极晶体管包括：具有第一主面1S1和第二主面1S2的第一导电类型的半导体衬底1，其中，所述半导体衬底1包括原胞区2、位于所述原胞区2外侧的终端保护区4以及位于所述原胞区2和所述终端保护区4之间的过渡区3；形成于所述半导体衬底1的第一主面1S1侧的第一导电类型的第一半导体层5，其中，所述第一半导体层5的掺杂浓度高于所述半导体衬底1的掺杂浓度；形成于所述原胞区2内的第一半导体层5的第一主面1S1侧的绝缘栅型晶体管单元，其中所述绝缘栅型晶体管单元导通时其形成有第一导电类型的沟道；形成于所述终端保护区4内的第一半导体层5的第一主面1S1侧的保护终端；在所述半导体衬底1的第二主面1S2侧形成的第二导电类型的第二半导体层6。
所述绝缘栅双极晶体管还包括：在形成有所述绝缘栅型晶体管单元的第一半导体层5的第一主面1S1上形成的第一主电极12；以及在所述第二半导体层6上形成的第二主电极13。
下面以所述第一导电类型为N型，所述第二导电类型为P型为例，结合图1对本发明中的绝缘栅双极晶体管的结构进行具体介绍。
在图1所示的实施例中，所述第一导电类型的半导体衬底1为N-型半导体衬底（也称为N-层）。形成于所述半导体衬底1的第一主面1S1侧的第一导电类型的第一半导体层5为N+型半导体层（或者称为FaceN+层）。所述保护终端为场限环加场板终端结构，其包括：自所述终端保护区4的第一主面1S1向所述N+型半导体层5内选择性的进行P型杂质掺杂以形成的P型场限环区7（或称为场限环结构）以及位于所述P型场限环区上方并与所述P型场限环区电性接触的金属场板500。所述保护终端还包括自所述P型场限环区7的边缘部分的第一主面和所述终端保护区4的未形成P型场限环区7的第一主面上形成的场氧化层210和在所述场氧化层210上表面形成的介质层400。易于思及的是，所述保护终端也可以为现有技术中的其他保护终端结构，比如，场限环终端结构。
所述绝缘栅型晶体管单元为具有第一导电类型的沟道（在此为N型沟道）的MOSFET。具体的说，该N型沟道的MOSFET为DMOS（Double-diffused Metal Oxide Semiconductor，双扩散MOS）结构的MOSFET，其包括：自所述原胞区2的第一主面1S1向所述N+型半导体层5内有选择的扩散P型杂质形成的P-body区( 或者称为P基区)8；自P-body区8的表面向该P-body区8内有选择的扩散高浓度的N型杂质形成的N+有源区（或者称为N+发射极区）9；自所述N+有源区9内侧的P-body区8表面向该P-body区8内扩散高浓度的P型杂质形成的P+有源区10；自所述P-body区8的边缘部分的第一主面和所述原胞区2的未形成P-body区8的第一主面上形成的栅极氧化层（简称栅氧层）220；在栅极氧化层220的上表面上形成的多晶硅栅电极300；覆盖栅极氧化层220和多晶硅栅电极300露出表面的介质层400，其中，多晶硅栅电极300正下方的P-body区8的部分称为沟道区。
在图1所示的实施例中，所述第二导电类型的第二半导体层6为自所述第二主面1S2向所述N-型半导体衬底1内注入P型杂质形成的P+层（或者称为P+集电极层）。位于所述P+集电极层6和N+型半导体层5之间的N-型半导体衬底1部分为N-型漂移区11。
图1中的绝缘栅双极晶体管还包括：在原胞区2的第一主面1S1上覆盖所述介质层400形成的第一主电极（在本实施例中为发射极）12，该第一主电极12与所述N+有源区9和所述P+有源区10电性接触；在第二半导体层6上形成的第二主电极（在本实施例中为集电极）13，该第二主电极13与第二半导体层6电性接触；以及覆盖于第一主电极8、场氧化层400和金属场板500上的用于保护芯片表面不受外界离子玷污的第一钝化层600和第二钝化层700。其中，在本文中，N-、N+、P+中的“+”表示掺杂浓度较高，“-”表示掺杂浓度较低。
与现有技术相比，图1所示的本发明中的绝缘栅双极晶体管在N-型半导体衬底1的第一主面1S1侧形成N+型半导体层5，由于N+型半导体层5的掺杂浓度比半导体衬底1的掺杂浓度高，且绝缘栅型晶体管单元基于N+型半导体层5形成，因此，N+型半导体层5在所述原胞区2中充当载流子存储层。当图1中的绝缘栅双极晶体管正向导通时，从第二主面1S2的P+集电极层6注入到N-型漂移区11内的空穴在其扩散的中途受到N+半导体层5形成的势垒的阻挡，使少数载流子空穴蓄积在P-body区8和N+型半导体层5的界面下方附近，根据电中性原理，使得该区域载流子浓度大大增加，从而降低本发明中的绝缘栅双极晶体管的正向导通压降。另外，由于N+型半导体层5的掺杂浓度比半导体衬底1的掺杂浓度高，且所述保护终端基于N+型半导体层5形成，这样可以提高所述保护终端表面的杂质浓度（即增大了保护终端表面的电荷Qf，参照背景技术部分的公式（1）），从而降低了可动电荷对保护终端表面电场的影响，进而提高了器件的耐压可靠性。
在图1所示的实施例中，所述绝缘栅性晶体管单元为DMOS结构的MOSFET，在其他实施例中，其还可以为沟槽型MOSFET或V字形的MOSFET。
图13为图1中的绝缘栅双极晶体管的制造方法800在一个实施例中的流程图。结合图1和图13所示，所述制造方法800包括如下操作。
步骤810，制备具有第一主面1S1和第二主面1S2的第一导电类型的半导体衬底1，其中，所述半导体衬底1包括原胞区2和位于所述原胞区2外侧的终端保护区4。
步骤820，在所述半导体衬底1的第一主面1S1侧形成第一导电类型的第一半导体层5，其中所述第一半导体层5的掺杂浓度高于半导体衬底1的的掺杂浓度。
步骤830，在所述终端保护区4内的第一半导体层5的第一主面1S1侧形成保护终端，在所述原胞区2内的第一半导体层5的第一主面1S1侧形成绝缘栅型晶体管单元。
步骤840，在形成绝缘栅型晶体管单元的原胞区2的第一主面1S1上形成第一主电极12；
步骤850，从所述半导体衬底1的第二主面起减薄该绝缘栅型晶体管单元形成后的半导体衬底1，使其符合规定的厚度要求。
步骤860，自减薄后的半导体衬底1的第二主面1S2向所述半导体衬底1内形成第二导电类型的第二半导体层6。
步骤870，在所述第二半导体层6形成后的半导体衬底1的第二主面1S2上形成与第二半导体层6电性接触的第二主电极13。
接下来，以所述第一导电类型为N型，所述第二导电类型为P型为例，结合图2-12详细介绍图1中的绝缘栅双极晶体管在一个具体实施例中的制造方法。所述制造方法包括如下步骤：
步骤一，制备具有第一主面1S1和第二主面1S2的N-型半导体衬底1。
步骤二，如图2所示，在所述N-型半导体衬底1的第一主面1S1上形成预氧层200，所述预氧层的厚度可以为1000Å~3000 Å。
步骤三，如图2所示，透过所述预氧层200在所述N-型半导体衬底1的第一主面侧进行N型杂质注入以形成N+层130。所述N型杂质的注入剂量可以为2e11~1e13cm-2、能量可以为60KEV~120KEV。
步骤四，如图3所示，高温推阱形成所述N+型半导体层5，随后在所述预氧层200上形成场氧层210。具体的，可以经过1100℃~1200℃有氧环境推阱形成N+型导体层5，同时生长6000 Å ~20000 Å场氧层210。在一个优选的实施例中，形成的N+型导体层5的方块电阻可以为100ohm/sp~6000ohm/sp。
可以看出，第二步骤至第四步骤为所述N+型导体层5的形成过程。
步骤五，如图4所示，选择性的刻蚀所述场氧层210以刻蚀出P型场限环区7的注入窗口，并自刻蚀出的该注入窗口向所述N+型半导体层5内进行P型扩散以形成P型区域140。具体的，可以采用Ring(环)光刻版，经过涂胶、曝光、湿法腐蚀、去胶等步骤，在所述场氧层210上刻蚀出P型场限环区7的注入窗口，并自刻蚀出的该注入窗口向所述N+型导体层5注入剂量为1e13~1e15cm-2、能量为60KEV~120KEV的P型杂质，从而在N+型导体层5内选择性的形成P型区域140。
步骤六，如图5所示，高温推阱形成P型场限环区7。具体的，经过清洗等步骤，进行1100℃~1200℃有氧环境推阱形成P型场限环区7。在一个优选的实施例中，形成的P型场限环区7的方块电阻可以为10ohm/sp~1200ohm/sp。
步骤七，如图6所示，在所述原胞区2的第一主面1S1上形成栅极氧化层220，并在所述栅极氧化层220和所述场氧化层210上淀积多晶硅栅极层300。具体的，采用Active(有源区)光刻版，经过涂胶、曝光、湿法腐蚀、去胶等步骤，在所述原胞区2的第一主面1S1上热生长一层800 Å ~1200 Å栅氧化层220，在所述栅极氧化层220和所述场氧化层210的上表面淀积6000 Å ~12000 Å多晶硅并掺杂形成多晶硅栅层300。
步骤八，如图7所示，除去所述场氧化层210的上表面的多晶硅栅极层300，选择性的在所述多晶硅栅极层300上刻蚀出P-body区8的注入窗口，并自刻蚀出的该注入窗口向所述N+型导体层5内进行P型扩散以形成P型区域150。具体的，采用Poly(多晶硅)光刻板，经过涂胶、曝光、干法腐蚀、去胶等步骤，选择性的在所述多晶硅栅极层300上刻蚀出P-body区8的注入窗口，并自该窗口注入剂量为1e13~1e15cm-2 、能量为60KEV~120KEV的P型杂质，以在N+型半导体层5中形成P型区域150。
步骤九，如图8所示，高温推结形成P-body区8，自P-body区8的表面向该P-body区8内有选择的扩散高浓度的N型杂质形成N+有源区（或者称为N+发射极）9。具体的，经过清洗等步骤，进行1100℃~1200℃N2(氮)环境推阱形成Pbody区8，自P-body区8的表面向该P-body区8内有选择的注入剂量为5e14~1e16cm-2、能量为60KEV~120KEV的N型杂质，经过800℃~1000℃高温退火激活形成N+有源区（或者称为N+发射极）9。
步骤十，如图9所示，自所述N+有源区9内侧的P-body区8表面向该P-body区8内形成P+有源区10，在所述N+型半导体层5的第一主面1S1上形成介质层400。具体的，淀积氧化层，先后对整个器件进行Spacer腐蚀和硅刻蚀，进行硼注入，形成P+有源区10，淀积8000A~16000A的BPSG(硼磷硅玻璃，boro-phospho-silicate-glass，BPSG)，经过850℃~950℃回流，形成介质层400。
步骤十一，如图10所示，通过光刻、刻蚀工艺在原胞区2中刻蚀出短接N+有源区9和P+有源区10的接触孔，在所述终端保护区4中刻蚀出连接P型场限环区7的接触孔；在所述N+型半导体层5的第一主面上形成覆盖介质层400的金属层；通过光刻、刻蚀工艺选择性的刻蚀去部分以在所述原胞区2形成覆盖介质层400且电性连接N+有源区9和P+有源区10的发射极12，在所述终端保护区4形成部分覆盖介质层400且电性连接P型场限环区7的金属场板500。具体为，采用Cont（接触孔）光刻版先后进行孔刻蚀，溅射金属，并采用Metal(金属)光刻版刻蚀金属层，形成金属发射极12和金属场板500。
可以看出，第五步骤至第十一步骤为形成所述保护终端、绝缘栅型晶体管单元以及发射极12的过程。
步骤十二，如图11所示，在金属发射极12和金属场板500上依次淀积钝化层600和700，并留出用于引出栅电极300和发射极12的PAD（焊盘）区域（未示出）。具体的，采用PAD1(焊盘1)和PAD2(焊盘2)光刻版，先后经过涂胶、曝光、去胶、380℃~450℃退火固化等步骤，形成钝化层600及700。也可以通过其他方式具体实现步骤十二，比如，通过化学气相淀积的方式，在金属发射极12和金属场板500上依次淀积用于保护芯片表面不受外界离子玷污的钝化层600和700，并通过光刻、刻蚀工艺，刻蚀出用于引出栅电极300和发射极12的PAD（焊盘）区域。在一个优选的实施例中，可以采用厚度为4um~18um的光敏Polyimide(聚酰亚胺)作为器件的钝化层。
步骤十三，如图12所示，通过背面减薄工艺，将N-型半导体衬底1的厚度减薄，并在减薄后的N-型半导体衬底1的第二主面1S2侧形成P+集电极6，然后在P+集电极6上形成一定厚度的金属层(比如Al-Ti-Ni-Ag)13，此金属层13即为第二主电极（在此实施例中为集电极）。具体的，可以对N-型半导体衬底1进行背面减薄，减薄至所需厚度后，自减薄后的N-型半导体衬底1的第二主面1S2注入剂量为5e12~1e15cm-2能量为60KEV~120KEV的P型杂质，退火激活形成P+集电极6，然后进行背面金属化形成集电极13。
这样就可以制造出图1中的NPT型绝缘栅双极晶体管。普通领域内的技术人员根据上述制造方法的精神，还可以对其进行各种各样的改变或替换。比如，在一个改变的实施例中，可以将步骤三中的高温推结和步骤五中的高温推结合并为步骤五中的一次高温推结过程。步骤五至步骤十一为在所述N+型半导体层5的第一主面1S1侧生成绝缘栅型晶体管单元、保护终端和发射极12的过程，假如绝缘栅型晶体管为其他类型的MOSFET，或者保护终端为P型场限环等其他保护终端结构，那么，制造步骤也需要相应的改变。
本发明中的绝缘栅双极晶体管的制造方法，在制备绝缘栅型晶体管单元和保护终端之前，通过增加一次离子注入，在第一导电类型的半导体衬底1的第一主面1S1侧形成第一导电类型的第一半导体层5，且所述第一半导体层5中的掺杂浓度高于所述半导体衬底1中的掺杂浓度。这样，所述第一半导体层5在原胞区3中充当载流子存储层，从而可以降低本发明中的绝缘栅双极晶体管的正向导通压降；同时提高了保护终端表面的杂质浓度，降低了可动电荷对保护终端表面电场的影响，从而提高本发明中的绝缘栅双极晶体管的耐压可靠性。相对传统制造方法，该方法不需要增加光刻板即可实现载流子存储层结构，具有成本低、控制精确的优点。
在上述实施例中，以所述第一导电类型为N型，所述第二导电类型为P型为例进行介绍，在其他改变的实施例中，也可以使得第一导电类型为P型，所述第二导电类型为N型，此时采用P-型的半导体衬底1，第一半导体层5为P+半导体层，所述绝缘栅型晶体管为P沟道的MOSFET单元，第二主电极13为发射极，第一主电极12为集电极，具体结构和原理与上文的中绝缘栅双极晶体管相似，这里不在赘述。
上述实施例中，是以NPT型绝缘栅双极晶体管进行阐述，本发明同样适用于场阻型绝缘栅双极晶体管。
需要指出的是，熟悉该领域的技术人员对本发明的具体实施方式所做的任何改动均不脱离本发明的权利要求书的范围。相应地，本发明的权利要求的范围也并不仅仅局限于前述具体实施方式。

Claims (13)

  1. 一种绝缘栅双极晶体管，其特征在于，其包括：
    具有第一主面和第二主面的第一导电类型的半导体衬底，其中，所述半导体衬底包括原胞区和位于所述原胞区外侧的终端保护区；
    形成于所述半导体衬底的第一主面侧的第一导电类型的第一半导体层，其中，所述第一半导体层的掺杂浓度高于所述半导体衬底的掺杂浓度高；及
    形成于所述原胞区内的第一半导体层的第一主面侧的绝缘栅型晶体管单元，其中，所述绝缘栅型晶体管单元导通时形成有第一导电类型的沟道。
  2. 根据权利要求1所述的绝缘栅双极晶体管，其特征在于，其还包括：形成于所述终端保护区内的第一半导体层的第一主面侧的保护终端。
  3. 根据权利要求2所述的绝缘栅双极晶体管，其特征在于，其还包括：
    在所述半导体衬底的第二主面侧形成的第二导电类型的第二半导体层；
    在形成有所述绝缘栅型晶体管单元的第一半导体层的第一主面上形成的第一主电极；
    在所述第二半导体层上形成的第二主电极。
  4. 根据权利要求3所述的绝缘栅双极晶体管，其特征在于，所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，
    所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型半导体衬底，所述第一半导体层为N+型半导体层，所述第二半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极。
  5. 根据权利要求4所述的绝缘栅双极晶体管，其特征在于，所述N型沟道MOSFET单元包括：
    自所述原胞区内的N+型半导体层的第一主面向内有选择的形成的P型基区；
    自所述P型基区的表面向该P型基区内有选择的形成的N+有源区；
    自所述N+有源区内侧的P型基区表面向该P型基区内形成的P+有源区；
    自所述P型基区的边缘部分的第一主面和所述原胞区内的N+型半导体层的未形成P型基区的第一主面上形成的栅极氧化层；
    在栅极氧化层的上表面上形成的多晶硅栅电极；
    覆盖栅极氧化层和多晶硅栅电极露出表面的介质层；
    其中，第一主电极形成于所述介质层的外侧并与所述N+有源区和所述P+有源区电性接触。
  6. 根据权利要求4所述的绝缘栅双极晶体管，其特征在于，所述保护终端包括形成于所述终端保护区内的第一半导体层的第一主面侧的P型场限环区以及位于所述P型场限环区上方并与所述P型场限环区电性接触的金属场板。
  7. 一种绝缘栅双极晶体管的制造方法，其特征在于，其包括：
    制备具有第一主面和第二主面的第一导电类型的半导体衬底，其中，所述半导体衬底包括原胞区和位于所述原胞区外侧的终端保护区；
    在所述半导体衬底的第一主面侧形成第一导电类型的第一半导体层，其中，所述第一半导体层的掺杂浓度高于半导体衬底的掺杂浓度；
    在所述原胞区的第一半导体层的第一主面侧形成绝缘栅型晶体管单元，其中，所述绝缘栅型晶体管单元导通时，其形成有第一导电类型的沟道。
  8. 根据权利要求7所述的绝缘栅双极晶体管的制造方法，其特征在于，其还包括：在所述终端保护区内的第一半导体层的第一主面侧形成保护终端。
  9. 根据权利要求8所述的绝缘栅双极晶体管的制造方法，其特征在于，其还包括：
    在形成有所述绝缘栅型晶体管单元的第一半导体层的第一主面上形成第一主电极；
    从所述半导体衬底的第二主面起减薄该绝缘栅型晶体管单元形成后的半导体衬底；
    自减薄后的半导体衬底的第二主面向所述半导体衬底内形成第二导电类型的第二半导体层；
    在所述第二半导体层上形成与第二半导体层电性接触的第二主电极。
  10. 根据权利要求9所述的绝缘栅双极晶体管的制造方法，其特征在于，所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，
    所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型半导体衬底，所述第一半导体层为N+型半导体层，所述第二半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极。
  11. 根据权利要求10所述的绝缘栅双极晶体管的制造方法，其特征在于，形成所述N+型半导体层的过程包括：
    在所述N-型半导体衬底的第一主面上形成预氧层；
    透过所述预氧层在所述N-型半导体衬底的第一主面侧进行N型杂质注入以形成N+层；和
    高温推阱形成所述N+型半导体层。
  12. 根据权利要求11所述的绝缘栅双极晶体管的制造方法，其特征在于，所述预氧层的厚度为1000Å~3000 Å，所述N型杂质的注入剂量2e11~1e13cm-2，能量为60KEV~120KEV。
  13. 根据权利要求10所述的绝缘栅双极晶体管的制造方法，其特征在于，
    所述保护终端包括形成于所述终端保护区内的第一半导体层的第一主面侧的P型场限环区以及位于所述P型场限环区上方并与所述P型场限环区电性接触的金属场板，
    所述N型沟道MOSFET单元包括：
    自所述原胞区内的N+型半导体层的第一主面向内有选择的形成的P型基区；
    自P型基区的表面向该P型基区内有选择的形成的N+有源区；
    自所述N+有源区内侧的P型基区表面向该P型基区内形成的P+有源区；
    自所述P型基区的边缘部分的第一主面和所述原胞区内的N+型半导体层的未形成P型基区的第一主面上形成的栅极氧化层；
    在栅极氧化层的上表面上形成的多晶硅栅电极；
    覆盖栅极氧化层和多晶硅栅电极露出表面的介质层；
    其中第一主电极形成于所述介质层的外侧并与所述N+有源区和所述P+有源区电性接触。
PCT/CN2014/082730 2013-07-22 2014-07-22 绝缘栅双极晶体管及其制造方法 WO2015010606A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/902,517 US9954074B2 (en) 2013-07-22 2014-07-22 Insulated gate bipolar transistor and manufacturing method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310306819.6 2013-07-22
CN201310306819.6A CN104332494B (zh) 2013-07-22 2013-07-22 一种绝缘栅双极晶体管及其制造方法

Publications (1)

Publication Number Publication Date
WO2015010606A1 true WO2015010606A1 (zh) 2015-01-29

Family

ID=52392731

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/082730 WO2015010606A1 (zh) 2013-07-22 2014-07-22 绝缘栅双极晶体管及其制造方法

Country Status (3)

Country Link
US (1) US9954074B2 (zh)
CN (1) CN104332494B (zh)
WO (1) WO2015010606A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9620615B2 (en) 2013-07-29 2017-04-11 Csmc Technologies Fab1 Co., Ltd. IGBT manufacturing method
US9666682B2 (en) 2013-09-02 2017-05-30 Csmc Technologies Fab1 Co., Ltd. Reverse conduction insulated gate bipolar transistor (IGBT) manufacturing method
US9673193B2 (en) 2013-08-23 2017-06-06 Csmc Technologies Fab1 Co., Ltd. Manufacturing method for reverse conducting insulated gate bipolar transistor
US9862595B2 (en) 2014-01-07 2018-01-09 Csmc Technologies Fab1 Co., Ltd. Method for manufacturing thin-film support beam
US10818655B2 (en) 2013-12-06 2020-10-27 Csmc Technologies Fab2 Co., Ltd. Semiconductor device and related method of adjusting threshold voltage in semiconductor device during manufacture via counter doping in diffusion region

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531465B (zh) * 2013-09-13 2018-04-06 上海集成电路研发中心有限公司 快恢复二极管制备方法
JP6363540B2 (ja) * 2015-03-16 2018-07-25 株式会社東芝 半導体装置
CN106409893A (zh) * 2015-07-28 2017-02-15 无锡华润华晶微电子有限公司 一种绝缘栅双极晶体管及其制备方法
CN106483758B (zh) 2015-09-02 2019-08-20 无锡华润上华科技有限公司 光学邻近效应修正方法和系统
CN106653842B (zh) 2015-10-28 2019-05-17 无锡华润上华科技有限公司 一种具有静电释放保护结构的半导体器件
CN106816468B (zh) 2015-11-30 2020-07-10 无锡华润上华科技有限公司 具有resurf结构的横向扩散金属氧化物半导体场效应管
CN107465983B (zh) 2016-06-03 2021-06-04 无锡华润上华科技有限公司 Mems麦克风及其制备方法
CN107742642A (zh) * 2017-09-22 2018-02-27 广东美的制冷设备有限公司 绝缘栅双极晶体管及其终端结构的制作方法、ipm模块以及空调器
CN109994381A (zh) * 2017-12-29 2019-07-09 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法、电子装置
US11222858B1 (en) * 2020-06-19 2022-01-11 Alpha And Omega Semiconductor International Lp Semiconductor package having enlarged gate pad and method of making the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1328345A (zh) * 2000-06-07 2001-12-26 三菱电机株式会社 半导体器件
CN101345254A (zh) * 2007-07-12 2009-01-14 富士电机电子技术株式会社 半导体器件

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4750933B2 (ja) * 2000-09-28 2011-08-17 株式会社東芝 薄型パンチスルー型パワーデバイス
JP2003347547A (ja) * 2002-05-27 2003-12-05 Mitsubishi Electric Corp 電力用半導体装置及びその製造方法
JP4982948B2 (ja) * 2004-08-19 2012-07-25 富士電機株式会社 半導体装置の製造方法
DE102005039564B4 (de) * 2004-09-02 2011-03-31 Fuji Electric Systems Co., Ltd. Verfahren zum Herstellen eines Halbleiterbauteils
JP5515922B2 (ja) * 2010-03-24 2014-06-11 富士電機株式会社 半導体装置
US9570541B2 (en) * 2010-12-17 2017-02-14 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US8766325B2 (en) * 2011-10-17 2014-07-01 Rohm Co., Ltd. Semiconductor device
CN104221152B (zh) * 2012-07-18 2017-10-10 富士电机株式会社 半导体装置以及半导体装置的制造方法
CN104347401B (zh) 2013-07-29 2017-05-10 无锡华润上华半导体有限公司 一种绝缘栅双极性晶体管的制造方法
CN104425245B (zh) 2013-08-23 2017-11-07 无锡华润上华科技有限公司 反向导通绝缘栅双极型晶体管制造方法
CN104425259B (zh) 2013-09-02 2017-09-15 无锡华润上华半导体有限公司 反向导通绝缘栅双极型晶体管制造方法
CN104701356B (zh) 2013-12-06 2018-01-12 无锡华润上华科技有限公司 半导体器件及其制备方法
CN104760925B (zh) 2014-01-07 2016-05-25 无锡华润上华半导体有限公司 一种薄膜支撑梁的制作方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1328345A (zh) * 2000-06-07 2001-12-26 三菱电机株式会社 半导体器件
CN101345254A (zh) * 2007-07-12 2009-01-14 富士电机电子技术株式会社 半导体器件

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9620615B2 (en) 2013-07-29 2017-04-11 Csmc Technologies Fab1 Co., Ltd. IGBT manufacturing method
US9673193B2 (en) 2013-08-23 2017-06-06 Csmc Technologies Fab1 Co., Ltd. Manufacturing method for reverse conducting insulated gate bipolar transistor
US9666682B2 (en) 2013-09-02 2017-05-30 Csmc Technologies Fab1 Co., Ltd. Reverse conduction insulated gate bipolar transistor (IGBT) manufacturing method
US10818655B2 (en) 2013-12-06 2020-10-27 Csmc Technologies Fab2 Co., Ltd. Semiconductor device and related method of adjusting threshold voltage in semiconductor device during manufacture via counter doping in diffusion region
US9862595B2 (en) 2014-01-07 2018-01-09 Csmc Technologies Fab1 Co., Ltd. Method for manufacturing thin-film support beam

Also Published As

Publication number Publication date
CN104332494A (zh) 2015-02-04
US20160380072A1 (en) 2016-12-29
CN104332494B (zh) 2018-09-21
US9954074B2 (en) 2018-04-24

Similar Documents

Publication Publication Date Title
WO2015010606A1 (zh) 绝缘栅双极晶体管及其制造方法
WO2015010610A1 (zh) 绝缘栅双极晶体管及其制造方法
CN101771083B (zh) 一种深沟槽功率mos器件及其制造方法
WO2014071673A1 (zh) 一种大电流密度的横向超薄绝缘栅双极型晶体管
JP3308505B2 (ja) 半導体装置
US11094790B2 (en) Silicon carbide semiconductor device
WO2015062411A1 (zh) 高压半导体器件、高压半导体器件终端及其制造方法
WO2016124086A1 (zh) 横向双扩散场效应管
WO2013067888A1 (zh) 沟槽型绝缘栅双极型晶体管及其制备方法
WO2015021944A1 (zh) 横向双扩散金属氧化物半导体场效应晶体管
WO2016124093A1 (zh) 横向绝缘栅双极型晶体管
WO2014206189A1 (zh) 场截止型反向导通绝缘栅双极型晶体管及其制造方法
WO2014206160A1 (zh) 绝缘栅双极晶体管及其制造方法
WO2016032069A1 (ko) 절연 또는 반절연 ＳｉＣ 기판에 구현된 ＳｉＣ 반도체 소자 및 그 제조 방법
CN103050523A (zh) 绝缘栅双极型晶体管及其制造方法
WO2014206300A1 (zh) 绝缘栅双极晶体管的制造方法
WO2014206196A1 (zh) 具有内置二极管的igbt及其制造方法
CN114497201A (zh) 集成体继流二极管的场效应晶体管、其制备方法及功率器件
WO2015043378A2 (zh) 功率二极管的制备方法
CN110419111A (zh) 自对准且稳健的绝缘栅双极晶体管器件
WO2023243882A1 (ko) 실리콘 카바이드 기반의 래터럴 전력 반도체 장치 및 그 제조 방법
WO2013020472A1 (zh) Ldmos器件及其制造方法
CN114068721B (zh) 双梯形槽保护梯形槽碳化硅mosfet器件及制造方法
WO2015014289A1 (zh) 绝缘栅双极型晶体管的制造方法
WO2015027920A1 (zh) 绝缘栅双极晶体管的制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14829210

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 14902517

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14829210

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 14829210

Country of ref document: EP

Kind code of ref document: A1