WO2015010610A1 - 绝缘栅双极晶体管及其制造方法 - Google Patents

绝缘栅双极晶体管及其制造方法 Download PDF

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WO2015010610A1
WO2015010610A1 PCT/CN2014/082740 CN2014082740W WO2015010610A1 WO 2015010610 A1 WO2015010610 A1 WO 2015010610A1 CN 2014082740 W CN2014082740 W CN 2014082740W WO 2015010610 A1 WO2015010610 A1 WO 2015010610A1
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type
layer
active region
semiconductor layer
region
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PCT/CN2014/082740
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English (en)
French (fr)
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钟圣荣
邓小社
王根毅
周东飞
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无锡华润上华半导体有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors

Definitions

  • the present invention relates to the field of semiconductor design and manufacturing technology, and in particular to an insulated gate bipolar transistor (Insulated Gate Bipolar) Transistor, referred to as IGBT) and its manufacturing method.
  • IGBT Insulated Gate Bipolar Transistor
  • IGBT is made of BJT (Bipolar Junction Transistor) Composite fully-regulated voltage-driven power semiconductor device composed of MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor), combining high input impedance of MOSFET and low on-state voltage of BJT
  • MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • Insulated gate bipolar transistor has DMOS (Double-diffused Metal Oxide) due to conductance modulation effect Semiconductor, double-diffused MOS) MOSFETs have lower on-resistance, but on-resistance determines the conduction losses of IGBTs during operation, limiting their maximum output power, in order to maximize the IGBT
  • DMOS Double-diffused Metal Oxide
  • MOSFETs Semiconductor, double-diffused MOS MOSFETs have lower on-resistance, but on-resistance determines the conduction losses of IGBTs during operation, limiting their maximum output power, in order to maximize the IGBT
  • the performance of a transistor requires constant reduction of its on-resistance. It is mainly determined by factors such as cell size, arrangement layout, current density, and substrate thickness. Please refer to FIG. 1 , which is a schematic diagram of the equivalent resistance of the insulated gate bipolar transistor.
  • the equivalent resistance of the insulated gate bipolar transistor mainly includes a front MOS resistor RC, JFET (Junction Field-effect Transistor, junction field effect transistor) region resistance RJ, drift region resistance RD and substrate PN junction resistance RP.
  • JFET Joint Field-effect Transistor, junction field effect transistor
  • drift region resistance RD drift region resistance RD
  • substrate PN junction resistance RP substrate PN junction resistance RP.
  • the JFET region resistance RJ there are currently three main methods: first, increasing the carrier concentration at the JFET region and reducing the JFET region resistance, but this method requires an increase in the process steps and the effect is not very obvious; second, by adding a planar gate The size of the JFET region is reduced, this method will reduce the current density and breakdown voltage of the device, and the design needs to be optimized. Third, the trench gate is used instead of the planar gate structure to remove the JFET region in the planar gate. The method directly removes the partial resistance of the JFET, effectively increasing the current density of the device, and is widely used in the low voltage IGBT, but the manufacturing process of the method is complicated, and the shape and process control of the trench gate are applied to the IGBT. Reliability has a large impact and is not commonly used in high voltage IGBTs.
  • the drift region resistance RD it is mainly achieved by reducing the thickness of the drift region.
  • PT- IGBT through-type insulated gate bipolar transistors
  • NPT- non-punch-through insulated gate bipolar transistor
  • FS-IGBT field-stop insulated gate bipolar transistor. The main difference between the three is the different substrate PN junction structure and different drift region thickness.
  • PT-IGBT and NPT-IGBT Compared with PT-IGBT and NPT-IGBT, FS-IGBT has the thinnest thickness, and its forward conduction voltage drop is significantly reduced to 600V/25A.
  • the substrate thickness required for NPT-IGBT products is about 120um, while the FS-IGBT only needs 60um, and the thickness is reduced.
  • the forward voltage drop is also reduced from 1.6V to 1.2V, a drop of nearly 30%.
  • IGBTs especially low voltage IGBTs.
  • An insulated gate bipolar transistor comprising: a first conductivity type semiconductor substrate having a first major surface and a second major surface, wherein the semiconductor substrate includes an active region and is outside the active region a terminal protection region; a first semiconductor layer of a first conductivity type formed on a first main surface side of the active region, wherein a doping concentration of the first semiconductor layer is higher than a doping of the semiconductor substrate a concentration; an insulated gate type transistor cell formed on a first main surface side of the first semiconductor layer, wherein the insulated gate type transistor cell is formed with a channel of a first conductivity type when turned on.
  • the insulated gate bipolar transistor further includes: a protection terminal formed on a first main surface side of the terminal protection region.
  • the insulated gate bipolar transistor further includes: a second semiconductor layer of a second conductivity type formed on a second main surface side of the semiconductor substrate; and the insulated gate transistor unit is formed a first main electrode formed on a first main surface of the first semiconductor layer; and a second main electrode formed on the second semiconductor layer.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the insulated gate transistor unit is an N-channel MOSFET unit
  • the first conductivity type semiconductor lining The bottom is an N-type semiconductor substrate
  • the first semiconductor layer is an N+ type semiconductor layer
  • the second semiconductor layer is a P+ type collector layer
  • the first main electrode is an emitter
  • the second main electrode It is a collector.
  • the N-channel MOSFET cell includes: a selectively formed P-type base region from a first main face of an N+ type semiconductor layer in the active region; from the P-type base a surface of the region is selectively formed in the P-type base region; a P+ active region formed from a surface of the P-type base region inside the N+ active region toward the P-type base region; a first main surface of the edge portion of the P-type base region and a gate oxide layer formed on the first main surface of the N+ type semiconductor layer in the active region where the P-type base region is not formed; in the gate oxide layer a polysilicon gate electrode formed on the upper surface; a dielectric layer covering the gate oxide layer and the polysilicon gate electrode exposed surface; wherein the first main electrode is formed outside the dielectric layer and with the N+ active region and P+ active area is electrically contacted.
  • a method of fabricating an insulated gate bipolar transistor comprising: providing a semiconductor substrate of a first conductivity type having a first major surface and a second major surface, wherein the semiconductor substrate includes an active region and is located a terminal protection region outside the source region; forming a first semiconductor layer of a first conductivity type on a first main surface side of the active region, wherein a doping concentration of the first semiconductor layer is higher than a doping of the semiconductor substrate a concentration; forming an insulated gate type transistor cell on a first main surface side of the first semiconductor layer, wherein the insulated gate type transistor cell is formed with a channel of a first conductivity type when turned on.
  • the method of fabricating the insulated gate bipolar transistor further includes forming a protection terminal on a first major surface side within the termination protection.
  • the method of manufacturing the insulated gate bipolar transistor further includes: Forming a first main electrode on a first main surface of the first semiconductor layer on which the insulated gate transistor unit is formed; and thinning the insulated gate transistor unit from a second main surface of the semiconductor substrate a semiconductor substrate; a second semiconductor layer of a second conductivity type formed in the semiconductor substrate from the second main surface of the thinned semiconductor substrate; and an electrical property with the second semiconductor layer formed on the second semiconductor layer The second main electrode that is in contact.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the insulated gate transistor unit is an N-channel MOSFET unit
  • the first conductivity type semiconductor lining The bottom is an N-type semiconductor substrate
  • the first semiconductor layer is an N+ type semiconductor layer
  • the second semiconductor layer is a P+ type collector layer
  • the first main electrode is an emitter
  • the second main electrode It is a collector.
  • the process of forming the N+ type semiconductor layer includes: forming a field oxide layer on a first main surface of the N-type semiconductor substrate; and transmitting the field oxide layer in the active region The first main surface side is subjected to N-type impurity implantation to form an N+ layer; and the high temperature push well forms the N+ type semiconductor layer.
  • the N-channel MOSFET unit includes: a selectively formed P-type base region from a first main surface of the N+ type semiconductor layer in the active region; and a P-type base region a surface selectively forming an N+ active region into the P-type base; a P+ active region formed from a surface of the P-type base region inside the N+ active region toward the P-type base region; a first main surface of the edge portion of the type base region and a gate oxide layer formed on the first main surface of the N+ type semiconductor layer in the active region where the P type base region is not formed; on the gate oxide layer a polysilicon gate electrode formed on the surface; a dielectric layer covering the exposed surface of the gate oxide layer and the polysilicon gate electrode; wherein a first main electrode is formed on an outer side of the dielectric layer and is associated with the N+ active region and the P+ The source area is in electrical contact.
  • a method of fabricating an insulated gate bipolar transistor comprising: step one, providing an N-type semiconductor substrate having a first major surface and a second major surface, the N-type semiconductor substrate including an active region and a terminal a protective region; a second step of forming a pre-oxygen layer on the first main surface of the N-type semiconductor substrate; and a third step in the terminal protection region by photolithography based on the termination ring lithography and ion implantation
  • the main surface layer forms a termination ring; in step 4, high temperature oxidation forms a field oxide layer on the pre-oxygen layer; and step 5, through photolithography, etching, ion implantation, high temperature push-pull based on a P-type field limiting ring region lithography plate
  • the process forms a P-type field limiting ring region in the terminal protection region; and in step 6, the first main surface side of the active region is formed by photolithography, etching, ion implantation, and high temperature push-trap based on the active
  • the first semiconductor layer of the first conductivity type is formed on the first main surface side of the active region in the semiconductor substrate of the first conductivity type, and The doping concentration in the first semiconductor layer is higher than the doping concentration in the semiconductor substrate; the insulated gate transistor unit is formed on the first main surface side of the first semiconductor layer.
  • the first semiconductor layer not only increases the carrier concentration at the JFET region, reduces the JFET region resistance RJ in the active region, but also acts as a carrier storage layer, optimizes the carrier distribution of the drift region, and reduces drift.
  • the area resistance RD thereby reducing the forward voltage drop of the insulated gate bipolar transistor of the present invention.
  • 1 is a schematic diagram of an equivalent resistance of a conventional insulated gate bipolar transistor
  • Figure 2 is a longitudinal cross-sectional view showing a portion of an insulated gate bipolar transistor in one embodiment
  • FIG. 3 is a schematic flow chart of a method of manufacturing an IGBT in one embodiment
  • FIG. 4 through 17 are longitudinal cross-sectional views showing respective manufacturing processes of the insulated gate bipolar transistor of Fig. 2 in one embodiment.
  • one embodiment or “an embodiment” as used herein refers to a particular feature, structure, or characteristic that can be included in at least one implementation of the invention.
  • the insulated gate bipolar transistor includes: a first conductive type semiconductor substrate 1 having a first main surface 1S1 and a second main surface 1S2, wherein the semiconductor substrate 1 includes an active region 2, and the a terminal protection region 4 outside the source region 2; a first semiconductor layer 5 of a first conductivity type formed on the first main surface 1S1 side of the active region 2, wherein the doping concentration of the first semiconductor layer 5 is higher than a doping concentration of the semiconductor substrate 1; an insulated gate transistor unit formed on a first main surface 1S1 side of the first semiconductor layer 5, wherein the insulated gate transistor unit is formed with a first a channel of a conductivity type; a protection terminal formed on a side of the first main surface 1S1 of the terminal protection region 4; a second semiconductor of a second conductivity type formed on a side of the second main surface 1S2 of the semiconductor substrate 1 Layer 6.
  • the insulated gate bipolar transistor further includes: a first main electrode 12 formed on a first main surface 1S1 of the first semiconductor layer 5 on which the insulated gate transistor unit is formed; and a second semiconductor layer 6 The second main electrode 13 is formed thereon.
  • the structure of the insulated gate bipolar transistor of the present invention will be specifically described below with reference to FIG. 2, taking the first conductivity type as N-type and the second conductivity type as P-type as an example.
  • the first conductivity type semiconductor substrate 1 is an N-type semiconductor substrate (also referred to as an N-layer).
  • the first semiconductor layer 5 of the first conductivity type formed on the first main surface 1S1 side of the active region 2 is an N+ type semiconductor layer.
  • the protection terminal is a field limiting ring termination structure, and the field limiting ring termination structure includes selectively performing P-type impurity doping into the N-type semiconductor substrate 1 from the first main surface 1S1 in the termination protection region 4.
  • a field oxide layer is further formed on the first main surface 1S1 of the terminal protection region 4.
  • protection terminal can also be other protection terminal structures in the prior art, for example, a field limiting ring plus field plate terminal structure.
  • An N+ type termination ring 15 is further formed on the first main surface 1S1 side outside the field limiting ring terminal structure.
  • the insulated gate transistor unit is a MOSFET having a channel of a first conductivity type (here, an N-type channel).
  • the N-channel MOSFET is DMOS (Double-diffused Metal Oxide a semiconductor, double-diffused MOS) MOSFET comprising: a P-body region formed from a first main surface 1S1 of the active region 2 to a selected diffused P-type impurity in the N+ type semiconductor layer 5 ( Or referred to as a P-base region 8; an N+ active region (or referred to as an N+ emitter region) formed from the surface of the P-body region 8 to the P-body region 8 with selective diffusion of a high concentration of N-type impurities.
  • DMOS Double-diffused Metal Oxide a semiconductor, double-diffused MOS MOSFET comprising: a P-body region formed from a first main surface 1S1 of the active region 2 to a selected diffused P-type impurity in the N+ type semiconductor layer
  • a P+ active region 10 formed by diffusing a high concentration of P-type impurities from the surface of the P-body region 8 inside the N+ active region 9 into the P-body region 8; from the P-body region 8 a first main surface of the edge portion and a gate oxide layer (abbreviated as gate oxide layer) 220 formed on the first main surface of the active region 2 where the P-body region 8 is not formed; on the gate oxide layer 220
  • the second semiconductor layer 6 of the second conductivity type is a P+ layer formed by injecting a P-type impurity into the N-type semiconductor substrate 1 from the second main surface 1S2. (Or called P+ collector layer).
  • the portion of the N-type semiconductor substrate 1 located between the P+ collector layer 6 and the N+ type semiconductor layer 5 is an N-type drift region 11.
  • the insulated gate bipolar transistor of FIG. 2 further includes: a first main electrode (in the present embodiment, an emitter) 12 formed on the first main surface 1S1 of the active region 2 to cover the dielectric layer 400, the first a main electrode 12 is in electrical contact with the N+ active region 9 and the P+ active region 10; a second main electrode (in the present embodiment, a collector) 13 is formed on the second semiconductor layer 6, which The second main electrode 13 is in electrical contact with the second semiconductor layer 6; and the first passivation layer 600 and the second covering the first main electrode 12 and the field oxide layer 14 for protecting the surface of the chip from external ions Passivation layer 700.
  • a first main electrode in the present embodiment, an emitter
  • a second main electrode in the present embodiment, a collector 13 is formed on the second semiconductor layer 6, which The second main electrode 13 is in electrical contact with the second semiconductor layer 6
  • the first passivation layer 600 and the second covering the first main electrode 12 and the field oxide layer 14 for protecting the surface of the chip from external ions Passivation layer 700
  • the insulated gate bipolar transistor of the present invention shown in FIG. 2 forms the N+ type semiconductor layer 5 on the first main surface 1S1 side of the active region 2 in the N-type semiconductor substrate 1, due to
  • the doping concentration of the N+ type semiconductor layer 5 is higher than the doping concentration of the semiconductor substrate 1, and the insulated gate type transistor cell is formed based on the N+ type semiconductor layer 5. Therefore, the N+ type semiconductor layer 5 not only increases the JFET region (refer to Figure 1 shows the carrier concentration, reduces the JFET region resistance RJ, and also acts as a carrier storage layer, optimizes the carrier distribution of the drift region 11, and reduces the drift region resistance RD, thereby reducing the insulated gate in the present invention.
  • the forward voltage drop of a bipolar transistor is not only increases the JFET region (refer to Figure 1 shows the carrier concentration, reduces the JFET region resistance RJ, and also acts as a carrier storage layer, optimizes the carrier distribution of the drift region 11, and reduces the drift region resistance RD, thereby reducing the
  • the N+ type semiconductor layer 5 acts as a carrier storage layer in the active region 2, specifically, when the insulated gate bipolar transistor in FIG. 2 is forward-conducting, the P+ collector from the second main surface 1S2
  • the holes injected into the N-type drift region 11 by the layer 6 are blocked by the barrier formed by the N+ semiconductor layer 5 in the middle of diffusion thereof, and the minority carrier holes are accumulated in the P-body region 8 and the N+ type semiconductor layer.
  • the carrier concentration in the region is greatly increased, thereby reducing the forward voltage drop of the insulated gate bipolar transistor in the present invention.
  • the insulated gate transistor cell is a MOSFET of a DMOS structure, and in other embodiments, it may also be a trench MOSFET or a V-shaped MOSFET.
  • FIG. 3 is a flow chart of a method of fabricating the insulated gate bipolar transistor of FIG. 2 in one embodiment. 2 and 3, the manufacturing method includes the following operations.
  • Step 210 providing a semiconductor substrate 1 of a first conductivity type having a first main surface 1S1 and a second main surface 1S2, wherein the semiconductor substrate 1 includes an active region 2 and is located outside the active region 2 Terminal protection zone 4.
  • Step 220 forming a protection terminal on the first main surface 1S1 side of the terminal protection region 4 of the semiconductor substrate 1.
  • Step 230 forming a first semiconductor layer 5 of a first conductivity type on a side of the first main surface 1S1 of the active region 2, wherein a doping concentration of the first semiconductor layer 5 is higher than a doping of the semiconductor substrate 1 Miscellaneous concentration.
  • Step 240 forming an insulated gate transistor unit on the first main surface 1S1 side of the first semiconductor layer 5.
  • Step 250 forming a first main electrode 12 on the first main surface 1S1 of the active region 2 forming the insulated gate transistor unit;
  • Step 260 thinning the semiconductor substrate 1 after the formation of the insulated gate transistor unit from the second main surface of the semiconductor substrate 1 to meet a predetermined thickness requirement.
  • Step 270 forming a second semiconductor layer 6 of the second conductivity type into the semiconductor substrate 1 from the second main surface 1S2 of the thinned semiconductor substrate 1.
  • Step 280 forming a second main electrode 13 in electrical contact with the second semiconductor layer 6 on the second main surface 1S2 of the semiconductor substrate 1 after the second semiconductor layer 6 is formed.
  • the manufacturing method includes the following steps:
  • Step one providing an N-type semiconductor substrate 1 having a first main surface 1S1 and a second main surface 1S2.
  • Step 2 as shown in FIG. 4, a pre-oxygen layer 200 is formed on the first main surface 1S1 of the N-type semiconductor substrate 1.
  • Step 3 as shown in FIG. 5, a Stop is formed on the first main surface 1S1 layer of the terminal protection area 4 A ring (end ring), that is, a high-concentration N-type impurity implantation from the first main surface 1S1 into the N-type semiconductor substrate 1 at the outer edge of the terminal protection region 4 to form an N+ type termination ring 15.
  • the ring lithography plate performs photolithography on the pre-oxygen layer 200, and phosphorus is implanted to form a Stop ring.
  • Step 4 as shown in FIG. 6, after the photoresist is removed, high temperature oxidation is performed to form a field oxide layer 210 on the pre-oxygen layer 200.
  • Step 5 selectively etching the field oxide layer 210 in the terminal protection region 4 to etch the injection window of the P-type field limiting ring region 7 by photolithography and etching processes, and
  • the implantation window self-etching is P-type diffused into the N-type semiconductor substrate 1 to form a P-type region 140.
  • a Ring (lithographic) lithography plate can be used to etch the injection window of the P-type field limiting ring region 7 on the field oxide layer 210 through steps of coating, exposing, wet etching, and de-glue.
  • a P-type impurity for example, phosphorus
  • the P-type region 140 is located inside the termination ring.
  • step 6 the high temperature push trap forms a P-type field limiting ring region 7. Specifically, after the photoresist is removed, the aerobic environment is pushed to form a P-type field limiting ring region 7, and trap oxygen is generated.
  • steps two through six are the formation processes of the termination ring 15, the field oxide layer 210 and the P-type field limiting ring region 7.
  • Step seven as shown in FIG. 9, an N+ semiconductor layer 5 is formed on the first main surface 1S1 side of the active region 2.
  • photolithography is performed on the field oxide layer 210 by an active (active region) lithography plate to implant a high concentration of N-type impurities to form an N+ semiconductor layer on the first main surface 1S1 side of the active region 2. 5.
  • Step eight as shown in FIG. 10, the high temperature push well forms the N+ semiconductor layer 5. Specifically, after the photoresist is removed, the well is heated for a long time to form the N+ semiconductor layer 5.
  • steps 7 and 8 are the formation processes of the N+ semiconductor layer 5.
  • Step nine as shown in FIG. 11, a gate of the MOS unit is formed on the N+ semiconductor layer 5. Specifically, the remaining field oxide layer on the active region 2 is removed by wet etching, and the gate oxide layer 220, the deposited polysilicon gate layer 300, and the polysilicon doping are sequentially formed on the first main surface 1S1 of the N+ semiconductor layer 5. And etching is performed using a Poly (polysilicon) lithography plate to form a gate of the MOS unit.
  • Step 10 as shown in FIG. 12, self-aligned boron implantation is performed using the polysilicon gate 300, and a high temperature push well is formed to form the Pbody region 8.
  • Step 11 As shown in FIG. 13, self-aligned arsenic implantation is performed using the polysilicon gate 300, and high temperature annealing is performed to selectively form the N+ active region 9 in the Pbody region 3.
  • Step 12 forming a P+ active region 10 from the surface of the P-body region 8 inside the N+ active region 9 into the P-body region 8. Specifically, depositing an oxide layer, and performing Spacer etching on the entire device. And silicon etching, boron implantation, high temperature push well to form P + active region 10.
  • Step 13 As shown in FIG. 14, a dielectric layer 400 covering the polysilicon gate 300 is deposited on the first main surface 1S1 of the active region 2. Specifically, 8000A ⁇ 16000A is deposited on the first main surface 1S1 of the active region 2
  • the BPSG boro-phospho-silicate-glass, BPSG
  • BPSG boro-phospho-silicate-glass
  • steps 9 to 13 are the formation processes of the MOS unit.
  • a first main electrode (here, an emitter) is formed on the first main surface 1S1 of the active region 2 on which the MOS cell is formed. Specifically, a contact hole shorting the N+ active region and the P well is etched in the active region 2 by photolithography and etching, and a cover dielectric layer 7 is formed on the first main surface 1S1 of the active region 2.
  • the first main electrode (here the emitter) of the exposed surface is metal 12.
  • the Cont lithography plate is used to sequentially perform hole etching, sputtering metal, and etching a metal layer using a Metal lithography plate to form a metal emitter 12.
  • a passivation layer 600 and a passivation layer 700 are sequentially deposited on the first main electrode metal 8 and the field oxide layer 13. Specifically, a passivation layer 600 and a passivation layer 700 for protecting the surface of the chip from external ions are sequentially deposited on the first main electrode metal 8 and the field oxide layer 13 by chemical vapor deposition. A photolithography, etching process etches a PAD (pad) region (not shown) for extracting the gate electrode 4 and the emitter 8.
  • Step 16 As shown in FIG. 17, the thickness of the N-type semiconductor substrate 1 is thinned by the back surface thinning process, and is formed on the second main surface 1S2 side of the thinned N-type semiconductor substrate 1.
  • the N-type semiconductor substrate 1 can be back-thinned and thinned to a desired thickness, and the second main surface 1S2 of the self-thinned N-type semiconductor substrate 1 is implanted at a dose of 5e12 to 1e15 cm . 2
  • the NPT type insulated gate bipolar transistor of Fig. 2 can be manufactured.
  • a person skilled in the art can also make various changes or substitutions according to the spirit of the above manufacturing method.
  • the high temperature push knot in step six and the high temperature push in step eight can be combined and become a high temperature push knot process in step eight.
  • the ion implantation in step three and the ion implantation in step seven can be combined and performed in step seven to save cost.
  • the first semiconductor layer 5 of the first conductivity type is formed on the first main surface 1S1 side of the active region by adding one ion implantation before preparing the insulated gate transistor unit, And the doping concentration in the first semiconductor layer 5 is higher than the doping concentration in the semiconductor substrate 1.
  • the first semiconductor layer not only increases the carrier concentration at the JFET region, reduces the JFET region resistance RJ in the active region, but also acts as a carrier storage layer, optimizes the carrier distribution of the drift region, and reduces drift.
  • the area resistance RD thereby reducing the forward voltage drop of the insulated gate bipolar transistor of the present invention.
  • CE is formed by Active (active region) self-aligned injection method.
  • the layer does not need to increase the number of lithography plates, and completes the high-temperature push-knot process before the polysilicon gate is prepared, thereby avoiding the influence of doping ions in the polysilicon on the gate oxide and the channel region during the high-temperature process. Solved the problem that the gate oxide is easily destroyed during the thermal process.
  • the first conductivity type is N-type
  • the second conductivity type is P-type.
  • the first conductivity type may be P-type.
  • the second conductivity type is N-type, in which case a P-type semiconductor substrate 1 is used, the first semiconductor layer 5 is a P+ semiconductor layer, the insulated gate transistor is a P-channel MOSFET unit, and the second main electrode 13 is an emitter, and the first main electrode 12 is a collector.
  • the specific structure and principle are similar to those of the above-mentioned insulated gate bipolar transistor, and are not described here.

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Abstract

一种绝缘栅双极晶体管及其制造方法，包括：具有第一主面（1S1）和第二主面（1S2）的第一导电类型的半导体衬底（1），形成于半导体衬底（1）的有源区（2）的第一主面（1S1）侧的第一导电类型的第一半导体层（5），第一半导体层（5）的掺杂浓度高于半导体衬底（1）的掺杂浓度；形成于第一半导体层（5）的第一主面（1S1）侧的绝缘栅型晶体管单元。第一半导体层（5）在有源区（2）中不仅降低JFET区域电阻，而且还充当载流子存储层，降低漂移区电阻，从而降低绝缘栅双极晶体管的正向导通压降。

Description

绝缘栅双极晶体管及其制造方法
【技术领域】
本发明涉及半导体设计及制造技术领域，特别涉及一种绝缘栅双极晶体管（Insulated Gate Bipolar Transistor，简称IGBT）及其制造方法。
【背景技术】
IGBT是由BJT （Bipolar Junction Transistor，双极结型晶体管） 和MOSFET（Metal-Oxide-Semiconductor-Field-Effect-Transistor，金属氧化物半导体场效应晶体管）组成的复合全控型电压驱动式功率半导体器件，兼有MOSFET的高输入阻抗和BJT的低导通压降两方面的优点，具有工作频率高，控制电路简单，电流密度高，通态压低等特点，广泛应用于功率控制领域。
由于电导调制效应，绝缘栅双极晶体管具有比DMOS（Double-diffused Metal Oxide Semiconductor，双扩散MOS）结构的MOSFET更低的导通电阻，但导通电阻决定了绝缘栅双极晶体管工作时的导通损耗，限制了其最大输出功率，为了尽可能的提高绝缘栅双极晶体管的性能，需要不断的降低其导通电阻，它主要由原胞尺寸、排列布局、电流密度、衬底厚度等因素决定。请参考图1所示，其为绝缘栅双极晶体管的等效电阻示意图。该绝缘栅双极晶体管的等效电阻主要包括正面MOS电阻RC，JFET(Junction Field-effect Transistor，结型场效应晶体管)区域电阻RJ，漂移区电阻RD以及衬底PN结电阻RP。对于高压绝缘栅双极晶体管来说，影响正向导通压降Vce（on）的主要是JFET区域电阻RJ和漂移区电阻RD。因而，如何尽量降低这两部分电阻是大功率绝缘栅双极晶体管设计的重要考虑因素。
针对JFET区域电阻RJ，目前主要有三类方法：第一、增加JFET区域处载流子浓度，降低JFET区域电阻，但这种方法需要增加工艺步骤且效果不是非常明显；第二、通过增加平面栅的尺寸来降低JFET区域电阻，这种方法会降低器件的电流密度和击穿电压，需要优化设计；第三、使用采用沟槽栅代替平面栅结构，将平面栅中的JFET区域去除，这种方法直接去除了JFET这部分电阻，有效地增大了器件的电流密度，在低压IGBT中得到了广泛地应用，但是这种方法制造工艺复杂，且沟槽栅的形貌及工艺控制对IGBT的可靠性具有很大的影响，在高压IGBT中并不常用。
针对漂移区电阻RD，主要通过降低漂移区厚度来实现。迄今为止，主要有穿通型绝缘栅双极晶体管PT- IGBT、非穿通型绝缘栅双极晶体管NPT- IGBT和场截止型绝缘栅双极晶体管FS-IGBT三种结构，三者之间的主要差异是不同的衬底PN结结构和不同的漂移区厚度。相对PT-IGBT和NPT-IGBT来讲，FS-IGBT具有最薄的厚度，其正向导通压降得到明显的下降，以600V/25A IGBT为例，NPT-IGBT产品所需衬底厚度大约为120um，而FS-IGBT只需要60um，厚度降低了一般，其正向导通压降也从1.6V降低至1.2V，降幅近30％。然而，随着半导体晶圆尺寸的不断提高，薄片设备的价格、工艺复杂程度以及很高的碎片率严重的限制了IGBT（特别是低压IGBT）性能的不断提升。
因此，有必要提供一种改进的技术方案来克服上述问题。
【发明内容】
基于此，有必要提供一种绝缘栅双极晶体管及其制造方法，可以降低该绝缘栅双极晶体管的正向导通压降。
一种绝缘栅双极晶体管，其包括：具有第一主面和第二主面的第一导电类型的半导体衬底，其中，所述半导体衬底包括有源区和位于所述有源区外侧的终端保护区；形成于所述有源区的第一主面侧的第一导电类型的第一半导体层，其中所述第一半导体层的掺杂浓度高于所述半导体衬底的掺杂浓度；形成于第一半导体层的第一主面侧的绝缘栅型晶体管单元，其中所述绝缘栅型晶体管单元导通时，其形成有第一导电类型的沟道。
在一个实施例中，所述绝缘栅双极晶体管还包括：形成于所述终端保护区的第一主面侧的保护终端。
在一个实施例中，所述绝缘栅双极晶体管还包括：在所述半导体衬底的第二主面侧形成的第二导电类型的第二半导体层；在形成有所述绝缘栅型晶体管单元的第一半导体层的第一主面上形成的第一主电极；在所述第二半导体层上形成的第二主电极。
在一个实施例中，所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型半导体衬底，所述第一半导体层为N+型半导体层，所述第二半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极。
在一个实施例中，所述N型沟道MOSFET单元包括：自所述有源区内的N+型半导体层的第一主面向内有选择的形成的P型基区；自所述P型基区的表面向该P型基区内有选择的形成的N+有源区；自所述N+有源区内侧的P型基区表面向该P型基区内形成的P+有源区；自所述P型基区的边缘部分的第一主面和所述有源区内的N+型半导体层的未形成P型基区的第一主面上形成的栅极氧化层；在栅极氧化层的上表面上形成的多晶硅栅电极；覆盖栅极氧化层和多晶硅栅电极露出表面的介质层；其中，第一主电极形成于所述介质层的外侧并与所述N+有源区和所述P+有源区电性接触。
一种绝缘栅双极晶体管的制造方法，其包括：提供具有第一主面和第二主面的第一导电类型的半导体衬底，其中所述半导体衬底包括有源区和位于所述有源区外侧的终端保护区；在所述有源区的第一主面侧形成第一导电类型的第一半导体层，其中所述第一半导体层的掺杂浓度高于半导体衬底的掺杂浓度；在所述第一半导体层的第一主面侧形成绝缘栅型晶体管单元，其中所述绝缘栅型晶体管单元导通时，其形成有第一导电类型的沟道。
在一个实施例中，所述绝缘栅双极晶体管的制造方法还包括：在所述终端保护内的第一主面侧形成保护终端。
在一个实施例中，所述绝缘栅双极晶体管的制造方法还包括： 在形成有所述绝缘栅型晶体管单元的第一半导体层的第一主面上形成第一主电极；从所述半导体衬底的第二主面起减薄该绝缘栅型晶体管单元形成后的半导体衬底；自减薄后的半导体衬底的第二主面向所述半导体衬底内形成第二导电类型的第二半导体层；在所述第二半导体层上形成与第二半导体层电性接触的第二主电极。
在一个实施例中，所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型半导体衬底，所述第一半导体层为N+型半导体层，所述第二半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极。
在一个实施例中，形成所述N+型半导体层的过程包括：在所述N-型半导体衬底的第一主面上形成场氧层；透过所述场氧层在所述有源区的第一主面侧进行N型杂质注入以形成N+层；和高温推阱形成所述N+型半导体层。
在一个实施例中，所述N型沟道MOSFET单元包括：自所述有源区内的N+型半导体层的第一主面向内有选择的形成的P型基区；自P型基区的表面向该P型基区内有选择的形成的N+有源区；自所述N+有源区内侧的P型基区表面向该P型基区内形成的P+有源区；自所述P型基区的边缘部分的第一主面和所述有源区内的N+型半导体层的未形成P型基区的第一主面上形成的栅极氧化层；在栅极氧化层的上表面上形成的多晶硅栅电极；覆盖栅极氧化层和多晶硅栅电极露出表面的介质层；其中，第一主电极形成于所述介质层的外侧并与所述N+有源区和所述P+有源区电性接触。
一种绝缘栅双极晶体管的制造方法，其包括：步骤一、提供具有第一主面和第二主面的N-型半导体衬底，所述N-型半导体衬底包括有源区和终端保护区；步骤二，在所述N-型半导体衬底的第一主面上形成预氧层；步骤三、通过基于终止环光刻板的光刻、离子注入在所述终端保护区的第一主面层形成终止环；步骤四，高温氧化在所述预氧层上形成场氧层；步骤五，通过基于P型场限环区光刻板的光刻、刻蚀、离子注入、高温推阱工艺在所述终端保护区中形成P型场限环区；步骤六，通过基于有源区光刻板的光刻、蚀刻、离子注入、高温推阱在所述有源区的第一主面侧制备N+型半导体层；步骤七，依次在N+半导体层的第一主面上形成栅极氧化层和淀积多晶硅栅极层；步骤八，通过基于多晶硅光刻板进行光刻、刻蚀、多晶硅栅极自对准离子注入、高温推阱形成Pbody区；步骤九，多晶硅栅极自对准离子注入以形成N+有源区；步骤十，淀积覆盖多晶硅栅极的介质层、形成正面金属电极和钝化层；步骤十一、通过背面减薄工艺，将N-型半导体衬底1的厚度减薄，并在减薄后的N-型半导体衬底的第二主面侧形成P+集电极，然后在P+集电极上形成背面金属层。
与现有技术相比，上述绝缘栅双极晶体管及其制造方法，在第一导电类型的半导体衬底中的有源区的第一主面侧形成第一导电类型的第一半导体层，且所述第一半导体层中的掺杂浓度高于所述半导体衬底中的掺杂浓度；绝缘栅型晶体管单元形成于第一半导体层的第一主面侧。这样，所述第一半导体层在有源区中不仅增加了JFET区域处载流子浓度，降低JFET区域电阻RJ，而且还充当载流子存储层，优化漂移区的载流子分布，降低漂移区电阻RD，从而降低本发明中的绝缘栅双极晶体管的正向导通压降。
【附图说明】
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。其中：
图1为现有的绝缘栅双极晶体管的等效电阻示意图；
图2为一个实施例中的绝缘栅双极晶体管的一部分的纵剖面图；
图3为一个实施例中的IGBT的制造方法的流程示意图；
图4至图17为图2中的绝缘栅双极晶体管在一个具体实施例中的各个制造工序的纵剖面图。
【具体实施方式】
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。
此处所称的“一个实施例”或“实施例”是指可包含于本发明至少一个实现方式中的特定特征、结构或特性。在本说明书中不同地方出现的“在一个实施例中”并非均指同一个实施例，也不是单独的或选择性的与其他实施例互相排斥的实施例。
请参考图2所示，其为本发明在一个实施例中的绝缘栅双极晶体管的一部分的纵剖面图。所述绝缘栅双极晶体管包括：具有第一主面1S1和第二主面1S2的第一导电类型的半导体衬底1，其中，所述半导体衬底1包括有源区2、位于所述有源区2外侧的终端保护区4；形成于有源区2的第一主面1S1侧的第一导电类型的第一半导体层5，其中，所述第一半导体层5的掺杂浓度高于所述半导体衬底1的掺杂浓度；形成于所述第一半导体层5的第一主面1S1侧的绝缘栅型晶体管单元，其中，所述绝缘栅型晶体管单元导通时其形成有第一导电类型的沟道；形成于所述终端保护区4的第一主面1S1侧的保护终端；形成于所述半导体衬底1的第二主面1S2侧的第二导电类型的第二半导体层6。
所述绝缘栅双极晶体管还包括：在形成有所述绝缘栅型晶体管单元的第一半导体层5的第一主面1S1上形成的第一主电极12；以及在所述第二半导体层6上形成的第二主电极13。
下面以所述第一导电类型为N型，所述第二导电类型为P型为例，结合图2对本发明中的绝缘栅双极晶体管的结构进行具体介绍。
在图2所示的实施例中，所述第一导电类型的半导体衬底1为N-型半导体衬底（也称为N-层）。形成于所述有源区2的第一主面1S1侧的第一导电类型的第一半导体层5为N+型半导体层。所述保护终端为场限环终端结构，该场限环终端结构包括自终端保护区4中的第一主面1S1向所述N-型半导体衬底1内选择性的进行P型杂质掺杂以形成的P型场限环区7。在所述终端保护区4的第一主面1S1上还形成有场氧化层。易于思及的是，所述保护终端也可以为现有技术中的其他保护终端结构，比如，场限环加场板终端结构。在所述场限环终端结构外侧的第一主面1S1侧还形成有N+型终止环15。
所述绝缘栅型晶体管单元为具有第一导电类型的沟道（在此为N型沟道）的MOSFET。具体的说，该N型沟道的MOSFET为DMOS（Double-diffused Metal Oxide Semiconductor，双扩散MOS）结构的MOSFET，其包括：自所述有源区2的第一主面1S1向所述N+型半导体层5内有选择的扩散P型杂质形成的P-body区( 或者称为P基区)8；自P-body区8的表面向该P-body区8内有选择的扩散高浓度的N型杂质形成的N+有源区（或者称为N+发射极区）9；自所述N+有源区9内侧的P-body区8表面向该P-body区8内扩散高浓度的P型杂质形成的P+有源区10；自所述P-body区8的边缘部分的第一主面和所述有源区2的未形成P-body区8的第一主面上形成的栅极氧化层（简称栅氧层）220；在栅极氧化层220的上表面上形成的多晶硅栅电极300；覆盖栅极氧化层220和多晶硅栅电极300露出表面的介质层400，其中，多晶硅栅电极300正下方的P-body区8的部分称为沟道区。
在图2所示的实施例中，所述第二导电类型的第二半导体层6为自所述第二主面1S2向所述N-型半导体衬底1内注入P型杂质形成的P+层（或者称为P+集电极层）。位于所述P+集电极层6和N+型半导体层5之间的N-型半导体衬底1部分为N-型漂移区11。
图2中的绝缘栅双极晶体管还包括：在有源区2的第一主面1S1上覆盖所述介质层400形成的第一主电极（在本实施例中为发射极）12，该第一主电极12与所述N+有源区9和所述P+有源区10电性接触；在第二半导体层6上形成的第二主电极（在本实施例中为集电极）13，该第二主电极13与第二半导体层6电性接触；以及覆盖于第一主电极12和场氧化层14上的用于保护芯片表面不受外界离子玷污的第一钝化层600和第二钝化层700。其中，在本文中，N-、N+、P+中的“+”表示掺杂浓度较高，“-”表示掺杂浓度较低。
与现有技术相比，图2所示的本发明中的绝缘栅双极晶体管在N-型半导体衬底1内的有源区2的第一主面1S1侧形成N+型半导体层5，由于N+型半导体层5的掺杂浓度比半导体衬底1的掺杂浓度高，且绝缘栅型晶体管单元基于N+型半导体层5形成，因此，所述N+型半导体层5不仅增加了JFET区域（参照图1所示）处载流子浓度，降低JFET区域电阻RJ，而且还充当载流子存储层，优化漂移区11的载流子分布，降低漂移区电阻RD，从而降低本发明中的绝缘栅双极晶体管的正向导通压降。 其中，N+型半导体层5在所述有源区2中充当载流子存储层，具体为，当图2中的绝缘栅双极晶体管正向导通时，从第二主面1S2的P+集电极层6注入到N-型漂移区11内的空穴在其扩散的中途受到N+半导体层5形成的势垒的阻挡，使少数载流子空穴蓄积在P-body区8和N+型半导体层5的界面下方附近，根据电中性原理，使得该区域载流子浓度大大增加，从而降低本发明中的绝缘栅双极晶体管的正向导通压降。
在图2所示的实施例中，所述绝缘栅性晶体管单元为DMOS结构的MOSFET，在其他实施例中，其还可以为沟槽型MOSFET或V字形的MOSFET。
图3为图2中的绝缘栅双极晶体管的制造方法在一个实施例中的流程图。结合图2和图3所示，所述制造方法包括如下操作。
步骤210，提供具有第一主面1S1和第二主面1S2的第一导电类型的半导体衬底1，其中，所述半导体衬底1包括有源区2和位于所述有源区2外侧的终端保护区4。
步骤220，在所述半导体衬底1的终端保护区4的第一主面1S1侧形成保护终端。
步骤230，在所述有源区2的第一主面1S1侧形成第一导电类型的第一半导体层5，其中，所述第一半导体层5的掺杂浓度高于半导体衬底1的掺杂浓度。
步骤240，在所述第一半导体层5的第一主面1S1侧形成绝缘栅型晶体管单元。
步骤250，在形成绝缘栅型晶体管单元的有源区2的第一主面1S1上形成第一主电极12；
步骤260，从所述半导体衬底1的第二主面起减薄该绝缘栅型晶体管单元形成后的半导体衬底1，使其符合规定的厚度要求。
步骤270，自减薄后的半导体衬底1的第二主面1S2向所述半导体衬底1内形成第二导电类型的第二半导体层6。
步骤280，在所述第二半导体层6形成后的半导体衬底1的第二主面1S2上形成与第二半导体层6电性接触的第二主电极13。
接下来，以所述第一导电类型为N型，所述第二导电类型为P型为例，结合图4-12详细介绍图2中的绝缘栅双极晶体管在一个具体实施例中的制造方法。所述制造方法包括如下步骤：
步骤一，提供具有第一主面1S1和第二主面1S2的N-型半导体衬底1。
步骤二，如图4所示，在所述N-型半导体衬底1的第一主面1S1上形成预氧层200。
步骤三，如图5所示，在所述终端保护区4的第一主面1S1层形成Stop ring（终止环），即在所述终端保护区4的外侧边缘自第一主面1S1向所述N-型半导体衬底1内进行高浓度N型杂质注入以形成N+型终止环15。具体为，采用Stop ring光刻版在所述预氧层200上进行光刻，磷注入，形成Stop ring。
步骤四，如图6所示，去除光刻胶后，高温氧化，在所述预氧层200上形成场氧层210。
步骤五，如图7所示，通过光刻、刻蚀工艺，选择性的刻蚀所述终端保护区4中的场氧层210以刻蚀出P型场限环区7的注入窗口，并自刻蚀出的该注入窗口向所述N-型半导体衬底1内进行P型扩散以形成P型区域140。具体的，可以采用Ring(环)光刻版，经过涂胶、曝光、湿法腐蚀、去胶等步骤，在所述场氧层210上刻蚀出P型场限环区7的注入窗口，并自刻蚀出的该注入窗口向所述N-型半导体衬底1注入P型杂质（比如，磷），从而在终端保护区1的第一主面1S1侧选择性的形成P型区域140，该P型区域140位于所述终止环内侧。
步骤六，如图8所示，高温推阱形成P型场限环区7。具体的，去除光刻胶后，进行有氧环境推阱形成P型场限环区7，并生成阱氧。
可以看出，步骤二至步骤六为所述终止环15、场氧层210和P型场限环区7的形成过程。
步骤七，如图9所示，在有源区2的第一主面1S1侧制备N+半导体层5。具体为，在所述场氧层210上通过Active(有源区)光刻版进行光刻，注入高浓度的N型杂质，以在有源区2的第一主面1S1侧形成N+半导体层5。
步骤八，如图10所示，高温推阱形成N+半导体层5。具体为，去除光刻胶后，进行长时间高温推阱以形成N+半导体层5。
可以看出，步骤七和步骤八为所述N+半导体层5的形成过程。
步骤九，如图11所示，在N+半导体层5上制备MOS单元的栅极。具体为，湿法刻蚀去除有源区2上的剩余场氧层，依次在N+半导体层5的第一主面1S1上形成栅极氧化层220、淀积多晶硅栅极层300和多晶硅掺杂，并采用Poly（多晶硅）光刻板进行刻蚀形成MOS单元的栅极。
步骤十，如图12所示，利用多晶硅栅300进行自对准硼注入，并进行高温推阱形成Pbody区8。
步骤十一，如图13所示，利用多晶硅栅300进行自对准砷注入，高温退火以在Pbody区3内选择性的形成N+有源区9。
步骤十二，自所述N+有源区9内侧的P-body区8表面向该P-body区8内形成P+有源区10，具体的，淀积氧化层，先后对整个器件进行Spacer腐蚀和硅刻蚀，进行硼注入、高温推阱，以形成P+有源区10。
步骤十三，图14所示，在有源区2的第一主面1S1上淀积形成有覆盖多晶硅栅极300的介质层400。具体为，在有源区2的第一主面1S1上淀积8000A~16000A 的BPSG(硼磷硅玻璃，boro-phospho-silicate-glass，BPSG)，经过850℃~950℃回流，形成介质层400。
可以看出，步骤九至步骤十三为MOS单元的形成过程。
步骤十四，结合图15所示，在形成有MOS单元的有源区2的第一主面1S1上形成第一主电极（在此为发射极）。具体为，通过光刻、刻蚀工艺在有源区2中刻蚀出短接N+有源区和P阱的接触孔，并在有源区2的第一主面1S1上形成覆盖介质层7的露出表面的第一主电极（在此为发射极）金属12。具体为，采用Cont光刻版先后进行孔刻蚀，溅射金属，并采用Metal(金属)光刻版刻蚀金属层，形成金属发射极12。
步骤十五，结合图16所示，在第一主电极金属8和场氧化层13上依次淀积钝化层600和钝化层700。具体为，通过化学气相淀积的方式，在第一主电极金属8和场氧化层13上依次淀积用于保护芯片表面不受外界离子玷污的钝化层600和钝化层700，并通过光刻、刻蚀工艺，刻蚀出用于引出栅电极4和发射极8的PAD（焊盘）区域（未示出）。
步骤十六，结合图17所示，通过背面减薄工艺，将N-型半导体衬底1的厚度减薄，并在减薄后的N-型半导体衬底1的第二主面1S2侧形成P+集电极6，然后在P+集电极6上形成一定厚度的金属层(比如Al-Ti-Ni-Ag)13，此金属层13即为第二主电极（在此实施例中为集电极）。具体的，可以对N-型半导体衬底1进行背面减薄，减薄至所需厚度后，自减薄后的N-型半导体衬底1的第二主面1S2注入剂量为5e12~1e15cm-2能量为60KEV~120KEV的P型杂质，退火激活形成P+集电极6，然后进行背面金属化形成集电极13。
这样就可以制造出图2中的NPT型绝缘栅双极晶体管。普通领域内的技术人员根据上述制造方法的精神，还可以对其进行各种各样的改变或替换。比如，在一个改变的实施例中，可以将步骤六中的高温推结和步骤八中的高温推结合并为步骤八中的一次高温推结过程。步骤三中的离子注入和步骤七中的离子注入可以合并在步骤七中执行，以节省成本。
本发明中的绝缘栅双极晶体管的制造方法，在制备绝缘栅型晶体管单元之前通过增加一次离子注入，在有源区的第一主面1S1侧形成第一导电类型的第一半导体层5，且所述第一半导体层5中的掺杂浓度高于所述半导体衬底1中的掺杂浓度。这样，所述第一半导体层在有源区中不仅增加了JFET区域处载流子浓度，降低JFET区域电阻RJ，而且还充当载流子存储层，优化漂移区的载流子分布，降低漂移区电阻RD，从而降低本发明中的绝缘栅双极晶体管的正向导通压降。
同时，通过Active(有源区)自对准注入的方法形成CE layer(载流子存储层)，不需要增加光刻版数量，且在多晶硅栅制备之前完成高温推结过程，避免了高温过程时多晶硅中的掺杂离子对栅氧及沟道区的影响，解决了热过程中栅氧易被破坏的难题。
在上述实施例中，以所述第一导电类型为N型，所述第二导电类型为P型为例进行介绍，在其他改变的实施例中，也可以使得第一导电类型为P型，所述第二导电类型为N型，此时采用P-型的半导体衬底1，第一半导体层5为P+半导体层，所述绝缘栅型晶体管为P沟道的MOSFET单元，第二主电极13为发射极，第一主电极12为集电极，具体结构和原理与上文的中绝缘栅双极晶体管相似，这里不在赘述。
上述实施例中，是以NPT型绝缘栅双极晶体管进行阐述，本发明同样适用于场阻型绝缘栅双极晶体管。
需要指出的是，熟悉该领域的技术人员对本发明的具体实施方式所做的任何改动均不脱离本发明的权利要求书的范围。相应地，本发明的权利要求的范围也并不仅仅局限于前述具体实施方式。

Claims (12)

  1. 一种绝缘栅双极晶体管，其特征在于，其包括：
    具有第一主面和第二主面的第一导电类型的半导体衬底，其中，所述半导体衬底包括有源区和位于所述有源区外侧的终端保护区；
    形成于所述有源区的第一主面侧的第一导电类型的第一半导体层，其中所述第一半导体层的掺杂浓度高于所述半导体衬底的掺杂浓度；
    形成于第一半导体层的第一主面侧的绝缘栅型晶体管单元，其中所述绝缘栅型晶体管单元导通时，其形成有第一导电类型的沟道。
  2. 根据权利要求1所述的绝缘栅双极晶体管，其特征在于，其还包括：形成于所述终端保护区的第一主面侧的保护终端。
  3. 根据权利要求2所述的绝缘栅双极晶体管，其特征在于，其还包括：
    在所述半导体衬底的第二主面侧形成的第二导电类型的第二半导体层；
    在形成有所述绝缘栅型晶体管单元的第一半导体层的第一主面上形成的第一主电极；
    在所述第二半导体层上形成的第二主电极。
  4. 根据权利要求3所述的绝缘栅双极晶体管，其特征在于，所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，
    所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型半导体衬底，所述第一半导体层为N+型半导体层，所述第二半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极。
  5. 根据权利要求4所述的绝缘栅双极晶体管，其特征在于，所述N型沟道MOSFET单元包括：
    自所述有源区内的N+型半导体层的第一主面向内有选择的形成的P型基区；
    自所述P型基区的表面向该P型基区内有选择的形成的N+有源区；
    自所述N+有源区内侧的P型基区表面向该P型基区内形成的P+有源区；
    自所述P型基区的边缘部分的第一主面和所述有源区内的N+型半导体层的未形成P型基区的第一主面上形成的栅极氧化层；
    在栅极氧化层的上表面上形成的多晶硅栅电极；
    覆盖栅极氧化层和多晶硅栅电极露出表面的介质层；
    其中，第一主电极形成于所述介质层的外侧并与所述N+有源区和所述P+有源区电性接触。
  6. 一种绝缘栅双极晶体管的制造方法，其特征在于，其包括：
    提供具有第一主面和第二主面的第一导电类型的半导体衬底，其中所述半导体衬底包括有源区和位于所述有源区外侧的终端保护区；
    在所述有源区的第一主面侧形成第一导电类型的第一半导体层，其中所述第一半导体层的掺杂浓度高于半导体衬底的掺杂浓度；
    在所述第一半导体层的第一主面侧形成绝缘栅型晶体管单元，其中所述绝缘栅型晶体管单元导通时，其形成有第一导电类型的沟道。
  7. 根据权利要求6所述的绝缘栅双极晶体管的制造方法，其特征在于，其还包括：在所述终端保护内的第一主面侧形成保护终端。
  8. 根据权利要求7所述的绝缘栅双极晶体管的制造方法，其特征在于，其还包括：
    在形成有所述绝缘栅型晶体管单元的第一半导体层的第一主面上形成第一主电极；
    从所述半导体衬底的第二主面起减薄该绝缘栅型晶体管单元形成后的半导体衬底；
    自减薄后的半导体衬底的第二主面向所述半导体衬底内形成第二导电类型的第二半导体层；
    在所述第二半导体层上形成与第二半导体层电性接触的第二主电极。
  9. 根据权利要求8所述的绝缘栅双极晶体管的制造方法，其特征在于，所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，
    所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型半导体衬底，所述第一半导体层为N+型半导体层，所述第二半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极。
  10. 根据权利要求9所述的绝缘栅双极晶体管的制造方法，其特征在于，形成所述N+型半导体层的过程包括：
    在所述N-型半导体衬底的第一主面上形成场氧层；
    透过所述场氧层在所述有源区的第一主面侧进行N型杂质注入以形成N+层；和
    高温推阱形成所述N+型半导体层。
  11. 根据权利要求10所述的绝缘栅双极晶体管的制造方法，其特征在于，
    所述N型沟道MOSFET单元包括：
    自所述有源区内的N+型半导体层的第一主面向内有选择的形成的P型基区；
    自P型基区的表面向该P型基区内有选择的形成的N+有源区；
    自所述N+有源区内侧的P型基区表面向该P型基区内形成的P+有源区；
    自所述P型基区的边缘部分的第一主面和所述有源区内的N+型半导体层的未形成P型基区的第一主面上形成的栅极氧化层；
    在栅极氧化层的上表面上形成的多晶硅栅电极；
    覆盖栅极氧化层和多晶硅栅电极露出表面的介质层；
    其中第一主电极形成于所述介质层的外侧并与所述N+有源区和所述P+有源区电性接触。
  12. 一种绝缘栅双极晶体管的制造方法，其特征在于，其包括：
    步骤一、提供具有第一主面和第二主面的N-型半导体衬底，所述N-型半导体衬底包括有源区和终端保护区；
    步骤二，在所述N-型半导体衬底的第一主面上形成预氧层；
    步骤三、通过基于终止环光刻板的光刻、离子注入在所述终端保护区的第一主面层形成终止环；
    步骤四，高温氧化在所述预氧层上形成场氧层；
    步骤五，通过基于P型场限环区光刻板的光刻、刻蚀、离子注入、高温推阱工艺在所述终端保护区中形成P型场限环区；
    步骤六，通过基于有源区光刻板的光刻、蚀刻、离子注入、高温推阱在所述有源区的第一主面侧制备N+型半导体层；
    步骤七，依次在N+半导体层的第一主面上形成栅极氧化层和淀积多晶硅栅极层；
    步骤八，通过基于多晶硅光刻板进行光刻、刻蚀、多晶硅栅极自对准离子注入、高温推阱形成Pbody区；
    步骤九，多晶硅栅极自对准离子注入以形成N+有源区；
    步骤十，淀积覆盖多晶硅栅极的介质层、形成正面金属电极和钝化层；
    步骤十一、通过背面减薄工艺，将N-型半导体衬底1的厚度减薄，并在减薄后的N-型半导体衬底的第二主面侧形成P+集电极，然后在P+集电极上形成背面金属层。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104992968A (zh) * 2015-06-01 2015-10-21 电子科技大学 一种绝缘栅双极型晶体管及其制造方法
CN112053953A (zh) * 2020-09-29 2020-12-08 上海华虹宏力半导体制造有限公司 绝缘栅双极型晶体管及其制造方法
CN113130628A (zh) * 2021-04-14 2021-07-16 上海擎茂微电子科技有限公司 一种鲁棒性高的半导体装置及其制备方法
CN113707711A (zh) * 2021-08-20 2021-11-26 南瑞联研半导体有限责任公司 一种包含融合电阻的结终端结构及其制造方法
CN117038451A (zh) * 2023-10-09 2023-11-10 深圳市锐骏半导体股份有限公司 沟槽栅igbt器件、制作方法及仿真方法

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Publication number Priority date Publication date Assignee Title
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CN110473913A (zh) * 2019-09-11 2019-11-19 厦门芯达茂微电子有限公司 一种反向导通场截止型igbt及其制作方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1347158A (zh) * 2000-09-28 2002-05-01 株式会社东芝 半导体器件及其制造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19829614B4 (de) * 1998-07-02 2004-09-23 Semikron Elektronik Gmbh Verfahren zur Herstellung eines Leistungshalbleiterbauelementes
JP4422671B2 (ja) * 2005-12-06 2010-02-24 トヨタ自動車株式会社 半導体装置とその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1347158A (zh) * 2000-09-28 2002-05-01 株式会社东芝 半导体器件及其制造方法

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CN104992968B (zh) * 2015-06-01 2018-03-02 电子科技大学 一种绝缘栅双极型晶体管及其制造方法
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