WO2014206189A1 - 场截止型反向导通绝缘栅双极型晶体管及其制造方法 - Google Patents

场截止型反向导通绝缘栅双极型晶体管及其制造方法 Download PDF

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WO2014206189A1
WO2014206189A1 PCT/CN2014/079250 CN2014079250W WO2014206189A1 WO 2014206189 A1 WO2014206189 A1 WO 2014206189A1 CN 2014079250 W CN2014079250 W CN 2014079250W WO 2014206189 A1 WO2014206189 A1 WO 2014206189A1
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layer
type
substrate
bipolar transistor
electric field
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PCT/CN2014/079250
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English (en)
French (fr)
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张硕
芮强
王根毅
邓小社
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无锡华润上华半导体有限公司
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Priority to US14/392,251 priority Critical patent/US10096699B2/en
Priority to EP14816878.4A priority patent/EP3016144B1/en
Publication of WO2014206189A1 publication Critical patent/WO2014206189A1/zh

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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
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Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a field-off type reverse conducting insulated gate bipolar transistor, and a method of fabricating a field-off type reverse conducting insulated gate bipolar transistor.
  • Insulated gate bipolar transistors are generally used in the form of anti-parallel freewheeling diodes.
  • this method wastes the package area on the one hand, and on the other hand, the parallel connection increases the power consumption due to parasitic effects such as parasitic inductance. Therefore, the technology of integrating IGBTs and diodes on the same chip has received increasing attention.
  • the conventional reverse conducting insulated gate bipolar transistor (RC-IGBT) structure has N+ and P+ types on the back side of the entire IGBT.
  • the diode is reversely recovered, the holes stored in the lower portion of the terminal cannot disappear quickly, and the recovery characteristics of the diode must be improved by carrier lifetime control techniques such as irradiation.
  • a field-cut reverse-conducting insulated gate bipolar transistor comprising a peripheral termination structure and an active region surrounded by the termination structure, the substrate of the field-cut reverse-conducting insulated gate bipolar transistor is An N-type substrate having an N-type electric field stop layer on a back surface thereof, a side of the electric field stop layer facing away from the substrate is provided with a back P-type structure, the back P-type structure facing away from the substrate The surface is provided with a back metal layer; the active region is formed with a plurality of notches extending from the back metal layer into the back surface P-type structure into the electric field stop layer, and the back metal layer is filled with metal A metal structure extending into the electric field stop layer is formed in the notch, and the notch and the metal structure extending into the electric field stop layer are not disposed in the terminal structure.
  • a field limiting ring is disposed in the front surface and the terminal structure of the substrate, and the field limiting ring is provided with a silicon oxide layer; and a P well is disposed on the front surface and the active region of the substrate.
  • An N-type emitter is disposed in the P-well, a gate oxide layer is disposed on a front surface of the substrate, a polysilicon gate is disposed on a surface of the gate oxide layer, and the polysilicon gate is coated by the silicon oxide
  • the layer is covered, and the P-well is provided with an emitter metal structure, and the silicon oxide layer and the emitter metal structure are covered with a passivation layer.
  • the electric field stop layer and the emitter are both N+ type, and the back P type structure is P+ type.
  • the back metal layer and the metal structure extending into the electric field stop layer are aluminum-titanium-nickel-silver structures.
  • the field-cut reverse conducting insulated gate bipolar transistor is a planar gate insulated gate bipolar transistor.
  • a method of manufacturing a field-cut reverse-conducting insulated gate bipolar transistor comprising the steps of: Step A, providing an N-type substrate, using one side of the substrate as a back surface, and forming an N-type electric field on the back surface a termination layer; step B, performing a first-stage front side process; forming a withstand voltage structure in a terminal structure region on a periphery of a front surface of the substrate of the field-cut reverse-conducting insulated gate bipolar transistor, surrounded by the terminal structure a front surface of the substrate of the active region region forms a gate oxide layer, and a polysilicon gate forming a surface of the gate oxide layer, and a P well is formed in a front surface of the substrate and in the active region region, in the P well Forming an N-type emitter to form a silicon oxide layer covering the front surface of the substrate and the polysilicon gate; and step C, forming a back surface P-type structure on a side of the electric field stop layer facing away from the substrate; Step
  • the step B includes: implanting a P-type impurity on the front surface of the substrate by photolithography, forming a field limiting ring as a withstand voltage structure after thermal diffusion; and growing the front surface of the substrate Oxidizing the layer, and photolithography and etching away the field oxide layer on the active region; growing a gate oxide layer on the front side of the substrate, and forming a polysilicon layer on the surface of the gate oxide layer; photolithography and engraving Etching to remove excess polysilicon layer and gate oxide layer, forming a polysilicon gate, and ion-implanting P-type impurities into the substrate by a self-aligned implantation process, forming a P-well after pushing the well; photolithography and Injecting N-type ions into the P well to form the emitter; depositing an oxide dielectric layer, the field oxide layer and the deposited oxide dielectric layer constituting the front surface of the substrate and the oxidation of the polysilicon gate Silicon layer.
  • the step of growing the gate oxide layer on the front side of the substrate in the step B is to grow a gate oxide layer of 600 ⁇ to 1500 ⁇ thick.
  • the step E is to form a notch through the back surface P-type structure into the electric field termination layer in the active region region by photolithography and etching, and through a sputtering process.
  • Forming the back metal layer and the metal structure extending into the electric field stop layer; the electric field stop layer and the emitter are both N+ type, and the back P type structure is P+ type.
  • step C further comprising the step of forming a front protective layer on the silicon oxide layer; after the step C, before the step D, further comprising removing the front protective layer step.
  • the field-cut reverse-conducting insulated gate bipolar transistor does not form a metal structure extending into the electric field stop layer in the termination structure. Thus, when the diode is turned on, only a small part of the holes flow through the drift region in the termination structure, which reduces the recovery current when the built-in diode is restored, and improves the reverse recovery capability of the built-in diode.
  • FIG. 1 is a top plan view showing a termination structure and an active region of a field-off type reverse conducting insulated gate bipolar transistor according to an embodiment
  • FIG. 2 is a cross-sectional view showing a field-off type reverse conducting insulated gate bipolar transistor in an embodiment
  • FIG. 3 is a flow chart showing a method of fabricating a field-off type reverse conducting insulated gate bipolar transistor in an embodiment
  • 4A-4K are cross-sectional views showing a field-cut reverse conducting insulated gate bipolar transistor in a manufacturing process in an embodiment
  • FIG. 5 is a specific flowchart of step S320 in an embodiment.
  • FIG. 1 is a top plan view showing a termination structure and an active region of a field-cut reverse-conducting insulated gate bipolar transistor according to an embodiment
  • FIG. 2 is a cross-sectional view of a field-cut reverse conducting insulated gate bipolar transistor in an embodiment.
  • the field stop type reverse conducting insulated gate bipolar transistor includes a peripheral termination structure 200 and an active region 100 surrounded by the termination structure 200.
  • the substrate of the field-cut reverse conducting insulated gate bipolar transistor is an N-type substrate.
  • An N-type electric field stop layer 1 ie, a field stop layer
  • the doping concentration of the electric field stop layer 1 is greater than the doping concentration of the substrate.
  • the back side of the electric field stop layer 1 facing away from the substrate is provided with a back P-type structure 10.
  • a back metal layer 12 is provided on the surface of the back P-type structure 10 facing away from the substrate.
  • the back metal layer 12 has a structure of Al-Ti-Ni-Ag.
  • a plurality of metal structures are formed in the active region 100 from the back metal layer 12 through the back surface P-type structure 10 to the electric field stop layer 1.
  • the metal structure is formed first through the back surface P-type structure 10 to the trench in the electric field stop layer 1. After the mouth, the back surface metal layer 12 is filled into the notch.
  • the slot structure and the metal structure extending into the electric field stop layer 1 are not provided in the terminal structure 200.
  • the field stop type reverse conducting insulated gate bipolar transistor does not form a metal structure extending into the electric field stop layer 1 in the termination structure 200. Thus, when the diode is turned on, only a small part of the holes flow through the drift region in the termination structure 200, which reduces the recovery current when the built-in diode is restored, and improves the reverse recovery capability of the built-in diode.
  • FIG. 2 illustrates a structure of an IGBT by taking a planar gate insulated gate bipolar transistor as an example. It can be understood that the above-mentioned metal structure extending only into the electric field stop layer 1 in the active region 100 is formed. The structure is equally applicable to Trench gate IGBTs.
  • a P-type field limiting ring 2 is provided in the front surface and terminal structure 200 of the substrate.
  • a plurality of field limit rings 2 can be provided, and the number thereof is omitted in FIG.
  • a field oxide layer 14 and an oxide dielectric layer 7 are disposed on the field limiting ring 2, and the field oxide layer 14 and the oxide dielectric layer 7 constitute a silicon oxide layer.
  • a P well 5 is disposed in the front surface of the substrate, in the active region 100, and an N-type emitter 6 is disposed in the P well 5.
  • a gate oxide layer 3 is provided on the front surface of the substrate, and a polysilicon gate 4 is provided on the surface of the gate oxide layer 3.
  • the polysilicon gate 4 is also covered by a silicon oxide layer (oxide dielectric layer 7).
  • the polysilicon gate 4 is disposed between the adjacent two P wells 5 and between a P well 5 and the field limiting ring 2 at the junction of the active region 100 and the termination structure 200.
  • the P well 5 is provided with an emitter metal structure 8, and the silicon oxide layer and the emitter metal structure 8 are covered with a passivation layer 9.
  • the function of the passivation layer 9 is to protect the surface of the chip from external ions.
  • the material of the passivation layer 9 is SiN.
  • the electric field stop layer 1 and the emitter 6 are both of the N+ type, and the back P type structure 10 is of the P+ type.
  • a method for fabricating the above field-cut reverse conducting insulated gate bipolar transistor includes the following steps:
  • an N-type substrate is provided, and an N-type electric field stop layer is formed on the back surface of the N-type substrate.
  • the doping concentration of the N+ electric field stop layer 1 is greater than the doping concentration of the substrate.
  • Step S320 specifically includes forming a withstand voltage structure in a region of the terminal structure 200 on the periphery of the front surface of the substrate of the field-cut reverse-conducting insulated gate bipolar transistor.
  • a gate oxide layer 3 is formed on the front surface of the substrate in the region of the active region 100 surrounded by the termination structure 200, and a polysilicon gate 4 is formed on the surface of the gate oxide layer 3.
  • a P well 5 is formed in the front surface of the substrate and in the region of the active region 100.
  • An N-type emitter 6 is formed in the P well 5.
  • a silicon oxide layer covering the front side of the substrate and the polysilicon gate is formed.
  • the silicon oxide layer is composed of a field oxide layer 14 and an oxide dielectric layer 7.
  • a step of forming the front surface protective layer 13 on the silicon oxide layer is further included.
  • 4G is a schematic cross-sectional view of the field-off type reverse conducting insulated gate bipolar transistor after completion of step S330.
  • the front protective layer 13 needs to be removed.
  • 4J is a schematic cross-sectional view of the field-off type reverse conducting insulated gate bipolar transistor after completion of step S340.
  • the second stage front surface process specifically includes photolithography and etching of the oxide dielectric layer 7, partially exposing the P well 5 and the emitter 6 to form a contact hole, filling the contact hole with the emitter metal structure 8, and then forming a passivation layer.
  • the emitter metal structure 8 is disposed on the P well 5, and the passivation layer 9 is overlying the silicon oxide layer and the emitter metal structure 8.
  • the function of the passivation layer 9 is to protect the surface of the chip from external ions.
  • the material of the passivation layer 9 is SiN.
  • the notch 11 is formed, and then the back metal layer 12 is filled to form a metal structure extending into the electric field stop layer 1, as shown in FIG.
  • the back metal layer 12 has a structure of Al-Ti-Ni-Ag.
  • the back surface lithography is generally performed twice after the front side process is completed. That is, a lithography, implantation, and diffusion are first performed to form a P+ type region, and then photolithography, implantation, and diffusion are performed to form an N+ type region. Since the formation of the metal layer has been completed in the front side process, the subsequent annealing process can only use a lower temperature, and it is difficult to obtain a better annealing effect.
  • the above-described field-cut reverse-conducting insulated gate bipolar transistor manufacturing method adopts a front-end process in two steps to advance the fabrication of the back-side P-type structure 10 to the metal layer of the front side process (ie, the emitter metal structure 8).
  • the emitter metal structure 8 the metal layer of the front side process
  • S320 specifically includes the following steps:
  • a P-type impurity is implanted on the front surface of the substrate by photolithography, and the field-limiting ring 2 is formed as a withstand voltage structure after thermal diffusion.
  • a field limiting ring is used as the withstand voltage structure.
  • the field plate may be used as the withstand voltage structure, or the field limiting ring + field plate withstand voltage structure, or other terminal withstand voltage structure.
  • 4B is a schematic cross-sectional view of the field-off type reverse conducting insulated gate bipolar transistor after completion of step S322.
  • FIG. 4C is a schematic cross-sectional view of the field-off type reverse conducting insulated gate bipolar transistor after completion of step S323.
  • a gate oxide layer 3 of 600 ⁇ to 1500 ⁇ thick is grown by thermal oxidation, and then a polysilicon layer 4 is formed on the surface of the gate oxide layer 3.
  • 4D is a schematic cross-sectional view of the field-off type reverse conducting insulated gate bipolar transistor after completion of step S324.
  • the P well 5 is formed by ion implantation by a self-aligned implantation process.
  • 4E is a schematic cross-sectional view of the field-off type reverse conducting insulated gate bipolar transistor after completion of step S325. After the N+ implantation window is formed by photolithography, the N+ emitter 6 is formed by ion implantation and push-trap.
  • the foregoing front protective layer 13 is formed by depositing an oxide dielectric layer 7 and then passing through a furnace tube. Therefore, the back side of the wafer also forms a protective layer, and it is necessary to remove the back surface before performing step S330.
  • step S330 is performed.
  • P-type ions can be implanted after photolithography to form a P+ backside P-type structure 10.
  • the emitter metal structure 8 is formed by a sputtering process, and a part of excess metal needs to be removed by photolithography and etching processes.
  • the passivation layer 9 is formed by a chemical vapor deposition process, and a pad (PAD) region for extracting the gate electrode and the emitter electrode is required to be photolithographically and etched. (Not shown in Figure 4J).
  • the notch 11 in Fig. 4K can be formed by photolithography etching. By adjusting the width and depth of the notch 11, the characteristics of the IGBT and its built-in diode can be adjusted to make it compromise.

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Abstract

一种场截止型反向导通绝缘栅双极型晶体管及其制造方法，包括终端结构（200）和有源区（100），场截止型反向导通绝缘栅双极型晶体管的衬底为N型衬底，衬底的背面设有N型的电场终止层（1），电场终止层背离衬底的一面设有背面P型结构（10），背面P型结构的表面设有背面金属层（12）；有源区（100）内形成有多个从背面金属层（12）贯穿背面P型结构（10）至电场终止层（1）内的槽口（11），背面金属层（12）的金属填充入槽口（11）中形成伸入电场终止层（1）的金属结构。

Description

场截止型反向导通绝缘栅双极型晶体管及其制造方法
【技术领域】
本发明涉及半导体器件的制造方法，特别是涉及一种场截止型反向导通绝缘栅双极型晶体管，还涉及一种场截止型反向导通绝缘栅双极型晶体管的制造方法。
【背景技术】
绝缘栅双极型晶体管（IGBT）一般采用反向并联续流二极管的方式使用。但这种方式一方面浪费封装面积，另一方面由于寄生电感等寄生效应的存在，并联额外增加了功耗。因此，将IGBT与二极管集成在同一个芯片的技术日益受到重视。
传统的反向导通绝缘栅双极型晶体管（RC-IGBT）结构背面N+型和P+型遍布整个IGBT背面区域。二极管导通时由正极（IGBT发射极）注入的大量空穴，一部分通过终端部分的N-漂移区进入到阴极。当二极管反向恢复时，存储于终端下方部分的空穴无法空过迅速消失，必须通过辐照等载流子寿命控制技术来改善二极管的恢复特性。
【发明内容】
基于此，有必要提供一种反向恢复特性较好的场截止型反向导通绝缘栅双极型晶体管。
一种场截止型反向导通绝缘栅双极型晶体管，包括外围的终端结构和被所述终端结构包围的有源区，所述场截止型反向导通绝缘栅双极型晶体管的衬底为N型衬底，所述衬底的背面设有N型的电场终止层，所述电场终止层背离所述衬底的一面设有背面P型结构，所述背面P型结构背离所述衬底的表面设有背面金属层；所述有源区内形成有多个从背面金属层贯穿所述背面P型结构至所述电场终止层内的槽口，所述背面金属层的金属填充入所述槽口中形成伸入电场终止层的金属结构，所述终端结构内不设置所述槽口和所述伸入电场终止层的金属结构。
在其中一个实施例中，所述衬底的正面、终端结构内设有场限环，所述场限环上设有氧化硅层；所述衬底的正面、有源区内设有P阱，所述P阱内设有N型的发射极，所述衬底的正表面设有栅氧化层，所述栅氧化层的表面设有多晶硅栅极，所述多晶硅栅极被所述氧化硅层覆盖，所述P阱上设有发射极金属结构，所述氧化硅层和发射极金属结构上覆盖有钝化层。
在其中一个实施例中，所述电场终止层和发射极均为N+型，所述背面P型结构是P+型。
在其中一个实施例中，所述背面金属层和伸入电场终止层的金属结构是铝-钛-镍-银结构。
在其中一个实施例中，所述场截止型反向导通绝缘栅双极型晶体管是平面栅极绝缘栅双极型晶体管。
还有必要提供一种场截止型反向导通绝缘栅双极型晶体管的制造方法。
一种场截止型反向导通绝缘栅双极型晶体管的制造方法，包括下列步骤：步骤A，提供N型衬底，将所述衬底的一面作为背面，在所述背面形成N型的电场终止层；步骤B，进行第一阶段正面工艺；包括在所述场截止型反向导通绝缘栅双极型晶体管的衬底正面外围的终端结构区域形成耐压结构，在被所述终端结构包围的有源区区域的衬底的正表面形成栅氧化层、及形成栅氧化层表面的多晶硅栅极，在衬底的正面、所述有源区区域内形成P阱，在所述P阱内形成N型的发射极，形成覆盖所述衬底的正面和所述多晶硅栅极的氧化硅层；步骤C，在所述电场终止层背离所述衬底的一面形成背面P型结构； 步骤D，进行第二阶段正面工艺；包括光刻和刻蚀所述氧化硅层，形成使所述P阱和发射极呈部分露出的接触孔，向所述接触孔内填入发射极金属结构，形成覆盖所述氧化硅层和发射极金属结构的钝化层；步骤E，在所述有源区区域内形成贯穿所述背面P型结构至所述电场终止层内的槽口，并形成背面金属层，所述背面金属层填充入所述槽口中形成伸入电场终止层的金属结构。
在其中一个实施例中，所述步骤B包括：通过光刻在所述衬底正面注入P型杂质，热扩散后形成场限环作为所述耐压结构；在所述衬底的正面生长场氧化层，并光刻和刻蚀掉所述有源区区域上的场氧化层；在所述衬底的正面生长栅氧化层，并在所述栅氧化层表面形成多晶硅层；光刻和刻蚀去除多余的多晶硅层和栅氧化层，形成多晶硅栅极，并通过自对准注入工艺向所述衬底内离子注入P型杂质，推阱后形成所述P阱；光刻并向所述P阱内注入N型离子形成所述发射极；淀积氧化物介质层，所述场氧化层和淀积氧化物介质层组成所述覆盖所述衬底的正面和所述多晶硅栅极的氧化硅层。
在其中一个实施例中，所述步骤B中在所述衬底的正面生长栅氧化层的步骤是生长600埃~1500埃厚的栅氧化层。
在其中一个实施例中，所述步骤E是通过光刻和刻蚀在所述有源区区域内形成贯穿所述背面P型结构至所述电场终止层内的槽口，并通过溅射工艺形成所述背面金属层和所述伸入电场终止层的金属结构；所述电场终止层和发射极均为N+型，所述背面P型结构是P+型。
在其中一个实施例中，所述步骤C之前，还包括在所述氧化硅层上形成正面保护层的步骤；所述步骤C之后，所述步骤D之前，还包括去除所述正面保护层的步骤。
上述场截止型反向导通绝缘栅双极型晶体管，在终端结构内不形成伸入电场终止层的金属结构。这样当二极管导通时，只会有很少的一部分空穴流过终端结构内的漂移区，减小了内置二极管恢复时的恢复电流的大小，改善了内置二极管的反向恢复能力。
【附图说明】
图1是一实施例中场截止型反向导通绝缘栅双极型晶体管终端结构和有源区的俯视示意图；
图2是一实施例中场截止型反向导通绝缘栅双极型晶体管的剖面示意图；
图3是一实施例中场截止型反向导通绝缘栅双极型晶体管的制造方法的流程图；
图4A~4K是一实施例中场截止型反向导通绝缘栅双极型晶体管在制造过程中的剖面示意图；
图5是一实施例中步骤S320的具体流程图。
【具体实施方式】
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
图1是一实施例中场截止型反向导通绝缘栅双极型晶体管终端结构和有源区的俯视示意图，图2是一实施例中场截止型反向导通绝缘栅双极型晶体管的剖面示意图。场截止型反向导通绝缘栅双极型晶体管包括外围的终端结构200和被终端结构200包围的有源区100。在图2所示实施例中，场截止型反向导通绝缘栅双极型晶体管的衬底为N型衬底。衬底的背面设有N型的电场终止层1（即场截止层），电场终止层1的掺杂浓度大于衬底的掺杂浓度。电场终止层1背离衬底的一面设有背面P型结构10。背面P型结构10背离衬底的表面设有背面金属层12。在本实施例中，背面金属层12采用Al-Ti-Ni-Ag的结构。有源区100内形成有多个从背面金属层12贯穿背面P型结构10至电场终止层1内的金属结构，该金属结构是先形成贯穿背面P型结构10至电场终止层1内的槽口后，向槽口内填入背面金属层12形成的。终端结构200内不设置槽口和伸入电场终止层1的该金属结构。
上述场截止型反向导通绝缘栅双极型晶体管，在终端结构200内不形成伸入电场终止层1的金属结构。这样当二极管导通时，只会有很少的一部分空穴流过终端结构200内的漂移区，减小了内置二极管恢复时的恢复电流的大小，改善了内置二极管的反向恢复能力。
图2所示实施例是以平面栅极绝缘栅双极型晶体管为例对IGBT的结构进行说明，可以理解的，上述仅于有源区100内形成伸入电场终止层1的金属结构的背面结构，同样适用于沟槽（Trench）栅极IGBT。
参照图2，衬底的正面、终端结构200内设有P型的场限环2。场限环2可以设置多个，图2中将其数量进行了省略。场限环2上设有场氧化层14和氧化物介质层7，场氧化层14和氧化物介质层7组成氧化硅层。
衬底的正面、有源区100内设有P阱5，P阱5内设有N型的发射极6。衬底的正表面设有栅氧化层3，栅氧化层3的表面设有多晶硅栅极4，多晶硅栅极4同样被氧化硅层（氧化物介质层7）覆盖。多晶硅栅极4设于相邻的两个P阱5之间，及有源区100和终端结构200交界处的一个P阱5和场限环2之间。P阱5上设有发射极金属结构8，氧化硅层和发射极金属结构8上覆盖有钝化层9。钝化层9的作用是保护芯片表面不受外界离子污染，在本实施例中钝化层9的材质为SiN。
在图2所示实施例中，电场终止层1和发射极6均为N+型，背面P型结构10是P+型。
如图3所示，一种制造上述的场截止型反向导通绝缘栅双极型晶体管的方法，包括下列步骤：
S310，提供N型衬底，在N型衬底的背面形成N型的电场终止层。
参照图4A，在本实施例中，N+电场终止层1的掺杂浓度大于衬底的掺杂浓度。
S320，进行第一阶段正面工艺。
图4F是步骤S320完成后场截止型反向导通绝缘栅双极型晶体管的剖面示意图。步骤S320具体包括：在场截止型反向导通绝缘栅双极型晶体管的衬底正面外围的终端结构200区域形成耐压结构。在被终端结构200包围的有源区100区域的衬底的正表面形成栅氧化层3，及在栅氧化层3表面形成多晶硅栅极4。在衬底的正面、有源区100区域内形成P阱5。在P阱5内形成N型的发射极6。形成覆盖衬底的正面和多晶硅栅极的氧化硅层。氧化硅层由场氧化层14和氧化物介质层7组成。
在图4F所示的实施例中，为了保护圆片（wafer）在进行背面工艺时不损伤其正面结构，在形成氧化硅层后，还包括在氧化硅层上形成正面保护层13的步骤。
S330，在电场终止层背离衬底的一面形成背面P型结构。
图4G是步骤S330完成后场截止型反向导通绝缘栅双极型晶体管的剖面示意图。
参照图4H，步骤S330完成后还需要去除正面保护层13。
S340，进行第二阶段正面工艺。
图4J是步骤S340完成后场截止型反向导通绝缘栅双极型晶体管的剖面示意图。第二阶段正面工艺具体包括光刻和刻蚀氧化物介质层7，使P阱5和发射极6呈部分露出形成接触孔，向接触孔内填入发射极金属结构8，然后形成钝化层9。发射极金属结构8设于P阱5上，钝化层9覆盖于氧化硅层和发射极金属结构8上。钝化层9的作用是保护芯片表面不受外界离子污染，在本实施例中钝化层9的材质为SiN。
S350，在有源区内形成贯穿背面P型结构至电场终止层内的槽口，并填充背面金属层。
参照图4K，形成槽口11，然后填充背面金属层12，形成伸入电场终止层1的金属结构，如图2所示。在本实施例中，背面金属层12采用Al-Ti-Ni-Ag的结构。
采用上述场截止型反向导通绝缘栅双极型晶体管制造方法制造的器件，在终端结构200内不形成伸入电场终止层1的金属结构。这样当二极管导通时，只会有很少的一部分空穴流过终端结构200内的漂移区，减小了内置二极管恢复时的恢复电流的大小，改善了内置二极管的反向恢复能力。
另一方面，传统技术中RC-IGBT的制造工艺，一般在正面工艺完成以后进行两次背面光刻。即先进行一次光刻、注入和扩散形成P+型区域，然后再进行一次光刻、注入和扩散形成N+型区域。由于正面工艺中已完成了金属层的形成，因此后续的退火工艺只能采用较低的温度，难以获得较好的退火效果。
而上述场截止型反向导通绝缘栅双极型晶体管制造方法，采用正面工艺分两步完成的方式，将背面P型结构10的制作提前到正面工艺的金属层（即发射极金属结构8）之前，因此可以在形成发射极金属结构8之前，采用较高的温度进行退火，获得较高的背面注入离子的激活率。
参见图5，在其中一个实施例中， S320具体包括如下的步骤：
S321，通过光刻在衬底正面注入P型杂质，热扩散后形成场限环2作为耐压结构。
本实施例中采用场限环作为耐压结构，在其它实施例中也可以采用场板作为耐压结构，或者场限环+场板的耐压结构，又或者其它的终端耐压结构。
S322，在衬底的正面生长场氧化层14，并光刻和刻蚀掉有源区区域上的场氧化层14。
图4B是步骤S322完成后场截止型反向导通绝缘栅双极型晶体管的剖面示意图。
S323，在衬底的正面生长栅氧化层，并在栅氧化层表面形成多晶硅层。
图4C是步骤S323完成后场截止型反向导通绝缘栅双极型晶体管的剖面示意图。在本实施例中，是通过热氧化生长600Ǻ~1500Ǻ厚的栅氧化层3，然后在栅氧化层3表面淀积形成多晶硅层4。
S324，光刻和刻蚀去除多余的多晶硅和栅氧化层，形成多晶硅栅极，并向衬底内离子注入P型杂质，推阱后形成P阱。
图4D是步骤S324完成后场截止型反向导通绝缘栅双极型晶体管的剖面示意图。在本实施例中，是通过自对准注入工艺进行离子注入，形成P阱5。
S325，光刻并向P阱内注入N型离子形成发射极。
图4E是步骤S325完成后场截止型反向导通绝缘栅双极型晶体管的剖面示意图。通过光刻形成N+注入窗口后，通过离子注入和推阱形成N+发射极6。
S326，形成覆盖衬底的正面和多晶硅栅极的氧化物介质层。
在本实施例中，是通过淀积形成氧化物介质层7，然后通过炉管的方式形成前述的正面保护层13。因此，圆片的背面同样会形成保护层，需要在进行步骤S330之前将背面的去除掉。
步骤S326完成后执行步骤S330。参见图4F和图4G，可以光刻后注入P型离子，形成P+的背面P型结构10。
参见图4I，在本实施例中，发射极金属结构8是通过溅射工艺形成，并且需要通过光刻和刻蚀工艺去除部分多余的金属。
参见图4J，在本实施例中，钝化层9是通过化学气相淀积的工艺形成的，并且需要通过光刻和刻蚀出用于引出栅电极和发射极电极的焊盘（PAD）区域（图4J中未示）。
图4K中的槽口11可以通过光刻后刻蚀形成。通过调整槽口11的宽度和深度能够调整IGBT及其内置二极管的特性使其折中。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种场截止型反向导通绝缘栅双极型晶体管，包括外围的终端结构和被所述终端结构包围的有源区，所述场截止型反向导通绝缘栅双极型晶体管的衬底为N型衬底，所述衬底的背面设有N型的电场终止层，所述电场终止层背离所述衬底的一面设有背面P型结构，所述背面P型结构背离所述衬底的表面设有背面金属层；
    其特征在于，所述有源区内形成有多个从背面金属层贯穿所述背面P型结构至所述电场终止层内的槽口，所述背面金属层的金属填充入所述槽口中形成伸入电场终止层的金属结构，所述终端结构内不设置所述槽口和所述伸入电场终止层的金属结构。
  2. 根据权利要求1所述的场截止型反向导通绝缘栅双极型晶体管，其特征在于，所述衬底的正面、终端结构内设有场限环，所述场限环上设有氧化硅层；
    所述衬底的正面、有源区内设有P阱，所述P阱内设有N型的发射极，所述衬底的正表面设有栅氧化层，所述栅氧化层的表面设有多晶硅栅极，所述多晶硅栅极被所述氧化硅层覆盖，所述P阱上设有发射极金属结构，所述氧化硅层和发射极金属结构上覆盖有钝化层。
  3. 根据权利要求2所述的场截止型反向导通绝缘栅双极型晶体管，其特征在于，所述电场终止层和发射极均为N+型，所述背面P型结构是P+型。
  4. 根据权利要求1所述的场截止型反向导通绝缘栅双极型晶体管，其特征在于，所述背面金属层和伸入电场终止层的金属结构是铝-钛-镍-银结构。
  5. 根据权利要求1所述的场截止型反向导通绝缘栅双极型晶体管，其特征在于，所述场截止型反向导通绝缘栅双极型晶体管是平面栅极绝缘栅双极型晶体管。
  6. 一种场截止型反向导通绝缘栅双极型晶体管的制造方法，包括下列步骤：
    步骤A，提供N型衬底，将所述衬底的一面作为背面，在所述背面形成N型的电场终止层；
    步骤B，进行第一阶段正面工艺；包括在所述场截止型反向导通绝缘栅双极型晶体管的衬底正面外围的终端结构区域形成耐压结构，在被所述终端结构包围的有源区区域的衬底的正表面形成栅氧化层、及形成栅氧化层表面的多晶硅栅极，在衬底的正面、所述有源区区域内形成P阱，在所述P阱内形成N型的发射极，形成覆盖所述衬底的正面和所述多晶硅栅极的氧化硅层；
    步骤C，在所述电场终止层背离所述衬底的一面形成背面P型结构；
    步骤D，进行第二阶段正面工艺；包括光刻和刻蚀所述氧化硅层，形成使所述P阱和发射极呈部分露出的接触孔，向所述接触孔内填入发射极金属结构，形成覆盖所述氧化硅层和发射极金属结构的钝化层；及
    步骤E，在所述有源区区域内形成贯穿所述背面P型结构至所述电场终止层内的槽口，并形成背面金属层，所述背面金属层填充入所述槽口中形成伸入电场终止层的金属结构。
  7. 根据权利要求6所述的场截止型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，所述步骤B包括：
    通过光刻在所述衬底正面注入P型杂质，热扩散后形成场限环作为所述耐压结构；
    在所述衬底的正面生长场氧化层，并光刻和刻蚀掉所述有源区区域上的场氧化层；
    在所述衬底的正面生长栅氧化层，并在所述栅氧化层表面形成多晶硅层；
    光刻和刻蚀去除多余的多晶硅层和栅氧化层，形成多晶硅栅极，并通过自对准注入工艺向所述衬底内离子注入P型杂质，推阱后形成所述P阱；
    光刻并向所述P阱内注入N型离子形成所述发射极；
    淀积氧化物介质层，所述场氧化层和淀积氧化物介质层组成所述覆盖所述衬底的正面和所述多晶硅栅极的氧化硅层。
  8. 根据权利要求7所述的场截止型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，所述步骤B中在所述衬底的正面生长栅氧化层的步骤是生长600埃~1500埃厚的栅氧化层。
  9. 根据权利要求7所述的场截止型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，所述步骤E是通过光刻和刻蚀在所述有源区区域内形成贯穿所述背面P型结构至所述电场终止层内的槽口，并通过溅射工艺形成所述背面金属层和所述伸入电场终止层的金属结构；
    所述电场终止层和发射极均为N+型，所述背面P型结构是P+型。
  10. 根据权利要求6所述的场截止型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，所述步骤C之前，还包括在所述氧化硅层上形成正面保护层的步骤；所述步骤C之后，所述步骤D之前，还包括去除所述正面保护层的步骤。
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