WO2015027881A1 - 绝缘栅双极型晶体管的制备方法 - Google Patents

绝缘栅双极型晶体管的制备方法 Download PDF

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WO2015027881A1
WO2015027881A1 PCT/CN2014/085094 CN2014085094W WO2015027881A1 WO 2015027881 A1 WO2015027881 A1 WO 2015027881A1 CN 2014085094 W CN2014085094 W CN 2014085094W WO 2015027881 A1 WO2015027881 A1 WO 2015027881A1
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Prior art keywords
type
region
polysilicon
forming
bipolar transistor
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PCT/CN2014/085094
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English (en)
French (fr)
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钟圣荣
周东飞
邓小社
王根毅
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无锡华润上华半导体有限公司
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Priority to EP14839057.8A priority Critical patent/EP3041036B1/en
Priority to US14/902,432 priority patent/US9590029B2/en
Publication of WO2015027881A1 publication Critical patent/WO2015027881A1/zh

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Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating an insulated gate bipolar transistor.
  • IGBT Insulated Gate Bipolar Transistor
  • BJT bipolar transistor
  • MOS metal oxide semiconductor field effect transistor
  • Conventional insulated gate bipolar transistors have a high turn-on voltage drop.
  • a method for fabricating an insulated gate bipolar transistor comprising: providing a substrate, forming a field oxide layer on a front surface of the substrate, photolithography using a termination protection ring, and etching the field oxide layer P-type ions are implanted into the substrate under the etched region to form a termination protection ring; photolithographic plates are used to lithographically etch and etch away the field oxide layer in the active region region, using photoresist as The masking film injects N-type ions into the substrate, deposits polysilicon on the substrate on which the field oxide layer is etched, forms a protective layer on the deposited polysilicon, and lithography and etching with polysilicon lithography Etching excess polysilicon and protective layer to form a polysilicon gate, and then forming a carrier enhancement region by pushing the implanted region of the N-type ion; or etching and etching away the active region region by using an active region lithography
  • the field oxide layer is filled with N-type ions into the
  • the polysilicon and the protective layer form a polysilicon gate; the P-well photolithography lithography is used to implant P-type ions into the carrier enhancement region, and the P-type body region is formed after the junction; the polysilicon gate is applied to the P-type body region.
  • Self-aligned implantation of N-type ions formation of N-type heavily doped regions after push-bonding; formation of sidewalls on both sides of the polysilicon gate, injection of P-type ions into the N-type heavily doped regions, and formation of P-type after push-knotting a heavily doped region; after removing the protective layer, performing polysilicon implant doping on the polysilicon gate; forming an interlayer dielectric, performing a front metallization process of the insulated gate bipolar transistor, performing backside thinning, P-type ion implantation, and Annealing process, and back metallization process of insulated gate bipolar transistor.
  • the method further includes: The step of etching to form the pit region is performed, and the pit region is recessed inwardly to a depth of 0.15 ⁇ m to 0.3 ⁇ m with respect to the substrates on both sides.
  • the step of forming a protective layer on the deposited polysilicon includes forming a first oxide layer on the surface of the polysilicon and depositing a silicon nitride layer on a surface of the first oxide layer.
  • the performing a front side metallization process of the insulated gate bipolar transistor further includes the step of performing a P-type ion implantation into the P-type heavily doped region.
  • the P-type ions are boron ions;
  • the N-type ions are phosphorus ions; and the step of photolithography using a P-well photolithography and injecting P-type ions into the carrier enhancement region
  • the P-type ion is a boron ion; in the step of performing a self-aligned injection of an N-type ion into the P-type body region by the polysilicon gate, the N-type ion is an arsenic ion; the N-type heavily doped
  • the P-type ions are boron ions; in the step of removing the protective layer and performing doping implantation into the polysilicon gate, the implanted ions are phosphorus ions.
  • the step of forming sidewalls on both sides of the polysilicon gate includes: depositing a second oxide layer, and then removing excess of the second oxide layer by etching, the remaining second oxide layer forming the Side wall.
  • the step of performing a front side metallization process of the insulated gate bipolar transistor includes photolithographically etching a contact hole with a contact hole lithography plate and sputtering conductive on the interlayer dielectric The metal is then photolithographically etched using a metal lithography and the sputtered metal is etched to form a metal wiring layer overlying the interlayer dielectric.
  • the material of the substrate is one of silicon, silicon carbide, gallium arsenide, indium phosphide or germanium silicon.
  • the substrate is made of single crystal silicon having a crystal orientation of ⁇ 100>.
  • the step of forming the interlayer dielectric is to deposit borophosphosilicate glass and perform thermal reflow to form an interlayer dielectric covering the polysilicon gate surface and the sidewall surface.
  • N-type ions are implanted to increase a carrier concentration in the channel.
  • a carrier enhancement region is formed, thereby reducing the conduction voltage drop.
  • FIG. 1 is a schematic structural view of an insulated gate bipolar transistor according to an embodiment
  • FIG. 2 is a flow chart showing a method of fabricating an insulated gate bipolar transistor in an embodiment
  • 3A-3F are partial cross-sectional views of an insulated gate bipolar transistor prepared by a method for fabricating an insulated gate bipolar transistor in an embodiment.
  • FIG. 1 is a schematic structural view of an insulated gate bipolar transistor 100 according to an embodiment, including a peripheral termination structure (not shown in FIG. 1) and an active region surrounded by the termination structure.
  • the substrate of the insulated gate bipolar transistor 100 is an N-type substrate 10, a P-type region 16 is disposed on the back surface of the substrate 10, a back metal structure 18 is disposed on the back surface of the P-type region 16, and a terminal protection ring is disposed in the terminal structure (Fig. 1 not shown).
  • a polysilicon gate 31 is disposed on the front surface of the substrate 10 of the active region, and sidewall spacers 72 are disposed on the substrate 10 on both sides of the polysilicon gate 31.
  • the substrate 10 is provided with an interlayer dielectric 81 covering the polysilicon gate 31 and the sidewall spacers 72.
  • the interlayer dielectric 81 is covered with a metal wiring layer 91.
  • N-type carrier enhancement carrier
  • the P-type body region 51 is disposed in the carrier enhancement region 41
  • the N-type heavily doped region 61 is disposed in the P-type body region 51
  • the P-type heavy doping is provided in the N-type heavily doped region 61.
  • the impurity region 71, the surface of the P-type heavily doped region 71 is formed with a recessed region 62 recessed inwardly, and the depth of the recessed region 62 with respect to the inward recess of the substrate on both sides (ie, a in FIG. 1) is 0.15 ⁇ m. ⁇ 0.3 microns.
  • the present invention further provides a method for fabricating the above insulated gate bipolar transistor 100, comprising the following steps:
  • the material of the substrate 10 is one of silicon, silicon carbide, gallium arsenide, indium phosphide or germanium silicon.
  • the substrate 10 is a single crystal silicon wafer having a crystal orientation of ⁇ 100>.
  • a field oxide layer 20 is first grown on the front side of the substrate 10, and then a photo-etching layer is directly etched away from the substrate 10 where the termination protection ring is to be formed by photolithography using a termination protection ring. 20. P-type ions are then implanted with the field oxide layer 20 as a masking layer to form a termination guard ring.
  • Three terminal guard rings 21, 22, 23 are shown in FIG. 3A, wherein the termination guard ring 23 is located near the middle of the substrate 10. Active area area. It can be understood that the number of the terminal protection ring is not limited to the embodiment, and those skilled in the art can select the setting according to the actual needs of the device.
  • FIG. 3A is a cross-sectional view showing a partial structure of the insulated gate bipolar transistor after the step S110 is completed in the embodiment.
  • the P-type ions implanted in step S110 are boron ions. It can be understood that the specifically implanted P-type/N-type ions given in the ion implantation steps of the present embodiment are only a preferred embodiment, and other Ps which are well known to those skilled in the art may also be used in other embodiments. Type / N type ions instead.
  • the active region lithography is used to lithography and etch away the field oxide layer 20 in the active region, and then the N-type ions are implanted into the substrate 10 using the photoresist as a masking film.
  • the N-type ions implanted in step S120 are phosphorus ions.
  • FIG. 3B is a partial cross-sectional view of the insulated gate bipolar transistor after the step S120 is completed in the embodiment, and the structure shown is located on the right side of FIG. 3A.
  • Polysilicon is deposited on the substrate 10 from which the field oxide layer 20 is etched, a protective layer is formed on the deposited polysilicon, and polysilicon lithography is used to lithography and etch away excess polysilicon and protective layers to form a polysilicon gate 31.
  • the protective layer includes a silicon nitride layer 32, and one oxidation is required before the deposition of the silicon nitride, and a first oxide layer is formed on the surface of the deposited polysilicon (not shown in FIG. 3C).
  • a silicon nitride layer 32 is formed on the oxide layer by deposition. The deposition of a first oxide layer between the polysilicon gate 31 and the silicon nitride layer 32 improves the stress problem relative to depositing silicon nitride directly on the surface of the polysilicon.
  • FIG. 3C is a partial cross-sectional view showing the insulated gate bipolar transistor after the completion of step S130 in the present embodiment.
  • the N-type ion implantation region in step S120 forms a carrier enhanced region 41 after the push-knot.
  • steps S130 and S140 can be reversed.
  • the high-temperature push-bonding is performed to form the carrier-enhanced region 41, and then the polysilicon gate 31 and the silicon nitride layer 32 are formed. .
  • the P-type ions implanted in step S150 are boron ions, and the P-body 51 is formed after the high temperature is pushed.
  • FIG. 3D is a partial cross-sectional view showing the insulated gate bipolar transistor after the completion of step S150 in the present embodiment, and the structure shown is located on the right side of FIG. 3C.
  • the N-type ions implanted in step S160 are arsenic ions, and the N-type heavily doped regions (NSD) 61 are formed after the high temperature is pushed.
  • FIG. 3E is a partial cross-sectional view showing the insulated gate bipolar transistor after the step S160 is completed in the embodiment.
  • a second oxide layer is deposited first, and then the sidewall is etched, and the excess second oxide layer is etched away, and spacers 72 are formed on both sides of the polysilicon gate 31.
  • the step of performing silicon etching on the N-type heavily doped regions 61 to form the pit regions 62 is further included.
  • the pit region 62 is a shallow pit recessed inwardly to a depth of 0.15 ⁇ m to 0.3 ⁇ m.
  • a shallow pit (pit region 62) of 0.15 ⁇ m to 0.3 ⁇ m is etched in the P-type heavily doped region, so that the device can obtain good impurity distribution. And a larger metal contact area, reducing power consumption, improving product reliability, and further reducing the turn-on voltage drop.
  • P-type ions are implanted after the pit region 62 is etched.
  • the implanted P-type ions are boron ions.
  • the high temperature push is performed to form a P-type heavily doped region (PSD) 71.
  • the protective layer in this embodiment includes the silicon nitride layer 32. After the silicon nitride layer 32 on the surface of the polysilicon gate 31 is removed, the polysilicon gate 31 is doped with N-type ions. In this embodiment, the implantation doping of the polysilicon gate 31 can be performed after photolithography using a polysilicon lithography.
  • FIG. 3F is a partial cross-sectional view showing the insulated gate bipolar transistor after the completion of step S180 in the present embodiment.
  • step S180 After the step S180 is completed, conventional processes such as interlayer dielectric (ILD), front metallization, backside thinning, implantation and annealing, and back metallization can be performed.
  • ILD interlayer dielectric
  • front metallization backside thinning
  • back metallization backside thinning
  • implantation and annealing back metallization
  • borophosphosilicate glass BPSG
  • BPSG borophosphosilicate glass
  • Photolithography and contact etching are performed using a contact hole lithography plate, and a conductive metal is sputtered on the surface of the device, and then the conductive metal is etched using a metal photolithography plate to form a metal wiring layer 91 covering the interlayer dielectric 81. .
  • the back surface of the substrate 10 is thinned to a desired thickness, and the back surface of the substrate 10 is subjected to P-type ion implantation and annealed to form a P-type region 16.
  • the P-type region 16 and the substrate 10 constitute a substrate PN junction.
  • the P-type ions implanted in step S210 are boron ions.
  • a conductive metal is sputtered on the back side of the substrate 10, and a back metal structure 18 is formed on the surface of the P-type region 16 as a collector metal lead.
  • 1 is a cross-sectional view showing a partial structure of an insulated gate bipolar transistor 100 after completion of step S220 in the present embodiment.
  • a total of six lithographic plates were used in the above preparation process, namely a termination protection ring lithography plate, an active region lithography plate, a polysilicon lithography plate, a P-well lithography plate, a contact hole lithography plate, and a metal lithography plate.
  • the ion implantation of the carrier enhancement region 41 directly utilizes the photoresist pattern formed by photolithography in the step S120 as a masking film, and it is not necessary to additionally manufacture a photolithography plate for ion implantation of the carrier enhancement region 41, which can save cost.
  • the implantation doping of the polysilicon gate 31 is performed after the P-type heavily doped region 71 is prepared, so that the doping ions in the polysilicon during the high temperature process can be avoided after the implantation doping is completed in the previous five high-temperature push-knots.
  • the influence on the gate oxide and the channel region solves the problem that the gate oxide is easily destroyed during the thermal process.
  • the preparation method of the above insulated gate bipolar transistor is compatible with the DMOS process, and has the advantages of universality and good portability of different IC production lines.
  • step S200 is performed by photolithography and contact hole etching using a contact hole lithography plate
  • PSD implantation may be further performed before sputtering of the metal, and P-type ions are implanted into the P-type heavily doped region. To obtain good ohmic contact and improve device performance.

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Abstract

一种绝缘栅双极型晶体管（100）的制备方法，包括：提供衬底（10），在衬底（10）的正面形成场氧层（20），并形成终端保护环（23）；用有源区光刻版光刻并刻蚀掉有源区区域的场氧层（20），以光刻胶为掩蔽膜向衬底（10）内注入N型离子；在场氧层（20）被刻蚀掉的衬底（10）上淀积并形成多晶硅栅（31），在多晶硅栅（31）上形成保护层；对N型离子的注入区域进行推结后形成载流子增强区（41）；用P阱光刻版光刻并向载流子增强区（41）内注入P型离子，推结后形成P型体区；借助多晶硅栅向P型体区内进行自对准注入N型离子，推结后形成N型重掺杂区；在多晶硅栅两侧形成侧墙，再向N型重掺杂区内注入P型离子，推结后形成P型重掺杂区；去除保护层后进行多晶硅栅注入掺杂。所述制备方法通过形成载流子增强区降低了器件的导通压降。

Description

绝缘栅双极型晶体管的制备方法
【技术领域】
本发明涉及半导体器件的制造方法，特别是涉及一种绝缘栅双极型晶体管的制备方法。
【背景技术】
IGBT（Insulated Gate Bipolar Transistor），绝缘栅双极型晶体管，是由双极型三极管（BJT）和金属氧化物半导体场效应管（MOS）组成的功率半导体器件。传统的绝缘栅双极型晶体管的导通压降很高。
【发明内容】
基于此，有必要提供一种制备具有低导通压降的绝缘栅双极型晶体管的绝缘栅双极型晶体管的制备方法。
一种绝缘栅双极型晶体管的制备方法，包括：提供衬底，在所述衬底的正面形成场氧层，用终端保护环光刻版光刻并刻蚀所述场氧层，并向被刻蚀开的区域下面的衬底内注入P型离子，形成终端保护环；用有源区光刻版光刻并刻蚀掉有源区区域的所述场氧层，以光刻胶为掩蔽膜向所述衬底内注入N型离子，并在场氧层被刻蚀掉的所述衬底上淀积多晶硅，在淀积的多晶硅上形成保护层，用多晶硅光刻版光刻并刻蚀掉多余的多晶硅和保护层，形成多晶硅栅，再对N型离子的注入区域进行推结后形成载流子增强区；或用有源区光刻版光刻并刻蚀掉有源区区域的所述场氧层，以光刻胶为掩蔽膜向所述衬底内注入N型离子，再推结后形成载流子增强区，并在场氧层被刻蚀掉的所述衬底上淀积多晶硅，在淀积的多晶硅上形成保护层，用多晶硅光刻版光刻并刻蚀掉多余的多晶硅和保护层，形成多晶硅栅；用P阱光刻版光刻并向载流子增强区内注入P型离子，推结后形成P型体区；借助多晶硅栅向P型体区内进行自对准注入N型离子，推结后形成N型重掺杂区；在多晶硅栅两侧形成侧墙，再向所述N型重掺杂区内注入P型离子，推结后形成P型重掺杂区；去除所述保护层后向所述多晶硅栅进行多晶硅注入掺杂；形成层间介质，进行绝缘栅双极型晶体管的正面金属化工艺，进行背面减薄、P型离子注入及退火工艺，及进行绝缘栅双极型晶体管的背面金属化工艺。
在其中一个实施例中，所述在多晶硅栅两侧形成侧墙的步骤之后，向所述N型重掺杂区内注入P型离子的步骤之前，还包括对所述N型重掺杂区进行刻蚀形成凹坑区域的步骤，所述凹坑区域向内凹陷的深度相对于两侧的衬底为0.15微米~0.3微米。
在其中一个实施例中，所述在淀积的多晶硅上形成保护层的步骤包括在所述多晶硅表面形成第一氧化层，在所述第一氧化层表面淀积氮化硅层。
在其中一个实施例中，所述进行绝缘栅双极型晶体管的正面金属化工艺之后还包括再向所述P型重掺杂区内进行一次P型离子注入的步骤。
在其中一个实施例中，所述向被刻蚀开的区域下面的衬底内注入P型离子，形成终端保护环的步骤中，所述P型离子为硼离子；所述以光刻胶为掩蔽膜向所述衬底内注入N型离子的步骤中，所述N型离子为磷离子；所述用P阱光刻版光刻并向载流子增强区内注入P型离子的步骤中，所述P型离子为硼离子；所述借助多晶硅栅向P型体区内进行自对准注入N型离子的步骤中，所述N型离子为砷离子；所述向N型重掺杂区内注入P型离子的步骤中，所述P型离子为硼离子；所述去除保护层后向所述多晶硅栅进行多晶硅注入掺杂的步骤中，注入的离子为磷离子。
在其中一个实施例中，所述在多晶硅栅两侧形成侧墙的步骤包括：淀积第二氧化层、然后通过腐蚀去除多余的所述第二氧化层，剩余的第二氧化层形成所述侧墙。
在其中一个实施例中，所述进行绝缘栅双极型晶体管的正面金属化工艺的步骤包括用接触孔光刻版光刻并刻蚀出接触孔，并在所述层间介质上溅射导电金属，之后采用金属光刻版光刻并刻蚀溅射的金属形成覆盖所述层间介质的金属引线层。
在其中一个实施例中，所述衬底的材质为硅、碳化硅、砷化镓、磷化铟或锗硅中的一种。
在其中一个实施例中，所述衬底的材质为晶向<100>的单晶硅。
在其中一个实施例中，所述形成层间介质的步骤是淀积硼磷硅玻璃并进行热回流，形成覆盖所述多晶硅栅表面和侧墙表面的层间介质。
上述绝缘栅双极型晶体管的制备方法，通过在用有源区光刻版将有源区区域的场氧层刻开时，就进行N型离子的注入，以增加沟道中载流子浓度，形成载流子增强区，从而降低了导通压降。
【附图说明】
图1是一实施例中绝缘栅双极型晶体管的结构示意图；
图2是一实施例中绝缘栅双极型晶体管的制备方法的流程图；
图3A~图3F是一实施例中采用绝缘栅双极型晶体管的制备方法制备的绝缘栅双极型晶体管在制备过程中的局部剖视图。
【具体实施方式】
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
图1是一实施例中绝缘栅双极型晶体管100的结构示意图，包括外围的终端结构（图1未示）和被终端结构包围的有源区。绝缘栅双极型晶体管100的衬底为N型衬底10，衬底10背面设有P型区16，P型区16背面设有背面金属结构18，终端结构内设有终端保护环（图1未示）。有源区的衬底10正面设有多晶硅栅31，衬底10上多晶硅栅31的两侧设有侧墙72，衬底10上设有覆盖多晶硅栅31和侧墙72的层间介质81，层间介质81上覆盖有金属引线层91。有源区的衬底10内设有N型的载流子增强（Carrier Enhanced）区41，载流子增强区41内设有P型体区51，P型体区51内设有N型重掺杂区61，N型重掺杂区61内设有P型重掺杂区71，P型重掺杂区71表面形成有向内凹陷的凹坑区域62，凹坑区域62相对于两侧的衬底向内凹陷的深度（即图1中的a）为0.15微米~0.3微米。
参见图2，本发明还提供一种上述绝缘栅双极型晶体管100的制备方法，包括下列步骤：
S110，提供衬底，在衬底的正面形成场氧层，并形成终端保护环。
衬底10的材质为硅、碳化硅、砷化镓、磷化铟或锗硅中的一种。在本实施例中，衬底10采用晶向是<100>的单晶硅晶圆（wafer）。
在本实施例中，先在衬底10的正面生长一层场氧层20，然后采用终端保护环光刻版光刻并刻蚀掉需要形成终端保护环的衬底10正上方的场氧化层20。然后以场氧化层20为掩蔽层注入P型离子，形成终端保护环，图3A中示出了三个终端保护环21、22、23，其中终端保护环23所处的位置靠近衬底10中间的有源区区域。可以理解的，终端保护环的数量并不以本实施例为限，本领域技术人员可根据器件实际需要自行选择设置。
图3A为本实施例中步骤S110完成后绝缘栅双极型晶体管的局部结构剖视图。在本实施例中，步骤S110注入的P型离子为硼离子。可以理解的，本实施例各离子注入步骤中所给出的具体注入的P型/N型离子仅是一个较佳实施例，在其它实施例中也可以用本领域技术人员习知的其它P型/N型离子代替。
S120，用有源区光刻版光刻并刻蚀掉有源区区域的场氧层，以光刻胶为掩蔽膜向衬底内注入N型离子。
用有源区光刻版光刻并刻蚀掉有源区区域的场氧层20，然后先不去胶，而是以该光刻胶为掩蔽膜向衬底10内注入N型离子。在本实施例中，步骤S120注入的N型离子为磷离子。图3B为本实施例中步骤S120完成后绝缘栅双极型晶体管的局部结构剖视图，其示出的结构位于图3A右侧。
S130，在场氧层被刻蚀掉的衬底上淀积并形成多晶硅栅，在多晶硅栅上形成保护层。
在场氧层20被刻蚀掉的衬底10上淀积多晶硅，在淀积的多晶硅上形成保护层，再用多晶硅光刻版光刻并刻蚀掉多余的多晶硅和保护层，形成多晶硅栅31。在本实施例中，保护层包括氮化硅层32，在淀积氮化硅之前还需要进行一次氧化，在淀积的多晶硅表面形成第一氧化层（图3C未示），再于第一氧化层上通过淀积形成氮化硅层32。相对于直接在多晶硅表面淀积氮化硅，在多晶硅栅31与氮化硅层32之间淀积一层第一氧化层能够改善应力的问题。
图3C是本实施例中步骤S130完成后绝缘栅双极型晶体管的局部结构剖视图。
S140，对N型离子的注入区域进行推结后形成载流子增强区。
步骤S120中的N型离子注入区域在推结后形成载流子增强（Carrier Enhanced）区41。
在其它实施例中，步骤S130与S140的顺序可以调换，即步骤S120注入N型离子后，先进行高温推结形成载流子增强区41，再淀积形成多晶硅栅31与氮化硅层32。
S150，用P阱光刻版光刻并向载流子增强区内注入P型离子，推结后形成P型体区。
在本实施例中，步骤S150注入的P型离子为硼离子，高温推结后形成P型体区（P-body）51。图3D是本实施例中步骤S150完成后绝缘栅双极型晶体管的局部结构剖视图，其示出的结构位于图3C右侧。
S160，借助多晶硅栅向P型体区内进行自对准注入N型离子，推结后形成N型重掺杂区。
在本实施例中，步骤S160注入的N型离子为砷离子，高温推结后形成N型重掺杂区（NSD）61。图3E是本实施例中步骤S160完成后绝缘栅双极型晶体管的局部结构剖视图。
S170，在多晶硅栅两侧形成侧墙，再向N型重掺杂区内注入P型离子，推结后形成P型重掺杂区。
先淀积一层第二氧化层，然后对器件进行侧墙腐蚀，多余的第二氧化层被腐蚀掉，在多晶硅栅31两侧形成侧墙（spacer）72。
在本实施例中，在侧墙72形成后，向N型重掺杂区61内注入P型离子之前，还包括对N型重掺杂区61进行硅刻蚀、形成凹坑区域62的步骤。凹坑区域62是一个向内凹陷的深度为0.15微米~0.3微米的浅坑。
在向N型重掺杂区61内注入P型离子之前，于P型重掺杂区内刻蚀出0.15微米~0.3微米的浅坑（凹坑区域62），能够使器件获得良好的杂质分布和更大的金属接触面积，降低功耗，提高产品的可靠性，并进一步降低导通压降。
刻蚀出凹坑区域62后进行P型离子的注入。在本实施例中，注入的P型离子为硼离子。注入完成后进行高温推结，形成P型重掺杂区（PSD）71。
S180，去除保护层后进行多晶硅栅注入掺杂。
如前述，本实施例中保护层包括氮化硅层32。去除多晶硅栅31表面的氮化硅层32后，再对多晶硅栅31进行N型离子的注入掺杂。在本实施例中，可以用多晶硅光刻版光刻后进行多晶硅栅31的注入掺杂。图3F是本实施例中步骤S180完成后绝缘栅双极型晶体管的局部结构剖视图。
步骤S180完成后可以进行常规的生成层间介质（ILD），正面金属化，背面减薄、注入及退火，以及背面金属化等工艺。以下同样给出一个具体的实施例。
S190，形成覆盖多晶硅栅和侧墙表面的层间介质。
在器件表面淀积硼磷硅玻璃（BPSG）后进行热回流，形成覆盖多晶硅栅31和侧墙72表面的层间介质81。
S200，进行正面金属化。
采用接触孔光刻版进行光刻和接触孔（contact）刻蚀，并在器件表面溅射导电金属，之后采用金属光刻版刻蚀该导电金属，形成覆盖层间介质81的金属引线层91。
S210，进行背面减薄、P型离子注入及退火。
将衬底10的背面减薄至所需厚度，对衬底10背面进行P型离子注入并退火，形成P型区16。P型区16与衬底10构成衬底PN结。在本实施例中，步骤S210注入的P型离子是硼离子。
S220，进行背面金属化。
对衬底10背面溅射导电金属，在P型区16表面形成背面金属结构18，作为集电极金属引线。图1是本实施例中步骤S220完成后绝缘栅双极型晶体管100的局部结构剖视图。
上述绝缘栅双极型晶体管的制备方法，通过在步骤S120中有源区光刻版将有源区区域的场氧层20刻蚀开时，就进行磷离子的注入，以增加沟道中载流子浓度，形成载流子增强区41，从而降低了导通压降。
上述制备过程中共采用6张光刻版，分别是终端保护环光刻版、有源区光刻版、多晶硅光刻版、P阱光刻版、接触孔光刻版以及金属光刻版。载流子增强区41的离子注入直接利用步骤S120中光刻形成的光刻胶图案作为掩蔽膜，不需要额外为载流子增强区41的离子注入制造一块光刻版，能够节省成本。
另外，在制备完P型重掺杂区71后才进行多晶硅栅31的注入掺杂，使得该注入掺杂位于前面的5次高温推结完成之后，能够避免高温过程中多晶硅内的掺杂离子对栅氧及沟道区的影响，解决了热过程中栅氧易被破坏的难题。同时上述绝缘栅双极型晶体管的制备方法与DMOS工艺兼容，具有普适性和不同IC生产线可移植性好等优点。
在其中一个实施例中，步骤S200采用接触孔光刻版进行光刻和接触孔刻蚀之后，溅射金属之前，还可以再进行一次PSD注入，向P型重掺杂区内注入P型离子，以获得良好的欧姆接触，提高器件的性能。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种绝缘栅双极型晶体管的制备方法，包括：
    提供衬底，在所述衬底的正面形成场氧层，用终端保护环光刻版光刻并刻蚀所述场氧层，并向被刻蚀开的区域下面的衬底内注入P型离子，形成终端保护环；
    用有源区光刻版光刻并刻蚀掉有源区区域的所述场氧层，以光刻胶为掩蔽膜向所述衬底内注入N型离子，并在场氧层被刻蚀掉的所述衬底上淀积多晶硅，在淀积的多晶硅上形成保护层，用多晶硅光刻版光刻并刻蚀掉多余的多晶硅和保护层，形成多晶硅栅，再对N型离子的注入区域进行推结后形成载流子增强区；或用有源区光刻版光刻并刻蚀掉有源区区域的所述场氧层，以光刻胶为掩蔽膜向所述衬底内注入N型离子，再推结后形成载流子增强区，并在场氧层被刻蚀掉的所述衬底上淀积多晶硅，在淀积的多晶硅上形成保护层，用多晶硅光刻版光刻并刻蚀掉多余的多晶硅和保护层，形成多晶硅栅；
    用P阱光刻版光刻并向载流子增强区内注入P型离子，推结后形成P型体区；
    借助多晶硅栅向P型体区内进行自对准注入N型离子，推结后形成N型重掺杂区；
    在多晶硅栅两侧形成侧墙，再向所述N型重掺杂区内注入P型离子，推结后形成P型重掺杂区；
    去除所述保护层后向所述多晶硅栅进行多晶硅注入掺杂；及
    形成层间介质，进行绝缘栅双极型晶体管的正面金属化工艺，进行背面减薄、P型离子注入及退火工艺，及进行绝缘栅双极型晶体管的背面金属化工艺。
  2. 根据权利要求1所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述在多晶硅栅两侧形成侧墙的步骤之后，向所述N型重掺杂区内注入P型离子的步骤之前，还包括对所述N型重掺杂区进行刻蚀形成凹坑区域的步骤，所述凹坑区域向内凹陷的深度相对于两侧的衬底为0.15微米~0.3微米。
  3. 根据权利要求1所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述在淀积的多晶硅上形成保护层的步骤包括在所述多晶硅表面形成第一氧化层，在所述第一氧化层表面淀积氮化硅层。
  4. 根据权利要求1所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述进行绝缘栅双极型晶体管的正面金属化工艺之后还包括再向所述P型重掺杂区内进行一次P型离子注入的步骤。
  5. 根据权利要求1所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述向被刻蚀开的区域下面的衬底内注入P型离子，形成终端保护环的步骤中，所述P型离子为硼离子；所述以光刻胶为掩蔽膜向所述衬底内注入N型离子的步骤中，所述N型离子为磷离子；所述用P阱光刻版光刻并向载流子增强区内注入P型离子的步骤中，所述P型离子为硼离子；所述借助多晶硅栅向P型体区内进行自对准注入N型离子的步骤中，所述N型离子为砷离子；所述向N型重掺杂区内注入P型离子的步骤中，所述P型离子为硼离子；所述去除保护层后向所述多晶硅栅进行多晶硅注入掺杂的步骤中，注入的离子为磷离子。
  6. 根据权利要求1所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述在多晶硅栅两侧形成侧墙的步骤包括：淀积第二氧化层、然后通过腐蚀去除多余的所述第二氧化层，剩余的第二氧化层形成所述侧墙。
  7. 根据权利要求1所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述进行绝缘栅双极型晶体管的正面金属化工艺的步骤包括用接触孔光刻版光刻并刻蚀出接触孔，并在所述层间介质上溅射导电金属，之后采用金属光刻版光刻并刻蚀溅射的金属形成覆盖所述层间介质的金属引线层。
  8. 根据权利要求1所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述衬底的材质为硅、碳化硅、砷化镓、磷化铟或锗硅中的一种。
  9. 根据权利要求8所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述衬底的材质为晶向为<100>的单晶硅。
  10. 根据权利要求1所述的绝缘栅双极型晶体管的制备方法，其特征在于，所述形成层间介质的步骤是淀积硼磷硅玻璃并进行热回流，形成覆盖所述多晶硅栅表面和侧墙表面的层间介质。
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