WO2015043396A1 - 场截止型绝缘栅双极型晶体管的背面工艺 - Google Patents

场截止型绝缘栅双极型晶体管的背面工艺 Download PDF

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Publication number
WO2015043396A1
WO2015043396A1 PCT/CN2014/086647 CN2014086647W WO2015043396A1 WO 2015043396 A1 WO2015043396 A1 WO 2015043396A1 CN 2014086647 W CN2014086647 W CN 2014086647W WO 2015043396 A1 WO2015043396 A1 WO 2015043396A1
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layer
substrate
bipolar transistor
insulated gate
gate bipolar
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PCT/CN2014/086647
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English (en)
French (fr)
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王根毅
邓小社
钟圣荣
周东飞
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无锡华润上华半导体有限公司
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Publication of WO2015043396A1 publication Critical patent/WO2015043396A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a backside process of a field-off insulated gate bipolar transistor.
  • Insulated Gate Bipolar Transistor Insulated Gate Bipolar Transistor (Insulated Gate Bipolar Transistor) IGBT) has a lower on-resistance than DMOS. So far, IGBTs mainly have punch-through PT-IGBTs and non-punch-through NPT- Three structures of IGBT and field-stop FS-IGBT, the main difference between the three is different substrate PN junction structure and different drift region thickness. Compared with PT-IGBT and NPT-IGBT, the thickness of FS-IGBT is the thinnest, but the high cost of the thin-film equipment, the complicated process and the high fragmentation rate limit the performance of FS-IGBT (especially low-voltage IGBT). constantly improving.
  • the traditional FS-IGBT is usually after the FS layer is finished on the back side, and then the back side P+ layer is implanted according to the conventional IGBT front side process. This is easy to cause the front side of the wafer to be scratched, which is not conducive to the chip. The realization of normal functions.
  • a backside process for a field-stop insulated gate bipolar transistor comprising: providing a substrate and growing an oxide layer on the front and back sides of the substrate; implanting N-type ions into the back surface of the substrate; and pushing the well to implant N
  • the region of the type ions forms a field stop layer; the field stop layer is implanted with P-type ions to form a back side P+ layer, and the back side P+ layer is pushed to sink; and the oxide layer on the front side of the substrate is removed.
  • the step of removing the oxide layer on the front side of the substrate further comprises depositing on the oxide layer on the back side of the substrate.
  • the step of the polysilicon layer is
  • the deposited polysilicon layer has a thickness of 7000 angstroms.
  • the method further comprises the steps of: preparing an insulated gate bipolar in the substrate and on the substrate by using an insulated gate bipolar transistor front side process The front side structure of the transistor; forming a front metal layer and a back metal layer; and the step of forming the front metal layer and the back metal layer further includes the step of removing the polysilicon layer.
  • the step of removing the polysilicon layer is performed by dry etching.
  • phosphorus ions are implanted.
  • the step of forming the field stop layer by implanting the N-type implant region is performed by using an annealing menu of 1000 degrees Celsius or more to form a field stop layer having a depth of 20 micrometers after diffusion.
  • the step of pushing the backside P+ layer is to push the well using an annealing temperature of 700 degrees Celsius to form a backside P+ layer having a depth of 1 micrometer.
  • the step of removing the oxide layer on the front side of the substrate is removed by wet etching.
  • the thickness of the substrate is 400 ⁇ m.
  • the back side process of the field-cut insulated gate bipolar transistor protects the front side of the wafer by an oxide layer structure grown on the front side of the substrate so that it is not easily scratched during the manufacturing process.
  • FIG. 1 is a flow chart showing a back surface process of a field-off insulated gate bipolar transistor in an embodiment
  • 2A-2D are partial cross-sectional views showing the FS-IGBT prepared by the back surface process of the field-stop type insulated gate bipolar transistor in the preparation process.
  • FIG. 1 is a flow chart showing a back surface process of a field-off insulated gate bipolar transistor in an embodiment, including the following steps:
  • a wafer having a thickness of about 400 ⁇ m is used as the substrate 11, and the oxide layer 12 is grown on the front and back surfaces of the substrate 11, see Fig. 2A.
  • an oxide layer is formed on both the front side and the back side, and the oxide layers on the front and back sides of the substrate 11 in the drawing are collectively referred to as the oxide layer 12.
  • the wafer can be inverted and then implanted into the back side of the wafer by a front implanting machine.
  • the implanted N-type ions pass through the oxide layer 12 on the back side into the substrate.
  • the implanted N-type ions are phosphorus ions, and in other embodiments, other types of N-type ions may be implanted.
  • the oxide layer 12 on the back side can prevent surface damage of the substrate 11 caused by ion implantation in step S120.
  • the well is pushed with an annealing menu of more than 1000 degrees Celsius to form a diffused N+ layer as the field stop (FS) layer 14.
  • the depth of the field stop layer 14 after diffusion is about 20 microns.
  • the implantation can be performed using a front implantation machine, implanting boron ions, and pushing the well with an annealing temperature of about 700 degrees Celsius to form a back P+ layer 23 having a depth of about 1 micrometer, as shown in Fig. 2B.
  • the step of forming the polysilicon layer 13 on the oxide layer 12 on the back surface of the substrate 11 is further included after the step S140.
  • a polysilicon layer is formed on both the front side and the back side, and the front and back polysilicon layers are collectively labeled as the polysilicon layer 13.
  • the thickness of the deposited polysilicon layer 13 is 7000 angstroms. In other embodiments, the thickness of the polysilicon layer 13 can also be adjusted according to specific conditions.
  • the polysilicon layer 13 on the back side can protect the N-type ions implanted in step S120, preventing contamination of the field stop layer 14 and the back side P+ layer 23 by subsequent operations.
  • the oxide layer 12 on the front side of the substrate not only the oxide layer 12 on the front side of the substrate but also the polysilicon layer 13 on the front side of the substrate is removed.
  • the front polysilicon layer 13 is removed by dry etching, and the oxide layer 12 is removed by wet etching.
  • the structure after the removal is completed as shown in FIG. 2C.
  • the back surface process of the FS-IGBT is substantially completed, and the subsequent operations can be completed by a conventional conventional process.
  • the front side structure of the IGBT can be fabricated using a conventional IGBT front side process.
  • the front side structure on the substrate 11 includes a polysilicon gate 18, an interlayer dielectric (ILD) 19, and the like.
  • a front metal layer 27 and a back metal layer 28 are formed.
  • the formation of the metal layer can be carried out by a conventional process and will not be described herein.
  • the polysilicon layer 13 on the back side needs to be removed before the back metal layer 28 is formed.
  • the front surface of the wafer can be protected from being easily scratched during the manufacturing process.
  • the implantation of the back P+ layer and the push-pull are performed before the formation of the metal layer (step S170), and the high-temperature push-bonding may employ an annealing menu of more than 1000 degrees Celsius, which is advantageous for improving the performance of the device.
  • the back side process of the field-off insulated gate bipolar transistor described above is compatible with the existing MOS process, and can save cost.

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Abstract

一种场截止型绝缘栅双极型晶体管的背面工艺，包括：提供衬底，并在衬底的正面和背面生长氧化层；向所述衬底背面内注入N型离子；推阱，使注入了N型离子的区域形成场截止层；对所述场截止层进行P型离子的注入，形成背面P+层，并对所述背面P+层进行推阱；去除衬底正面的所述氧化层。通过在衬底正面生长氧化层结构，对圆片的正面进行保护，令其在制造过程中不会被轻易划伤。

Description

场截止型绝缘栅双极型晶体管的背面工艺
【技术领域】
本发明涉及半导体器件的制造方法，特别是涉及一种场截止型绝缘栅双极型晶体管的背面工艺。
【背景技术】
由于电导调制效应，绝缘栅双极晶体管（Insulated Gate Bipolar Transistor， 简称 IGBT）具有比DMOS更低的导通电阻。迄今为止，IGBT主要有穿通型PT- IGBT、非穿通型NPT- IGBT和场截止型FS-IGBT三种结构，三者之间的主要差异是不同的衬底PN结结构和不同的漂移区厚度。相对PT-IGBT和NPT-IGBT来讲，FS-IGBT的厚度是最薄的，但薄片设备价格贵、工艺复杂以及很高的碎片率严重的限制了FS-IGBT（特别是低压IGBT）性能的不断提升。
另一方面，传统的FS-IGBT，通常是背面做完FS层以后，再按照常规的IGBT正面工艺流程最后进行背面P+层的注入，这样做很容易造成圆片的正面划伤，不利于芯片正常功能的实现。
【发明内容】
基于此有必要提供一种对圆片的正面进行保护，令其在制造过程中不会被轻易划伤的场截止型绝缘栅双极型晶体管的背面工艺。
一种场截止型绝缘栅双极型晶体管的背面工艺，包括：提供衬底，并在衬底的正面和背面生长氧化层；向衬底背面内注入N型离子；推阱，使注入了N型离子的区域形成场截止层；对所述场截止层进行P型离子的注入，形成背面P+层，并对所述背面P+层进行推阱；去除衬底正面的所述氧化层。
在其中一个实施例中，所述对背面P+层进行推阱的步骤之后，所述去除衬底正面的所述氧化层的步骤之前，还包括在衬底背面的所述氧化层上淀积形成多晶硅层的步骤。
在其中一个实施例中，所述在衬底背面的所述氧化层上淀积形成多晶硅层的步骤中，淀积的多晶硅层的厚度为7000埃。
在其中一个实施例中，所述去除衬底正面的所述氧化层的步骤之后，还包括下列步骤：采用绝缘栅双极型晶体管正面工艺在衬底内和衬底上制备出绝缘栅双极型晶体管的正面结构；形成正面金属层和背面金属层；所述形成正面金属层和背面金属层的步骤之前，还包括去除所述多晶硅层的步骤。
在其中一个实施例中，所述去除所述多晶硅层的步骤，是采用干法刻蚀的方式去除。
在其中一个实施例中，所述向衬底内注入N型离子的步骤中，注入的是磷离子。
在其中一个实施例中，所述推阱使注入了N型离子的区域形成场截止层的步骤，是采用1000摄氏度以上的退火菜单进行，形成扩散后深度为20微米的场截止层。
在其中一个实施例中，所述对背面P+层进行推阱的步骤，是采用700摄氏度的退火温度进行推阱，形成深度为1微米的背面P+层。
在其中一个实施例中，所述去除衬底正面的所述氧化层的步骤中，是采用湿法腐蚀的方式去除。
在其中一个实施例中，所述提供衬底的步骤中，衬底的厚度为400微米。
上述场截止型绝缘栅双极型晶体管的背面工艺，通过在衬底正面生长的氧化层结构，对圆片的正面进行保护，令其在制造过程中不会被轻易划伤。
【附图说明】
图1是一实施例中场截止型绝缘栅双极型晶体管的背面工艺的流程图；
图2A~图2D是一实施例中采用场截止型绝缘栅双极型晶体管的背面工艺制备的FS-IGBT在制备过程中的局部剖面示意图。
【具体实施方式】
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
图1是一实施例中场截止型绝缘栅双极型晶体管的背面工艺的流程图，包括下列步骤：
S110，提供衬底，并在衬底的正面和背面生长氧化层。
在本实施例中，采用厚度为约400微米的圆片（wafer）作为衬底11，并在衬底11的正面和背面生长氧化层12，参照图2A。可以理解的是，在本实施例中，由于工艺的限制，会同时在正面和背面形成氧化层，附图中衬底11正面和背面的氧化层统一标号为氧化层12。
S120，向衬底的背面注入N型离子。
可以将圆片翻转后用正面注入机台实现对圆片背面的注入，注入的N型离子穿过背面的氧化层12进入衬底。在本实施例中，注入的N型离子为磷离子，在其它实施例中注入的也可以是其它种类的N型离子。
背面的氧化层12可以防止步骤S120中的离子注入时所导致的衬底11表面损伤。
S130，推阱，使衬底的背面注入了N型离子的区域形成场截止层。
在本实施例中，是用超过1000摄氏度的退火菜单进行推阱，形成扩散后的N+层作为场截止（FS）层14。在本实施例中，扩散后的场截止层14的深度为20微米左右。
S140，对场截止层进行P型离子的注入，形成背面P+层，并对背面P+层进行推阱。
注入可以使用正面注入机台进行，注入硼离子，并用700摄氏度左右的退火温度进行推阱，以形成深度为1微米左右的背面P+层23，如图2B所示。
在本实施例中，于步骤S140之后还包括在衬底11背面的氧化层12上淀积形成多晶硅层13的步骤。可以理解的，由于工艺的限制，在本实施例中，会同时在正面和背面形成多晶硅层，正面和背面的多晶硅层统一标号为多晶硅层13。在本实施例中，淀积的多晶硅层13的厚度为7000埃，在其它实施例中也可以根据具体情况调整多晶硅层13的厚度。
背面的多晶硅层13可以保护步骤S120中注入的N型离子，防止后续作业对场截止层14和背面P+层23的污染。
S150，去除衬底的正面的氧化层。
在本实施例中，不仅要去除衬底正面的氧化层12，而且要去除衬底正面的多晶硅层13。其中，正面的多晶硅层13采用干法刻蚀去除，氧化层12采用湿法腐蚀去除。去除完成后的结构如图2C所示，至此，该FS-IGBT的背面工艺基本完成，后续作业可以通过习知的传统工艺来完成。
S160，采用IGBT正面工艺在衬底内和衬底上制备出IGBT的正面结构。
可以使用常规的IGBT正面工艺来制备IGBT的正面结构。衬底11上的正面结构包括多晶硅栅18、层间介质（ILD）19等。
S170，在所述正面结构和所述背面P+层其中之一上形成正面金属层，并于另一个上形成背面金属层。
如图2D所示，形成正面金属层27和背面金属层28。金属层的形成可以采用习知的工艺进行，此处不再赘述。在本实施例中，形成背面金属层28之前需要将背面的多晶硅层13去除。
上述场截止型绝缘栅双极型晶体管的背面工艺，通过在步骤S110中生长正面的氧化层12，能够保护圆片的正面，令其在制造过程中不会被轻易划伤。背面P+层的注入和推阱在形成金属层（步骤S170）之前进行，高温推结可以采用大于1000摄氏度的退火菜单，有利于提升器件的性能。
另外，上述场截止型绝缘栅双极型晶体管的背面工艺与现有的MOS工艺兼容，能够节省成本。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种场截止型绝缘栅双极型晶体管的背面工艺，包括：
    提供衬底，并在所述衬底的正面和背面生长氧化层；
    向所述衬底的背面内注入N型离子；
    推阱，使所述衬底的背面注入了N型离子的区域形成场截止层；
    对所述场截止层进行P型离子的注入，形成背面P+层，并对所述背面P+层进行推阱；及
    去除所述衬底的正面的所述氧化层。
  2. 根据权利要求1所述的场截止型绝缘栅双极型晶体管的背面工艺，其特征在于，所述对所述背面P+层进行推阱的步骤之后，所述去除所述衬底的正面的所述氧化层的步骤之前，还包括在所述衬底的背面的所述氧化层上淀积形成多晶硅层的步骤。
  3. 根据权利要求2所述的场截止型绝缘栅双极型晶体管的背面工艺，其特征在于，所述多晶硅层的厚度为7000埃。
  4. 根据权利要求2所述的场截止型绝缘栅双极型晶体管的背面工艺，其特征在于，所述去除所述衬底的正面的所述氧化层的步骤之后，还包括下列步骤：
    采用绝缘栅双极型晶体管正面工艺在衬底内和衬底上制备出绝缘栅双极型晶体管的正面结构；
    在所述正面结构和所述背面P+层其中之一上形成正面金属层，并于另外一个上形成背面金属层；
    所述形成正面金属层和背面金属层的步骤之前，还包括去除所述多晶硅层的步骤。
  5. 根据权利要求4所述的场截止型绝缘栅双极型晶体管的背面工艺，其特征在于，采用干法刻蚀的方式去除所述多晶硅层。
  6. 根据权利要求1所述的场截止型绝缘栅双极型晶体管的背面工艺，其特征在于，所述N型离子为磷离子。
  7. 根据权利要求1所述的场截止型绝缘栅双极型晶体管的背面工艺，其特征在于，所述推阱使所述衬底的背面注入了N型离子的区域形成场截止层的步骤，是采用1000摄氏度以上的退火菜单进行，形成扩散后深度为20微米的场截止层。
  8. 根据权利要求1所述的场截止型绝缘栅双极型晶体管的背面工艺，其特征在于，所述对所述背面P+层进行推阱的步骤，是采用700摄氏度的退火温度进行推阱，形成深度为1微米的背面P+层。
  9. 根据权利要求1所述的场截止型绝缘栅双极型晶体管的背面工艺，其特征在于，采用湿法腐蚀的方式去除所述氧化层。
  10. 根据权利要求1所述的场截止型绝缘栅双极型晶体管的背面工艺，其特征在于，所述衬底的厚度为400微米。
PCT/CN2014/086647 2013-09-26 2014-09-16 场截止型绝缘栅双极型晶体管的背面工艺 WO2015043396A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004273772A (ja) * 2003-03-10 2004-09-30 Fuji Electric Holdings Co Ltd 半導体装置の製造方法
CN102142372A (zh) * 2010-12-24 2011-08-03 江苏宏微科技有限公司 制备场阻断型绝缘栅双极晶体管的方法
CN102347355A (zh) * 2010-07-30 2012-02-08 万国半导体股份有限公司 最小化场阑igbt的缓冲区及发射极电荷差异的方法
CN102693912A (zh) * 2011-03-24 2012-09-26 上海北车永电电子科技有限公司 制作igbt器件的方法及其装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004273772A (ja) * 2003-03-10 2004-09-30 Fuji Electric Holdings Co Ltd 半導体装置の製造方法
CN102347355A (zh) * 2010-07-30 2012-02-08 万国半导体股份有限公司 最小化场阑igbt的缓冲区及发射极电荷差异的方法
CN102142372A (zh) * 2010-12-24 2011-08-03 江苏宏微科技有限公司 制备场阻断型绝缘栅双极晶体管的方法
CN102693912A (zh) * 2011-03-24 2012-09-26 上海北车永电电子科技有限公司 制作igbt器件的方法及其装置

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