WO2015014289A1 - 绝缘栅双极型晶体管的制造方法 - Google Patents

绝缘栅双极型晶体管的制造方法 Download PDF

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WO2015014289A1
WO2015014289A1 PCT/CN2014/083345 CN2014083345W WO2015014289A1 WO 2015014289 A1 WO2015014289 A1 WO 2015014289A1 CN 2014083345 W CN2014083345 W CN 2014083345W WO 2015014289 A1 WO2015014289 A1 WO 2015014289A1
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conductivity type
semiconductor substrate
main surface
bipolar transistor
forming
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PCT/CN2014/083345
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English (en)
French (fr)
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邓小社
芮强
张硕
王根毅
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无锡华润上华半导体有限公司
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Publication of WO2015014289A1 publication Critical patent/WO2015014289A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Definitions

  • the invention belongs to the technical field of power semiconductor devices, and relates to an insulated gate bipolar transistor (IGBT), in particular to a method for preparing an insulated gate bipolar transistor which simplifies the process.
  • IGBT insulated gate bipolar transistor
  • IGBT is made of GTR (Giant Transistor, Power Transistor or Giant Transistor) Composite fully-regulated voltage-driven power semiconductor device composed of MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor), combining high input impedance of MOSFET and low on-voltage of GTR
  • MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • IGBT can be divided into planar IGBT according to the structure type of the gate And trench IGBTs, their structural features and their corresponding characteristics are known to those skilled in the art.
  • these two kinds of IGBTs In the preparation process, both the front side process and the back side process are included, wherein the front side process is mainly used to complete the IGBT
  • the gate (Gate, G) and the emitter (Emitter, E) are prepared, and the back surface process is mainly used to complete the IGBT collector (Collector, C).
  • planar IGBTs are mainly formed by the following two methods.
  • the first is to complete the front side process on a single crystal silicon substrate, and then thin the back side of the substrate and multiple ion implantation on the back side to form a collector; this method does not depend on the epitaxial process, but relies on high energy ion implantation. And the annealing activation process, the high energy ion implantation equipment has high cost and the process realization cost is high; and the activation rate of the doping source in the collector region formed by ion implantation and annealing is not high, thereby leading to IGBT The saturation characteristics are not good.
  • the second method is: epitaxially growing a thick epitaxial layer on a single crystal silicon substrate, and performing a front surface process on the epitaxial layer, and then thinning the silicon substrate on the back surface thereof to form a collector;
  • the epitaxial process is used and the IGBT is mainly prepared by an epitaxial layer (the buffer layer is formed by the epitaxial layer), the epitaxial layer is relatively thick and the performance of the epitaxial layer is very high (for example, the number of defects), often because the quality of the epitaxial layer is not good enough. Lead to IGBT Poor performance (for example, poor overvoltage withstand capability and overcurrent tolerance) or low yield.
  • IGBTs are used in a variety of circuits. It is not difficult to find that the existing process flow has a separate lithographic version of the terminal structure, the process is complicated, and the manufacturing cost is high. It is necessary to provide an improved technical solution to overcome the above problems.
  • a method of fabricating an insulated gate bipolar transistor comprising: providing a semiconductor substrate of a first conductivity type, the semiconductor substrate having a first major surface and a second major surface; wherein the semiconductor substrate of the first conductivity type is Source region lithography and ion implantation of a first conductivity type; forming a base region of the second conductivity type on the first main surface of the first conductivity type semiconductor substrate having the active region and having the first main surface of the active region Forming a protection terminal of a second conductivity type on the outer side; forming a remaining first main surface structure of the insulated gate bipolar transistor based on the formed base region on the first main surface of the semiconductor substrate; on the second main surface of the semiconductor substrate The side forms a second main surface structure of the insulated gate bipolar transistor.
  • the process of forming the protection terminal and the base region includes: generating a field oxide layer on a first main surface of a first conductivity type semiconductor substrate; and protecting a termination region and a base region Photolithography, etching, second conductivity type ion implantation, push well formation to form the protection termination and the base region; growth of a gate oxide layer on the first major surface having the active region.
  • the forming the second main surface structure of the insulated gate bipolar transistor on the second main surface side of the semiconductor substrate comprises: splicing the first conductive type semiconductor lining by a backside thinning process a thick bottom of the bottom is thinned from the second main surface; a second semiconductor layer of a second conductivity type is formed from a second main surface of the thinned semiconductor substrate toward the inside of the semiconductor substrate; and a second semiconductor of the second conductivity type A metal layer is formed on the layer to form a second main electrode.
  • the first conductivity type is N-type and the second conductivity type is P-type.
  • forming the remaining first major surface structure of the insulated gate bipolar transistor based on the formed base region on the first main surface of the semiconductor substrate comprises: selectively performing a base region along the second conductivity type Forming a first conductivity type emitter region into the first conductivity type semiconductor substrate; depositing a dielectric layer; etching the contact hole in the dielectric layer; depositing a surface metal by depositing a metal and planarizing process The layers form a first main electrode.
  • the front side structure of the IGBT further includes: a passivation layer formed on the outer side of the first main electrode on the first main surface.
  • the second conductivity type ion implantation has an energy of 20 KeV to 1 MeV and a dose of 1E11/cm 2 to 1E14/cm 2 .
  • the IGBT structure of the above method for manufacturing an insulated gate bipolar transistor POLY lithography and P-Body region and Ring region etching, P-type impurity implantation, push-well forming body well and Ring region P-well are completed in the same step, and are reduced.
  • the invention is directed to the existing process technology, which has the problem that the terminal structure has a separate lithography plate, the process is complicated, the manufacturing cost is high, and the like, and the IGBT is provided to reduce the number of lithography plates, the process flow is simple, the manufacturing cost is reduced, and the application reliability is high. method.
  • FIGS. 1 to 11 are schematic flow charts showing a method of fabricating an IGBT according to a first embodiment of the present invention.
  • the first embodiment of the present invention uses a silicon wafer as a semiconductor substrate, and relates to a method for fabricating an IGBT device. The specific process is shown in FIGS. 1 to 11.
  • the semiconductor substrate in this embodiment may include a semiconductor element such as single crystal, polycrystalline or amorphous silicon or silicon germanium (SiGe), and may also include a mixed semiconductor structure such as silicon carbide or germanium. Indium, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof; or silicon-on-insulator (SOI). Further, the semiconductor substrate may further include other materials such as an epitaxial layer or a buried layer multilayer structure. Although a few examples of materials that can form a semiconductor substrate are described herein, any material that can be used as a semiconductor substrate falls within the spirit and scope of the present invention.
  • a semiconductor substrate of a first conductivity type is provided, the semiconductor substrate having a first major surface and a second major surface.
  • the N-type substrate 101 silicon wafer is preferred, and the N-doping concentration and thickness are selected according to the required IGBT characteristics. For example, the higher the breakdown voltage, the higher the N-doping concentration requirement. Low, the thicker the thickness requirement, and the formation of an oxide layer 102 having a thickness of 300 ⁇ to 20,000 ⁇ on the first main surface.
  • active region lithography and ion implantation of the first conductivity type are performed on the semiconductor substrate of the first conductivity type.
  • the oxide layer 102 of the active region 100 and the oxide layer pattern of the termination region 200 are etched by a photolithography process on the first main surface of the N-type substrate 101, followed by JFET implantation to perform N-type impurities.
  • the energy of ion implantation is 20 keV to 1 MeV, and the dose is, for example, 1E11/cm 2 to 1E14/cm 2 to form a JFET region.
  • a gate oxide layer 401 is formed by a thermal oxidation growth process on the first main surface having the active region 100, and a polysilicon is deposited on the gate oxide layer 401 as shown in FIGS. 3 and 4.
  • Layer 402 is used to fabricate a polysilicon gate.
  • a gate oxide layer 401 is formed on a first main surface having an active region 100.
  • the gate oxide layer 401 in this embodiment includes at least silicon oxide.
  • the gate oxide layer 401 may be formed in an active manner.
  • the gate oxide layer 401 is grown once on the first main surface of the region 100.
  • the gate oxide layer 401 is formed by a thermal oxidation method at a lower temperature than the conventional high temperature process, specifically, first at 800 ° C ⁇ 850 Dry oxygen for 5 min at °C, then carry out H 2 -O 2 synthesis oxidation according to the required thickness of the oxide layer, then dry oxygen oxidation at 800 ° C ⁇ 850 ° C for 3 min ⁇ 5 min, and finally annealed in N 2 atmosphere for 10 min at 1000 ° C ⁇ 1250 ° C ⁇ 1000min; this is because the continuous high temperature oxidation process will greatly increase the interface charge of the SiO 2 layer in the gate and the lattice defect density of silicon, resulting in high device leakage current, which will reduce the reliability and radiation resistance of the device.
  • Low-temperature thermal oxidation can inhibit the growth of defects such as stacking faults and the segregation of impurities in the channel region.
  • High-temperature annealing reduces the fixed charge of the SiO 2 layer and improves the quality of the oxide layer to form a gate oxide with a thickness of 500 ⁇ to 1500 ⁇ .
  • Layer 401
  • a polysilicon layer 402 is deposited on the gate oxide layer 401.
  • a thickness of 4000 ⁇ is formed.
  • a base region of the second conductivity type is formed on the first main surface of the first conductivity type semiconductor substrate having the active region, and a terminal of the second conductivity type is formed on the outside of the first main surface having the active region Protected area 200.
  • the active region 100 on the first main surface of the N-type substrate 101 is etched by a photolithography process to etch the gate oxide layer 401 and the polysilicon layer 402, and a photolithography process is used in the gate.
  • a photoresist layer having a gate region pattern is formed on the surface of the polysilicon layer, and then a photoresist layer having a gate region pattern is used as a mask, and a polysilicon gate 501 is formed by dry etching (see FIG. 5) and the first a pattern of the P well region 301 and the second P well region 302, while forming a terminal protection region 200 of the second conductivity type outside the first main surface of the lithography, and forming an ion implantation layer of the first P well region 301 by ion implantation.
  • the ion implantation layer of the second P well region 302, and the terminal P well region 201 advances and activates the ion implantation layer of the first P well region 301, the ion implantation layer of the second P well region 302, and the P well region 201.
  • the P-type impurity forms a first P well region 301, a second P well region 302, and a terminal P well region 201.
  • the energy of ion implantation is 20 KeV to 1 MeV
  • the dose is, for example, 1E12/cm 2 to 1E16/cm 2 , and then the well is pushed for 20 min to 1000 min at 1100 ° C to 1250 ° C.
  • the surface of the first conductivity type semiconductor substrate is selectively along the surface of the second conductivity type base region (here, the first P well region 301 and the second P well region 302).
  • An active region of the first conductivity type (here, N-type) is formed (here, the N-type substrate 101).
  • an N+ implant window is selected on the surfaces of the first P well region 301 and the second P well region 302 by a photolithography process, and a first P well region below the polysilicon gate 501 is implanted by an ion implantation and annealing process.
  • An N-type heavily doped first source region 602 and a second source region 601 are formed in the 301 and second P well regions 302, respectively.
  • the energy of ion implantation is 20 KeV to 1 MeV, and the dose is, for example, 1E15/cm 2 to 1E16/cm 2 ;
  • the annealing process has an annealing temperature of 800 ° C to 1000 ° C and a time of 10 min to 1000 min.
  • the dielectric is deposited in the fifth step to form a dielectric layer 701 surrounding the side and top surfaces of the polysilicon gate 501 (see FIG. 7), engraved in the dielectric layer 701.
  • the contact hole is etched, and then the N-type impurity of the hole is implanted twice.
  • the energy of the first ion implantation is 20 KeV to 90 KeV, and the dose is, for example, 1E12/cm 2 to 1E16/cm 2 ; the energy of the second ion implantation is 20 KeV ⁇
  • the dose is, for example, 1E13/cm 2 to 1E16/cm 2 .
  • one-time injection of the N-type impurity of the hole can also be used.
  • a surface metal layer (Al/AlCu/AlSiCu/AlSi) is deposited on the surface of the silicon wafer by using a deposited metal.
  • the metal layer has a thickness of about 2 ⁇ m to 6 ⁇ m, and then the metal layer is subjected to a metal layer.
  • Photolithography and etching form a metal wiring layer 801 to form a first main electrode (here, an emitter).
  • a first main electrode here, an emitter
  • a passivation layer 901 is deposited on the first main electrode (here, the emitter) metal wiring layer 801 and the oxide layer 102.
  • a passivation layer 901 for protecting the surface of the chip from external ions is deposited on the first main electrode (here, the emitter) and the oxide layer 102 by chemical vapor deposition, and is photolithographically processed. And an etching process to etch a PAD (pad) region (not shown) for extracting the gate electrode and the emitter.
  • the thick bottom of the semiconductor substrate of the first conductivity type (here, the N-type substrate 101) is thinned by the back surface thinning process. Specifically, the semiconductor substrate is polished from the second main surface of the N-type substrate 101 to meet a predetermined thickness requirement, and the back silicon stress layer is removed by a wet method.
  • a second conductivity type is formed toward the inside of the N-type substrate 101 from the second main surface of the terminal protection region 200 of the thinned N-type substrate 101.
  • a second semiconductor layer here, P+ collector layer 1101
  • a second semiconductor layer of a second conductivity type selectively formed from a second main surface having the active region 100 toward the inside of the semiconductor substrate (here P+ collector layer 1101).
  • a P-type impurity is selectively implanted from a second main surface of the ground N-type semiconductor substrate 1 by a photolithography process to form a P+ collector layer 1101 and annealed and activated.
  • the energy of ion implantation is 20 KeV to 80 KeV, and the dose is, for example, 1E12/cm 2 to 1E16/cm 2 ; during annealing, the temperature is 300 ° C to 550 ° C, and the duration is 10 min to 500 min.
  • a metal layer 1201 is formed on the second semiconductor layer of the second conductivity type (here, P+ collector layer 1101) to form a second main electrode.
  • the OLED structure, the POL lithography, the P-Body region and the Ring region etch, the P-type impurity implantation, the push-well forming the body well and the Ring region P-well are completed in the same step, and are reduced.

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Abstract

一种绝缘栅双极型晶体管的制造方法，包括，提供第一导电类型的半导体衬底（101）,该半导体衬底（101）具有第一主面和第二主面；在第一导电类型的半导体衬底（101）进行有源区（100）光刻以及第一导电类型的离子注入；在第一导电类型的半导体衬底（101）的具有有源区（100）的第一主面形成第二导电类型的基区（301，302）以及在具有有源区（100）的第一主面外侧形成第二导电类型的保护终端（200）；在该半导体衬底（101）的第一主面基于形成的基区（301，302）形成绝缘栅双极型晶体管的剩余第一主面结构；在该半导体衬底（101）的第二主面侧形成绝缘栅双极型晶体管的第二主面结构。该IGBT制作方法降低了光刻版使用数量，工艺流程简单，制造成本降低且应用可靠性高。

Description

绝缘栅双极型晶体管的制造方法
【技术领域】
本发明属于功率半导体器件技术领域，涉及绝缘栅双极型晶体管（IGBT），尤其是简化工艺的绝缘栅双极型晶体管的制备方法。
【背景技术】
IGBT是由GTR （Giant Transistor，电力晶体管或者巨型晶体管） 和MOSFET（Metal-Oxide-Semiconductor-Field-Effect-Transistor,金属氧化物半导体场效应晶体管）组成的复合全控型电压驱动式功率半导体器件，兼有MOSFET的高输入阻抗和GTR的低导通压降两方面的优点，具有工作频率高，控制电路简单，电流密度高，通态压低等特点，广泛应用于功率控制领域。
IGBT按照栅极的结构类型，可以分为平面型IGBT 和沟槽型IGBT，二者的结构特征及其相应特性为本领域技术人员所知悉。但是，这两种IGBT 在制备的过程中，均包括正面工艺和背面工艺，其中，正面工艺主要用来完成IGBT 的栅极（Gate，G）和发射极（Emitter，E）的制备，背面工艺主要用来完成IGBT 的集电极（Collector，C）的制备。
通常地，现有的平面型IGBT 主要通过以下两种方法制备形成。
第一种是，在单晶硅衬底上完成正面工艺，然后对衬底背面减薄、背面多次离子注入以引出形成集电极；这种方法不依赖于外延工艺，但是依赖于高能离子注入以及退火激活工艺过程，高能离子注入的设备成本高、工艺过程实现成本也比较高；并且，离子注入并退火形成的集电极区的掺杂源的激活率不高，进而导致IGBT 的饱和特性不佳。
第二种是，在单晶硅衬底上反型外延生长较厚的外延层，并在该外延层上完成正面工艺，然后在其背面对硅衬底减薄并形成集电极；这种方法采用外延工艺并且以外延层来主要制备IGBT（缓冲层以上均由外延层来形成），外延层比较厚并且对外延层的性能要求非常高（例如缺陷数目），常常因为外延层的质量不够好而导致IGBT 性能变差（例如，过压承受能力和过电流承受能力差）或者成品率低。
随着世界对节能减排的需求，IGBT应用越来越广泛，IGBT用于多种电路，不难发现，现有工艺流程为终端结构有单独光刻版，工艺复杂，制造成本较高，因此，有必要提供一种改进的技术方案来克服上述问题。
【发明内容】
基于此，提供一种降低光刻版使用数量，工艺流程简单的IGBT制作方法。
一种绝缘栅双极型晶体管的制造方法，包括：提供第一导电类型的半导体衬底，该半导体衬底具有第一主面和第二主面；在第一导电类型的半导体衬底进行有源区光刻以及第一导电类型的离子注入；在第一导电类型的半导体衬底的具有有源区的第一主面形成第二导电类型的基区以及在具有有源区第一主面外侧形成第二导电类型的保护终端；在该半导体衬底的第一主面基于形成的基区形成绝缘栅双极型晶体管的剩余第一主面结构；在该半导体衬底的第二主面侧形成绝缘栅双极型晶体管的第二主面结构。
在其中的一个实施例中，形成所述保护终端和所述基区的过程包括：在第一导电类型的半导体衬底的第一主面上生成场氧化层；在保护终端区域和基区区域光刻、蚀刻、第二导电类型离子注入、推阱以形成所述保护终端和所述基区；在具有有源区的第一主面上生长栅氧化层。
在其中的一个实施例中，所述在该半导体衬底的第二主面侧形成绝缘栅双极型晶体管的第二主面结构包括：通过背面减薄工艺，将第一导电类型的半导体衬底的厚底自第二主面减薄；从减薄后的半导体衬底的第二主面起朝向半导体衬底内部形成第二导电类型的第二半导体层；在第二导电类型的第二半导体层上形成金属层以形成第二主电极。
在其中的一个实施例中，第一导电类型为N型，第二导电类型为P型。
在其中的一个实施例中，在该半导体衬底的第一主面基于形成的基区形成绝缘栅双极型晶体管的剩余第一主面结构包括：选择性的沿第二导电类型的基区的表面向第一导电类型的半导体衬底内形成第一导电类型发射极区；淀积形成介质层；在介质层中刻蚀接触孔；采用淀积金属和平坦化工艺淀积一层表面金属层以形成第一主电极。
在其中的一个实施例中，所述IGBT的正面结构还包括：形成于第一主面所述第一主电极外侧的钝化层。
在其中的一个实施例中，所述第二导电类型离子注入，离子注入的能量为20KeV～1MeV，剂量为1E11/cm2 ～1E14/cm2。
上述绝缘栅双极型晶体管的制造方法的IGBT结构中POLY光刻以及P-Body区域和Ring区域刻蚀，P型杂质注入，推阱形成body阱和Ring区P阱在同一步骤中完成，降低了光刻版的使用层数。本发明针对现有流程工艺为终端结构有单独光刻版，工艺复杂，制造成本较高等问题，提供一种降低光刻版使用数量，工艺流程简单，制造成本降低且应用可靠性高的IGBT制作方法。
【附图说明】
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。其中：
图1~图11是根据本发明第一实施方式制作IGBT的方法流程示意图。
【具体实施方式】
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。
其次，本发明结合示意图进行详细描述，在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
本发明第一实施方式以硅片为半导体衬底，涉及一种制作IGBT器件的方法，具体流程如图1~图11 所示。
需要说明的是，本实施例中的半导体衬底可以包括半导体元素，例如单晶、多晶或非晶结构的硅或硅锗(SiGe)，也可以包括混合的半导体结构，例如碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合；也可以是绝缘体上硅(SOI)。此外，半导体衬底还可以包括其它的材料，例如外延层或掩埋层的多层结构。虽然在此描述了可以形成半导体衬底的材料的几个示例，但是可以作为半导体衬底的任何材料均落入本发明的精神和范围。
如图1所示，第一步，提供第一导电类型的半导体衬底，该半导体衬底具有第一主面和第二主面。在本实施方式中，具体地说，首选N-型衬底101硅片，N-掺杂浓度和厚度根据所需要的IGBT特性选择，例如击穿电压越高，N-的掺杂浓度要求越低，厚度要求越厚，并在第一主面上形成厚度为300Å~20000Å的氧化层102。
第二步，如图2所示，在第一导电类型的半导体衬底进行有源区光刻以及第一导电类型的离子注入。具体为，在所述N-型衬底101的第一主面通过光刻工艺刻蚀有源区100的氧化层102，和终端区域200的氧化层图形，之后进行JFET注入，进行N型杂质注入，在本实施例中，离子注入的能量为20KeV～1MeV，剂量例如为1E11/cm2～1E14/cm2，形成JFET区域。
第三步，在具有有源区100的第一主面上通过热氧化生长工艺形成一层栅氧化层401，如图3和图4所示，在栅氧化层401之上淀积一层多晶硅层402用以制造多晶硅栅极。
参见图3，在具有有源区100的第一主面上形成栅氧化层401，本实施例中的栅氧化层401至少包括氧化硅，形成栅氧化层401的方式可以为，在具有有源区100的第一主面上一次性生长栅氧化层401，在本实施例中，采用相对于传统高温工艺较低温度的热氧化法形成栅氧化层401，具体为，首先在800℃~850℃时干氧5min,之后根据需要的氧化层厚度进行H2-O2合成氧化,再在800℃~850℃干氧氧化3min~5min, 最后在1000℃~1250℃时N2气氛中退火10min~1000min；这样是因为持续的高温氧化过程会大大增加栅极里SiO2层的界面电荷以及硅的晶格缺陷密度，导致高的器件泄漏电流,使器件的可靠性及抗辐照能力下降，而低温热氧化则能抑制堆垛层错等缺陷的生长和沟道区杂质的分凝，高温退火会降低SiO2层的固定电荷，改善氧化层质量，形成厚度为500 Å ~1500Å的栅氧化层401。
如图4所示，在栅氧化层401上淀积多晶硅层402，在本实施例中，形成厚度为4000 Å ~15000Å的多晶硅层402，其中多晶硅层402可采用化学气相淀积、物理气相淀积或其它方式形成，本实施例不做具体限定。
第四步，在第一导电类型的半导体衬底的具有有源区的第一主面形成第二导电类型的基区以及在具有有源区的第一主面外侧形成第二导电类型的终端保护区200。如图5所示，具体为，在所述N-型衬底101的第一主面的有源区100通过光刻工艺刻蚀栅氧化层401和多晶硅层402，采用光刻工艺在该栅多晶硅层表面上形成具有栅区图案的光刻胶层，之后以具有栅区图案的光刻胶层为掩膜，采用干法刻蚀的方式形成多晶硅栅极501（参见图5）和第一P阱区301和第二P阱区302的图形，同时光刻第一主面外侧形成第二导电类型的终端保护区200，采用离子注入的方式形成第一P阱区301的离子注入层，第二P阱区302的离子注入层，以及终端P阱区201，对第一P阱区301的离子注入层、第二P阱区302的离子注入层以及P阱区域201进行推进并激活注入的P 型杂质，形成第一P阱区301、第二P阱区302和终端P阱区201。在本实施例中，离子注入的能量为20KeV～1MeV，剂量例如为1E12/cm2～1E16/cm2，然后在1100℃~1250℃的条件下推阱20min~1000min。
第五步，如图6所示，选择性的沿第二导电类型的基区（在此为第一P阱区301以及第二P阱区302）的表面向第一导电类型的半导体衬底（在此为N-型衬底101）内形成第一导电类型（在此为N型）的有源区。具体为，通过光刻工艺在所述第一P阱区301以及第二P阱区302的表面选择N+注入窗口，采用离子注入和退火工艺在多晶硅栅极501两侧下方的第一P阱区301和第二P阱区302中分别形成N型重掺杂第一源区602和第二源区601。在本实施例中，离子注入的能量为20KeV～1MeV，剂量例如为1E15/cm2～1E16/cm2；所述退火工艺，其退火温度为800℃~1000℃，时间为10min~1000min，形成N型重掺杂第一源区602和第二源区601。
第六步，参见图7，在本实施例中，介质在所述第五步中淀积形成介质层701包围多晶硅栅极501（参见图7）的侧面和顶面，在介质层701中刻蚀接触孔，然后进行孔的N型杂质两次注入，第一次离子注入的能量为20KeV～90KeV，剂量例如为1E12/cm2～1E16/cm2；第二次离子注入的能量为20KeV～1MeV，剂量例如为1E13/cm2～1E16/cm2。当然，也可使用孔的N型杂质一次注入。
第七步，采用淀积金属，在硅片表面淀积一层表面金属层（Al/AlCu/AlSiCu/AlSi），本实施例中，该金属层厚度约为2μm~6μm，然后对金属层进行光刻与刻蚀，形成金属布线层801，形成第一主电极（在此为发射极）。这些步骤都完成后的硅片剖面如图8所示。
参见图9，第八步，在第一主电极（在此为发射极）金属布线层801和氧化层102上淀积钝化层901。具体为，通过化学气相淀积的方式，在第一主电极（在此为发射极）和氧化层102上淀积用于保护芯片表面不受外界离子玷污的钝化层901，并通过光刻、刻蚀工艺，刻蚀出用于引出栅电极和发射极的PAD（焊盘）区域（图中未示出）。
第九步，通过背面减薄工艺，将第一导电类型的半导体衬底（在此为N-型衬底101）的厚底减薄。具体为，从N-型衬底101的第二主面起研磨该半导体衬底，使其符合规定的厚度要求，并采用湿法去除背面硅应力层。
第十步，如图10所示，参见图3，从减薄后的N-型衬底101的终端保护区200的第二主面起朝向N-型衬底101内部形成第二导电类型的第二半导体层（在此为P+集电极层1101），和从具有有源区100的第二主面起朝向半导体衬底内部选择性的形成第二导电类型的第二半导体层（在此为P+集电极层1101）。具体为，在从研磨后的N-型半导体衬底1的第二主面通过光刻工艺选择性的注入P型杂质，形成P+集电极层1101并退火激活。在本实施例中，离子注入的能量为20KeV～80KeV，剂量例如为1E12/cm2～1E16/cm2；退火时，温度为300℃~550℃，持续时间10min~500min。
最后，背面金属淀积，如图11所示，在第二导电类型的第二半导体层（在此为P+集电极层1101）上形成金属层1201以形成第二主电极。
不难发现，在本实施方式中，IGBT结构中POLY光刻以及P-Body区域和Ring区域刻蚀，P型杂质注入，推阱形成body阱和Ring区P阱在同一步骤中完成，降低了光刻版的使用层数。
应说明的是，以上实施例仅用以说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的精神和范围，其均应涵盖在本发明的权利要求范围当中。

Claims (7)

  1. 一种绝缘栅双极型晶体管的制造方法，其特征在于，包括：
    提供第一导电类型的半导体衬底，所述半导体衬底具有第一主面和第二主面；
    对所述第一导电类型的半导体衬底进行有源区光刻以及第一导电类型的离子注入；
    在所述第一导电类型的半导体衬底的具有有源区的第一主面形成第二导电类型的基区以及在具有有源区的第一主面外侧形成第二导电类型的保护终端；
    在所述半导体衬底的第一主面基于形成的基区形成绝缘栅双极型晶体管的剩余第一主面结构；
    在所述半导体衬底的第二主面侧形成绝缘栅双极型晶体管的第二主面结构。
  2. 如权利要求1所述的绝缘栅双极型晶体管的制造方法，其特征在于，
    形成所述保护终端和所述基区的过程包括：
    在所述第一导电类型的半导体衬底的第一主面上生成场氧化层；
    在保护终端区域和基区区域进行光刻、蚀刻、第二导电类型离子注入、推阱以形成所述保护终端和所述基区；
    在具有有源区的第一主面上生长栅氧化层。
  3. 根据权利要求1所述的绝缘栅双极型晶体管的制造方法，其特征在于，
    所述在所述半导体衬底的第二主面侧形成绝缘栅双极型晶体管的第二主面结构包括：
    通过背面减薄工艺，将第一导电类型的半导体衬底的厚底自第二主面减薄；
    从减薄后的半导体衬底的第二主面起朝向半导体衬底内部形成第二导电类型的第二半导体层；
    在第二导电类型的第二半导体层上形成金属层以形成第二主电极。
  4. 根据权利要求1所述的绝缘栅双极型晶体管的制造方法，其特征在于，
    第一导电类型为N型，第二导电类型为P型。
  5. 根据权利要求2所述的绝缘栅双极型晶体管的制造方法，其特征在于，
    在所述半导体衬底的第一主面基于形成的基区形成绝缘栅双极型晶体管的剩余第一主面结构包括：
    选择性的沿第二导电类型的基区的表面向第一导电类型的半导体衬底内形成第一导电类型发射极区；
    淀积形成介质层；
    在介质层中刻蚀接触孔；
    采用淀积金属和平坦化工艺淀积一层表面金属层以形成第一主电极。
  6. 根据权利要求5所述的IGBT的制造方法，其特征在于，所述IGBT的正面结构还包括：
    形成于第一主面所述第一主电极外侧的钝化层。
  7. 根据权利要求2所述的绝缘栅双极型晶体管的制造方法，其特征在于，所述第二导电类型离子注入的能量为20KeV～1MeV，剂量为1E11/cm2 ～1E14/cm2。
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