WO2011160591A1 - Vdmos器件及其制作方法 - Google Patents

Vdmos器件及其制作方法 Download PDF

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Publication number
WO2011160591A1
WO2011160591A1 PCT/CN2011/076175 CN2011076175W WO2011160591A1 WO 2011160591 A1 WO2011160591 A1 WO 2011160591A1 CN 2011076175 W CN2011076175 W CN 2011076175W WO 2011160591 A1 WO2011160591 A1 WO 2011160591A1
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type
epitaxial layer
layer
type epitaxial
semiconductor substrate
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PCT/CN2011/076175
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English (en)
French (fr)
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王乐
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无锡华润上华半导体有限公司
无锡华润上华科技有限公司
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Priority to JP2013514546A priority Critical patent/JP2013532379A/ja
Priority to US13/695,013 priority patent/US20130037878A1/en
Publication of WO2011160591A1 publication Critical patent/WO2011160591A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Definitions

  • the present invention relates to power devices, and more particularly to a method of fabricating a VDMOS device using a selective epitaxial process and a structure of a VDMOS device. Background technique
  • VDM0S Vertical double-diffused metal oxide semiconductor field effect transistors
  • a method of fabricating a VDM0S device is disclosed in the Chinese Patent Application No. 200810057881.5, specifically to FIG. 1 to FIG.
  • FIG. 1 first, an N-type semiconductor substrate 100 is provided, and an N-type epitaxial layer 101 is formed on the N-type semiconductor substrate 100; then, a gate oxide layer 111 is sequentially formed over the N-type epitaxial layer 101. And a polysilicon gate layer 108 over the gate oxide layer 111.
  • the N-type epitaxial layer 101 is P-well implanted to form a P-well 107, and the P-well 107 is located in the poly gate layer.
  • ion implantation is performed on the N-type epitaxial layer 101 under the P well 107 to form a P-type barrier layer 104; then, referring to FIG. 3, heavily doped ion implantation is performed, in the P well 107.
  • a drain metal layer 112 is formed on the back surface of the semiconductor substrate 100, and the back surface refers to the opposite surface of the device growth surface on the semiconductor substrate 100.
  • the gate metal layer 109 and the polysilicon gate layer 108 together form a gate G.
  • the source metal layer 110 and the N-type heavily doped region 106 together form a source S, the drain metal layer 112 and the semiconductor village.
  • the bottom 100 constitutes the drain D.
  • the p-type barrier layer formed by the prior art has poor uniformity of doping impurities, which increases the on-voltage drop and channel resistance of the VDMOS device.
  • the prior art performs multiple ion implantation on the N-type epitaxial layer 101.
  • a P-type barrier layer is formed on both sides of the N-type epitaxial layer 101.
  • multiple ion implantation and high temperature annealing steps have complicated processes, poor uniformity of ion implantation, and high manufacturing cost.
  • the invention provides a manufacturing method of a VDM0S device, which can form a P-type barrier layer with better uniformity, and has a single process, is easy to control, and has low manufacturing cost.
  • the present invention provides a method for fabricating a VDM0S device, including: providing a semiconductor substrate, wherein a first N-type epitaxial layer is formed on the semiconductor substrate; and forming over the first N-type epitaxial layer a hard mask layer having an opening;
  • the material of the first N-type epitaxial layer is epitaxial single crystal silicon, and the thickness ranges from 5 to 20 meters, and the resistivity ranges from 30 to 60 ohms ⁇ cm.
  • the material of the P-type barrier layer is epitaxial single crystal silicon, and the resistivity is 10 to 20 ohm ⁇ cm.
  • the material of the second N-type epitaxial layer is epitaxial single crystal silicon, and has a thickness ranging from 3 to 5 meters and a resistivity of 30 to 60 ohms ⁇ cm.
  • the forming method of the P-type barrier layer is a selective epitaxy method.
  • the material of the hard mask layer is selected from the group consisting of silicon oxide, silicon nitride, and low temperature oxide.
  • doping concentration and doping of the second N-type epitaxial layer and the first N-type epitaxial layer The same type.
  • the present invention further provides a VDMOS device, comprising: a semiconductor substrate, a first N-type epitaxial layer located in a semiconductor substrate, further comprising: a first N-type epitaxy on both sides of the first N-type epitaxial layer a P-type barrier layer having the same layer thickness; a second N-type epitaxial layer above the first N-type epitaxial layer and the P-type barrier layer, a gate on the second N-type epitaxial layer, and a gate electrode
  • the source in the second N-type epitaxial layer on the side is located at the drain of the back surface of the semiconductor substrate corresponding to the gate and the source.
  • the material of the first N-type epitaxial layer is epitaxial single crystal silicon, and the thickness ranges from 5 to 20 meters, and the resistivity ranges from 30 to 60 ohms ⁇ cm.
  • the material of the P-type barrier layer is epitaxial single crystal silicon, and the resistivity is 10-20 ohm ⁇ cm.
  • the material of the second N-type epitaxial layer is epitaxial single crystal silicon, and has a thickness ranging from 3 to 5 meters and a resistivity of 30 to 60 ohms ⁇ cm.
  • the present invention has the following advantages:
  • the method does not require high-energy ion implantation, and does not require multiple ion implantation and high-temperature annealing, and is formed at one time.
  • a better P-type barrier layer the method is simple, easy to control, and reduces the manufacturing cost of the VDMOS device.
  • FIG. 4 are schematic cross-sectional structural views showing a method of fabricating a VDMOS device of the prior art
  • FIG. 5 is a flow chart showing a method for fabricating a VDMOS device of the present invention
  • 6 to 12 are schematic cross-sectional structural views showing a method of fabricating a VDMOS device of the present invention. detailed description
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first feature and the second feature. The embodiment, such that the first and second features may not be in direct contact.
  • the prior art increases the doping concentration of the first N-type epitaxial layer, and forms the same thickness on both sides of the first N-type epitaxial layer as the first N-type epitaxial layer. P-type barrier.
  • the prior art is divided into a plurality of epitaxial steps to form a first N-type epitaxial layer, wherein each epitaxial step forms a sub-epitaxial layer having a thickness that is a portion of the thickness of the first N-type epitaxial layer.
  • P-type ion implantation is performed on the sub-epitaxial layer at a certain oblique angle (for example, 45 degrees), and a sub-blocking layer is formed on both sides of the sub-epitaxial layer until a plurality of sub-epitaxial layers are formed.
  • the first N-type epitaxial layer, the sub-barrier layer on both sides of the sub-epitaxial layer constitutes a P-type barrier layer.
  • the prior art also requires a high temperature annealing step after P-type ion implantation.
  • FIG. 5 is a schematic flow chart of a method for fabricating a VDMOS device according to the present invention. The method includes:
  • Step S1 providing a semiconductor substrate, a first N-type epitaxial layer is formed on the semiconductor substrate; Step S2, forming a hard mask layer having an opening above the first N-type epitaxial layer; Step S3, along the Opening etches the first N-type epitaxial layer to expose the semiconductor substrate to form a P-type barrier pattern;
  • Step S4 forming a P-type barrier layer in the P-type barrier pattern, which is the same thickness as the first N-type epitaxial layer;
  • Step S5 removing the hard mask layer
  • Step S6 forming a second N-type epitaxial layer on the first N-type epitaxial layer and the P-type barrier layer; Step S7, forming a gate above the second N-type epitaxial layer, on both sides of the gate A source is formed in the two N-type epitaxial layers, and a drain is formed on the back surface of the semiconductor substrate corresponding to the gate and the source.
  • FIG. 6 to FIG. 12 are schematic cross-sectional structural views of the manufacturing method of the VDMOS device of the present invention.
  • a semiconductor substrate 200 is provided.
  • the conductivity type of the semiconductor substrate 200 is N-type.
  • a first N-type epitaxial layer 201 is formed over the semiconductor substrate 200.
  • the material of the first N-type epitaxial layer 201 is epitaxial single crystal silicon, and the resistivity ranges from 30 to 60 ohm ⁇ cm, the thickness ranges from 5 to 20 micrometers, the doping impurity is AS, and the impurity concentration range is lE13. ⁇ lE15cm- 2 .
  • a hard mask layer 202 is deposited over the first N-type epitaxial layer 201.
  • the material of the hard mask layer 202 is selected from silicon oxide or silicon nitride.
  • the material of the hard mask layer 202 is selected from silicon oxide and has a thickness ranging from 300 to 500 angstroms.
  • the formation method may be a thermal oxidation method and a low temperature oxidation method.
  • the material of the hard mask layer 202 may be silicon nitride, and the thickness thereof ranges from 500 to 3500 angstroms, and the formation method may be a low pressure vapor deposition method; when the hard mask layer 202 In the case of silicon nitride, a buffer oxide layer having a thickness of 20 to 100 angstroms is further included between the hard mask layer 202 and the first N-type epitaxial layer 201 for buffering the hard mask layer 202 and the first N-type epitaxial layer. Stress between 202. Next, referring to FIG. 7, a photoresist pattern 203 is formed over the hard mask layer 202.
  • the photoresist pattern 203 covers a portion of the hard mask layer 202, and the photoresist pattern 203 is used as a mask for dry etching. In the etching process, the hard mask layer 202 not protected by the photoresist pattern 203 is removed, and an opening d is formed in the hard mask layer 202. It should be noted that, as an illustration, only the hard mask layer 202 between the two openings d is shown in FIG.
  • the photoresist pattern 203 is retained, and the same etching machine etching the hard mask layer 202 is used along the edge.
  • the opening d is etched until the semiconductor substrate 200 is exposed to form a P-type barrier pattern 215, which can reduce the time for exposing the product to air and reduce particle contamination of the product.
  • a wet etching process is performed to remove the photoresist pattern 203.
  • a P-type barrier layer 204 is formed in the P-type barrier pattern 215, which is the same thickness as the first N-type epitaxial layer 201.
  • the P-type barrier layer 204 is formed by a selective epitaxial process.
  • the material of the P-type barrier layer 204 is epitaxial single crystal silicon, and the resistivity is 10-20 ohm ⁇ cm.
  • a wet etching process may be performed to remove the photoresist pattern. Thereafter, dry etching is performed along the opening until the semiconductor substrate is exposed to form a P-type barrier pattern. Then, a P-type barrier layer is formed in the P-type barrier pattern.
  • the material of the P-type barrier layer is epitaxial single crystal silicon, and the resistivity is 10-20 ohm ⁇ cm.
  • an etching process is performed to remove the hard mask layer 202 to expose the remaining first N-type epitaxial layer 201; above the remaining first N-type epitaxial layer 201 and the P-type barrier layer 204.
  • a second N-type epitaxial layer 205 is formed.
  • the material of the second N-type epitaxial layer 205 is epitaxial single crystal silicon, and has a thickness ranging from 3 to 5 micrometers and a resistivity ranging from 10 to 20 ohms ⁇ cm.
  • the second N-type epitaxial layer 205 and the first N-type epitaxial layer 201 are formed by the same epitaxial deposition parameter, thereby ensuring the resistivity and doping concentration, doping type and first N-type epitaxy of the second N-type epitaxial layer 205.
  • Layer 201 is identical.
  • a P-type barrier layer 204 having an opposite conductivity type is formed on both sides of the first N-type epitaxial layer 201, the thickness of the P-type barrier layer 204 and the first N-type epitaxial layer. 201 is the same.
  • the resistivity of the P-type epitaxial layer 204 needs to be specifically set according to the doping concentration and resistivity of the P-type barrier layer of the prior art. Since only one process step is used to form a P-type barrier Compared with the prior art, the multi-epitaxial process, the multiple ion implantation and the high-temperature annealing process greatly reduce the process steps, reduce the process complexity, and reduce the manufacturing cost of the VDMOS device.
  • an oxide layer is deposited on the second N-type epitaxial layer 205, and the oxide layer is etched to form a gate dielectric layer 211.
  • the width of the gate dielectric layer 211 is greater than the width of the second N-type epitaxial layer 205 below it.
  • the thickness of the gate dielectric layer 211 ranges from 30 to 1000 angstroms.
  • Polysilicon is deposited on the gate dielectric layer 211 and etched to form a polysilicon gate layer 208 having a thickness in the range of 1000 to 4000 angstroms.
  • P-well implantation is performed in the second N-type epitaxial layer 205 on both sides of the gate dielectric layer 211 and the polysilicon gate 208 to form a P well 207.
  • the P well 207 is in contact with the P-type barrier layer 204, the first N-type epitaxial layer 205, and the width of the P-well 207 is greater than the width of the P-type barrier layer 204 below it.
  • the P-well implanted element is ⁇ BF 2
  • the energy range is
  • the dose range is lE12 ⁇ lE13cm- 2 .
  • N-type heavily doped ion implantation is performed in the P well 207 to form an N-type heavily doped region 206.
  • the element of the N-type heavily doped ion implantation is P, As, the energy range is 50 ⁇ 130KEV, and the dose range is 1E15 ⁇ 2E16 cm- 2 .
  • a metallization process is performed on the device, a source metal layer 210 is formed over the N-type heavily doped region 206, and a gate metal layer 209 is formed over the polysilicon gate layer 208;
  • the substrate 200 is subjected to backside thinning and a back metal process, and a drain metal layer 212 is formed on the back surface of the semiconductor substrate 200 corresponding to the polysilicon gate layer 208 and the N-type heavily doped region 206.
  • the back side of the present invention refers to the opposite side of the growth surface of the device on the semiconductor substrate 200.
  • the polysilicon gate layer 208 and the gate metal layer 209 form the gate G of the VDMOS device.
  • the N-type heavily doped region 206 and the source metal layer 210 together form the source S of the VDMOS device.
  • the bottom 200 and the drain metal layer 212 together form the drain of the VDMOS.
  • the present invention further provides a VDMOS device.
  • the device includes: an N-type semiconductor substrate 200; a first N-type epitaxial layer 201 located above the semiconductor substrate 200, located at the first N a P-type barrier layer 204 having the same thickness as the first N-type epitaxial layer 201 on both sides of the epitaxial layer 201; a second N-type epitaxial layer 205 located above the first N-type epitaxial layer 201 and the P-type barrier layer 204, a source S of the VDMOS located above the second N-type epitaxial layer 205, a gate G located in the second N-type epitaxial layer 205 on both sides of the source S, under the gate S and the source G The drain D of the VDMOS on the back of the semiconductor substrate 200.
  • the back side of the present invention refers to the opposite side of the growth surface of the device on the semiconductor substrate 200.
  • the source S is composed of a P well 207 located above the P-type barrier layer 204, an N-type heavily doped region 206 located within the P-well 207, and a source metal 210 over the N-type heavily doped region 206.
  • the gate G is composed of a polysilicon gate layer 208 over the second N-type epitaxial layer 205 and a gate metal layer 209 over the polysilicon gate layer 208.
  • the drain D is composed of the semiconductor substrate 200 and a drain metal layer 212 on the back surface of the semiconductor substrate 200.
  • the P well 207 is in contact with the first N-type epitaxial layer 201 and the P-type barrier layer 204, and the width of the P well 207 is greater than the width of the P-type barrier layer 204.
  • the material of the first N-type epitaxial layer 201 is epitaxial single crystal silicon, and the thickness ranges from 5 to 20 micrometers, and the resistivity ranges from 30 to 60 ohm ⁇ cm.
  • the material of the P-type barrier layer 204 is epitaxial single crystal silicon, and the resistivity is 10-20 ohm ⁇ cm.
  • the material of the second N-type epitaxial layer 205 is epitaxial single crystal silicon, and has a thickness ranging from 3 to 5 micrometers and a resistivity of 30 to 60 ohm.cm.
  • the method for fabricating a VDMOS device can also be used to fabricate an Insulated Gate Bipolar Transistor (IGBT).
  • the method includes: providing a semiconductor substrate, a first N-type epitaxial layer is formed on the semiconductor substrate; forming a hard mask layer having an opening above the first N-type epitaxial layer; Opening-etching the first N-type epitaxial layer to expose the semiconductor substrate to form a P-type barrier pattern; forming a P-type barrier layer in the P-type barrier pattern, having the same thickness as the first N-type epitaxial layer; a hard mask layer; forming a second N-type epitaxial layer on the first N-type epitaxial layer and the P-type barrier layer; forming a gate above the second N-type epitaxial layer on both sides of the gate A source is formed in the second N-type epitaxial layer, and a drain is formed on the back surface of the semiconductor substrate corresponding to the gate and the source. Prior to fabrication of the drain,
  • the present invention provides a VDMOS device and a method of fabricating the same, which form a P-type barrier layer directly on both sides of the first N-type epitaxial layer, which reduces the fabrication steps of the VDMOS device and reduces the fabrication cost of the VDMOS device.
  • the method can also be used to fabricate an insulated gate bipolar transistor.

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Description

VDMOS器件及其制作方法
本申请要求于 2010 年 6 月 25 日提交中国专利局、 申请号为 201010213340.4、 发明名称为" VDMOS器件及其制作方法"的中国专利申请的 优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及功率器件，特别涉及利用选择性外延工艺制作 VDMOS器件的 方法及 VDMOS器件的结构。 背景技术
垂直双扩散金属氧化物半导体场效应管（ VDM0S )作为功率器件的一种， 由于其具有高输入阻抗和低导通压降的优点而被广泛应用。
现有技术 VDM0S器件的制作方法如申请号为 200810057881.5的中国专 利申请中公开的， 具体参考图 1至图 4所示。 如图 1所示， 首先， 提供 N 型半导体村底 100, 在所述 N型半导体村底 100上形成 N型外延层 101; 然 后， 在所述 N型外延层 101上方依次形成栅氧化层 111和位于所述栅氧化 层 111上方的多晶硅栅层 108; 接着， 请参考图 2, 对所述 N型外延层 101 进行 P阱注入， 形成 P阱 107, 所述 P阱 107位于多晶栅层 108的两侧； 接着， 对所述 P阱 107下方的 N型外延层 101进行离子注入， 形成 P型阻 挡层 104; 然后， 参考图 3, 进行重掺杂离子注入， 在所述 P阱 107内形成 N型重掺杂区 106; 最后， 参考图 4, 进行金属化工艺， 在多晶硅栅层 108 上方形成栅极金属层 109, 在 N型重掺杂区 106上方形成源极金属层 110, 在半导体村底 100 的背面形成漏极金属层 112, 所述背面是指半导体村底 100上器件生长面的相对面。 所述栅极金属层 109与多晶硅栅层 108共同 构成栅极 G, 所述源极金属层 110和 N型重掺杂区 106共同构成了源极 S, 所述漏极金属层 112与半导体村底 100构成了漏极 D。
现有技术形成的 P型阻挡层的掺杂杂质的均匀性不好， 增大了 VDMOS 器件的导通压降与沟道电阻。
为了解决上述问题， 现有技术在所述 N型外延层 101进行多次离子注 入以及高温退火步骤， 在 N型外延层 1 01两侧形成 P型阻挡层。 但是多次 离子注入和高温退火步骤， 工艺复杂， 离子注入的均匀性不好控制， 并且 制造成本高。
因此， 需要一种 VDM0S器件的制作方法， 能够形成均匀性较好的 P型 阻挡层， 同时工艺筒单， 容易控制， 制造成本低。 发明内容
本发明提供了一种 VDM0S 器件的制作方法， 能够形成均匀性较好的 P 型阻挡层， 同时工艺筒单， 容易控制， 制造成本低。
为了实现上述目的， 本发明提供了一种 VDM0S器件的制作方法， 包括： 提供半导体村底， 所述半导体村底上形成有第一 N型外延层； 在所述第一 N型外延层上方形成具有开口的硬掩膜层；
沿所述开口刻蚀第一 N型外延层至露出半导体村底， 形成 P型阻挡图 形；
在所述 P型阻挡图形内形成 P型阻挡层， 与所述第一 N型外延层厚度 相同；
去除所述硬掩膜层；
在所述第一 N型外延层和 P型阻挡层上形成第二 N型外延层； 在所述第二 N型外延层上方形成栅极， 在栅极两侧的第二 N型外延层 内形成源极， 在与栅极和源极对应的半导体村底背面形成漏极。
可选的， 所述第一 N型外延层的材料为外延单晶硅， 厚度范围为 5 ~20 米， 电阻率范围为 30~60欧姆 ·厘米。
可选的， 所述 P型阻挡层的材料为外延单晶硅， 电阻率为 1 0~2 0欧姆 · 厘米。
可选的， 所述第二 N型外延层的材料为外延单晶硅， 厚度范围为 3~5 米， 电阻率为 30~60欧姆 ·厘米。
可选的， 所述 P型阻挡层的形成方法为选择性外延法。
可选的， 所述硬掩膜层的材质选自氧化硅、 氮化硅、 低温氧化物。 可选的， 所述第二 N型外延层和第一 N型外延层的掺杂浓度和掺杂类 型相同。
相应的， 本发明还提供一种 VDM0S器件， 包括： 半导体村底， 位于半 导体村底中的第一 N型外延层， 还包括： 位于第一 N型外延层两侧的与第 一 N型外延层厚度相同的 P型阻挡层； 位于所述第一 N型外延层和 P型阻 挡层上方的第二 N型外延层， 位于所述第二 N型外延层上的栅极， 位于栅 极两侧的第二 N型外延层内的源极， 位于栅极和源极对应的半导体村底背 面的漏极。
可选的， 所述第一 N型外延层的材料为外延单晶硅， 厚度范围为 5 ~20 米， 电阻率范围为 30~60欧姆 ·厘米。
可选的， 所述 P型阻挡层的材料为外延单晶硅， 电阻率为 1 0~20欧姆 · 厘米。
可选的， 所述第二 N型外延层的材料为外延单晶硅， 厚度范围为 3~5 米， 电阻率为 30~60欧姆 ·厘米。 与现有技术相比， 本发明具有以下优点：
通过刻蚀 N型外延层， 并在 N型外延层两侧形成与其相邻的 P型阻挡 层， 所述方法无需进行高能离子注入， 并且不需要进行多次离子注入和高 温退火， 一次形成均勾度较好的 P型阻挡层， 所述方法工艺筒单， 容易控 制， 并且降低了 VDM0S器件的制作成本。 附图说明 通过附图所示， 本发明的上述及其它目的、 特征和优势将更加清晰。 在全 部附图中相同的附图标记指示相同的部分。并未刻意按实际尺寸等比例缩放绘 制附图， 重点在于示出本发明的主旨。
图 1至图 4是现有技术 VDMOS器件的制作方法剖面结构示意图； 图 5是本发明的 VDMOS器件制作方法流程示意图；
图 6至图 12是本发明的 VDMOS器件制作方法剖面结构示意图。 具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。 为了筒化本发明的公开， 下文中对特定例子的部件和设置进行描述。 当然， 它 们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在不同例子中 重复参考数字和 /或字母。 这种重复是为了筒化和清楚的目的， 其本身不指示 所讨论各种实施例和 /或设置之间的关系。 此外， 本发明提供了的各种特定的 工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于 性和 /或其他材料的使用。
另外， 以下描述的第一特征在第二特征之 "上" 的结构可以包括第一和第 二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特 征之间的实施例， 这样第一和第二特征可能不是直接接触。
为了减小 VDMOS器件的导通压降并且改善沟道电阻，现有技术提高第一 N型外延层的掺杂浓度， 在第一 N型外延层两侧形成与第一 N型外延层厚度 相同的 P型阻挡层。 现有技术分为多个外延步骤形成第一 N型外延层， 其中， 每个外延步骤形成一个子外延层， 其厚度为第一 N型外延层厚度的一部分。 在形成一子外延层后， 以一定的倾斜角度（例如是 45度）对该子外延层进行 P型离子注入， 在所述子外延层两侧形成子阻挡层， 直至多个子外延层构成所 述第一 N型外延层， 所述子外延层两侧的子阻挡层构成 P型阻挡层。 通常为 了保证注入的离子激活，现有技术在进行 P型离子注入后还需要进行高温退火 步骤。
由于现有技术需要多次离子注入以及高温退火步骤，使 VDMOS器件制作 方法工艺较复杂， 不易控制， 并且 VDMOS器件的制造成本较高。发明人经过 研究发现， 对第一 N型外延层进行刻蚀后， 在其两侧直接形成与其厚度一致 的 P型阻挡层， 然后在所述第一 N型外延层和 P型阻挡层上方形成第二 N型 外延层， 在所述第二 N型外延层形成 VDMOS器件。 所述方法筒单， 容易控 制， 形成的 VDMOS器件的参数稳定， 降低了生产成本。 请参考图 5, 图 5是 本发明 VDMOS器件制作方法流程示意图。 所述方法包括：
步骤 S1 , 提供半导体村底， 所述半导体村底上形成有第一 N型外延层； 步骤 S2, 在所述第一 N型外延层上方形成具有开口的硬掩膜层； 步骤 S3 , 沿所述开口刻蚀第一 N型外延层至露出半导体村底， 形成 P型 阻挡图形；
步骤 S4, 在所述 P型阻挡图形内形成 P型阻挡层， 与所述第一 N型外延 层厚度相同；
步骤 S5 , 去除所述硬掩膜层；
步骤 S6, 在所述第一 N型外延层和 P型阻挡层上形成第二 N型外延层； 步骤 S7, 在所述第二 N型外延层上方形成栅极， 在栅极两侧的第二 N型 外延层内形成源极， 在与栅极和源极对应的半导体村底背面形成漏极。
下面将结合具体实施例对本发明的技术方案进行详细说明。 请参考图 6 至图 12, 图 6至图 12是本发明的 VDMOS器件制作方法剖面结构示意图。
首先， 请参考图 6, 提供半导体村底 200。 作为一个实施例， 所述半导体 村底 200的导电类型为 N型。 在所述半导体村底 200上方形成第一 N型外延层 201。 所述第一 N型外延层 201的材料为外延单晶硅， 其电阻率范围为 30~60 欧姆 ·厘米， 厚度范围为 5~20微米， 掺杂杂质为 AS, 掺杂杂质浓度范围为 lE13~lE15cm- 2。
继续参考图 6, 在所述第一 N型外延层 201上方沉积硬掩膜层 202, 所述 硬掩膜层 202的材质选自氧化硅或氮化硅。作为本发明的一个实例， 所述硬掩 膜层 202的材质选自氧化硅，其厚度范围为 300~500埃，形成方法可以是热氧 化方法和低温氧化的方法。作为本发明的另一实施例， 所述硬掩膜层 202的材 质可以为氮化硅， 其厚度范围为 500~3500埃， 形成方法可以是低压气相沉积 方法； 当所述硬掩膜层 202为氮化硅时， 则硬掩膜层 202和第一 N型外延层 201之间还包括厚度为 20~100埃的緩沖氧化层， 用于緩沖硬掩膜层 202与第 一 N型外延层 202之间的应力。 接着， 参考图 7, 在所述硬掩膜层 202上方形成光阻图案 203 , 所述光阻 图案 203覆盖部分硬掩膜层 202, 以所述光阻图案 203为掩膜， 进行干法刻蚀 工艺， 去除未被所述光阻图案 203保护的硬掩膜层 202, 在所述硬掩膜层 202 内形成开口 d。 需要说明的是， 作为示意， 在图 7中仅示出了两个开口 d之间 的硬掩膜层 202。
作为优选的实施例， 参考图 8, 在所述硬掩膜层 202内形成开口 d后， 保 留所述光阻图案 203 , 利用刻蚀所述硬掩膜层 202的同一刻蚀机台， 沿所述开 口 d进行刻蚀直至露出半导体村底 200, 形成 P型阻挡图形 215 , 这样可以减 小将产品暴露于空气的时间， 减少产品的颗粒污染。 然后， 参考图 9, 进行湿 法刻蚀工艺， 去除光阻图案 203。 然后， 在所述 P型阻挡图形 215内形成 P型 阻挡层 204, 与所述第一 N型外延层 201厚度相同。所述 P型阻挡层 204的制 作方法为选择性外延工艺。所述 P型阻挡层 204的材料为外延单晶硅， 电阻率 为 10~20欧姆 ·厘米。
作为又一实施例，可以在所述硬掩膜层内形成开口后，进行湿法刻蚀工艺， 去除所述光阻图案。 之后， 沿所述开口进行干法刻蚀， 直至露出半导体村底， 形成 P型阻挡图形。 然后， 在所述 P型阻挡图形内形成 P型阻挡层。 所述 P 型阻挡层的材料为外延单晶硅， 电阻率为 10~20欧姆 ·厘米。
接着， 参考图 10, 进行刻蚀工艺， 去除硬掩膜层 202, 露出剩余的第一 N 型外延层 201 ;在所述剩余的第一 N型外延层 201和所述 P型阻挡层 204上方 形成第二 N型外延层 205。 所述第二 N型外延层 205的材质为外延单晶硅， 其厚度范围为 3~5微米， 电阻率范围为 10~20欧姆 ·厘米。 所述第二 N型外延 层 205与第一 N型外延层 201利用同一外延沉积参数形成， 这样保证第二 N 型外延层 205的电阻率和掺杂浓度、 掺杂类型与第一 N型外延层 201完全相 同。
如图 10所示， 经过上述步骤， 在第一 N型外延层 201两侧形成了与其具 有相反导电类型的 P型阻挡层 204,所述 P型阻挡层 204的厚度与第一 N型外 延层 201相同。所述 P型外延层 204的电阻率需要根据现有技术的 P型阻挡层 的掺杂浓度和电阻率进行具体的设置。由于仅采用一个工艺步骤形成 P型阻挡 层， 与现有技术采用多次外延工艺、 多次离子注入以及高温退火工艺相比， 大 大减少了工艺步骤， 降低了工艺复杂程度， 降低了 VDMOS器件的制造成本。
然后， 请参考图 11 , 在所述第二 N型外延层 205上沉积氧化层， 对所述 氧化层进行刻蚀， 形成栅介质层 211。 所述栅介质层 211的宽度大于其下方的 第二 N型外延层 205的宽度。 所述栅介质层 211的厚度范围为 30~1000埃。 在所述栅介质层 211上沉积多晶硅， 对其进行刻蚀， 形成多晶硅栅层 208, 所 述多晶硅栅层 208的厚度范围为 1000~4000埃。
然后， 继续参考图 11 , 在所述栅介质层 211和多晶硅栅 208两侧的第二 N 型外延层 205内进行 P阱注入， 形成 P阱 207。 所述 P阱 207与 P型阻挡层 204、 第一 N型外延层 205接触，并且所述 P阱 207的宽度大于其下方的 P型阻挡层 204 的宽度。 作为一个实施例， 所述 P阱注入的元素为^ BF2, 能量范围为
40-80KEV, 剂量范围为 lE12~lE13cm— 2。 然后， 在所述 P阱 207内进行 N型重 掺杂离子注入， 形成 N型重掺杂区 206。 所述 N型重掺杂离子注入的元素为 P、 As , 能量范围为 50~130KEV, 剂量范围为 1E15~2E16 cm- 2。
接着， 参考图 12,对所述器件进行金属化工艺，在所述 N型重掺杂区 206 上方形成源极金属层 210, 在多晶硅栅层 208上方形成栅极金属层 209; 对所 述半导体村底 200进行背面减薄以及背面金属工艺， 在多晶硅栅层 208和 N 型重掺杂区 206对应的半导体村底 200背面形成漏极金属层 212。 其中本发明 所述背面是指半导体村底 200上器件生长面的相对面。 所述多晶硅栅层 208 与栅极金属层 209构成了 VDMOS器件的栅极 G, 所述 N型重掺杂区 206与 源极金属层 210共同构成了 VDMOS器件的源极 S,所述半导体村底 200与漏 极金属层 212共同构成了 VDMOS的漏极。
相应的， 本发明还提供一种 VDMOS器件， 请参考图 12, 所述器件包括： N型半导体村底 200; 位于所述半导体村底 200上方的第一 N型外延层 201 , 位于第一 N型外延层 201两侧的与第一 N型外延层 201厚度相同的 P型阻挡 层 204; 位于所述第一 N型外延层 201和 P型阻挡层 204上方的第二 N型外 延层 205, 位于所述第二 N型外延层 205上方的 VDMOS的源极 S, 位于源极 S两侧的第二 N型外延层 205内的栅极 G, 位于所述栅极 S和源极 G下方的 半导体村底 200背面的 VDMOS的漏极 D。其中本发明所述背面是指半导体村 底 200上器件生长面的相对面。 所述源极 S由位于 P型阻挡层 204上方的 P 阱 207、 位于 P阱 207内的 N型重掺杂区 206和位于 N型重掺杂区 206上方 的源极金属 210构成。 所述栅极 G由位于第二 N型外延层 205上方的多晶硅 栅层 208、 位于所述多晶硅栅层 208上方的栅极金属层 209构成。 所述漏极 D 由所述半导体村底 200和位于半导体村底 200背面的漏极金属层 212构成。所 述 P阱 207与所述第一 N型外延层 201、 P型阻挡层 204接触， 并且 P阱 207 的宽度大于所述 P型阻挡层 204的宽度。 本实施例中， 所述第一 N型外延层 201的材料为外延单晶硅， 厚度范围为 5~20微米， 电阻率范围为 30~60欧姆 · 厘米。 所述 P型阻挡层 204的材料为外延单晶硅， 电阻率为 10~20欧姆 ·厘米。 所述第二 N型外延层 205的材料为外延单晶硅， 厚度范围为 3~5微米， 电阻 率为 30~60欧姆 ·厘米。
需要说明的是，本发明提供的制作 VDMOS器件的制作方法，还可以用于 制作绝缘栅双极型晶体管（ Insulated Gate Bipolar Transistor, IGBT)。 作为一个 实施例， 所述方法包括： 提供半导体村底， 所述半导体村底上形成有第一 N 型外延层； 在所述第一 N型外延层上方形成具有开口的硬掩膜层； 沿所述开 口刻蚀第一 N型外延层至露出半导体村底， 形成 P型阻挡图形； 在所述 P型 阻挡图形内形成 P型阻挡层， 与所述第一 N型外延层厚度相同； 去除所述硬 掩膜层； 在所述第一 N型外延层和 P型阻挡层上形成第二 N型外延层； 在所 述第二 N型外延层上方形成栅极，在栅极两侧的第二 N型外延层内形成源极， 在与栅极和源极对应的半导体村底背面形成漏极。在制作所述漏极之前， 需要 对半导体村底的背面进行 p型重掺杂离子注入。其中本发明所述背面是指半导 体村底上器件生长面的相对面。
综上，本发明提供了一种 VDMOS器件及其制作方法，所述方法直接在第 一 N型外延层两侧形成 P型阻挡层， 减少了 VDMOS器件的制作步骤， 降低 了 VDMOS器件的制作成本， 所述方法还可以用于制作绝缘栅双极型晶体管。
本发明虽然已以较佳实施例公开如上，但其并不是用来限定本发明，任何 本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法 和技术内容对本发明技术方案做出可能的变动和修改， 因此， 凡是未脱离本发 改、 等同变化及修饰， 均属于本发明技术方案的保护范围。

Claims

权 利 要 求
1. 一种 VDMOS器件的制作方法， 其特征在于， 包括：
提供半导体村底， 所述半导体村底上形成有第一 N型外延层；
在所述第一 N型外延层上方形成具有开口的硬掩膜层；
沿所述开口刻蚀第一 N型外延层至露出半导体村底， 形成 P型阻挡图形； 在所述 P型阻挡图形内形成 P型阻挡层，与所述第一 N型外延层厚度相同； 去除所述硬掩膜层；
在所述第一 N型外延层和 P型阻挡层上形成第二 N型外延层；
在所述第二 N型外延层上方形成栅极，在栅极两侧的第二 N型外延层内形 成源极， 在与栅极和源极对应的半导体村底背面形成漏极。
2. 如权利要求 1所述的 VDMOS器件的制作方法， 其特征在于， 所述第一 N 型外延层的材料为外延单晶硅， 厚度范围为 5~20 微米 ， 电阻率范围为 30~60欧姆 ·厘米。
3. 如权利要求 1所述的 VDMOS器件的制作方法， 其特征在于， 所述 P型阻 挡层的材料为外延单晶硅， 电阻率为 10~20欧姆 ·厘米。
4. 如权利要求 1所述的 VDMOS器件的制作方法， 其特征在于， 所述第二 N 型外延层的材料为外延单晶硅， 厚度范围为 3~5微米， 电阻率为 30~60欧 姆 ·厘米。
5. 如权利要求 1所述的 VDMOS器件的制作方法， 其特征在于， 所述 P型阻 挡层的形成方法为选择性外延法。
6. 如权利要求 1所述的 VDMOS器件的制作方法， 其特征在于， 所述硬掩膜 层的材质选自氧化硅、 氮化硅、 低温氧化物。
7. 如权利要求 1所述的 VDMOS器件的制作方法， 其特征在于， 所述第二 N 型外延层和第一 N型外延层的掺杂浓度和掺杂类型相同。
8. 一种 VDMOS器件， 包括： 半导体村底， 位于半导体村底上方的第一 N型 外延层， 其特征在于， 还包括： 位于第一 N型外延层两侧的与第一 N型外 延层厚度相同的 P型阻挡层； 位于所述第一 N型外延层和 P型阻挡层上方 的第二 N型外延层， 位于所述第二 N型外延层上的栅极， 位于栅极两侧的 第二 N型外延层内的源极，位于栅极和源极对应的半导体村底背面的漏极。
9. 如权利要求 9所述的 VDMOS器件， 其特征在于， 所述第一 N型外延层的 材料为外延单晶硅， 厚度范围为 5~20微米， 电阻率范围为 30~60欧姆 *厘 米。
10.如权利要求 9所述的 VDMOS器件， 其特征在于， 所述 P型阻挡层的材料 为外延单晶硅， 电阻率为 10~20欧姆 ·厘米。
11.如权利要求 9所述的 VDMOS器件的制作方法， 其特征在于， 所述第二 N 型外延层的材料为外延单晶硅， 厚度范围为 3~5微米， 电阻率为 30~60欧 姆 ·厘米。
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