WO2021042611A1 - 一种碳化硅半导体器件终端及其制造方法 - Google Patents

一种碳化硅半导体器件终端及其制造方法 Download PDF

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WO2021042611A1
WO2021042611A1 PCT/CN2019/123744 CN2019123744W WO2021042611A1 WO 2021042611 A1 WO2021042611 A1 WO 2021042611A1 CN 2019123744 W CN2019123744 W CN 2019123744W WO 2021042611 A1 WO2021042611 A1 WO 2021042611A1
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silicon carbide
ring
auxiliary
well region
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PCT/CN2019/123744
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French (fr)
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温正欣
叶怀宇
张国旗
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深圳第三代半导体研究院
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of silicon carbide semiconductor device preparation, and in particular to a terminal structure and a preparation method for high-voltage silicon carbide power devices.
  • the structure is suitable for high-voltage silicon carbide power devices of 1200V to 20kV, and can be implanted in fewer terminals. To achieve high terminal doping tolerance under conditions, significantly improve the device yield.
  • Silicon carbide has excellent physical and electrical properties, low intrinsic carrier concentration, high thermal conductivity, high breakdown field strength and other advantages, as well as excellent physical and chemical stability. Therefore, silicon carbide has become an ideal material for high-temperature and high-power semiconductor devices.
  • silicon carbide-based power devices are much higher than traditional silicon-based power devices in terms of material cost and manufacturing cost, which limits the development and application of silicon carbide-based power devices.
  • junction discontinuities at the edge of the device due to the limited size of the device, there are junction discontinuities at the edge of the device, resulting in curvature of the junction edge, resulting in surface electric field concentration, making the junction edge electric field strength higher than the internal planar junction electric field strength, and premature breakdown occurs. This effect seriously affects the blocking characteristics of power devices.
  • a junction termination structure is usually arranged at the edge of the power device junction.
  • Common terminal structures mainly include field boards, field limit loops, and junction terminal extensions (JTE).
  • the field plate structure is usually used for lower voltage power semiconductor devices, and is usually used in combination with other structures in high voltage power semiconductor devices.
  • the field limiting ring structure occupies a large amount of device area and requires high lithography accuracy.
  • the extension of the junction terminal is very sensitive to the terminal doping concentration and the interface charge of the passivation layer. Because the selective doping of the silicon carbide material needs to be achieved by annealing activation after ion implantation, the activation rate is affected by the ion implantation temperature, doping concentration and activation temperature It is difficult to accurately grasp the influence of many factors such as the activation time and the activation time. Therefore, the terminal yield rate of the high-voltage silicon carbide device prepared by the junction terminal expansion is relatively low.
  • the present invention provides a terminal structure suitable for high-voltage silicon carbide power devices and a preparation method, which utilizes fewer photoetching times and ion implantation times to form a terminal structure suitable for high-voltage silicon carbide power devices, and has tolerance to terminal doping concentration Large, compatible with the advantages of existing silicon carbide power device technology.
  • the present invention proposes a terminal structure suitable for high-voltage silicon carbide devices.
  • the terminal structure occupies a small area of the wafer.
  • the breakdown voltage has a high tolerance to the terminal doping concentration, and it is fully compatible with the existing silicon carbide power device technology.
  • the technical scheme of the present invention comprehensively considers the aspects of material characteristics, process difficulty, device performance and cost, etc., and provides a terminal structure suitable for high-voltage silicon carbide power devices.
  • the terminal structure can be implemented in devices such as silicon carbide MOSFET and silicon carbide IGBT.
  • the left side of Figure 1 is the device cell structure, and the dashed box on the right side is the new device terminal structure proposed by the present invention.
  • the terminal includes several well area auxiliary rings (3), a junction terminal extension (4), several junction terminal auxiliary rings (5), several base area auxiliary rings (6) and a passivation layer (7).
  • the well region auxiliary ring (3) is located outside the well region (2).
  • the junction terminal auxiliary ring (5) is located outside the junction terminal extension (4), and the base area auxiliary ring (6) is located outside the junction terminal auxiliary ring (5).
  • the top of the well region auxiliary ring (3), junction terminal extension (4), junction terminal auxiliary ring (5) and base region auxiliary ring (6) are provided with a passivation layer (7) formed by thermal oxidation and PECVD.
  • the well region auxiliary ring (3) and the well region (2) are formed at the same time, so they have the same doping concentration and depth as the well region (2).
  • the number of well region auxiliary rings is more than 3, and the ring width is equal.
  • the spacing gradually increases.
  • the doping concentration of the well region is 2 ⁇ 10 17 cm -3 to 2 ⁇ 10 18 cm -3
  • the depth is 0.6 ⁇ m to 1 ⁇ m
  • the auxiliary ring of the well region is composed of 5 rings.
  • the depth of the junction terminal extension (4) is smaller than the depth of the well region (2).
  • the junction terminal auxiliary ring (5) and the junction terminal extension (4) are formed at the same time, so they have the same doping concentration and depth.
  • the number of junction terminal auxiliary rings (5) is more than 3, the ring widths are equal, and the ring spacing gradually increases.
  • the junction terminal extension (4) has a length of 20 ⁇ m to 400 ⁇ m, a doping concentration of 5 ⁇ 10 16 cm -3 to 3 ⁇ 10 17 cm -3 , and a depth of 0.4 ⁇ m to 0.5 ⁇ m.
  • the junction terminal auxiliary ring is 4 Ring formation
  • the base region auxiliary ring (6) is formed simultaneously with the P-type base region in the device cell, and therefore has the same doping concentration and depth as the P-type base region.
  • the number of auxiliary rings (6) in the base area is more than 3, the ring widths are equal, and the ring spacing gradually increases.
  • the doping concentration of the base auxiliary ring (6) is 1 ⁇ 10 18 cm -3 to 5 ⁇ 10 19 cm -3
  • the depth is 0.3 ⁇ m to 0.4 ⁇ m
  • the base auxiliary ring is composed of 4 rings.
  • a basic process flow of a silicon carbide MOSFET device including the terminal structure is proposed. It includes the following steps:
  • S1 epitaxially grow an N-type silicon carbide epitaxial layer on an N-type silicon carbide substrate;
  • junction terminal extension (4) and junction terminal auxiliary ring (5) Ion implantation forms junction terminal extension (4) and junction terminal auxiliary ring (5), and then activates annealing at high temperature.
  • the present invention designs a terminal structure suitable for silicon carbide power devices.
  • the silicon carbide power device using the terminal structure only needs to be formed on the basis of active region ion implantation and an additional junction terminal extended ion implantation.
  • the terminal also has the advantages of a smaller terminal area and higher tolerance to the terminal doping concentration.
  • FIG. 1 shows a schematic diagram of a silicon carbide MOSFET device using a single JTE terminal
  • FIG. 2 is a schematic diagram of a silicon carbide MOSFET device terminal structure using an embodiment of the present invention.
  • Figure 3 shows the relationship between the blocking voltage of a single JTE terminal and a silicon carbide MOSFET device using the terminal structure of the present invention and the expanded doping concentration of the junction terminal. It can be seen that the terminal structure of the present invention has a larger doping concentration tolerance range. .
  • Figure 4 shows the internal potential distribution of the 3300V silicon carbide MOSFET device using the terminal structure of the present invention in the blocking state. It can be seen that the well region auxiliary ring, the junction terminal expansion, the junction terminal auxiliary ring and the base auxiliary ring all bear the potential drop . Since the efficiency of the field limiting ring terminal is not sensitive to the doping concentration of the field limiting ring, but is sensitive to the spacing and depth of each ring, although the doping concentration of the auxiliary ring in the base region is much higher than the doping concentration of the junction terminal extension, In the design of the present invention, it is only necessary to ensure that the depth is less than the junction terminal extension, so that the auxiliary ring of the base region can further evenly share the electric potential.
  • Figure 1 is a schematic diagram of a silicon carbide MOSFET device using a single JTE terminal.
  • FIG. 2 is a schematic diagram of the terminal structure of a silicon carbide MOSFET device adopting an embodiment of the present invention
  • Figure 3 shows the internal potential distribution of a 3300V silicon carbide MOSFET device using the terminal structure of the present invention in a blocking state
  • Fig. 4 is a diagram showing the relationship between the blocking voltage of the single JTE terminal and the silicon carbide MOSFET device adopting the terminal structure of the present invention and the extension doping concentration of the junction terminal.
  • FIG. 5 is a flow chart of the device manufacturing process provided by an embodiment of the present invention.
  • step S2 of the device preparation process provided by an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of step S3 of the device preparation process provided by an embodiment of the present invention.
  • step S4 of the device preparation process provided by an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of step S5 of the device preparation process provided by an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a silicon carbide MOSFET structure adopting an embodiment of the present invention.
  • the dashed frame is the silicon carbide device terminal structure proposed by the present invention.
  • the terminal includes several well region auxiliary rings (3), a junction terminal extension (4), several junction terminal auxiliary rings (5), several base region auxiliary rings (6) and a passivation Layer (7).
  • the auxiliary ring (3) of the well region is located outside the well region (2), and the junction terminal extension (4) is next to the well region (2) and its depth is smaller than the depth of the well region (2).
  • junction terminal auxiliary ring (5) is located outside the junction terminal extension (4), and the base area auxiliary ring (6) is located outside the junction terminal auxiliary ring (5).
  • the top of the well region auxiliary ring (3), junction terminal extension (4), junction terminal auxiliary ring (5) and base region auxiliary ring (6) are provided with a passivation layer (7) formed by thermal oxidation and PECVD.
  • the doping concentration of the well region (2) and the well region auxiliary ring (3) is 2 ⁇ 10 17 cm -3 to 2 ⁇ 10 18 cm -3 , and the depth is 0.6 ⁇ m to 1 ⁇ m;
  • the junction terminal is expanded (4)
  • the length is 20 ⁇ m to 400 ⁇ m, the doping concentration is 5 ⁇ 10 16 cm -3 to 3 ⁇ 10 17 cm -3 , and the depth is 0.4 ⁇ m to 0.5 ⁇ m;
  • the doping concentration of the auxiliary ring (6) in the base region is 1 ⁇ 10 18 cm -3 to 5 ⁇ 10 19 cm -3 , with a depth of 0.3 ⁇ m to 0.4 ⁇ m.
  • the number of auxiliary rings (3) in the well region is set to 5, the width of each ring is 4 ⁇ m, and the spacing increases sequentially from the inside to the outside; the number of auxiliary rings (5) at the junction end is set to 4, the width of each ring is 4 ⁇ m, and the spacing is from the inside to the outside.
  • the outer portion increases sequentially, the number of the auxiliary ring (6) in the base area is set to 4, the ring width is 4 ⁇ m, and the spacing increases sequentially from the inside to the outside.
  • the device terminal of the present invention optimizes the electric field distribution in the high field region by introducing the well region auxiliary ring, the junction terminal auxiliary ring and the base region auxiliary ring on the basis of the expansion of the junction terminal, thereby improving the blocking characteristics of the device.
  • a basic process flow of a silicon carbide MOSFET device using the terminal of the present invention is provided, which includes the following steps:
  • Step S1 growing an N-type epitaxial layer on an N-type silicon carbide substrate.
  • Step S2 ion implantation simultaneously forms the well region (2) and the well region auxiliary ring (3).
  • Step S3 ion implantation to form an N-type doping source region.
  • the source region is formed after release implantation mask, then using the N ion implantation to form an N type source region at 500 °C, doping concentration is 1 ⁇ 10 18 cm -3 to 5 ⁇ 10 19 cm - 3. The depth is 0.25 ⁇ m.
  • the implantation mask is cleaned with a mixture of sulfuric acid and hydrogen peroxide to form a structure as shown in FIG. 5.
  • Step S4 ion implantation simultaneously forms the P-type doped base region and the base region auxiliary ring (6).
  • the metal is evaporated, and the implantation mask of the base region and the base region auxiliary ring is formed after stripping, and then Al ion is used to implant at 500 °C, and the base region and the base region auxiliary ring (6) are formed at the same time.
  • the doping concentration is 1 ⁇ 10 18 cm -3 to 5 ⁇ 10 19 cm -3 , with a depth of 0.3 ⁇ m to 0.4 ⁇ m.
  • Step S5 Ion implantation to form the junction terminal extension (4) and the junction terminal auxiliary ring (5), and then activate annealing at a high temperature.
  • the metal is evaporated, and the implantation mask for the junction termination extension area and junction termination auxiliary ring is formed after stripping.
  • Al ions are used for implantation at 500°C to form junction termination extension (4) and junction termination protection ring (5) at the same time ,
  • the doping concentration is 5 ⁇ 10 16 cm -3 to 3 ⁇ 10 17 cm -3 , and the depth is 0.4 ⁇ m to 0.5 ⁇ m.
  • the surface of the wafer is covered with a carbon film, and high-temperature activation annealing is performed in an Ar atmosphere for 2 hours, and the annealing temperature is above 1700°C.
  • the structure shown in Figure 7 is formed.
  • Step S6 thermal oxidation to form a gate oxide, deposit a polysilicon gate electrode, and deposit a passivation layer (7) after etching the electrode. Subsequent ohmic contact, etching and other processes form the final device.

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Abstract

本发明涉及功率半导体技术领域，公开了一种碳化硅半导体器件终端及其制造方法，该终端结构包含数个阱区辅助环、一结终端扩展、数个结终端辅助环、数个基区辅助环和一钝化层。阱区辅助环位于阱区外侧，结终端扩展紧临阱区，其深度小于阱区的深度。结终端辅助环位于结终端扩展的外侧，基区辅助环位于结终端辅助环外侧。利用较少的光刻次数和离子注入次数，通过引入阱区辅助环、结终端辅助环和基区辅助环，优化高场区的电场分布，从而改善器件的阻断特性，提高了器件阻断电压对终端掺杂浓度的容忍度。本发明还提供了在碳化硅MOSFET器件中使用本终端结构的工艺方法。

Description

一种碳化硅半导体器件终端及其制造方法 技术领域
本发明涉及碳化硅半导体器件制备领域，具体涉及一种用于高压碳化硅功率器件的终端结构及制备方法，该结构适用于1200V至20kV的高压碳化硅功率器件，能够在较少次终端注入的条件下实现高终端掺杂容忍度，显著提高器件良品率。
背景技术
碳化硅具有优良的物理和电学特性，具有低本征载流子浓度、高热导率、高击穿场强等优点以及优异的物理化学稳定性。因此碳化硅成为高温大功率半导体器件的理想材料。
然而，碳化硅基功率器件在材料成本和制备成本上远高于传统硅基功率器件，限制了碳化硅基功率器件的发展和应用。
在实际的半导体器件中，由于器件尺寸有限，在器件边缘存在结的不连续，使得结边缘存在曲率，导致表面电场集中，使得结边缘电场强度高于体内平面结电场强度，发生提前击穿。这种效应严重影响了功率器件的阻断特性。为了减缓结边缘电场集中带来的不利影响，通常会在功率器件结边缘设置结终端结构。常见的终端结构主要有场板、场限环、结终端扩展(JTE)等。
场板结构通常用于较低电压的功率半导体器件，在高压功率半导体器件中通常和其他结构复合使用。场限环结构会占用大量的器件面积，并且对光刻精度的要求较高。结终端扩展则对终端掺杂浓度以及钝化层界面电荷十分敏感，由于碳化硅材料的选择性掺杂需要通过离子注入后退火激活实现，其激活率受到离子注入温度，掺杂浓度，激活温度和激活时间等多方面因素的影响，难以 准确被掌握，因此结终端扩展制备高压碳化硅器件终端良品率较低。
本发明提出一种适用于高压碳化硅功率器件的终端结构及制备方法，利用较少的光刻次数和离子注入次数，形成适用于高压碳化硅功率器件终端结构，具有对终端掺杂浓度容忍性大，兼容现有碳化硅功率器件工艺等优点。
发明内容
(一)要解决的技术问题
为解决高压碳化硅功率半导体器件终端面积过大，击穿电压对掺杂浓度容忍度不高等问题，本发明提出一种适用于高压碳化硅器件的终端结构，该终端结构占据晶片面积较小，且击穿电压对终端掺杂浓度容忍度较高，同时与现有碳化硅功率器件工艺完全兼容。
(二)技术方案
本发明的技术方案综合考虑材料特性、工艺难度、器件性能和成本等方面，提供一种适用于高压碳化硅功率器件的终端结构。
该终端结构可在碳化硅MOSFET和碳化硅IGBT等器件中实现。图一左侧为器件元胞结构，右侧虚线框内为本发明所提出的新型器件终端结构。该终端包含数个阱区辅助环(3)、一结终端扩展(4)、数个结终端辅助环(5)、数个基区辅助环(6)和一钝化层(7)。如图1所示，阱区辅助环(3)位于阱区(2)外侧。结终端辅助环(5)位于结终端扩展(4)的外侧，基区辅助环(6)位于结终端辅助环(5)外侧。上述阱区辅助环(3)、结终端扩展(4)和结终端辅助环(5)和基区辅助环(6)的顶部有热氧化及PECVD形成的钝化层(7)。
所述阱区辅助环(3)与阱区(2)同时形成，因此和阱区(2)具有相同的掺杂浓度和深度，阱区辅助环的数目为3个以上，环宽度相等，环间距逐渐增大。可选的，阱区掺杂浓度为2×10 17cm -3至2×10 18cm -3，深度为0.6μm至1μm，阱区辅助环由5个环构成。
所述结终端扩展(4)的深度小于阱区(2)的深度。结终端辅助环(5)和结终端扩展(4)同时形成，因此具有相同的掺杂浓度和深度。结终端辅助环(5)的数目为3个以上，环宽度相等，环间距逐渐增大。可选的，结终端扩展(4)长度为20μm至400μm，掺杂浓度为5×10 16cm -3至3×10 17cm -3，深度为0.4μm至0.5μm，结终端辅助环由4个环构成
所述基区辅助环(6)与器件元胞内P型基区同时形成，因此和P型基区具有相同的掺杂浓度和深度。基区辅助环(6)的数目为3个以上，环宽度相等，环间距逐渐增大。可选的，基区辅助环(6)的掺杂浓度为1×10 18cm -3至5×10 19cm -3，深度为0.3μm至0.4μm，基区辅助环由4个环构成。
本发明的另一方面，提出了一种包含该终端结构的碳化硅MOSFET器件的基本工艺流程。包括以下步骤：
S1：在N型碳化硅衬底上外延生长N型碳化硅外延层；
S2：离子注入同时形成阱区(2)和阱区辅助环(3)；
S3：离子注入形成N型掺杂源区；
S4：离子注入同时形成P型掺杂基区和基区辅助环(6)；
S5：离子注入形成结终端扩展(4)和结终端辅助环(5)，之后在高温下激活退火。
S6：热氧化形成栅氧，沉积多晶硅栅电极，刻蚀电极之后淀积钝化层(7)。后续欧姆接触、刻蚀等工艺形成最终器件。
(三)有益效果
本发明设计了一种适用于碳化硅功率器件的终端结构，使用该终端结构的碳化硅功率器件，仅需要在有源区离子注入的基础上，附加一次结终端扩展离子注入就可以形成。同时该终端还具有较小的终端面积，对终端掺杂浓度的容忍性较高等优点。
图1显示了为采用单JTE终端的碳化硅MOSFET器件示意图，图2为采用本发明实施例的碳化硅MOSFET器件终端结构示意图。图3显示了单JTE终端 和采用本发明的终端结构的碳化硅MOSFET器件阻断电压与结终端扩展掺杂浓度的关系图，可以看到本发明的终端结构具有更大的掺杂浓度容忍范围。
图4显示了阻断状态下采用本发明的终端结构的3300V碳化硅MOSFET器件内部电势分布，可以看到阱区辅助环、结终端扩展、结终端辅助环和基区辅助环均承担了电势降。由于场限环终端的效率对场限环的掺杂浓度不敏感，而对各环的间距和深度敏感，因此虽然基区辅助环的掺杂浓度远高于结终端扩展的掺杂浓度，但在本发明的设计中只需确保其深度小于结终端扩展，就可以使基区辅助环起到进一步均匀分担电势的作用。
附图说明
图1为采用单JTE终端的碳化硅MOSFET器件示意图。
图2为采用本发明实施例的碳化硅MOSFET器件终端结构示意图；
图3为阻断状态下采用本发明的终端结构的3300V碳化硅MOSFET器件内部电势分布；
图4为单JTE终端和采用本发明的终端结构的碳化硅MOSFET器件阻断电压与结终端扩展掺杂浓度的关系图。
图5为本发明实施例所提供的器件制备工艺流程图；
图6为本发明实施例所提供的器件制备工艺步骤S2示意图；
图7为本发明实施例所提供的器件制备工艺步骤S3示意图；
图8为本发明实施例所提供的器件制备工艺步骤S4示意图；
图9为本发明实施例所提供的器件制备工艺步骤S5示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。
本发明实施例的一方面提供了一种碳化硅器件终端结构，图1为采用本发明实施例的碳化硅MOSFET结构示意图，其中虚线框内为本发明所提出的碳化硅器件终端结构。如图1所示，该终端包含数个阱区辅助环(3)、一结终端扩展(4)、数个结终端辅助环(5)、数个基区辅助环(6)和一钝化层(7)。阱区辅助环(3)位于阱区(2)外侧，所述结终端扩展(4)紧临阱区(2)其深度小于阱区(2)的深度。结终端辅助环(5)位于结终端扩展(4)的外侧，基区辅助环(6)位于结终端辅助环(5)外侧。上述阱区辅助环(3)、结终端扩展(4)和结终端辅助环(5)和基区辅助环(6)的顶部有热氧化及PECVD形成的钝化层(7)。
在本实施例中，阱区(2)和阱区辅助环(3)的掺杂浓度为2×10 17cm -3至2×10 18cm -3，深度为0.6μm至1μm；结终端扩展(4)长度为20μm至400μm，掺杂浓度为5×10 16cm -3至3×10 17cm -3，深度为0.4μm至0.5μm；基区辅助环(6)的掺杂浓度为1×10 18cm -3至5×10 19cm -3，深度为0.3μm至0.4μm。阱区辅助环(3)的数目设定为5个，各环宽度4μm，间距从内向外依次增加；结终端辅助环(5)的数目设定为4个，各环宽度4μm，间距从内向外依次增加，基区辅助环(6)的数目设定为4个，环宽4μm，间距从内向外依次增加。
本发明的器件终端是在结终端扩展的基础上，通过引入阱区辅助环、结终端辅助环和基区辅助环，优化高场区的电场分布，从而改善器件的阻断特性。
本发明实施例的另一方面，提供了在使用本发明终端的碳化硅MOSFET器件基本工艺流程，包括以下步骤：
步骤S1：在N型碳化硅衬底上生长N型外延层。
步骤S2：离子注入同时形成阱区(2)和阱区辅助环(3)。
在碳化硅表面首先沉积一层厚度为20nm至100nm的二氧化硅，光刻显影后蒸发金属，经过剥离形成阱区和阱区辅助环的注入掩膜，之后使用Al离子在500℃下注入同时形成阱区(2)和阱区辅助环(3)，掺杂浓度为2×10 17cm -3至2×10 18cm -3，深度为0.6μm。离子注入完成后，使用硫酸双氧水混合液清理掉注 入掩膜，形成如图4所示结构。
步骤S3：离子注入形成N型掺杂源区。
再次光刻显影后蒸发金属，经过剥离形成源区注入掩膜，之后使用N离子在500℃下注入形成N型源区，掺杂浓度为1×10 18cm -3至5×10 19cm -3，深度为0.25μm。离子注入完成后，使用硫酸双氧水混合液清理掉注入掩膜，形成如图5所示结构。
步骤S4：离子注入同时形成P型掺杂基区和基区辅助环(6)。
再次光刻显影后蒸发金属，经过剥离形成基区和基区辅助环的注入掩膜，之后使用Al离子在500℃下注入，同时形成基区和基区辅助环(6)，掺杂浓度为1×10 18cm -3至5×10 19cm -3，深度为0.3μm至0.4μm。离子注入完成后，使用硫酸双氧水混合液清洗，去掉注入掩膜，形成如图6所示结构。
步骤S5：离子注入形成结终端扩展(4)和结终端辅助环(5)，之后在高温下激活退火。
再次光刻显影后蒸发金属，经过剥离形成结终端扩展区域和结终端辅助环的注入掩膜，使用Al离子在500℃下注入，同时形成结终端扩展(4)和结终端保护环(5)，掺杂浓度为5×10 16cm -3至3×10 17cm -3，深度为0.4μm至0.5μm。注入完成后，使用硫酸双氧水混合液清理掉注入掩膜，BOE溶液去除表面二氧化硅保护层。后续在晶片表面覆盖碳膜，在Ar气环境下进行高温激活退火2小时，退火温度1700℃以上。形成如图7所示结构。
步骤S6：热氧化形成栅氧，沉积多晶硅栅电极，刻蚀电极之后淀积钝化层(7)。后续欧姆接触、刻蚀等工艺形成最终器件。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明。凡在本发明的精神和原则之内，通过改变某个区域厚度或掺杂浓度，增加或减少辅助环数目，或者在本发明的基础上，再额外增加复合终端的数目，均应包含在本发明的保护范围之内。

Claims (6)

  1. 一种碳化硅半导体器件终端，其特征在于，包含：
    数个阱区辅助环(3)、一结终端扩展(4)、数个结终端辅助环(5)、数个基区辅助环(6)和一钝化层(7)。其中，阱区辅助环(3)位于阱区(2)外侧，所述结终端扩展(4)紧临阱区(2)其深度小于阱区(2)的深度。结终端辅助环(5)位于结终端扩展(4)的外侧，基区辅助环(6)位于结终端辅助环(5)外侧。上述阱区辅助环(3)、结终端扩展(4)和结终端辅助环(5)和基区辅助环(6)的顶部有热氧化及PECVD形成的钝化层(7)。
  2. 根据权利要求1所述的碳化硅半导体器件终端，其特征在于，所述阱区辅助环(3)与阱区(2)具有相同的掺杂浓度和深度。阱区掺杂浓度为2×10 17cm -3至2×10 18cm -3，深度为0.6μm至1μm，阱区辅助环的数目在3个以上，环宽度相等，环间距逐渐增大。
  3. 根据权利要求1所述的碳化硅半导体器件终端，其特征在于，所述结终端扩展(4)的深度小于阱区(2)的深度，结终端扩展(4)长度为20μm至400μm，掺杂浓度为5×10 16cm -3至3×10 17cm -3，深度为0.4μm至0.5μm。
  4. 根据权利要求1所述的碳化硅半导体器件终端，其特征在于，结终端辅助环(5)和结终端扩展(4)同时形成，因此具有相同的掺杂浓度和深度，数目为3个以上，环宽度相等，环间距逐渐增大。
  5. 根据权利要求1所述的碳化硅半导体器件终端，其特征在于，所述基区辅助环(6)与器件元胞内P型基区同时形成，因此与P型基区具有相同的掺杂浓度和深度，基区辅助环的掺杂浓度为1×10 18cm -3至5×10 19cm -3，深度为0.3μm至0.4μm。基区辅助环(6)的数目为3个以上，环宽度相等，环间距逐渐增大。
  6. 一种如权利要求1-5任一项所述的碳化硅半导体器件终端的制造方法，其特征在于，包括以下步骤：
    S1：在N型碳化硅衬底上外延生长N型碳化硅外延层；
    S2：离子注入同时形成阱区(2)和阱区辅助环(3)；
    S3：离子注入形成N型掺杂源区；
    S4：离子注入同时形成P型掺杂基区和基区辅助环(6)；
    S5：离子注入形成结终端扩展(4)和结终端辅助环(5)，之后在高温下激活退火。
    S6：热氧化形成栅氧，沉积多晶硅栅电极，刻蚀电极之后淀积钝化层(7)。后续欧姆接触、刻蚀等工艺形成最终器件。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102479807A (zh) * 2010-11-26 2012-05-30 三菱电机株式会社 碳化硅半导体装置及其制造方法
US20150214164A1 (en) * 2013-04-04 2015-07-30 Monolith Semiconductor, Inc. Semiconductor devices comprising getter layers and methods of making and using the same
CN110534559A (zh) * 2019-09-03 2019-12-03 深圳第三代半导体研究院 一种碳化硅半导体器件终端及其制造方法

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CN104795435B (zh) * 2014-01-21 2017-11-24 瀚薪科技股份有限公司 碳化硅功率元件
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102479807A (zh) * 2010-11-26 2012-05-30 三菱电机株式会社 碳化硅半导体装置及其制造方法
US20150214164A1 (en) * 2013-04-04 2015-07-30 Monolith Semiconductor, Inc. Semiconductor devices comprising getter layers and methods of making and using the same
CN110534559A (zh) * 2019-09-03 2019-12-03 深圳第三代半导体研究院 一种碳化硅半导体器件终端及其制造方法

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