WO2014206191A1 - 非穿通型绝缘栅双极晶体管的制造方法 - Google Patents

非穿通型绝缘栅双极晶体管的制造方法 Download PDF

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WO2014206191A1
WO2014206191A1 PCT/CN2014/079275 CN2014079275W WO2014206191A1 WO 2014206191 A1 WO2014206191 A1 WO 2014206191A1 CN 2014079275 W CN2014079275 W CN 2014079275W WO 2014206191 A1 WO2014206191 A1 WO 2014206191A1
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silicon wafer
layer
bipolar transistor
insulated gate
gate bipolar
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PCT/CN2014/079275
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English (en)
French (fr)
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周东飞
钟圣荣
邓小社
王根毅
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无锡华润上华半导体有限公司
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Publication of WO2014206191A1 publication Critical patent/WO2014206191A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors

Definitions

  • the present invention relates to a semiconductor fabrication process, and more particularly to a method of fabricating a non-punch-through insulated gate bipolar transistor.
  • NPT Traditional non-punch-through insulated gate bipolar transistor (Non Punch Through Insulated Gate) Bipolar Transistor, NPT
  • the manufacturing method of the back surface P-type layer of the IGBT is mainly to apply a protective film to the front surface of the wafer after the front surface is completed, and then to perform back surface thinning and ion implantation.
  • the annealing temperature of the back P-type layer cannot be higher than 500 degrees. This makes NPT
  • the injection efficiency of the P-type layer on the back side of the IGBT is very low, and the forward voltage drop Vce of the NPT IGBT cannot be reduced to an ideal value, which greatly limits the performance of the NPT IGBT.
  • a manufacturing method of a non-punch-through insulated gate bipolar transistor includes the steps of: forming an insulated gate bipolar transistor structure on a front surface of a silicon wafer to deposit an interlayer dielectric; sequentially forming a silicon nitride layer on the interlayer dielectric
  • the oxide layer serves as a protective film; the silicon wafer is thinned from the back surface of the silicon wafer, and a P-type layer is formed on the back surface of the thinned silicon wafer; the protective film is removed, and the silicon wafer is removed Annealing treatment; wherein the annealing temperature is greater than 500 degrees Celsius; forming a metal layer on the surface of the P-type layer and the interlayer dielectric.
  • the step of sequentially forming a silicon nitride layer and an oxide layer as a protective film on the interlayer dielectric comprises: performing silicon nitride growth on the silicon wafer; performing oxide layer growth on the silicon wafer; An oxide layer on the back side of the silicon wafer; a silicon nitride layer on the back side of the silicon wafer; a protective film formed on the interlayer dielectric comprising a silicon nitride layer and an oxide layer formed on the surface of the interlayer dielectric.
  • the step of removing the oxide layer on the back side of the silicon wafer comprises: coating a photoresist on the oxide layer on the front side of the silicon wafer; and removing the oxide layer on the back side of the silicon wafer by wet etching.
  • the step of removing the silicon nitride layer on the back side of the silicon wafer comprises: removing the photoresist coated on the oxide layer on the front side of the silicon wafer; removing the silicon by using a silicon nitride stripping solution The silicon nitride layer on the back of the sheet.
  • the P-type layer is formed by ion implantation, and the implanted ions are boron.
  • the ion implantation is processed using a front side injection machine.
  • the annealing temperature is greater than 800 degrees Celsius.
  • the thinning process thins the silicon wafer to 300-500 microns.
  • the thinning treatment employs chemical mechanical polishing.
  • the annealing treatment temperature of the P-type layer is not limited by the melting temperature of the metal, and the annealing treatment can be performed at a higher temperature, thereby forming the NPT.
  • the performance of IGBTs is higher.
  • the method is also compatible with conventional processes and is therefore more efficient.
  • FIG. 1 is a flow chart showing a method of fabricating a non-punch-through insulated gate bipolar transistor according to an embodiment
  • FIG. 2 to 10 are schematic cross-sectional views showing intermediate structures corresponding to respective steps in the flow shown in Fig. 1.
  • FIG. 1 is a flow chart showing a method of manufacturing a non-punch-through insulated gate bipolar transistor according to an embodiment. The method includes the following steps.
  • Step S101 forming an insulated gate bipolar transistor structure on the front side of the silicon wafer to deposit the interlayer dielectric. This step is the same as the conventional process of fabricating an insulated gate bipolar transistor.
  • This step mainly includes:
  • Step S111 forming a field oxide layer on the N-type substrate and performing photolithography to form an implantation region.
  • the N-type substrate 100 is a silicon wafer lightly doped with an N-type impurity.
  • the field oxide layer 200 is obtained by oxidizing the surface of the N-type substrate 100. By performing photolithography on the field oxide layer 200, a corresponding portion of the field oxide layer 200 and the N-type substrate 100 that needs to form a P-type region is etched to form an implantation region on the field oxide layer 200.
  • Step S112 performing ion implantation on the implanted region to form a heavily doped P-type region.
  • a heavily doped P-type region 112 is formed on the N-type substrate 100 by implanting ions in a portion etched by the field oxide layer 200, that is, an implanted region portion. An oxidation treatment is then performed on the upper portion of the P-type region 112.
  • Step S113 performing gate oxide processing and polysilicon deposition, and performing photolithography to obtain a gate structure.
  • the surface of the N-type substrate 100 is again oxidized to form a gate oxide layer 300.
  • a polysilicon layer 400 is deposited on the gate oxide layer 300.
  • Photolithography is performed on the polysilicon layer 400 to obtain a gate structure 402.
  • the entire silicon wafer is deposited, and thus the polysilicon layer 400 is also formed on the back surface of the silicon wafer, that is, the back surface of the N-type substrate 100.
  • Step S114 performing ion implantation to form a lightly doped P-type region.
  • ion implantation is performed on both sides of the gate structure 402 to form a lightly doped P-type region 114.
  • the lightly doped P-type region 114 is interdiffused with the previously formed heavily doped P-type region 112.
  • the gate oxide layer 300 over the lightly doped P-type region 114 is then removed.
  • Step S115 performing ion implantation at a position where the gate oxide layer is removed to form a heavily doped N-type region. Referring to FIG. 6, ion implantation is performed on the lightly doped P-type region 114 to form a heavily doped N-type region 116.
  • Step S116 depositing an interlayer medium.
  • an interlayer dielectric 500 is formed over the entire wafer.
  • the interlayer dielectric 500 is used in the semiconductor fabrication process to insulate and isolate the conductive layer.
  • a metal layer is fabricated after the deposition of the interlayer dielectric, and a metal wiring process is performed.
  • step S111 ⁇ S116 is the specific step included in the step of forming the insulated gate bipolar transistor structure on the front side of the silicon wafer to the step of depositing the interlayer dielectric in step S101.
  • the front structure of the IGBT has not been fully formed.
  • Step S102 sequentially forming a silicon nitride layer and an oxide layer on the interlayer dielectric as a protective film.
  • This step mainly includes:
  • S121 The silicon wafer is grown by silicon nitride.
  • the growth of silicon nitride is carried out by deposition. Referring to Fig. 8, since the entire silicon wafer is deposited, a silicon nitride layer 610 is also formed on the back surface of the silicon wafer.
  • S122 The silicon wafer is subjected to oxide layer growth.
  • the oxide layer growth is carried out by means of thermal oxygen growth.
  • An oxide layer 620 is formed over the silicon nitride layer 610 layer.
  • S123 removing the oxide layer on the back side of the silicon wafer.
  • the photoresist layer 620 on the front side of the silicon wafer is coated with a photoresist to protect it, and then the oxide layer 620 on the back side of the silicon wafer is removed by wet etching.
  • step S124 Removing the silicon nitride layer on the back side of the silicon wafer.
  • the photoresist coated in step S123 is removed, and then the silicon nitride layer 610 on the back side of the silicon wafer is removed using a silicon nitride stripping solution.
  • S125 Removing the polysilicon layer on the back side of the silicon wafer.
  • the polysilicon layer 400 on the back side of the silicon wafer is removed by dry etching.
  • the oxide layer 620, the silicon nitride layer 610, and the polysilicon layer 400 on the back side of the silicon wafer are removed, leaving the oxide layer 620 and the silicon nitride layer 610 on the front side of the silicon wafer as a protective layer.
  • Step S103 thinning the silicon wafer from the back surface of the silicon wafer, and forming a P-type layer on the back surface of the thinned silicon wafer.
  • a P-type layer 700 is formed on the back surface of the N-type substrate 100.
  • the P-type layer 700 is formed by ion implantation, and the implanted ions are boron. This ion implantation can be performed directly using a front injection machine, which is compatible with conventional processes.
  • the thinning treatment may be performed by mechanical grinding or chemical etching.
  • the silicon wafer is thinned as a whole to 300 to 500 microns.
  • Step S104 removing the protective film and annealing the silicon wafer; wherein the annealing temperature is greater than 500 degrees Celsius.
  • the manner of removing the protective film can be performed by the methods of the foregoing steps S123 and S124 to remove the silicon nitride layer 610 and the oxide layer 620 on the front side of the silicon wafer, respectively. Since the metal layer is not formed at this time, annealing treatment can be performed using a higher temperature (greater than 500 degrees Celsius). In order to make the annealing effect better, the annealing temperature is greater than 800 degrees Celsius.
  • Step S105 forming a metal layer on the surface of the P-type layer and the interlayer dielectric.
  • a metal layer 800 is formed on the interlayer dielectric 500, and a metal layer 900 is formed on the P-type layer 700.
  • the metal layer 800 is formed on the interlayer dielectric 500 by first forming a via hole (contact hole) on the interlayer dielectric 500, and then forming a metal layer 800.
  • the electrodes of the gate, the collector, and the source are respectively extracted to form an NPT.
  • the annealing treatment temperature of the P-type layer is not limited by the melting temperature of the metal, and the annealing treatment can be performed at a higher temperature, thereby forming the NPT.
  • the performance of IGBTs is higher.

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Abstract

一种非穿通型绝缘栅双极晶体管的制造方法，包括如下步骤：在硅片正面形成绝缘栅双极晶体管结构至积淀完层间介质；在所述层间介质上覆盖保护膜；自所述硅片背面开始将所述硅片进行减薄处理，并在减薄后的硅片背面形成P型层；去掉所述保护膜，并对所述硅片进行退火处理；其中退火温度大于500摄氏度；在所述P型层和层间介质表面形成金属层。上述方法中，由于是在金属层形成之前进行P型层的退火处理，因此P型层的退火处理温度不会受到金属熔化温度的限制，可以采用较高的温度进行退火处理，从而形成的NPT IGBT的性能更高。同时，该方法也与传统工艺兼容，因此效率较高。

Description

非穿通型绝缘栅双极晶体管的制造方法
【技术领域】
本发明涉及半导体制造工艺，特别是涉及一种非穿通型绝缘栅双极晶体管的制造方法。
【背景技术】
传统的非穿通型绝缘栅双极晶体管（Non Punch Through Insulated Gate Bipolar Transistor，NPT IGBT）的背面P型层的制造方法主要是，在正面作业完成后，再给圆片正面贴保护膜，然后进行背面减薄以及注入离子。
受限于正面金属熔化温度，背面P型层的退火温度不能高于500度。这使得NPT IGBT背面P型层的注入效率很低，导致NPT IGBT的正向导通压降Vce不能减小到理想值，在很大程度上限制了NPT IGBT的性能。
【发明内容】
基于此，有必要提供一种能够提升性能的非穿通型绝缘栅双极晶体管的制造方法。
一种非穿通型绝缘栅双极晶体管的制造方法，包括如下步骤：在硅片正面形成绝缘栅双极晶体管结构至积淀完层间介质；在所述层间介质上依次形成氮化硅层和氧化层作为保护膜；自所述硅片背面开始将所述硅片进行减薄处理，并在减薄后的硅片背面形成P型层；去掉所述保护膜，并对所述硅片进行退火处理；其中退火温度大于500摄氏度；在所述P型层和层间介质表面形成金属层。
在其中一个实施例中，所述在层间介质上依次形成氮化硅层和氧化层作为保护膜的步骤包括：将硅片进行氮化硅生长；将硅片进行氧化层生长；去除所述硅片背面的氧化层；去除所述硅片背面的氮化硅层；所述层间介质上形成的保护膜包括形成于所述层间介质表面的氮化硅层和氧化层。
在其中一个实施例中，所述去除硅片背面的氧化层的步骤包括：在所述硅片正面的氧化层上涂覆光刻胶；采用湿法腐蚀去除所述硅片背面的氧化层。
在其中一个实施例中，所述去除硅片背面的氮化硅层的步骤包括：去除所述硅片正面的氧化层上涂覆的光刻胶；采用氮化硅剥离药液去除所述硅片背面的氮化硅层。
在其中一个实施例中，所述P型层采用离子注入方式形成，注入离子为硼。
在其中一个实施例中，所述离子注入采用正面注入机台处理。
在其中一个实施例中，所述退火温度大于800摄氏度。
在其中一个实施例中，所述减薄处理将硅片减薄至300~500微米。
在其中一个实施例中，所述减薄处理采用化学机械研磨。
上述方法中，由于是在金属层形成之前进行P型层的退火处理，因此P型层的退火处理温度不会受到金属熔化温度的限制，可以采用较高的温度进行退火处理，从而形成的NPT IGBT的性能更高。同时，该方法也与传统工艺兼容，因此效率较高。
【附图说明】
图1为一实施例的非穿通型绝缘栅双极晶体管的制造方法流程图；
图2至图10为图1所示流程中各个步骤对应的中间结构的断面示意图。
【具体实施方式】
以下结合实施例以及附图对非穿通型绝缘栅双极晶体管的制造方法进行进一步说明。
图1是一实施例的非穿通型绝缘栅双极晶体管的制造方法流程图。该方法包括如下步骤。
步骤S101：在硅片正面形成绝缘栅双极晶体管结构至积淀完层间介质。本步骤与传统的制造绝缘栅双极晶体管的工艺相同。
本步骤主要包括：
步骤S111：在N型衬底上形成场氧层，并进行光刻形成注入区域。参考图2，N型衬底100是轻掺杂N型杂质的硅片。通过对N型衬底100表面进行氧化即可得到场氧层200。通过对场氧层200进行光刻，将场氧层200上与N型衬底100需要形成P型区的对应部分刻蚀，在场氧层200上形成注入区域。
步骤S112：对注入区域进行离子注入，形成重掺杂的P型区。参考图3，在场氧层200刻蚀的部分，也即注入区域部分，通过注入离子，在N型衬底100上形成重掺杂的P型区112。然后对P型区112上方进行氧化处理。
步骤S113：进行栅氧处理和多晶硅淀积，并进行光刻得到栅极结构。参考图4，对N型衬底100表面再次进行氧化，形成栅氧层300。并在栅氧层300上淀积形成多晶硅层400。对所述多晶硅层400进行光刻，得到栅极结构402。其中，在多晶硅淀积时，是对整个硅片进行淀积处理，因此在硅片的背面，也即N型衬底100的背面也形成有该多晶硅层400。
步骤S114：进行离子注入，形成轻掺杂的P型区。参考图5，在栅极结构402两侧进行离子注入，形成轻掺杂的P型区114。该轻掺杂的P型区114与之前形成的重掺杂的P型区112相互扩散融合。然后去除轻掺杂的P型区114上方的栅氧层300。
步骤S115：在去除所述栅氧层的位置进行离子注入，形成重掺杂的N型区。参考图6，也即在轻掺杂的P型区114上进行离子注入形成重掺杂的N型区116。
步骤S116：积淀层间介质。参考图7，在整个硅片上形成层间介质500。层间介质500半导体制造工艺中是用来绝缘和隔离导电层的。在传统的工艺中，积淀完层间介质之后即制造金属层，进行金属连线工艺。
上述步骤S111 ~S116即步骤S101中的在硅片正面形成绝缘栅双极晶体管结构至积淀完层间介质的步骤中所包含的具体步骤。至此IGBT的正面结构并未完全形成。
上述步骤完成后，继续执行如下步骤。
步骤S102：在所述层间介质上依次形成氮化硅层和氧化层作为保护膜。本步骤主要包括：
S121：将硅片进行氮化硅生长。氮化硅的生长采用淀积的方式。参考图8，由于是对整个硅片进行淀积处理，因此硅片的背面也生成了氮化硅层610。
S122：将硅片进行氧化层生长。氧化层生长采用热氧生长的方式。继续参考图8。氧化层620在氮化硅层610层上形成。
S123：去除所述硅片背面的氧化层。在所述硅片正面的氧化层620上涂覆光刻胶对其进行保护，让后采用湿法腐蚀去除硅片背面的氧化层620。
S124：去除所述硅片背面的氮化硅层。去除步骤S123中涂覆的光刻胶，然后采用氮化硅剥离药液去除所述硅片背面的氮化硅层610。
S125：去除所述硅片背面的多晶硅层。采用干法刻蚀去除所述硅片背面的多晶硅层400。
这样，硅片背面的氧化层620、氮化硅层610以及多晶硅层400即被去除，留下硅片正面的氧化层620和氮化硅层610作为保护层。
步骤S103：自所述硅片背面开始将所述硅片进行减薄处理，并在减薄后的硅片背面形成P型层。参考图9，P型层700形成于N型衬底100的背面。所述P型层700采用离子注入方式形成，注入离子为硼。可以直接采用正面注入机台进行该离子注入，与传统的工艺兼容。所述减薄处理可以采用机械研磨或者化学腐蚀等方式进行减薄处理。硅片整体减薄至300~500微米。
步骤S104：去掉所述保护膜，并对所述硅片进行退火处理；其中退火温度大于500摄氏度。去掉该保护膜的方式可以采用前述步骤S123和步骤S124的方法，分别去掉硅片正面的氮化硅层610和氧化层620。由于此时金属层还未形成，可以使用较高的温度（大于500摄氏度）进行退火处理。为使退火效果更佳，所述退火温度大于800摄氏度。
步骤S105：在所述P型层和层间介质表面形成金属层。参考图10，在层间介质500上形成金属层800，在P型层700上形成金属层900。其中，在层间介质500上形成金属层800是先在层间介质500上形成通孔（接触孔），然后再形成金属层800。在形成金属层800和900后，分别引出栅极、集电极以及源极的电极，最终形成NPT IGBT的完整结构。
上述方法中，由于是在金属层形成之前进行P型层的退火处理，因此P型层的退火处理温度不会受到金属熔化温度的限制，可以采用较高的温度进行退火处理，从而形成的NPT IGBT的性能更高。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种非穿通型绝缘栅双极晶体管的制造方法，包括如下步骤：
    在硅片正面形成绝缘栅双极晶体管结构至积淀完层间介质；
    在所述层间介质上依次形成氮化硅层和氧化层作为保护膜；
    自所述硅片背面开始将所述硅片进行减薄处理，并在减薄后的硅片背面形成P型层；
    去掉所述保护膜，并对所述硅片进行退火处理；其中退火温度大于500摄氏度；及
    在所述P型层和层间介质表面形成金属层。
  2. 根据权利要求1所述的非穿通型绝缘栅双极晶体管的制造方法，其特征在于，所述在层间介质上依次形成氮化硅层和氧化层作为保护膜的步骤包括：
    将硅片进行氮化硅生长；
    将硅片进行氧化层生长；
    去除所述硅片背面的氧化层；
    去除所述硅片背面的氮化硅层；
    去除所述硅片背面的多晶硅层；所述层间介质上形成的保护膜包括形成于所述层间介质表面的氮化硅层和氧化层。
  3. 根据权利要求2所述的非穿通型绝缘栅双极晶体管的制造方法，其特征在于，所述去除硅片背面的氧化层的步骤包括：
    在所述硅片正面的氧化层上涂覆光刻胶；
    采用湿法腐蚀去除所述硅片背面的氧化层。
  4. 根据权利要求3所述的非穿通型绝缘栅双极晶体管的制造方法，其特征在于，所述去除硅片背面的氮化硅层的步骤包括：
    去除所述硅片正面的氧化层上涂覆的光刻胶；
    采用氮化硅剥离药液去除所述硅片背面的氮化硅层。
  5. 根据权利要求1所述的非穿通型绝缘栅双极晶体管的制造方法，其特征在于，所述P型层采用离子注入方式形成，注入离子为硼。
  6. 根据权利要求5所述的非穿通型绝缘栅双极晶体管的制造方法，其特征在于，所述离子注入采用正面注入机台处理。
  7. 根据权利要求1所述的非穿通型绝缘栅双极晶体管的制造方法，其特征在于，所述去除保护膜的步骤包括：
    采用湿法腐蚀BOE刻蚀掉所述硅片正面的氧化层；
    采用氮化硅剥离药液去除所述硅片正面的氮化硅层。
  8. 根据权利要求1所述的非穿通型绝缘栅双极晶体管的制造方法，其特征在于，所述退火温度大于800摄氏度。
  9. 根据权利要求1所述的非穿通型绝缘栅双极晶体管的制造方法，其特征在于，所述减薄处理将硅片减薄至300~500微米。
  10. 根据权利要求1所述的非穿通型绝缘栅双极晶体管的制造方法，其特征在于，所述减薄处理采用化学机械研磨。
PCT/CN2014/079275 2013-06-27 2014-06-05 非穿通型绝缘栅双极晶体管的制造方法 WO2014206191A1 (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107731662A (zh) * 2017-11-22 2018-02-23 上海华力微电子有限公司 一种提高器件均匀性的方法
CN109103242A (zh) * 2018-09-30 2018-12-28 江苏明芯微电子股份有限公司 一种穿通结构的可控硅芯片及其生产方法
CN111799161A (zh) * 2019-04-08 2020-10-20 上海先进半导体制造股份有限公司 低压屏蔽栅场效应晶体管制作方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106847909A (zh) * 2017-01-05 2017-06-13 江苏中科君芯科技有限公司 一种fs型igbt器件的制造方法
CN110246761A (zh) * 2019-06-19 2019-09-17 上海华力集成电路制造有限公司 一种去除晶圆背面氮化硅薄膜的方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020137264A1 (en) * 2001-03-23 2002-09-26 Ming-Jer Kao Method of fabrication thin wafer IGBT
US20070026577A1 (en) * 2005-07-27 2007-02-01 International Rectifier Corp. High voltage non punch through IGBT for switch mode power supplies
CN101452951A (zh) * 2007-12-04 2009-06-10 科达半导体有限公司 非穿通(npt)绝缘栅双极型晶体管igbt及其制造方法
US7897997B2 (en) * 2008-02-23 2011-03-01 Force Mos Technology Co., Ltd. Trench IGBT with trench gates underneath contact areas of protection diodes
CN102420133A (zh) * 2011-09-30 2012-04-18 上海华虹Nec电子有限公司 Igbt器件的制造方法
CN102693912A (zh) * 2011-03-24 2012-09-26 上海北车永电电子科技有限公司 制作igbt器件的方法及其装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103137473B (zh) * 2011-12-02 2016-02-10 上海华虹宏力半导体制造有限公司 以具有外延层的衬底制造场终止型igbt器件的方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020137264A1 (en) * 2001-03-23 2002-09-26 Ming-Jer Kao Method of fabrication thin wafer IGBT
US20070026577A1 (en) * 2005-07-27 2007-02-01 International Rectifier Corp. High voltage non punch through IGBT for switch mode power supplies
CN101452951A (zh) * 2007-12-04 2009-06-10 科达半导体有限公司 非穿通(npt)绝缘栅双极型晶体管igbt及其制造方法
US7897997B2 (en) * 2008-02-23 2011-03-01 Force Mos Technology Co., Ltd. Trench IGBT with trench gates underneath contact areas of protection diodes
CN102693912A (zh) * 2011-03-24 2012-09-26 上海北车永电电子科技有限公司 制作igbt器件的方法及其装置
CN102420133A (zh) * 2011-09-30 2012-04-18 上海华虹Nec电子有限公司 Igbt器件的制造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107731662A (zh) * 2017-11-22 2018-02-23 上海华力微电子有限公司 一种提高器件均匀性的方法
CN109103242A (zh) * 2018-09-30 2018-12-28 江苏明芯微电子股份有限公司 一种穿通结构的可控硅芯片及其生产方法
CN109103242B (zh) * 2018-09-30 2023-12-15 江苏明芯微电子股份有限公司 一种穿通结构的可控硅芯片及其生产方法
CN111799161A (zh) * 2019-04-08 2020-10-20 上海先进半导体制造股份有限公司 低压屏蔽栅场效应晶体管制作方法
CN111799161B (zh) * 2019-04-08 2023-08-29 上海积塔半导体有限公司 低压屏蔽栅场效应晶体管制作方法

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