WO2015027920A1 - 绝缘栅双极晶体管的制造方法 - Google Patents

绝缘栅双极晶体管的制造方法 Download PDF

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Publication number
WO2015027920A1
WO2015027920A1 PCT/CN2014/085301 CN2014085301W WO2015027920A1 WO 2015027920 A1 WO2015027920 A1 WO 2015027920A1 CN 2014085301 W CN2014085301 W CN 2014085301W WO 2015027920 A1 WO2015027920 A1 WO 2015027920A1
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Prior art keywords
bipolar transistor
gate bipolar
type
semiconductor wafer
conductive layer
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PCT/CN2014/085301
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English (en)
French (fr)
Inventor
黄璇
王万礼
王根毅
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无锡华润上华半导体有限公司
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Publication of WO2015027920A1 publication Critical patent/WO2015027920A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Definitions

  • the present invention relates to the field of semiconductor design and manufacturing technology, and in particular to an insulated gate bipolar transistor (Insulated Gate) Bipolar Transistor, IGBT) manufacturing method.
  • IGBT Insulated Gate Bipolar Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • BJT Bipolar Junction Transistor
  • MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • the parallel freewheeling diode can be integrated in the IGBT chip, that is, the IGBT is an IGBT having a built-in diode or a reverse conducting function.
  • a common reverse-conducting IGBT requires thinning and double-sided lithography to produce an implant window for the backside P+ collector region.
  • the shortcomings of this kind of solution mainly have two aspects: First, there is a need to reduce the throughput of the wafer, especially for the common IGBTs below 1200V, the thickness of which is below 200 ⁇ m, which requires high throughput of the sheet; second, A special double exposure machine is required to expose the wafer.
  • the existing reverse-conducting IGBTs usually use a two-side lithography technique, and the process is complicated.
  • a method of fabricating an insulated gate bipolar transistor comprising: providing a semiconductor wafer of a first conductivity type, the semiconductor wafer including a first surface and a second surface opposite the first surface, and performing impurities on the first surface of the semiconductor wafer Injecting to form a conductive layer of a first conductivity type or a second conductivity type; forming a groove at a surface of the first conductivity type or the second conductivity type conductive layer; filling the groove with a second conductivity type or first conductivity a type of semiconductor material to form a channel, wherein the conductivity type of the channel is different from the conductivity type of the conductive layer, the channel and the conductive layer are alternately staggered; an oxide layer is formed on the conductive layer and the channel; and the substrate semiconductor wafer is bonded on the oxide layer Thinning the semiconductor wafer from the second surface of the semiconductor wafer, and using the thinned first conductivity type semiconductor wafer as a drift region; forming a front surface structure of the insulated gate bipolar transistor
  • the semiconductor wafer is provided to have a thickness of 200 to 700 ⁇ m and a specific resistance of 5 to 500 ⁇ *cm.
  • the implanted conductive layer is implanted on the first surface of the semiconductor wafer at a dose of 1 x 10 -13 -1 x 10 -20 cm -2 and an energy of 30-200 KEV.
  • the grooves are formed on the surface of the first conductive type or the second conductive type conductive layer by a photolithography or etching process.
  • the depth of the groove is from 0.5 to 50 ⁇ m.
  • the filled semiconductor material is changed into single crystal silicon by a high temperature step, and then the first surface of the substrate is planarized by a chemical mechanical polishing process. .
  • the oxide layer is formed on the conductive layer and the channel by thermal oxidation or chemical vapor deposition, and the thickness of the oxide layer is 0.01 to 5 ⁇ m.
  • the thickness of the substrate semiconductor wafer bonded on the oxide layer is 50-650 ⁇ m.
  • the method before forming the front structure of the insulated gate bipolar transistor based on the drift region, the method further includes:
  • the second surface of the thinned semiconductor wafer is polished by chemical mechanical polishing or wet etching.
  • the sum of the thickness of the substrate semiconductor wafer and the thickness of the drift region formed by the bonding is 625 ⁇ m to 725 ⁇ m.
  • the manufacturing method of the insulated gate bipolar transistor first completes the fabrication of the mutually spaced collector regions and channels on the back surface of the insulated gate bipolar transistor, and then fabricates the insulated gate double on the second surface of the semiconductor wafer.
  • the front structure of the pole transistor requires only the steps of thinning and back metallization after the front structure is completed, and there is no special requirement for the sheet flow capacity, and the double-sided exposure machine equipment is not needed, which greatly reduces the process cost.
  • FIG. 1 is a flow chart showing a method of fabricating an insulated gate bipolar transistor according to an embodiment
  • FIG. 2 to 11 are schematic longitudinal cross-sectional views of the wafer obtained in each manufacturing process of Fig. 1.
  • the surface where the emitter and the gate of the IGBT are located is generally understood as the front side, and the surface on which the collector of the IGBT is located is generally understood to be the reverse side or the back side.
  • semiconductor wafers There are many types of semiconductor wafers, and silicon wafers are commonly used. In the following embodiments, silicon wafers will be exemplified.
  • FIG. 1 is a flow chart of a method 100 of fabricating an IGBT according to an embodiment. As shown in FIG. 1, the manufacturing method 100 includes the following steps.
  • Step 110 provides an N-type silicon wafer 10, wherein the silicon wafer 10 includes a first surface 11 and a second surface 12 opposite to the first surface 11, and impurities are formed on the first surface 11 of the silicon wafer 10.
  • the implantation is performed to form an N-type or P-type conductive layer 13.
  • the silicon wafer 10 may have a thickness of 200-700 ⁇ m and a resistivity of 5-500 ⁇ *cm.
  • the conductive layer 13 has an impurity implantation dose of 1 ⁇ 10 -13 -1 ⁇ 10 -20 cm -2 and an energy of 30 - 200 KEV.
  • the impurities may be donor impurities such as phosphorus or arsenic, or may be acceptor impurities such as boron or hydrogen.
  • Step 120 as shown in FIG. 3, a spacer groove 25 is formed on the surface of the N-type or P-type conductive layer 13 by photolithography and etching processes.
  • the depth of the groove 25 may be 0.5-50 ⁇ m.
  • Step 130 fills the recess 25 with an N-type or P-type semiconductor material to form an N-type or P-type via 14.
  • the conductive layer 13 is P-type
  • an N-type channel is formed in step 130.
  • the conductive layer 13 is N-type
  • a P-type channel is formed in step 130, and the conductive layers 13 and 14 have opposite conductivity types.
  • the conductive layer 13 is N-type and the channel 14 is P-type as an example.
  • the recess 25 is filled with a P-type semiconductor material (such as single crystal silicon, polycrystalline silicon, amorphous silicon) having a resistivity of 0.001-50 ⁇ *cm, and the filled semiconductor material is passed through a high temperature step.
  • the single crystal silicon is changed to obtain the activated P-type channel 14, and then the surface of the conductive layer 13 is planarized by a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • Activation of the P-type channel 14 typically occurs after the formation of the front side metal electrode in the related process, and the activation steps in the present invention occur prior to the formation of the metal electrode, increasing the activation efficiency of the doped region (such as the P-type channel 14).
  • Step 140 forms an oxide layer 15 on the conductive layer 13 and the via 14.
  • the surface of the conductive layer 13 and the channel 14 is removed by gel removal, and is subjected to thermal oxidation or chemical vapor deposition (CHEMICAL VAPOR).
  • CHEMICAL VAPOR thermal oxidation or chemical vapor deposition
  • an oxide layer 15 having a thickness of 0.01 to 5 ⁇ m is formed on the conductive layer 13 and the via 14 to protect the conductive layer 13 and the channel 14.
  • Step 150 flips the silicon wafer 10 and bonds the P-type or N-type substrate 16 on the oxide layer 15.
  • the thickness of the substrate 16 is related to the thickness of the bonding drift region mentioned below.
  • the oxide layer 15 is bonded to the N-type or P-type substrate 16 by a direct bonding (SDB) method, and the thickness of the substrate 16 is 50-650 ⁇ m.
  • SDB direct bonding
  • Step 160 thinning the silicon wafer 10 from the second surface 12 of the silicon wafer 10, and using the thinned silicon wafer 10 as an N-type drift region (N Drift) 17.
  • the thickness of the drift region 17 formed by thinning is related to the thickness of the substrate 16.
  • the sum of the thickness of the substrate 16 and the thickness of the drift region 17 is the thickness of the normal circulating silicon wafer, for example, the normal thickness of the 6-inch sheet is 625 ⁇ m or 675 ⁇ m, and the normal thickness of the 8-inch sheet is 725 ⁇ m.
  • Step 170 forms a front structure of the IGBT based on the drift region 17 using a normal IGBT process flow.
  • the front structure of a planar IGBT is shown in FIG.
  • the front side structure of the IGBT includes a P-type base region 18 selectively formed on the upper surface of the drift region 17, and a selectively formed N-type emitter region 19 in the P-type base region 18,
  • a gate oxide layer 20 is formed on the upper surface of the drift region 17, and a polysilicon gate 21 (G) formed on the gate oxide layer 20 forms a dielectric layer 22 covering the gate oxide layer 20 and the polysilicon gate 21, and is formed and formed.
  • the P-type base region 18 and the N-type emitter region 19 are electrically connected to the front metal electrode 23 (ie, the emitter E).
  • the front side metal electrode 23 is only schematically shown in FIG. 8, and in fact, the front side metal electrode 23 may cover the entire dielectric layer 22. Further, the front structure of the IGBT may also include a passivation layer (not shown) formed on the outside of the front surface metal electrode 23, such as silicon dioxide and silicon nitride.
  • a trench IGBT can also be fabricated.
  • the front structure of the trench IGBT is different from the front structure of the IGBT in FIG. 8, but many trench IGBTs have been disclosed in the prior art. The description is not repeated. It is to be understood that, from a certain aspect of the present invention, the present invention does not particularly concern the specific front structure of the IGBT as long as it has a front side structure and can form an IGBT device that can be used.
  • the present invention provides an example of a manufacturing flow of the front structure of the IGBT of FIG. 8, which includes:
  • Step 1 Form a gate oxide layer, such as a thickness of 100 ⁇ to 15,000 ⁇ .
  • Step 2 forming a polysilicon gate layer on the gate oxide layer, for example, having a thickness of 4000 ⁇ to 15,000 ⁇ .
  • Step 3 lithography, etching, ion implantation, and sinking of the polysilicon gate to form a P-base region, the P-type impurity implantation dose is 1 ⁇ 10 -12 -1 ⁇ 10 -15 cm -2 , and the implantation energy is 20KEV-1MEV;
  • the push trap temperature is 1000-1250 ° C, and the time is 10 min - 1000 min.
  • Step 4 photolithography, ion implantation, annealing of the N-type emitter region to form an N-type, the dose is 1 ⁇ 10 -14 -1 ⁇ 10 -16 cm -2 , the energy is 20KEV-1MEV; the annealing temperature is 800-1000 ° C , the time is 10min-1000min;
  • Step 5 forming a dielectric layer, thickness: 6000 ⁇ -20000 ⁇ ;
  • Step six photolithography, etching to form a contact hole, the contact hole is in communication with the N-type emitter region and the P-type base region;
  • Step seven depositing a front metal layer, the thickness of the front metal layer is about 2 ⁇ m-6 ⁇ m;
  • Step 8 Deposit a passivation layer.
  • the specific manufacturing process of the front structure of the IGBT is not the focus of the present invention, and it can be manufactured by using various existing manufacturing processes, so in order to highlight the focus of the present invention, the front side of the IGBT is concerned.
  • the specific manufacturing process of the structure is not described in detail herein.
  • Step 180 removes substrate 16.
  • the substrate 16 is thinned by a grinding process, and after being thinned to a certain thickness, the substrate 16 is further removed by wet etching until the oxide layer is exposed. 15.
  • Step 190 removes the oxide layer 15.
  • the oxide layer 15 is continuously removed by wet etching.
  • Step 200 as shown in FIG. 11, a back metal electrode (collector C) 24 is formed on the outer side of the conductive layer 13 and the channel 14 by sputtering or evaporation.
  • the back metal electrode 24 and the channel 14 and the conductive layer 13 are electrically connected. connection.
  • one of the features or objects of the present invention is to first complete the fabrication of mutually spaced N-type collector regions and P-channels on the back side of the IGBT, followed by fabrication of the silicon wafer 10
  • the front surface structure of the IGBT is prepared on the second surface 12, and only the thinning and back metallization steps are required after the front surface structure is completed, so that there is no special requirement for the sheet flowability, and no double-sided exposure machine equipment is needed.
  • the N type in the above embodiment may be referred to as a first conductivity type, and the P type may be referred to as a second conductivity type.
  • all of the P-type regions (such as the P-base region and the P-type collector region) involved in the above embodiments may be changed to N-type, and all N-type regions (N-type drift regions) , N-type emitter region, N-type cathode region) can be changed to P-type, in this case, it can be considered that the first conductivity type is P-type, and the second conductivity type is N-type.

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Abstract

一种绝缘栅双极晶体管的制造方法，包括提供第一导电类型的半导体晶片，半导体晶片包括第一表面和与第一表面相对的第二表面，在第一表面上进行杂质注入以形成第一导电类型或第二导电类型的导电层；在第一导电类型或第二导电类型的导电层的表面形成间隔的凹槽；在凹槽内填充第二导电类型或第一导电类型的半导体材料以形成通道，通道和导电层间隔交错排布；在导电层和通道上形成氧化层；在氧化层上键合衬底半导体晶片；自第二表面减薄半导体晶片，减薄后的第一导电类型的半导体晶片作为漂移区；基于漂移区形成绝缘栅双极晶体管的正面结构；去除衬底半导体晶片；去除氧化层；在通道和导电层上形成背面金属电极，背面金属电极与通道和导电层电性连接。

Description

绝缘栅双极晶体管的制造方法
【技术领域】
本发明涉及半导体设计及制造技术领域，特别涉及一种绝缘栅双极晶体管（Insulated Gate Bipolar Transistor，IGBT）的制造方法。
【背景技术】
绝缘栅双极晶体管（Insulated Gate Bipolar Transistor，IGBT）是由双极结型晶体管 （Bipolar Junction Transistor，BJT） 和金属氧化物半导体场效应晶体管（Metal-Oxide-Semiconductor-Field-Effect-Transistor，MOSFET）组成的复合全控型电压驱动式功率半导体器件，兼有MOSFET的高输入阻抗和BJT的低导通压降两方面的优点，具有工作频率高，控制电路简单，电流密度高，通态压低等特点，广泛应用于功率控制领域。在实际应用中，IGBT很少作为一个独立器件使用，尤其在感性负载的条件下，IGBT需要一个快恢复二极管续流。因此，现有的绝缘栅双极晶体管产品，一般采用并联一个续流二极管（Freewheeling diode，简称FWD）的方式来保护IGBT。为了降低成本，并联的续流二极管可以集成在IGBT芯片内，即该IGBT为具有内置二极管或具有反向导通功能的IGBT。
常见的反向导通的IGBT需要减薄后双面光刻制备出背面P+集电极区的注入窗口。这种方案的缺点主要有两个方面：第一、需要有减薄晶圆流通能力，特别是对于常见的1200V以下的IGBT，其厚度在200μm以下，对薄片流通工艺要求很高；第二、需要使用专门的双面曝光机对晶圆曝光。此外，现有的反向导通的IGBT通常采用背面两次光刻技术，工序复杂。
因此，有必要提供一种改进的技术方案来克服上述问题。
【发明内容】
基于此，有必要提供一种与现有的常规工艺兼容且工艺较为简单的绝缘栅双极晶体管的制造方法。
一种绝缘栅双极晶体管的制造方法，其包括：提供第一导电类型的半导体晶片，半导体晶片包括第一表面和与第一表面相对的第二表面，在半导体晶片的第一表面上进行杂质注入以形成第一导电类型或第二导电类型的导电层；在第一导电类型或第二导电类型的导电层的表面形成间隔的凹槽；在凹槽内填充第二导电类型或第一导电类型的半导体材料以形成通道，其中通道的导电类型与导电层的导电类型不同，通道和导电层间隔交错排布；在导电层和通道上形成氧化层；在氧化层上键合衬底半导体晶片;自半导体晶片的第二表面减薄半导体晶片，并将减薄后的第一导电类型的半导体晶片作为漂移区；基于漂移区形成绝缘栅双极晶体管的正面结构；去除衬底半导体晶片；去除氧化层；在通道和导电层上形成背面金属电极，该背面金属电极与通道和导电层电性连接。
在其中一个实施例中，提供的半导体晶片的厚度为200-700μm，电阻率为5-500Ω*cm。
在其中一个实施例中，在半导体晶片的第一表面上注入导电层的注入剂量为1×10-13-1×10-20cm-2，能量为30-200KEV。
在其中一个实施例中，通过光刻、蚀刻工艺在第一导电类型或第二导电类型的导电层的表面形成间隔的凹槽。
在其中一个实施例中，凹槽的深度为0.5-50μm。
在其中一个实施例中，在填充第二导电类型或第一导电类型的半导体材料后，通过高温步骤使填充的半导体材料变成单晶硅，随后通过化学机械抛光工艺平整衬底的第一表面。
在其中一个实施例中，通过热氧化或化学气相沉积方式在导电层及通道上形成氧化层，氧化层的厚度为0.01-5μm。
在其中一个实施例中，在氧化层上键合的衬底半导体晶片的厚度为50-650μm。
在其中一个实施例中，在基于漂移区形成绝缘栅双极晶体管的正面结构前，该方法还包括：
通过化学机械抛光或湿法腐蚀方式抛光减薄后的半导体晶片的第二表面。
在其中一个实施例中，衬底半导体晶片的厚度和键合形成的漂移区的厚度的和为625μm-725μm。
与相关技术相比，上述绝缘栅双极晶体管的制造方法，首先完成绝缘栅双极晶体管的背面的相互间隔的集电极区和通道的制作，之后在半导体晶片的第二表面上制备绝缘栅双极晶体管的正面结构，在正面结构完成后仅需要做减薄和背面金属化的步骤，对薄片流通能力没有特殊要求，更不需要双面曝光机设备，极大地降低了工艺成本。
【附图说明】
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。其中：
图1为一实施例的绝缘栅双极晶体管的制造方法的流程图；
图2至图11为图1中的各个制造工序所得到的晶圆的纵剖面示意图。
【具体实施方式】
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似改进，因此本发明不受下面公开的具体实施的限制。
在介绍本发明中的绝缘栅双极晶体管（Insulated Gate Bipolar Transistor，IGBT）的制造方法之前，需要说明的是，IGBT的发射极和栅极所在的面通常被理解为正面，而IGBT的集电极所在的面通常被理解反面或背面。半导体晶片种类众多，常用的为硅片，在以下实施例中，将以硅片为例。
图1为一实施例的IGBT的制造方法100的流程图。如图1所示，该制造方法100包括如下步骤。
步骤110，如图2所示，提供N型硅片10，其中硅片10包括第一表面11和与第一表面11相对的第二表面12，在硅片10的第一表面11上进行杂质注入以形成N型或P型的导电层13。
具体的，所述硅片10的厚度可以为200-700μm，电阻率可以为5-500Ω*cm。如图2所示，在硅片10的第一表面11上做普注，导电层13的杂质注入剂量为1×10-13-1×10-20cm-2，能量为30-200KEV，该杂质可以为施主杂质，如磷或砷等，也可以为受主杂质，如硼或氢等。
步骤120，如图3所示，通过光刻、蚀刻工艺在N型或P型的导电层13的表面形成间隔的凹槽25。
具体的，凹槽25的深度可以为0.5-50μm。
步骤130，如图4所示，在凹槽25内填充N型或P型半导体材料以形成N型或P型通道14。
在导电层13为P型时，步骤130中形成N型通道，在导电层13为N型时，步骤130中形成P型通道，导电层13和通道14的导电类型相反。在图2-11所示出的实施例中，以导电层13为N型，通道14为P型为例进行介绍。具体的，如图3所示，在凹槽25内填充P型半导体材料(比如单晶硅、多晶硅、非晶硅)，其电阻率为0.001-50Ω*cm，通过高温步骤使填充的半导体材料变成单晶硅从而得到激活后的P型通道14，随后通过化学机械抛光(CMP)工艺平整导电层13的表面。在图3中的光刻胶30可以在合适步骤中被去除。
在相关工艺中P型通道14的激活通常发生在正面金属电极形成之后，而本发明中的激活步骤都发生在金属电极形成之前，提高了掺杂区域(比如P型通道14)的激活效率。
步骤140，如图5所示，在导电层13和通道14上形成氧化层15。
具体的，注入完成后，去胶清理导电层13及通道14表面，通过热氧化或化学气相沉积(CHEMICAL VAPOR DEPOSITION，CVD)方式在导电层13及通道14上形成一厚度为0.01-5μm的氧化层15，以起到保护导电层13及通道14的作用。
步骤150，如图6所示，翻转硅片10，在氧化层15上键合P型或N型的衬底16。衬底16的厚度与下文提到的键合漂移区的厚度相关。
具体的，采用直接键合（SDB）方式将氧化层15与N型或P型的衬底16键合，衬底16的厚度为50-650μm。
步骤160，如图7所示，自硅片10的第二表面12减薄硅片10，并将减薄后的硅片10，作为N型漂移区(N Drift)17。
具体的，减薄形成的漂移区17的厚度与衬底16的厚度相关。衬底16的厚度和漂移区17的厚度之和为正常流通硅片厚度，比如对于6寸片的正常厚度为625μm或675μm，8寸片的正常厚度为725μm。
在减薄完成后，采用化学机械抛光 (CHEMICAL MECHANICAL POLISHING,CMP) 或湿法腐蚀方式抛光使硅片10的第二表面12光滑。
步骤170，如图8所示，基于漂移区17采用正常IGBT工艺流程形成所述IGBT的正面结构。
图8中展示了一种平面IGBT的正面结构。IGBT的正面结构包括：在漂移区17的上表面上有选择地形成的P型基区(P-body)18，在P型基区18内有选择地形成的N型发射极区19，在漂移区17的上表面上形成栅氧化层20，在栅极氧化层20上形成的多晶硅栅极21(G)，形成覆盖栅极氧化层20和多晶硅栅极21的介质层22，以及形成与所述P型基区18和所述N型发射极区19电性连接的正面金属电极23(即发射极E)。
图8中只是示意性的示出了正面金属电极23，事实上，正面金属电极23可能会覆盖整个介质层22。此外，IGBT的正面结构还可能包括形成于正面金属电极23外侧的钝化层(未示出)，比如二氧化硅和氮化硅。
在其他实施例中，也可以制造沟槽型IGBT，沟槽型IGBT的正面结构与图8中的IGBT的正面结构并不相同，不过现有技术中已经公开了很多沟槽型IGBT，在此不再重复描述了。需要知晓的是，从本发明的某个角度来说，本发明并不特别关心IGBT的具体正面结构，只要有正面结构并且能形成可以使用的IGBT器件即可。
本发明提出一种图8中的IGBT的正面结构的制造流程的一个示例，该流程包括：
步骤一、形成栅极氧化层，比如厚度为100Å-15000Å。
步骤二、在栅极氧化层上形成多晶硅栅极层，比如厚度为4000Å-15000Å。
步骤三、对多晶硅栅极光刻、蚀刻、离子注入、推阱以形成P基区，P型杂质注入剂量为1×10-12-1×10-15cm-2，注入能量为20KEV-1MEV；推阱温度为1000-1250℃，时间为10min-1000min。
步骤四、对N型发射区光刻、离子注入、退火以形成N型，剂量为1×10-14-1×10-16 cm-2，能量为20KEV-1MEV；退火温度为800-1000℃，时间为10min-1000min；
步骤五、形成介质层，厚度：6000Å-20000Å；
步骤六、光刻、蚀刻以形成接触孔，该接触孔与N型发射区和P型基区相通；
步骤七、淀积正面金属层，正面金属层的厚度约为2μm-6μm；
步骤八、淀积钝化层。
从另一个角度来讲，有关IGBT的正面结构的具体制造工艺也不属于本发明的重点，其可以采用现有的各种制造工艺制造而成，因此为了突出本发明的重点，有关IGBT的正面结构的具体制造工艺在本文中并未被详细描述。
步骤180，如图9所示，去除衬底16。
在一个实施例中，在IGBT的正面结构完成后，通过研磨(Grinding)工艺对衬底16进行减薄，在减薄到一定厚度后，用湿法腐蚀进一步去除衬底16，直至露出氧化层15。
步骤190，如图10所示，去除氧化层15。
在一个实施例中，在衬底16完全去除后，继续采用湿法腐蚀将氧化层15全部去除。
步骤200，如图11所示，在导电层13及通道14外侧通过溅射或蒸发的方式制得背面金属电极(集电极C)24，该背面金属电极24与通道14和导电层13电性连接。
所属领域内的普通技术人员应该能够理解的是，本发明的特点或目的之一在于：首先完成IGBT的背面的相互间隔的N型集电极区和P型通道的制作，之后在硅片10的第二表面12上制备IGBT的正面结构，在正面结构完成后仅需要做减薄和背面金属化步骤，这样对薄片流通能力没有特殊要求，更不需要双面曝光机设备。
上述实施例中的N型可以被称为第一导电类型，P型可以被称为第二导电类型。在其他实施例中，上述实施例中的所涉及的所有P型的区域(比如P基区、P型集电极区)都可以更改为N型的，所有的N型的区域(N型漂移区、N型发射极区、N型阴极区)都可以更改为P型，此时可以认为第一导电类型是P型，第二导电类型为N型。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种绝缘栅双极晶体管的制造方法，包括以下步骤：
    提供第一导电类型的半导体晶片，所述半导体晶片包括第一表面和与所述第一表面相对的第二表面，在所述半导体晶片的第一表面上进行杂质注入以形成第一导电类型或第二导电类型的导电层；
    在所述第一导电类型或第二导电类型的导电层的表面形成间隔的凹槽；
    在所述凹槽内填充第二导电类型或第一导电类型的半导体材料以形成通道，其中所述通道的导电类型与所述导电层的导电类型不同，所述通道和所述导电层间隔交错排布；
    在所述导电层和通道上形成氧化层；
    在所述氧化层上键合衬底半导体晶片;
    自所述半导体晶片的第二表面减薄所述半导体晶片，并将减薄后的第一导电类型的半导体晶片作为漂移区；
    基于所述漂移区形成所述绝缘栅双极晶体管的正面结构；
    去除所述衬底半导体晶片；
    去除所述氧化层；及
    在所述通道和导电层上形成背面金属电极，所述背面金属电极与所述通道和导电层电性连接。
  2. 根据权利要求1所述的绝缘栅双极晶体管的制造方法，其特征在于，提供的所述半导体晶片的厚度为200-700μm，电阻率为5-500Ω*cm。
  3. 根据权利要求1所述的绝缘栅双极晶体管的制造方法，其特征在于，在所述半导体晶片的第一表面上注入导电层的注入剂量为1×10-13-1×10-20cm-2，能量为30-200KEV。
  4. 根据权利要求1所述的绝缘栅双极晶体管的制造方法，其特征在于，通过光刻、蚀刻工艺在所述第一导电类型或第二导电类型的导电层的表面形成间隔的凹槽。
  5. 根据权利要求4所述的绝缘栅双极晶体管的制造方法，其特征在于，所述凹槽的深度为0.5-50μm。
  6. 根据权利要求4所述的绝缘栅双极晶体管的制造方法，其特征在于，在填充第二导电类型或第一导电类型的半导体材料后，通过高温步骤使填充的半导体材料变成单晶硅，随后通过化学机械抛光工艺平整所述衬底的第一表面。
  7. 根据权利要求1所述的绝缘栅双极晶体管的制造方法，其特征在于，通过热氧化或化学气相沉积方式在所述导电层和通道上形成氧化层，所述氧化层的厚度为0.01-5μm。
  8. 根据权利要求1所述的绝缘栅双极晶体管的制造方法，其特征在于，在所述氧化层上键合的所述衬底半导体晶片的厚度为50-650μm。
  9. 根据权利要求1所述的绝缘栅双极晶体管的制造方法，其特征在于，在基于所述漂移区形成所述绝缘栅双极晶体管的正面结构前，所述制造方法还包括：
    通过化学机械抛光或湿法腐蚀方式抛光所述减薄后的所述半导体晶片的第二表面。
  10. 根据权利要求1所述的绝缘栅双极晶体管的制造方法，其特征在于，所述衬底半导体晶片的厚度和所述键合形成的漂移区的厚度的和为625μm-725μm。
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