WO2014206196A1 - 具有内置二极管的igbt及其制造方法 - Google Patents

具有内置二极管的igbt及其制造方法 Download PDF

Info

Publication number
WO2014206196A1
WO2014206196A1 PCT/CN2014/079460 CN2014079460W WO2014206196A1 WO 2014206196 A1 WO2014206196 A1 WO 2014206196A1 CN 2014079460 W CN2014079460 W CN 2014079460W WO 2014206196 A1 WO2014206196 A1 WO 2014206196A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor substrate
layer
main surface
active region
igbt
Prior art date
Application number
PCT/CN2014/079460
Other languages
English (en)
French (fr)
Inventor
邓小社
张硕
芮强
王根毅
Original Assignee
无锡华润上华半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润上华半导体有限公司 filed Critical 无锡华润上华半导体有限公司
Priority to EP14817399.0A priority Critical patent/EP3016142A4/en
Priority to US14/901,622 priority patent/US9595520B2/en
Publication of WO2014206196A1 publication Critical patent/WO2014206196A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

Definitions

  • the present invention relates to the field of semiconductor design and manufacturing technology, and in particular to an IGBT (Insulated Gate) with a built-in diode Bipolar Transistor, insulated gate bipolar transistor) and its method of manufacture.
  • IGBT Insulated Gate
  • insulated gate bipolar transistor built-in diode Bipolar Transistor, insulated gate bipolar transistor
  • IGBT is made of BJT (Bipolar Junction Transistor) Composite fully-regulated voltage-driven power semiconductor device composed of MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor), combining high input impedance of MOSFET and low on-state voltage of BJT
  • MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • FWD Freewheeling Diode
  • an IGBT having a built-in diode is generally subjected to a back surface two-lithography technique, which selectively implants and diffuses to form a spacer N+ region and a P+ region, respectively, and the N+ region and the P+ region are spread over the entire IGBT back surface.
  • the area (the entire back area includes the active area and the termination protection area), resulting in poor recovery characteristics of the built-in diode of this type of IGBT.
  • an IGBT having a built-in diode and a method of manufacturing the same are provided, which can improve the recovery characteristics of the built-in diode.
  • An IGBT having a built-in diode comprising: a semiconductor substrate of a first conductivity type having a first major surface and a second major surface, wherein the semiconductor substrate includes an active region and a terminal outside the active region a protected gate electrode unit formed on a first main surface side of the active region, which is formed with a channel of a first conductivity type when it is turned on; and is formed at a distance from each other on the semiconductor substrate a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type of the active region on the second main face side.
  • the IGBT having a built-in diode includes only the second semiconductor layer in the terminal protection region on the second main surface side of the semiconductor substrate.
  • the IGBT having a built-in diode further includes: a protection terminal formed on a first main surface side of the termination protection region; a semiconductor substrate of a first conductivity type formed with an insulated gate transistor unit A first main electrode for the IGBT formed on the first main surface and a second main electrode for the IGBT formed on the first semiconductor layer and the second semiconductor layer.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the insulated gate transistor unit is an N-channel MOSFET unit
  • the first conductivity type semiconductor lining The bottom is an N-type semiconductor substrate
  • the first semiconductor layer is an N+ type cathode layer
  • the second semiconductor layer is a P+ type collector layer
  • the first main electrode is an emitter
  • the second main The electrode is a collector.
  • the N-channel MOSFET cell includes: a P-well selectively formed from the first main surface of the active region in the N-type semiconductor substrate; from the P-well a surface selectively forming an N+ active region in the P well; a gate oxide layer selectively formed on a first major surface of the active region, wherein the gate oxide layer is located at an edge of the P well a first main surface of the portion and a first main surface of the active region where the P well is not formed; a polysilicon gate electrode formed on an upper surface of the gate oxide layer; covering the gate oxide layer and polysilicon The gate electrode exposes a dielectric layer of the surface, wherein the first main electrode is formed outside the dielectric layer and is in electrical contact with the N+ active region and the P well.
  • a method of fabricating an IGBT having a built-in diode comprising: providing a semiconductor substrate of a first conductivity type having a first main surface and a second main surface, the semiconductor substrate including an active region and an outer side of the active region a terminal protection region; forming an insulated gate transistor unit on a first main surface side of the active region of the semiconductor substrate; and thinning the insulated gate transistor unit from a second main surface of the semiconductor substrate a semiconductor substrate; a second semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type are formed in the semiconductor substrate from a second main surface of the thinned semiconductor substrate, the first semiconductor The layer and the second semiconductor layer are formed at intervals on the second main surface side of the active region; the terminal protection region on the second main surface side forms only the second semiconductor layer.
  • the manufacturing method further includes: forming a protection terminal on a first main surface side of the termination protection region; forming an IGBT on a first main surface of the semiconductor substrate forming an insulated gate transistor unit A second main electrode for IGBT that is in contact with the first semiconductor layer and the second semiconductor layer is formed on the second main surface of the semiconductor substrate after the first semiconductor layer and the second semiconductor layer are formed.
  • the first semiconductor layer is formed first, and then the second semiconductor layer is formed; or when the first semiconductor layer and the second semiconductor layer are formed, the first Two semiconductor layers are formed to form a first semiconductor layer.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the insulated gate transistor unit is an N-channel MOSFET unit
  • the first conductivity type semiconductor lining The bottom is an N-type semiconductor substrate
  • the first semiconductor layer is an N+ type cathode layer
  • the second semiconductor layer is a P+ type collector layer
  • the first main electrode is an emitter
  • the second main The electrode is a collector.
  • forming the insulated gate transistor unit on the first main surface side of the active region of the semiconductor substrate includes: generating a field oxide layer on the first main surface of the N-type semiconductor substrate, And etching a region of the active region; forming a gate oxide layer on the first main surface of the active region, and depositing a polysilicon gate on the gate oxide layer; Selectively etching the gate oxide layer and the polysilicon gate to etch the implantation window of the P well, and forming a P well along the etched P well window into the N-type semiconductor substrate; selectively from the P Forming a N+ active region into the N-type semiconductor substrate; depositing a dielectric layer on the first main surface of the active region, and etching a contact between the shorted N+ active region and the P well a hole, wherein the first main electrode is formed outside the dielectric layer and is in electrical contact with the N+ active region and the P well.
  • the IGBT having a built-in diode and the method of manufacturing the same, wherein a first semiconductor layer of a first conductivity type and a second semiconductor of a second conductivity type are formed at a distance from each other on a second main surface side of an active region of the semiconductor substrate a layer, and only a second semiconductor layer is formed on a second main surface side of the termination protection region of the semiconductor substrate, so that a semiconductor substrate stored under the termination protection region when the built-in diode is reversely restored can be reduced
  • the number of carriers inside can be used to optimize the reverse recovery characteristics of the built-in diode, while at the same time ensuring that the characteristics of the IGBT are not affected.
  • 1 is a longitudinal cross-sectional view of a portion of an IGBT having a built-in diode of one embodiment
  • FIG. 2 to FIG. 12 are longitudinal cross-sectional views of the IGBT having a built-in diode of FIG. 1 in various manufacturing processes of one embodiment
  • FIG. 13 is a flow chart showing a method of manufacturing the IGBT having a built-in diode shown in FIG. 1 in one embodiment.
  • one embodiment or “an embodiment” as used herein refers to a particular feature, structure, or characteristic that can be included in at least one implementation of the invention.
  • FIG. 1 is a longitudinal cross-sectional view of a portion of an IGBT having a built-in diode in one embodiment.
  • the IGBT includes: a semiconductor substrate 1 of a first conductivity type having a first main surface 1S1 and a second main surface 1S2, wherein the semiconductor substrate 1
  • the structure in which the first conductivity type is N-type and the second conductivity type is P-type is taken as an example, and the structure of the IGBT having the built-in diode described above is specifically described with reference to FIG.
  • the first conductivity type semiconductor substrate 1 is an N-type semiconductor substrate (also referred to as an N-layer), and the protection terminal is a field limiting ring termination structure, and the field limiting ring termination structure
  • a P-type layer 2 formed by selectively doping P-type impurities into the N-type semiconductor substrate 1 from the first main surface 1S1 in the termination protection region 200 is included.
  • a field oxide layer 13 is also formed on the first main surface 1S1 in the terminal protection region 200. It is easy to think that the protection terminal can also be other protection terminal structures in the prior art, for example, a field limiting ring plus field plate terminal structure.
  • the insulated gate transistor unit is a MOSFET having a channel of a first conductivity type (here, an N-type channel).
  • the N-channel MOSFET is DMOS.
  • DMOS Double-diffused Metal Oxide Semiconductor, double diffused MOS
  • a structured MOSFET comprising: a P well 5 formed by selectively diffusing a P-type impurity from the first main surface 1S1 of the active region 100 into the N-type semiconductor substrate 1; a surface from the P well 5
  • An N+ active region (or referred to as an N+ emitter) 6 formed by selectively diffusing a high concentration of N-type impurities into the P well 5; selectively formed on the first main surface of the active region 100 a gate oxide layer (abbreviated as gate oxide layer) 3, wherein the gate oxide layer 3 is located on a first main surface of an edge portion of the P well 5 and a first main surface of the active region where a P well is not formed a polysilicon gate electrode 4
  • the second semiconductor layer 11 is a P+ layer formed by selectively implanting P-type impurities into the N-type semiconductor substrate 1 from the second main surface 1S2 (or
  • the first semiconductor layer 10 is an N+ layer formed by selectively implanting N-type impurities into the N-type semiconductor substrate 1 from the second main surface 1S2 (also referred to as a P+ collector layer).
  • N+ cathode layer wherein the P+ collector layer 11 and the N+ cathode layer 10 are formed on the second main surface 1S2 side of the active region 200 at intervals from each other, and on the second main surface 1S2 side of the terminal protection region 200 Only the P+ collector layer 11 is present.
  • the IGBT having a built-in diode in FIG. 1 further includes: a first main electrode (in this embodiment, an emitter) formed on the first main surface 1S1 of the active region 100 to cover the dielectric layer 7; a second main electrode (collector in the present embodiment) 12 formed on the semiconductor layer 10 and the second semiconductor layer 11; covering the first main electrode 8 and the field oxide layer 13 for protecting the surface of the chip from A passivation layer 9 that is smeared by external ions.
  • the second main electrode 12 is in electrical contact with the first semiconductor layer 10 and the second semiconductor layer 11, and the first main electrode 8 is in electrical contact with the N+ active region 6 and the P well 5.
  • the channel region The inversion is an N-type region, and a channel connecting the N-layer 1 and the N+ active region 6 is electrically formed in the P well 5, and electrons are injected from the emitter 8 into the N-layer 1 through the channel, utilizing The injected electrons form a forward bias between the P+ collector layer 11 and the N-layer 1, and holes are injected from the P+ collector layer 11, and the resistance of the N-layer 1 is greatly lowered, and the current capacity of the IGBT is increased. Large, that is, the IGBT is turned on.
  • the gate voltage VGE applied between the emitter 8 and the gate electrode 4 is 0 V in the on state, or the emitter 8 and the gate electrode 4 are reverse biased, the channel region is returned to In the P-type region, since the injection of electrons from the emitter 8 is stopped, the injection of holes from the P+ collector layer 11 is also stopped. Thereafter, the electrons and holes remaining in the N-layer 1 are respectively withdrawn to the collector 12 and the emitter 8, or recombined with each other in the N-layer 1 to disappear, that is, the IGBT is turned off.
  • a PIN (positive-intrinsic-negative) junction diode i.e., a built-in diode in the IGBT
  • a voltage VEC of opposite polarity is applied to the IGBT
  • the built-in diode flows through a forward current (ie, conduction) from the hole injected by the P well 5 and the electron injected by the N+ cathode layer 10.
  • the injection of holes from the P well 5 is stopped, and the injection of electrons from the N+ cathode layer 10 is also stopped, and thereafter, as electrons and holes remaining in the N-layer 1, respectively It exits from the collector 12 and the emitter 8, or recombines in the N-layer 1 and disappears.
  • the current flowing through the built-in diode is referred to as a recovery current, which is opposite to the direction in which the current flows when the built-in diode is turned on.
  • the recovery characteristics of the built-in diode can be improved by reducing the recovery current.
  • an IGBT having a built-in diode is generally subjected to a back-surface two-lithography technique, which selectively implants and diffuses to form mutually spaced N+ regions (or N+ cathode layers) and P+ regions (or P+ regions).
  • the electrode layer), and the N+ region and the P+ region are spread over the entire back surface region of the IGBT (the entire back surface region includes an active region and a terminal protection region).
  • the existing IGBT structure when a built-in diode is turned on, a large number of holes injected by the P well 5, a part of which holes enter the back surface area of the IGBT through the N-layer in the termination protection region 200.
  • the N+ cathode layer 10 and the P+ collector layer 11 are formed on the second main surface 1S2 side of the active region 200 at intervals, and only the P+ collector layer 11 is formed on The second main surface 1S2 side of the terminal protection zone 200.
  • the number of carriers stored in the semiconductor substrate 1 under the terminal protection region 200 when the built-in diode is reversely recovered can be reduced, so that the reverse recovery characteristic of the built-in diode can be optimized well, and at the same time It is well guaranteed that the characteristics of the IGBT are not affected.
  • the insulated gate transistor is a MOSFET of a DMOS structure, and in other embodiments, it may also be a trench MOSFET or a V-shaped MOSFET.
  • the bottom 1 includes an active region 100 and a terminal protection region 200 outside the active region; a protection terminal is formed on a first main surface 1S1 side of the terminal protection region 200 of the semiconductor substrate 1; on the semiconductor substrate 1 An insulated gate transistor unit is formed on the first main surface 1S1 side of the active region 100; a first main electrode 8 for IGBT is formed on the first main surface 1S1 of the semiconductor substrate 1 on which the insulated gate transistor unit is formed;
  • the second main surface 1S2 of the semiconductor substrate 1 serves to thin the semiconductor substrate 1 after the insulated gate transistor unit is formed; the second main surface 1S2 of the self-thinned semiconductor substrate 1 is directed into the semiconductor substrate 1 Forming the first semiconductor layer 10 of the first conductivity type and the second semiconductor layer
  • Step 110 providing an N-type semiconductor substrate 1 having a first major surface 1S1 and a second major surface 1S2.
  • Step 120 forms a protection terminal on the first main surface 1S1 side of the terminal protection region 200 of the N-type semiconductor substrate 1.
  • a P-type impurity is selectively implanted in the first main surface 1S1 of the N-type semiconductor substrate 1 by a photolithography process, and a P-type layer 2 is formed in the terminal protection region 200 by diffusion to obtain a field limiting ring terminal. structure.
  • Step 130 as shown in FIG. 3, generates a field oxide layer 13 on the first main surface 1S1 of the N-type semiconductor substrate 1, and etches a region of the active region 100.
  • the field oxide layer 13 is formed on the first main surface 1S1 of the N-type semiconductor substrate 1, and the region of the active region 100 is selectively etched by photolithography and etching.
  • Step 140 as shown in FIG. 4, a gate oxide layer 3 is formed on the first main surface 1S1 in the active region 100, and a polysilicon gate 4 is deposited on the gate oxide layer 3.
  • a gate oxide layer 3 is formed on the first main surface 1S1 of the active region 100 by thermal oxidation, and the thick bottom of the gate oxide layer 3 is about 600 ⁇ to 1500.
  • a polysilicon gate 4 of a certain thickness is then deposited on the upper surface of the gate oxide layer 3.
  • Step 150 selectively etching the gate oxide layer 3 and the polysilicon gate 4 to etch the implantation window of the P-type base region or the P-well 5, and self-etching the window to the N P-type diffusion is performed in the -type semiconductor substrate 1 to form a P-type base region or a P well 5.
  • the gate oxide layer 3 and the polysilicon gate 4 are selectively etched by photolithography and etching processes to etch the implantation window of the P well 5, and the P type is injected through the self-aligned implantation process. Impurities, and a P well 5 is formed in the N-type semiconductor substrate 1 by a push well.
  • Step 160 selectively forms an N-type active region 6 from the surface of the P well 5 into the N-type semiconductor substrate 1.
  • an N+ implantation window is selectively formed on the surface of the P well 5 by a photolithography process, and an N+ active region (or N+ emitter) 6 is formed by implanting and pushing the well.
  • Step 170 as shown in FIG. 7, a dielectric layer 7 formed with a polysilicon gate 4 is deposited on the first main surface 1S1 of the active region 100, and is etched by photolithography and etching to short the N+. Contact holes of the source region 6 and the P well 5.
  • Step 180 as shown in FIG. 8, forming a first main electrode (here, emitter) metal 8 covering the exposed surface of the dielectric layer 7 on the first main surface 1S1 of the active region 100, wherein the first main The electrode metal 8 is electrically connected to the P well 5 and the N+ active region 6.
  • the emitter metal 8 is formed by sputtering, and a portion of the metal is selectively etched by photolithography and etching processes.
  • the emitter metal 8 may be formed by other means, such as by depositing a metal. The way.
  • Step 190 as shown in FIG. 9, a passivation layer 9 is deposited on the first main electrode metal 8 and the field oxide layer 13. Specifically, a passivation layer 9 for protecting the surface of the chip from external ions is deposited on the first main electrode metal 8 and the field oxide layer 13 by chemical vapor deposition, and is lithographically and etched. A PAD (pad) region (not shown) for extracting the gate electrode 4 and the emitter 8 is etched.
  • step 210 the thick bottom of the N-type semiconductor substrate 1 is thinned by a backside thinning process. Specifically, the semiconductor substrate 1 is polished from the second main surface of the N-type semiconductor substrate 1 to meet a predetermined thickness requirement.
  • Step 220 selectively performing P-type impurity implantation from the second main surface of the thinned N-type semiconductor substrate 1 toward the inside of the semiconductor substrate 1 to form a P-type second semiconductor layer (or P+ collector layer) 11, wherein only a continuous second semiconductor layer is formed at the second main surface of the termination protection region 200, and a second semiconductor is formed at intervals along the second main surface of the active region 100 Floor.
  • a P-type second semiconductor layer or P+ collector layer
  • Step 230 selectively injecting N-type impurities from the second main surface 1S2 of the active region of the N-type semiconductor substrate 1 toward the inside of the semiconductor substrate 1 by a photolithography process to form and
  • the second semiconductor layer 11 is spaced apart from each other by an N-type first semiconductor layer (here, an N+ cathode layer) 10.
  • Step 240 as shown in FIG. 12, the first semiconductor layer 10 and the second semiconductor layer 11 are activated by low temperature annealing, and a metal layer of a certain thickness (such as Al) is formed on the first semiconductor layer 10 and the second semiconductor layer 11.
  • a metal layer of a certain thickness such as Al
  • this metal layer 12 is the second main electrode for IGBT.
  • the IGBT having the built-in diode in Fig. 1 can be manufactured.
  • the metal layer 12 may be formed on the first semiconductor layer 10 and the second semiconductor layer 11, and then the first semiconductor layer 10 and the second semiconductor layer 11 may be activated.
  • Steps 140 to 180 are processes of forming an insulated gate transistor on the first main surface of the active region of the N-type semiconductor substrate 1, and therefore, if the insulated gate transistor is another type of MOSFET, the corresponding manufacturing steps are also Need to change accordingly.
  • the formation order of forming the P+ collector layer 11 and the N+ cathode layer 10 may also be reversed, that is, first on the second main surface of the active region of the N-type semiconductor substrate 1.
  • the N+ cathode layer 10 is formed on the side; then, the P+ collector layer 11 spaced apart from the N+ cathode layer 10 is formed on the second main surface side 1S2 of the N-type semiconductor substrate 1.
  • the first conductivity type is N-type
  • the second conductivity type is P-type.
  • the first conductivity type may be P-type.
  • the second conductivity type is N-type, in which case a P-type semiconductor substrate 1 is used, the insulated gate transistor is a P-channel MOSFET unit, and the second main electrode 12 is an emitter, and the first main electrode 8
  • the specific structure and principle are similar to those of the above IGBT, and are not described here.
  • the IGBT having a built-in diode and the method of fabricating the same the first semiconductor layer 10 of the first conductivity type is formed at a distance from each other on the second main surface side of the active region 100 of the semiconductor substrate 1
  • the second semiconductor layer 11 of the second conductivity type, and only the second semiconductor layer 11 is formed on the second main surface side of the termination protection region 200 of the semiconductor substrate 1, so that when the built-in diode is reversely restored
  • the number of carriers stored in the semiconductor substrate under the terminal protection area can optimize the reverse recovery characteristics of the built-in diode, and at the same time ensure that the characteristics of the IGBT are not affected.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

提供一种具有内置二极管的绝缘栅双极晶体管（IGBT）及其制造方法。所述IGBT包括：具有第一主面（1S1）和第二主面（1S2）的第一导电类型的半导体衬底（1），其中半导体衬底（1）包括有源区（100）和有源区外侧的终端保护区（200）；形成于有源区（100）的第一主面（1S1）侧的绝缘栅型晶体管单元，在其导通时其形成有第一导电类型的沟道；相互间隔地形成于半导体衬底（1）的第二主面（1S2）侧的有源区的第一导电类型的第一半导体层（10）和第二导电类型的第二半导体层（11）。其中，所述IGBT在所述半导体衬底（1）的第二主面侧（1S2）的所述终端保护区（200）仅包括第二半导体层（11）。

Description

具有内置二极管的IGBT及其制造方法
【技术领域】
本发明涉及半导体设计及制造技术领域，特别涉及一种具有内置二极管的IGBT（Insulated Gate Bipolar Transistor，绝缘栅双极晶体管）及其制造方法。
【背景技术】
IGBT是由BJT （Bipolar Junction Transistor，双极结型晶体管） 和MOSFET（Metal-Oxide-Semiconductor-Field-Effect-Transistor，金属氧化物半导体场效应晶体管）组成的复合全控型电压驱动式功率半导体器件，兼有MOSFET的高输入阻抗和BJT的低导通压降两方面的优点，具有工作频率高，控制电路简单，电流密度高，通态压低等特点，广泛应用于功率控制领域。在实际应用中，IGBT很少作为一个独立器件使用，尤其在感性负载的条件下，IGBT需要一个快恢复二极管续流。因此，现有的绝缘栅双极晶体管产品，一般采用并联一个续流二极管（Freewheeling diode ，简称FWD）以保护IGBT。为了降低成本，并联的续流二极管可以集成在IGBT芯片内，即具有内置二极管的IGBT。
现有技术中对具有内置二极管的IGBT通常采用背面两次光刻技术，分别有选择性地注入、扩散来形成间隔性的N+区域和P+区域，且该N+区域和P+区域遍布整个IGBT的背面区域(整个背面区域包括有源区和终端保护区)，导致该类型IGBT的内置二极管的恢复特性较差。
【发明内容】
基于此，提供一种具有内置二极管的IGBT及其制造方法，其可以改善内置二极管的恢复特性。
一种具有内置二极管的IGBT，包括：具有第一主面和第二主面的第一导电类型的半导体衬底，其中，所述半导体衬底包括有源区和所述有源区外侧的终端保护区；形成于所述有源区的第一主面侧的绝缘栅型晶体管单元，在其导通时其形成有第一导电类型的沟道；相互间隔地形成于所述半导体衬底的第二主面侧的有源区的第一导电类型的第一半导体层和第二导电类型的第二半导体层。其中，所述具有内置二极管的IGBT在所述半导体衬底的第二主面侧的所述终端保护区仅包括第二半导体层。
在一个实施例中，所述具有内置二极管的IGBT还包括：在所述终端保护区的第一主面侧形成的保护终端；在形成有绝缘栅型晶体管单元的第一导电类型的半导体衬底的第一主面上形成的IGBT用第一主电极；在所述第一半导体层和第二半导体层上形成的IGBT用第二主电极。
在一个实施例中，所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型的半导体衬底，所述第一半导体层为N+型阴极层，所述第二半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极。
在一个实施例中，所述N型沟道MOSFET单元包括：自所述有源区中的第一主面向所述N-型半导体衬底内有选择地形成的P阱；自所述P阱的表面向该P阱内有选择地形成的N+有源区；在所述有源区的第一主面上有选择地形成的栅氧化层，其中，所述栅氧化层位于P阱的边缘部分的第一主面和所述有源区的未形成P阱的第一主面上；在所述栅极氧化层的上表面上形成的多晶硅栅电极；覆盖所述栅极氧化层和多晶硅栅电极露出表面的介质层，其中，第一主电极形成于所述介质层的外侧并与所述N+有源区和所述P阱电性接触。
一种具有内置二极管的IGBT的制造方法，包括：提供具有第一主面和第二主面的第一导电类型的半导体衬底，所述半导体衬底包括有源区和所述有源区外侧的终端保护区；在所述半导体衬底的有源区的第一主面侧形成绝缘栅型晶体管单元；从所述半导体衬底的第二主面起减薄该绝缘栅型晶体管单元形成后的半导体衬底；自减薄后的半导体衬底的第二主面向所述半导体衬底内形成第一导电类型的第一半导体层和第二导电类型的第二半导体层，所述第一半导体层和第二半导体层相互间隔地形成于所述第二主面侧的所述有源区；在所述第二主面侧的所述终端保护区仅形成所述第二半导体层。
在一个实施例中，所述制造方法还包括：在所述终端保护区的第一主面侧形成保护终端；在形成绝缘栅型晶体管单元的所述半导体衬底的第一主面上形成IGBT用第一主电极；在所述第一半导体层和第二半导体层形成后的半导体衬底的第二主面上形成与第一半导体层和第二半导体层接触的IGBT用第二主电极。
在一个实施例中，在形成第一半导体层和第二半导体层时，先形成第一半导体层，后形成第二半导体层；或者在形成第一半导体层和第二半导体层时，先形成第二半导体层，后形成第一半导体层。
在一个实施例中，所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型的半导体衬底，所述第一半导体层为N+型阴极层，所述第二半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极。
在一个实施例中，所述在所述半导体衬底的有源区的第一主面侧形成绝缘栅型晶体管单元包括：在N-型半导体衬底的第一主面上生成场氧化层，并刻蚀出所述有源区的区域；在所述有源区的第一主面上生成栅氧层，并在所述栅氧层上淀积多晶硅栅极； 选择性地刻蚀栅氧层和多晶硅栅极以刻蚀P阱的注入窗口，并沿刻蚀出的该P阱窗口向N-型半导体衬底内形成P阱；选择性地自所述P阱表面向所述N-型半导体衬底内形成N+有源区；在有源区的第一主面上淀积介质层，并刻蚀出短接N+有源区和所述P阱的接触孔，其中第一主电极形成于所述介质层的外侧并与所述N+有源区和所述P阱电性接触。
上述具有内置二极管的IGBT及其制造方法，在所述半导体衬底的有源区的第二主面侧相互间隔地形成有第一导电类型的第一半导体层和第二导电类型的第二半导体层，而在所述半导体衬底的终端保护区的第二主面侧仅形成有第二半导体层，这样，可以减少当内置二极管反向恢复时，存储于该终端保护区下方的半导体衬底内的载流子数量，从而可以很好的优化内置二极管的反向恢复特性，同时又能很好的保证IGBT的特性不受影响。
【附图说明】
通过附图中所示的本发明的优选实施例的更具体说明，本发明的上述及其它目的、特征和优势将会变得更加清晰。在全部附图中相同的附图标记指示相同的部分，且并未刻意按实际尺寸等比例缩放绘制附图，重点在于示出本发明的主旨。
图1为一个实施例的具有内置二极管的IGBT的一部分的纵剖面图；
图2至图12为图1中的具有内置二极管的IGBT在一个实施例的各个制造工序的纵剖面图；
图13为制造图1所示的具有内置二极管的IGBT的方法在一个实施例中的流程图。
【具体实施方式】
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似改进，因此本发明不受下面公开的具体实施的限制。
此处所称的“一个实施例”或“实施例”是指可包含于本发明至少一个实现方式中的特定特征、结构或特性。在本说明书中不同地方出现的“在一个实施例中”并非均指同一个实施例，也不是单独的或选择性的与其他实施例互相排斥的实施例。
请参考图1，其为在一个实施例中的具有内置二极管的IGBT的一部分的纵剖面图。所述IGBT包括：具有第一主面1S1和第二主面1S2的第一导电类型的半导体衬底1，其中，所述半导体衬底1 包括有源区100和所述有源区100外侧的终端保护区200；形成于所述有源区100的第一主面1S1侧的绝缘栅型晶体管单元，在其导通时，其形成有第一导电类型的沟道；形成于所述终端保护区200的第一主面1S1侧的保护终端；相互间隔地形成于所述半导体衬底1的第二主面1S2侧的有源区的第一导电类型的第一半导体层10和第二导电类型的第二半导体层11；仅形成于所述终端保护区200的第二主面1S2侧的第二半导体层11。
下面以所述第一导电类型为N型，所述第二导电类型为P型为例，结合图1对上述具有内置二极管的IGBT的结构进行具体介绍。
如图1所示，所述第一导电类型的半导体衬底1为N-型半导体衬底（也称为N-层），所述保护终端为场限环终端结构，该场限环终端结构包括自终端保护区200中的第一主面1S1向所述N-型半导体衬底1内选择性地进行P型杂质掺杂以形成的P型层2。在所述终端保护区200内的第一主面1S1上还形成有场氧化层13。易于思及的是，所述保护终端也可以为现有技术中的其他保护终端结构，比如，场限环加场板终端结构。
所述绝缘栅型晶体管单元为具有第一导电类型的沟道（在此为N型沟道）的MOSFET。具体的说，该N型沟道的MOSFET为DMOS （Double-diffused Metal Oxide Semiconductor，双扩散MOS） 结构的MOSFET，其包括：自所述有源区100的第一主面1S1向所述N-型半导体衬底1内有选择地扩散P型杂质形成的P阱5；自P阱5的表面向该P阱5内有选择地扩散高浓度的N型杂质形成的N+有源区（或者称为N+发射极）6；在所述有源区100的第一主面上有选择地形成的栅极氧化层（简称栅氧层）3，其中，所述栅极氧化层3位于P阱5的边缘部分的第一主面和所述有源区的未形成P阱的第一主面上；在栅极氧化层3的上表面上形成的多晶硅栅电极4；覆盖栅极氧化层3和多晶硅栅电极4露出表面的介质层7，其中，多晶硅栅电极4正下方的P阱5的部分称为沟道区。
在图1所示的实施例中，所述第二半导体层11为自所述第二主面1S2向所述N-型半导体衬底1内选择性地注入P型杂质形成的P+层（或者称为P+集电极层），所述第一半导体层10为自所述第二主面1S2向所述N-型半导体衬底1内选择性地注入N型杂质形成的N+层（或者称为N+阴极层），其中P+集电极层11和N+阴极层10相互间隔地形成于所述有源区200的第二主面1S2侧，而在所述终端保护区200的第二主面1S2侧只有P+集电极层11。
图1中的具有内置二极管的IGBT还包括：在有源区100的第一主面1S1上覆盖所述介质层7形成的第一主电极（在本实施例中为发射极）8；在第一半导体层10和第二半导体层11上形成的第二主电极（在本实施例中为集电极）12；覆盖于第一主电极8和场氧化层13上的用于保护芯片表面不受外界离子玷污的钝化层9。该第二主电极12与第一半导体层10和第二半导体层11电性接触，该第一主电极8与所述N+有源区6和所述P阱5电性接触。
以下具体介绍图1中的具有内置二极管的IGBT的工作原理。
在图1所示的结构中，如果在发射极8与集电极12之间施加规定的集电极电压VCE，而且在发射极8与栅电极4之间施加规定的栅电压VGE，则沟道区反型为N型区，在P阱5内形成电性的连接N-层1与N+有源区6的沟道，通过该沟道将电子从发射极8注入到N-层1内，利用该被注入的电子，使P+集电极层11与N-层1间形成正向偏置，从P+集电极层11注入空穴，N-层1的电阻大幅度地下降，IGBT的电流容量增大，即所述IGBT导通。如果在导通状态时，使发射极8与栅电极4之间施加的栅电压VGE为0V，或者使发射极8与栅电极4之间成为反向偏置，则该沟道区重新返回为P型区，由于来自发射极8的电子的注入停止的缘故，来自P+集电极层11的空穴的注入也停止了。其后，在N-层1中停留的电子和空穴分别向集电极12和发射极8退出，或在N-层1内相互复合而消失，即所述IGBT关断。
此外，由N+阴极层10、N-层1和P阱5构成PIN(positive-intrinsic-negative)型结二极管（即所述IGBT中的内置二极管），当对本IGBT施加极性相反的电压VEC时，该内置二极管流过正向电流（即导通），此正向电流来自P阱5注入的空穴和N+阴极层10注入的电子。当该内置二极管反向恢复时，来自P阱5的空穴的注入停止，而且来自N+阴极层10的电子的注入也停止，其后，作为在N-层1内停留的电子和空穴分别从集电极12和发射极8退出，或者在N-层1内互相复合而消失，此时流过内置二极管的电流称为恢复电流，其与内置二极管导通状态时流过的电流方向相反。通过减少该恢复电流就可以改善该内置二极管的恢复特性。
在现有技术中对具有内置二极管的IGBT通常采用背面两次光刻技术，分别有选择性地注入、扩散来形成互相间隔的N+区域(或称N+阴极层)和P+区域(或称P+集电极层)，且该N+区域和P+区域遍布整个IGBT的背面区域(整个背面区域包括有源区和终端保护区)。在现有的这种IGBT结构下，当其内置二极管导通时，由P阱5注入的大量空穴，其中一部分空穴通过终端保护区200中的N-层进入到该IGBT背面区域中的N+阴极层；当该内置二极管反向恢复时，存储于该终端保护区下方的N-层内的空穴无法迅速消失，必须通过辐照等载流子寿命控制技术来改善该内置二极管的恢复特性。而在本发明中的内置有二极管的IGBT中，N+阴极层10和P+集电极层11相互间隔地形成于所述有源区200的第二主面1S2侧，只有P+集电极层11形成于所述终端保护区200的第二主面1S2侧。这样，可以减少当内置二极管反向恢复时存储于该终端保护区200下方的所述半导体衬底1内的载流子数量，从而可以很好的优化内置二极管的反向恢复特性，同时又能很好地保证IGBT的特性不受影响。
在图1所示的实施例中，所述绝缘栅性晶体管为DMOS结构的MOSFET，在其他实施例中，其还可以为沟槽型MOSFET或V字形的MOSFET。
以下介绍本发明中的具有内置二极管的IGBT的制造方法，该制造方法包括：提供具有第一主面1S1和第二主面1S2的第一导电类型的半导体衬底1，其中，所述半导体衬底1包括有源区100和所述有源区外侧的终端保护区200；在所述半导体衬底1的终端保护区200的第一主面1S1侧形成保护终端；在所述半导体衬底1的有源区100的第一主面1S1侧形成绝缘栅型晶体管单元；在形成绝缘栅型晶体管单元的半导体衬底1的第一主面1S1上形成IGBT用第一主电极8；从所述半导体衬底1的第二主面1S2起减薄该绝缘栅型晶体管单元形成后的半导体衬底1；自减薄后的半导体衬底1的第二主面1S2向所述半导体衬底1内形成第一导电类型的第一半导体层10和第二导电类型的第二半导体层11，其中所述第一半导体层10和第二半导体层11相互间隔地形成于所述第二主面1S2侧的所述有源区100，在所述第二主面侧1S2的所述终端保护区200仅形成所述第二半导体层11；在所述第一半导体层10和第二半导体层11形成后的半导体衬底1的第二主面1S2上形成与第一半导体层10和第二半导体层11电性接触的IGBT用第二主电12。
接下来，以所述第一导电类型为N型，所述第二导电类型为P型为例，结合图2-13详细介绍图1中的具有内置二极管的IGBT的制造方法。
步骤110，提供具有第一主面1S1和第二主面1S2的N-型半导体衬底1。
步骤120，如图2所示，在所述N-型半导体衬底1的终端保护区200的第一主面1S1侧形成保护终端。具体为，在所述N-型半导体衬底1的第一主面1S1通过光刻工艺选择性地注入P型杂质，通过扩散在终端保护区200中形成P型层2以得到场限环终端结构。
步骤130，如图3所示，在所述N-型半导体衬底1的第一主面1S1上生成场氧化层13，并刻蚀出有源区100的区域。具体为，在N-型半导体衬底1的第一主面1S1上生成场氧化层13，并通过光刻、刻蚀工艺选择性得刻蚀出有源区100的区域。
步骤140，如图4所示，在所述有源区100中的第一主面1S1上生成栅极氧层3，并在所述栅极氧层3上淀积多晶硅栅极4。具体为，通过热氧化的方式在有源区100的第一主面1S1上生成栅极氧层3，该栅极氧层3的厚底约为600Å~1500 Å，随后在所述栅极氧层3的上表面淀积一定厚度的多晶硅栅极4。
步骤150，如图5所示，选择性得刻蚀栅极氧层3和多晶硅栅极4以刻蚀出P型基区或P阱5的注入窗口，并自刻蚀出的该窗口向N-型半导体衬底1内进行P型扩散以形成P型基区或P阱5。具体为，沿纵剖面方向，通过光刻、刻蚀工艺选择性地刻蚀栅极氧层3和多晶硅栅极4以刻蚀出P阱5的注入窗口，通过自对准注入工艺注入P型杂质，并通过推阱在N-型半导体衬底1中形成P阱5。
步骤160，如图6所示，选择性地自P阱5的表面向N-型半导体衬底1内形成N型的有源区6。具体为，通过光刻工艺在所述P阱5的表面选择性地制作出N+注入窗口，并通过注入和推阱形成N+有源区（或者N+发射极）6。
步骤170，如图7所示，在有源区100的第一主面1S1上淀积形成有覆盖多晶硅栅极4的介质层7，并通过光刻、刻蚀工艺刻蚀出短接N+有源区6和P阱5的接触孔。
步骤180，如图8所示，在有源区100的第一主面1S1上形成覆盖介质层7的露出表面的第一主电极（在此为发射极）金属8，其中所述第一主电极金属8与所述P阱5和N+有源区6电性连接。具体为，通过溅射的方式形成所述发射极金属8，并通过光刻、刻蚀工艺选择性地刻蚀去部分金属，当然也可以通过其他方式形成发射极金属8，比如通过淀积金属的方式。
步骤190，如图9所示，在第一主电极金属8和场氧化层13上淀积钝化层9。具体为，通过化学气相淀积的方式，在第一主电极金属8和场氧化层13上淀积用于保护芯片表面不受外界离子玷污的钝化层9，并通过光刻、刻蚀工艺，刻蚀出用于引出栅电极4和发射极8的PAD（焊盘）区域（未示出）。
步骤210，通过背面减薄工艺，将N-型半导体衬底1的厚底减薄。具体为，从N-型半导体衬底1的第二主面起研磨该半导体衬底1，使其符合规定的厚度要求。
步骤220，如图10所示，从减薄后的N-型半导体衬底1的第二主面起朝向半导体衬底1内选择性地进行P型杂质注入以形成P型的第二半导体层（或称P+集电极层）11，其中在终端保护区200的第二主面处只形成有连续的第二半导体层，在有源区100的第二主面处间隔地形成有第二半导体层。
步骤230，如图11所示，从N-型半导体衬底1的有源区的第二主面1S2起朝向半导体衬底1内通过光刻工艺选择性地注入N型杂质以形成与所述第二半导体层11相互间隔地N型的第一半导体层（在此为N+阴极层）10。
步骤240，如图12所示，通过低温退火激活第一半导体层10和第二半导体层11，并在所述第一半导体层10和第二半导体层11上形成一定厚度的金属层(比如Al-Ti-Ni-Ag)12，此金属层12即为IGBT用第二主电极。
这样就可以制造出图1中的具有内置二极管的IGBT。普通领域内的技术人员根据上述制造方法的精神，还可以对其进行各种各样的改变或替换。比如，在一个改变的实施例中，也可以先在所述第一半导体层10和第二半导体层11上形成金属层12，然后再激活第一半导体层10和第二半导体层11。步骤140至步骤180为在N-型半导体衬底1的有源区的第一主面形成绝缘栅型晶体管的过程，因此，假如绝缘栅型晶体管为其他类型的MOSFET，那么相应的制造步骤也需要相应地改变。此外，在另一个改变的实施例中，也可以调换形成P+集电极层11和N+阴极层10的形成顺序，即可以首先在N-型的半导体衬底1的有源区的第二主面侧形成N+阴极层10；然后再在N-型的半导体衬底1的第二主面侧1S2形成与N+阴极层10相互间隔地P+集电极层11。
在上述实施例中，以所述第一导电类型为N型，所述第二导电类型为P型为例进行介绍，在其他改变的实施例中，也可以使得第一导电类型为P型，所述第二导电类型为N型，此时采用P-型的半导体衬底1，所述绝缘栅型晶体管为P沟道的MOSFET单元，第二主电极12为发射极，第一主电极8为集电极，具体结构和原理与上文的中IGBT相似，这里不在赘述。
综上所述，上述具有内置二极管的IGBT及其制造方法，在所述半导体衬底1的有源区100的第二主面侧相互间隔地形成有第一导电类型的第一半导体层10和第二导电类型的第二半导体层11，而在所述半导体衬底1的终端保护区200的第二主面侧仅形成有第二半导体层11，这样，可以减少当内置二极管反向恢复时，存储于该终端保护区下方的半导体衬底内的载流子数量，从而可以很好的优化内置二极管的反向恢复特性，同时又能很好的保证IGBT的特性不受影响。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种具有内置二极管的IGBT，包括：
    具有第一主面和第二主面的第一导电类型的半导体衬底，其中，所述半导体衬底包括有源区和所述有源区外侧的终端保护区；
    形成于所述有源区的第一主面侧的绝缘栅型晶体管单元，在其导通时其形成有第一导电类型的沟道；
    相互间隔地形成于所述半导体衬底的第二主面侧的有源区的第一导电类型的第一半导体层和第二导电类型的第二半导体层；
    其特征在于：所述具有内置二极管的IGBT在所述半导体衬底的第二主面侧的所述终端保护区仅包括第二半导体层。
  2. 根据权利要求1所述的具有内置二极管的IGBT，其特征在于，其还包括：在所述终端保护区的第一主面侧形成的保护终端；
    在形成有绝缘栅型晶体管单元的第一导电类型的半导体衬底的第一主面上形成的IGBT用第一主电极；
    在所述第一半导体层和第二半导体层上形成的IGBT用第二主电极。
  3. 根据权利要求2所述的具有内置二极管的IGBT，其特征在于，所述保护终端为场限环终端结构。
  4. 根据权利要求2所述的具有内置二极管的IGBT，其特征在于，所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，
    所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型的半导体衬底，所述第一半导体层为N+型阴极层，所述第二半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极。
  5. 根据权利要求4所述的具有内置二极管的IGBT，其特征在于，所述N型沟道MOSFET单元包括：
    自所述有源区中的第一主面向所述N-型半导体衬底内有选择地形成的P阱；
    自所述P阱的表面向该P阱内有选择地形成的N+有源区；
    在所述有源区的第一主面上有选择地形成的栅氧化层，其中，所述栅氧化层位于P阱的边缘部分的第一主面和所述有源区的未形成P阱的第一主面上；
    在所述栅极氧化层的上表面上形成的多晶硅栅电极；
    覆盖所述栅极氧化层和多晶硅栅电极露出表面的介质层，
    其中，第一主电极形成于所述介质层的外侧并与所述N+有源区和所述P阱电性接触。
  6. 一种具有内置二极管的IGBT的制造方法，包括：
    提供具有第一主面和第二主面的第一导电类型的半导体衬底，所述半导体衬底包括有源区和所述有源区外侧的终端保护区；
    在所述半导体衬底的有源区的第一主面侧形成绝缘栅型晶体管单元；
    从所述半导体衬底的第二主面起减薄该绝缘栅型晶体管单元形成后的半导体衬底；
    自减薄后的半导体衬底的第二主面向所述半导体衬底内形成第一导电类型的第一半导体层和第二导电类型的第二半导体层，所述第一半导体层和第二半导体层相互间隔地形成于所述第二主面侧的所述有源区；在所述第二主面侧的所述终端保护区仅形成所述第二半导体层。
  7. 根据权利要求6所述的具有内置二极管的IGBT的制造方法，其特征在于，还包括：
    在所述终端保护区的第一主面侧形成保护终端；
    在形成绝缘栅型晶体管单元的所述半导体衬底的第一主面上形成IGBT用第一主电极；
    在所述第一半导体层和第二半导体层形成后的半导体衬底的第二主面上形成与第一半导体层和第二半导体层接触的IGBT用第二主电极。
  8. 根据权利要求6或者7所述的具有内置二极管的IGBT的制造方法，其特征在于，
    在形成第一半导体层和第二半导体层时，先形成第一半导体层，后形成第二半导体层；或者
    在形成第一半导体层和第二半导体层时，先形成第二半导体层，后形成第一半导体层。
  9. 根据权利要求6或者7所述的具有内置二极管的IGBT的制造方法，其特征在于，所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，
    所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型的半导体衬底，所述第一半导体层为N+型阴极层，所述第二半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极。
  10. 根据权利要求9所述的具有内置二极管的IGBT的制造方法，其特征在于，所述在所述半导体衬底的有源区的第一主面侧形成绝缘栅型晶体管单元包括：
    在N-型半导体衬底的第一主面上生成场氧化层，并刻蚀出所述有源区的区域；
    在所述有源区的第一主面上生成栅氧层，并在所述栅氧层上淀积多晶硅栅极；
    选择性地刻蚀栅氧层和多晶硅栅极以刻蚀P阱的注入窗口，并沿刻蚀出的该P阱窗口向N-型半导体衬底内形成P阱；
    选择性地自所述P阱表面向所述N-型半导体衬底内形成N+有源区；
    在有源区的第一主面上淀积介质层，并刻蚀出短接N+有源区和所述P阱的接触孔，其中第一主电极形成于所述介质层的外侧并与所述N+有源区和所述P阱电性接触。
PCT/CN2014/079460 2013-06-28 2014-06-09 具有内置二极管的igbt及其制造方法 WO2014206196A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP14817399.0A EP3016142A4 (en) 2013-06-28 2014-06-09 IGBT WITH INCORPORATED DIODE AND METHOD FOR MANUFACTURING SAME
US14/901,622 US9595520B2 (en) 2013-06-28 2014-06-09 IGBT with built-in diode and manufacturing method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310273099.8 2013-06-28
CN201310273099.8A CN104253154A (zh) 2013-06-28 2013-06-28 一种具有内置二极管的igbt及其制造方法

Publications (1)

Publication Number Publication Date
WO2014206196A1 true WO2014206196A1 (zh) 2014-12-31

Family

ID=52141019

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/079460 WO2014206196A1 (zh) 2013-06-28 2014-06-09 具有内置二极管的igbt及其制造方法

Country Status (4)

Country Link
US (1) US9595520B2 (zh)
EP (1) EP3016142A4 (zh)
CN (1) CN104253154A (zh)
WO (1) WO2014206196A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017175426A1 (ja) * 2016-04-06 2017-10-12 三菱電機株式会社 電力用半導体装置
JP6830767B2 (ja) * 2016-06-14 2021-02-17 株式会社デンソー 半導体装置
JP7158317B2 (ja) * 2019-03-07 2022-10-21 三菱電機株式会社 半導体装置
US11222858B1 (en) * 2020-06-19 2022-01-11 Alpha And Omega Semiconductor International Lp Semiconductor package having enlarged gate pad and method of making the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101170109A (zh) * 2006-10-27 2008-04-30 三菱电机株式会社 半导体装置及其制造方法
CN101330103A (zh) * 2003-08-27 2008-12-24 三菱电机株式会社 绝缘栅型晶体管以及逆变器电路
CN101764139A (zh) * 2008-12-24 2010-06-30 株式会社电装 包括绝缘栅极双极晶体管和二极管的半导体器件
CN102822968A (zh) * 2010-04-02 2012-12-12 丰田自动车株式会社 具备具有二极管区和绝缘栅双极性晶体管区的半导体基板的半导体装置
CN202796960U (zh) * 2012-07-12 2013-03-13 宁波比亚迪半导体有限公司 一种具有内置二极管的igbt结构

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970054363A (ko) * 1995-12-30 1997-07-31 김광호 다이오드를 내장한 절연게이트 바이폴라 트랜지스터 및 그 제조방법
JP3907174B2 (ja) * 2002-02-26 2007-04-18 新電元工業株式会社 半導体装置
DE10324751B4 (de) * 2003-05-30 2009-01-22 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiter-Struktur mit einem Halbleitersubstrat und mit diesem Verfahren hergestellte Halbleiter-Struktur
WO2004109808A1 (ja) * 2003-06-05 2004-12-16 Mitsubishi Denki Kabushiki Kaisha 半導体装置およびその製造方法
JP5332175B2 (ja) * 2007-10-24 2013-11-06 富士電機株式会社 制御回路を備える半導体装置
US8058670B2 (en) * 2009-06-04 2011-11-15 Force—MOS Technology Corporation Insulated gate bipolar transistor (IGBT) with monolithic deep body clamp diode to prevent latch-up

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101330103A (zh) * 2003-08-27 2008-12-24 三菱电机株式会社 绝缘栅型晶体管以及逆变器电路
CN101170109A (zh) * 2006-10-27 2008-04-30 三菱电机株式会社 半导体装置及其制造方法
CN101764139A (zh) * 2008-12-24 2010-06-30 株式会社电装 包括绝缘栅极双极晶体管和二极管的半导体器件
CN102822968A (zh) * 2010-04-02 2012-12-12 丰田自动车株式会社 具备具有二极管区和绝缘栅双极性晶体管区的半导体基板的半导体装置
CN202796960U (zh) * 2012-07-12 2013-03-13 宁波比亚迪半导体有限公司 一种具有内置二极管的igbt结构

Also Published As

Publication number Publication date
EP3016142A1 (en) 2016-05-04
US20160240528A1 (en) 2016-08-18
CN104253154A (zh) 2014-12-31
US9595520B2 (en) 2017-03-14
EP3016142A4 (en) 2016-12-14

Similar Documents

Publication Publication Date Title
WO2015010606A1 (zh) 绝缘栅双极晶体管及其制造方法
CN102334190A (zh) 半导体装置及其制造方法
CN101170109A (zh) 半导体装置及其制造方法
JP2015109472A (ja) 半導体装置
WO2015010610A1 (zh) 绝缘栅双极晶体管及其制造方法
US11094790B2 (en) Silicon carbide semiconductor device
JPH06196705A (ja) 逆導通型絶縁ゲートバイポーラトランジスタ及びその製造方法
JP3727827B2 (ja) 半導体装置
CN104303285A (zh) 半导体装置以及半导体装置的制造方法
WO2014206193A1 (zh) 场截止型反向导通绝缘栅双极型晶体管及其制造方法
JP2011061064A (ja) 電力用半導体装置
WO2014206196A1 (zh) 具有内置二极管的igbt及其制造方法
WO2014206189A1 (zh) 场截止型反向导通绝缘栅双极型晶体管及其制造方法
JP6869376B2 (ja) 半導体装置
WO2014206160A1 (zh) 绝缘栅双极晶体管及其制造方法
WO2016124093A1 (zh) 横向绝缘栅双极型晶体管
JP2011258640A (ja) 半導体装置
CN103050523A (zh) 绝缘栅双极型晶体管及其制造方法
US10692995B2 (en) Insulated-gate bipolar transistor structure and method for manufacturing the same
CN114497201A (zh) 集成体继流二极管的场效应晶体管、其制备方法及功率器件
CN111370479A (zh) 沟槽栅功率器件及其制造方法
CN103872108B (zh) 一种igbt结构及其制备方法
CN104253042A (zh) 一种绝缘栅双极晶体管的制造方法
WO2015014289A1 (zh) 绝缘栅双极型晶体管的制造方法
JPH08236762A (ja) 逆阻止型半導体装置及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14817399

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2014817399

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 14901622

Country of ref document: US