WO2015043378A2 - 功率二极管的制备方法 - Google Patents

功率二极管的制备方法 Download PDF

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WO2015043378A2
WO2015043378A2 PCT/CN2014/086348 CN2014086348W WO2015043378A2 WO 2015043378 A2 WO2015043378 A2 WO 2015043378A2 CN 2014086348 W CN2014086348 W CN 2014086348W WO 2015043378 A2 WO2015043378 A2 WO 2015043378A2
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region
photoresist
ions
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PCT/CN2014/086348
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English (en)
French (fr)
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WO2015043378A3 (zh
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钟圣荣
王根毅
邓小社
周东飞
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无锡华润上华半导体有限公司
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Priority to US14/902,294 priority Critical patent/US9502534B2/en
Publication of WO2015043378A2 publication Critical patent/WO2015043378A2/zh
Publication of WO2015043378A3 publication Critical patent/WO2015043378A3/zh

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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Definitions

  • the present invention relates to the field of semiconductor fabrication technology, and in particular, to a method for fabricating a power diode.
  • the power diode is the most basic component of the power electronic circuit, and its unidirectional conductivity can be used for rectification, clamping, and freewheeling of the circuit.
  • the proper application of power diode performance is an important part of power electronic circuits.
  • devices such as junction barrier control rectifiers and MOS control diodes (MCD) have been proposed at home and abroad.
  • Metal Oxygen Half Field Effect Transistor Metal-Oxide-Semiconductor) Field-Effect Transistor, MOSFET
  • MOSFET Metal Oxygen Half Field Effect Transistor
  • a method of fabricating a power diode comprising: providing a substrate having a front side and a back side opposite to the front surface, an N-type layer grown on a front side of the substrate, the N-type layer having a first surface facing away from the substrate; The first surface of the layer forms a termination protection ring; an oxide layer is formed on the first surface of the N-type layer to push the termination protection ring; the active area lithography plate is used for photolithography and the oxide layer of the active region is etched away And forming a gate oxide layer on the first surface of the N-type layer in the active region; depositing a polysilicon layer on the gate oxide layer; performing photolithography with a polysilicon lithography plate, and using the photoresist as a masking layer to the N-type The layer implants P-type ions, forms a P-type body region under the polysilicon layer by ion scattering; etches the polysilicon layer with photoresist as a masking layer, and implants N-type ions
  • Forming an N-type heavily doped region using a photoresist as a masking layer, sequentially performing gate oxide etching and silicon etching, and implanting P-type ions under the etched region by ion implantation to form a P+ region; Thermal annealing, activation of implanted impurities and removal Engraved gum; and be metallized surface and the back surface of the first substrate.
  • the step of forming a termination protection ring on the first surface of the N-type layer comprises: forming a thin pad oxide layer on the first surface of the N-type layer, and performing photolithography with a termination protection ring lithography to lithography
  • the glue acts as a masking layer to inject P-type ions into the N-type layer, and a P-type termination guard ring is formed under the thin pad oxide layer.
  • the photoresist is used as a masking layer, followed by gate oxide etching and silicon etching, and injecting P-type ions under the etched region by ion implantation to form a P+ region.
  • the thickness of the silicon removed by etching is 0.15 to 0.3 ⁇ m.
  • the lithography is performed by using a polysilicon lithography plate, and a P-type ion is implanted into the N-type layer by using the photoresist as a masking layer, and a P-type body region is formed under the polysilicon layer by ion scattering, P-type
  • the ion is a boron ion; the polysilicon layer is etched by using the photoresist as a masking layer, and the N-type ion is implanted into the P-type body region below the etched region to form an N-type heavily doped region, and the N-type
  • the ions are arsenic ions; the photoresist is used as a masking layer, and gate oxide etching and silicon etching are sequentially performed, and P-type ions are implanted under the etched region by ion implantation to form a P+ region, P
  • the type ions include boron ions and BF 2 ions.
  • the photolithography is performed by using a polysilicon lithography plate, and the P-type ions are implanted into the N-type layer by using the photoresist as a masking layer, and the boron ion is formed by ion scattering under the polysilicon layer to form a P-type body region.
  • the implantation energy is 30-50 KeV, and the implantation dose is 1 ⁇ 10 13 -5 ⁇ 10 13 cm -2 ; the polysilicon layer is etched with the photoresist as a masking layer, and is in the P-type body region below the etched region.
  • the arsenic ion implantation energy is 30-50 KeV, and the implantation dose is 1 ⁇ 10 15 to 1 ⁇ 10 16 cm ⁇ 2 ; the photoresist is used as a masking layer.
  • the boron ion implantation dose is 1 ⁇ 10 13 to 5 ⁇ 10 13 cm. -2
  • the implantation energy is 80 to 100 KeV
  • the BF 2 ion implantation energy is 20 to 40 KeV
  • the implantation dose is 6 ⁇ 10 14 to 1 ⁇ 10 15 cm -2 .
  • the lithography is performed by using a polysilicon lithography plate, and a P-type ion is implanted into the N-type layer by using the photoresist as a masking layer, and a P-type body region is formed under the polysilicon layer by ion scattering, P-type
  • the ions are divided into multiple injections.
  • the push-knot is performed in an oxygen-free environment having a temperature of less than or equal to 1100 degrees Celsius, and the knotting time is 60 to 200 minutes.
  • the polysilicon layer has a thickness of 800 to 6000 angstroms.
  • the N-type layer has a thickness of 3 to 20 microns and a resistivity of 0.5 to 10 ⁇ •cm.
  • the substrate is an N-type silicon wafer having a crystal orientation of 100.
  • the above method for manufacturing the power diode simplifies the process and reduces the cost by directly forming the P-type body region as the MOS channel by scattering of the implanted ions before the polysilicon etching.
  • FIG. 1 is a flow chart showing a method of fabricating a power diode in an embodiment
  • FIG. 2 to FIG. 10 are partial cross-sectional views showing a power diode prepared by a method for preparing a power diode in an embodiment
  • FIG. 11 is a cross-sectional view showing a power diode prepared by a method for fabricating a power diode in an embodiment.
  • FIG. 1 is a flow chart of a method of fabricating a power diode in an embodiment, including the following steps:
  • S102 providing a substrate having a front side and a back side opposite to the front surface, and growing an N-type layer on the front side of the substrate, the N-type layer having a first surface facing away from the substrate.
  • the material of the substrate 10 may be a semiconductor material such as silicon, silicon carbide, gallium arsenide, indium phosphide or germanium silicon.
  • the substrate 10 is an N-type silicon wafer having a crystal orientation of ⁇ 100>.
  • the N-type layer 20 of a certain thickness and resistivity is epitaxially grown on the front surface of the substrate 10 (the side on which the front surface structure of the power diode is formed).
  • the N-type layer 20 has a thickness of 3 to 20 ⁇ m and a specific resistance of 0.5 to 10 ⁇ •cm.
  • the thickness of the N-type layer 20 is set according to the power diode required to be set. In one embodiment, when the power diode is a 100V withstand voltage device, the thickness is 10 ⁇ m and the resistivity is 2 ⁇ •cm.
  • a thin pad oxide layer 30 is formed on the first surface of the N-type layer, and then photolithography is performed using a termination ring (Rear) lithography plate, and the P-type ions are implanted into the N-type layer by using the photoresist 40 as a masking layer.
  • a P-type termination protection ring is formed under the thin pad oxide layer 30 (P Ring).
  • Three termination guard rings 31, 32 and 33 are shown in Fig. 2, wherein the termination guard ring 31 is in the active area area and the termination guard ring 32 is partially located in the active area area.
  • the number of terminal protection rings is not limited to the number of terminal protection rings in this embodiment, and may be selected and set according to actual needs of the device.
  • the implanted P-type ions 301 are boron ions, the implantation energy is 50 to 80 KeV, and the dose is 1 ⁇ 10 13 to 1 ⁇ 10 14 cm -2 . In other embodiments, other P-type ions may be substituted.
  • FIG. 2 is a partial cross-sectional view showing the power diode after step S104 is completed.
  • FIG. 3 is a partial cross-sectional view of the power diode after step S106 is completed.
  • the push-knot process is an oxygen-free environment, the temperature is less than or equal to 1100 ° C, and the time is 60 to 200 minutes.
  • the formation of the oxide layer 50 and the push-knot process in this step can be combined into an aerobic push-knot process.
  • An active area etch is performed using an active area reticle (active lithography plate) in a region where the device is to be fabricated. After the oxide layer 50 of the active region region is etched away, the photoresist is removed and thermally grown to form the gate oxide layer 60. In the present embodiment, the gate oxide layer 60 has a thickness of 20 to 100 angstroms. 4 is a partial cross-sectional view of the power diode after step S108 is completed.
  • a polysilicon layer 70 is deposited over the gate oxide layer 60.
  • the polysilicon layer 70 is in-situ doped polysilicon and has a thickness of 800 to 6000 angstroms.
  • the impurity distribution of the doped region can be adjusted to achieve the purpose of reducing the forward voltage drop Vf of the device.
  • FIG. 5 is a partial cross-sectional view showing the power diode after step S110 is completed.
  • Photolithography is performed using a polycrystalline silicon (poly) lithography plate, and P-type ions are implanted into the N-type layer using the photoresist 40 as a masking layer to form a P-type body region (P body) 82.
  • the P-type ions are implanted in multiple passes, and the P-type body regions 82 are formed as MOS channels directly by lateral scattering of the implanted ions.
  • the implanted P-type ions are boron ions, which are implanted in four times, and the implantation energy is 30 to 50 KeV, and the total dose is 1 ⁇ 10 13 to 5 ⁇ 10 13 cm ⁇ 2 .
  • FIG. 6 is a partial cross-sectional view showing the power diode after step S112 is completed.
  • the P-type body region 82 As a MOS channel by lateral scattering directly using ion implantation before polysilicon etching, the flow is simplified and the cost is reduced.
  • the threshold voltage of the DMOS structure is adjusted by adjusting the thickness of the polysilicon layer 70 and the energy of the implanted ions, thereby adjusting the forward voltage drop of the diode according to the actual application.
  • good impurity distribution can be obtained by multiple injections, reducing the reverse recovery time of the device and improving the switching performance of the device.
  • the polysilicon layer 70 is etched using the photoresist 40 as a masking layer, and N-type ions are implanted into the P-type body region 82 under the etched region to form an N-type heavily doped region (NSD) 84.
  • the implanted N-type ions are arsenic ions, the implantation energy is 30 to 50 KeV, and the dose is 1 ⁇ 10 15 to 1 ⁇ 10 16 cm -2 .
  • FIG. 7 is a partial cross-sectional view showing the power diode after step S114 is completed.
  • the polysilicon photoresist 40 is used as a masking layer, and the gate oxide layer 60 is etched and silicon etched successively, and P-type ions are implanted under the etched region to form a deep P+ region 86.
  • the thickness of the silicon removed by etching is 0.15-0.3 micrometers, forming a shallow trench structure to obtain better impurity fraction and larger metal contact area, and improve The performance of the device.
  • the implanted P-type ions include boron ions and BF 2 ions.
  • the boron ions are injected in multiple times, and the implantation energy is 80-100 KeV, and the total dose is 1 ⁇ 10 13 to 5 ⁇ 10 13 cm -2 .
  • the BF 2 ion implantation energy is 20 to 40 KeV, and the dose is 6 ⁇ 10 14 to 1 ⁇ 10 15 cm -2 . Multiple injections can achieve good impurity distribution, reduce the reverse recovery time of the device, and improve the switching performance of the device.
  • FIG. 8 is a partial cross-sectional view showing the power diode after step S114 is completed.
  • the three doped layers of the P-type body region 82, the N-type heavily doped region 84, and the P+ region 86 are subjected to rapid thermal annealing to activate the implanted impurities and remove the photoresist 40. Impurity activation of the above three doped layers is accomplished by only one thermal annealing process, which simplifies the process and reduces cost without affecting product performance. In other embodiments, a rapid thermal process may also be performed after each injection.
  • FIG. 9 is a partial cross-sectional view showing the power diode after step S116 is completed.
  • An oxide layer is etched successively over the entire surface of the device to sputter the conductive metal.
  • the conductive metal is etched with a metal lithography plate to form a metal wiring layer 92 to complete the first surface metallization process.
  • the back surface of the substrate 10 is thinned to a desired thickness, and the back surface of the substrate 10 is sputtered with a conductive metal to form a back metal wiring layer 94 to complete the back metallization process.
  • the sputtered metal includes aluminum, titanium, nickel, silver, copper, and the like.
  • FIG. 10 is a partial cross-sectional view showing the power diode after step S120 is completed.
  • lithography plates which are a terminal protection ring lithography plate, an active area lithography plate, a polysilicon lithography plate and a metal lithography plate, which saves a lithography plate compared with the conventional preparation process, simplifies the process and reduces The cost.
  • Method for preparing the above power diode and double-diffused metal oxide semiconductor field effect transistor (Double-diffused The MOSFET, DMOS) process is fully compatible, with universality and portability of different IC production lines.
  • a good impurity distribution can be obtained by injecting P-type ions into the plurality of steps in steps S112 and S116, the reverse recovery time of the device is reduced, and the switching performance of the device is improved.
  • the P-type body region 82 as a MOS channel by lateral scattering directly using ion implantation before polysilicon etching, the flow is simplified and the cost is reduced. And does not affect the performance of the product.
  • FIG. 11 is a cross-sectional view of a power diode prepared by a method of fabricating a power diode in an embodiment, including a peripheral termination structure (not shown in FIG. 11) and an active region surrounded by the termination structure.
  • the substrate of the power diode is an N-type substrate 10, and the back surface of the substrate 10 is provided with a back metal wiring layer 94.
  • An N-type epitaxial layer 20 is provided on the front surface of the substrate 10.
  • a terminal protection ring (not shown in FIG. 11) is disposed in the terminal structure.
  • the front surface of the epitaxial layer 20 of the active region (the surface in the same direction as the substrate 10) is provided with a gate oxide layer 60, and the front surface of the gate oxide layer 60 (the surface facing the substrate 10) is provided with a polysilicon layer 70.
  • a P-type body region is provided in the epitaxial layer 20 of the active region (P In the body 82, an N-type heavily doped region 84 is provided in the P-type body region 82.
  • a P+ region 86 is provided below the P-type body region 82.
  • a front metal wiring layer 92 is provided on the front surface of the entire device (the surface in the same direction as the substrate 10).
  • the power diode has excellent performances such as low turn-on voltage, short reverse recovery time, low leakage current and high reliability. It can be widely used in AC-DC converters, UPS uninterruptible power supplies, automotive electronics, portable electronics, motor drive systems and Other energy conversion devices.

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Abstract

一种功率二极管的制备方法，包括：提供衬底（10），衬底（10）具有正面及与正面相对的背面，在衬底（10）的正面生长N型层（20），N型层（20）具有背离衬底（10）的第一表面；形成终端保护环（31、32、33）；形成氧化层（50），对终端保护环（31、32、33）进行推结；用有源区光刻板进行光刻并刻蚀掉有源区区域的氧化层（50），并在有源区区域的N型层（20）的第一表面形成栅氧化层（60）；在栅氧化层（60）上淀积形成多晶硅层（70）；用多晶硅光刻板进行光刻，并以光刻胶（40）为掩蔽层向N型层（20）注入P型离子，通过离子散射在多晶硅层（70）下方形成P型体区（82）；形成N型重掺杂区；形成P+区；进行热退火，激活注入的杂质并去除光刻胶（40）；及在第一表面和衬底（10）的背面进行金属化处理。

Description

功率二极管的制备方法
【技术领域】
本发明涉及半导体制备技术领域，特别是涉及一种功率二极管的制备方法。
【背景技术】
功率二极管是电力电子电路最基本的组成单元，它的单向导电性可用于电路的整流、箝位、续流。合理应用功率二极管的性能是电力电子电路的重要内容。为提高二极管的性能，目前国内外已经提出了结势垒控制整流器、MOS控制二极管（MCD）等器件。金氧半场效晶体管（Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET）是一种发展迅速、应用广泛的电力电子器件，它是利用垂直双扩散金属氧化物半导体场效应管开关速度快、电流密度大的优点优化的新器件，具有低正向压降、短反向恢复时间和低漏电流等特点。然而，针对这种MOSFET结构，传统的制备方法流程较为复杂、制备成本较高。
【发明内容】
基于此，有必要提供一种流程简便且制备成本低的功率二极管的制备方法。
一种功率二极管的制备方法，包括：提供衬底，衬底具有正面及与正面相对的背面，在衬底的正面生长N型层，N型层具有背离衬底的第一表面；在N型层的第一表面形成终端保护环；在N型层的第一表面形成氧化层，对终端保护环进行推结；用有源区光刻板进行光刻并刻蚀掉有源区区域的氧化层，并在有源区区域的N型层的第一表面形成栅氧化层；在栅氧化层上淀积形成多晶硅层；用多晶硅光刻板进行光刻，并以光刻胶为掩蔽层向N型层注入P型离子，通过离子散射在多晶硅层下方形成P型体区；以光刻胶作为掩蔽层刻蚀多晶硅层，并向被刻蚀开的区域下面的P型体区内注入N型离子，形成N型重掺杂区；以光刻胶作为掩蔽层，先后进行栅氧化层刻蚀和硅刻蚀，并通过离子注入向被刻蚀开的区域下方注入P型离子，形成P+区；进行热退火，激活注入的杂质并去除光刻胶；及在第一表面和衬底的背面进行金属化处理。
在其中一个实施例中，在N型层的第一表面形成终端保护环的步骤包括：在N型层的第一表面形成薄垫氧化层，用终端保护环光刻板进行光刻，以光刻胶作为掩蔽层向N型层注入P型离子，在薄垫氧化层下方形成P型终端保护环。
在其中一个实施例中，以光刻胶作为掩蔽层，先后进行栅氧化层刻蚀和硅刻蚀，并通过离子注入向被刻蚀开的区域下方注入P型离子，形成P+区的步骤中，被刻蚀去除的硅厚度为0.15～0.3微米。
在其中一个实施例中，用多晶硅光刻板进行光刻，并以光刻胶为掩蔽层向N型层注入P型离子，通过离子散射在多晶硅层下方形成P型体区的步骤中，P型离子为硼离子；以光刻胶作为掩蔽层刻蚀多晶硅层，并向被刻蚀开的区域下面的P型体区内注入N型离子，形成N型重掺杂区的步骤中，N型离子为砷离子；以光刻胶作为掩蔽层，先后进行栅氧化层刻蚀和硅刻蚀，并通过离子注入向被刻蚀开的区域下方注入P型离子，形成P+区的步骤中，P型离子包括硼离子和BF2离子。
在其中一个实施例中，用多晶硅光刻板进行光刻，并以光刻胶为掩蔽层向N型层注入P型离子，通过离子散射在多晶硅层下方形成P型体区的步骤中，硼离子注入能量为30～50KeV，注入剂量为1×1013～5×1013㎝-2；以光刻胶作为掩蔽层刻蚀多晶硅层，并向被刻蚀开的区域下面的P型体区内注入N型离子，形成N型重掺杂区的步骤中，砷离子注入能量为30～50KeV，注入剂量为1×1015～1×1016㎝-2；以光刻胶作为掩蔽层，先后进行栅氧化层刻蚀和硅刻蚀，并通过离子注入向被刻蚀开的区域下方注入P型离子，形成P+区的步骤中，硼离子注入剂量为1×1013～5×1013㎝-2，注入能量为80～100KeV，BF2离子注入能量为20～40KeV，注入剂量为6×1014～1×1015㎝-2。
在其中一个实施例中，用多晶硅光刻板进行光刻，并以光刻胶为掩蔽层向N型层注入P型离子，通过离子散射在多晶硅层下方形成P型体区的步骤中，P型离子分为多次进行注入。
在其中一个实施例中，推结在温度小于或等于1100摄氏度的无氧环境下进行，且推结时间为60～200分钟。
在其中一个实施例中，多晶硅层的厚度为800～6000埃。
在其中一个实施例中，N型层的厚度为3～20微米，电阻率为0.5～10Ω•cm。
在其中一个实施例中，衬底是晶向为100的N型硅片。
上述功率二极管的制备方法，通过在多晶硅刻蚀之前，直接利用注入离子的散射形成P型体区作为MOS沟道，简化了流程并降低了成本。
【附图说明】
图1为一实施例中功率二极管的制备方法的流程图；
图2～图10为一实施例中采用功率二极管的制备方法制备的功率二极管在制备过程中的局部剖面示意图；
图11为一实施例中采用功率二极管的制备方法制备的功率二极管的剖面示意图。
【具体实施方式】
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
图1为一实施例中功率二极管的制备方法的流程图，包括下列步骤：
S102，提供衬底，衬底具有正面及与正面相对的背面，在衬底的正面生长N型层，N型层具有背离衬底的第一表面。
衬底10的材质可以为硅、碳化硅、砷化镓、磷化铟或者锗硅等半导体材料。在本实施例中，衬底10为晶向<100>的N型硅片。
在本实施例中，在衬底10的正面（形成功率二极管的正面结构的一面）外延生长一定厚度以及电阻率的N型层20。N型层20的厚度为3～20μm，电阻率为0.5～10Ω•cm。N型层20的厚度根据需要制备的功率二极管对耐压需求进行设定，在一个实施例中，当功率二极管为100V耐压的器件时，其厚度为10μm，电阻率为2Ω•cm。
S104，在N型层的第一表面形成终端保护环。
具体地，在N型层的第一表面生成薄垫氧化层30，然后采用终端保护环（ring）光刻板进行光刻，以光刻胶40为掩蔽层向N型层注入P型离子，在薄垫氧化层30的下方形成P型终端保护环（P ring）。图2中示出了三个终端保护环31、32以及33，其中终端保护环31处于有源区区域，终端保护环32部分位于有源区区域。在其他的实施例中，终端保护环的数量并不限于本实施例的终端保护环的数量，可以根据器件实际需要进行选择和设置。
在本实施例中，注入的P型离子301为硼离子，注入能量为50～80KeV，剂量为1×1013～1×1014㎝-2。在其他的实施例中，也可以用其他的P型离子进行替代。图2为完成步骤S104后的功率二极管的局部剖面示意图。
S106，在N型层的第一表面形成氧化层，对终端保护环进行推结。
去除光刻胶40后，在N型层20的第一表面淀积厚度为1000～5000埃的氧化层50，并对P型终端保护环进行推结。图3为完成步骤S106后的功率二极管的局部剖面示意图。在本实施例中，推结过程为无氧环境，温度小于或等于1100℃，时间为60～200分钟。为节约成本，在其它实施例中，可以将本步骤中形成氧化层50和推结过程结合为有氧推结热过程。
S108，用有源区光刻板进行光刻并刻蚀掉有源区区域的氧化层，并在有源区区域的N型层的第一表面形成栅氧化层。
在需要制备器件的区域采用有源区光刻板（active光刻板）进行有源区刻蚀。刻蚀掉有源区区域的氧化层50后，去除光刻胶，热生长形成栅氧化层60。在本实施例中，栅氧化层60的厚度为20～100埃。图4为完成步骤S108后的功率二极管的局部剖面示意图。
S110，在栅氧化层上淀积形成多晶硅层。
在栅氧化层60上淀积形成多晶硅层70。在本实施例中，多晶硅层70为原位掺杂多晶硅，厚度为800～6000埃。通过对多晶硅层70厚度的调节，可以对掺杂区的杂质分布进行调节，从而达到降低器件正向压降Vf的目的。图5为完成步骤S110后的功率二极管的局部剖面示意图。
S112，用多晶硅光刻板进行光刻，并以光刻胶为掩蔽层向N型层注入P型离子，通过离子散射在多晶硅层下方形成P型体区。
用多晶硅（poly）光刻板进行光刻，以光刻胶40为掩蔽层向N型层注入P型离子，形成P型体区（P body）82。在本实施例中，P型离子是分多次进行注入的，并直接通过注入离子的横向散射形成P型体区82作为MOS沟道。具体地，注入的P型离子为硼离子，分4次注入，注入能量为30～50KeV，总剂量为1×1013～5×1013㎝-2。图6为完成步骤S112后的功率二极管的局部剖面示意图。
通过在多晶硅刻蚀之前，直接利用离子注入的横向散射形成P型体区82作为MOS沟道，简化了流程并降低了成本。同时，通过调节多晶硅层70的厚度以及注入离子的能量，来调节DMOS结构的阈值电压，从而实现了根据实际应用情况对二极管正向导通压降进行调节。此外，通过分多次注入可以获得良好的杂质分布，减小器件的反向恢复时间，提高器件的开关性能。
S114，以光刻胶为掩蔽层刻蚀多晶硅层，并向被刻蚀开的区域下面的P型体区内注入N型离子，形成N型重掺杂区。
以光刻胶40作为掩蔽层对多晶硅层70进行刻蚀，并在被刻蚀开的区域下面的P型体区82内注入N型离子，形成N型重掺杂区（NSD）84。在本实施例中，注入的N型离子为砷离子，注入能量为30～50KeV，剂量为1×1015～1×1016㎝-2。图7为完成步骤S114后的功率二极管的局部剖面示意图。
S116，以光刻胶为掩蔽层，先后进行栅氧化层刻蚀和硅刻蚀，并向被刻蚀开的区域下方注入P型离子，形成P+区。
以多晶硅光刻胶40作为掩蔽层，先后进行栅氧化层60的刻蚀和硅刻蚀，并向被刻蚀开的区域下方注入P型离子形成深P+区86。
在本实施例中，在进行硅刻蚀过程中，被刻蚀去除的硅的厚度为0.15～0.3微米，形成一个浅槽结构，以获得较好的杂质分和更大的金属接触面积，提高器件的性能。注入的P型离子包括硼离子和BF2离子。硼离子分多次注入，注入能量为80～100KeV，总剂量为1×1013～5×1013㎝-2。BF2离子注入能量为20～40KeV，剂量为6×1014～1×1015㎝-2。分多次注入可以获得良好的杂质分布，减小器件的反向恢复时间，提高器件的开关性能。图8为完成步骤S114后的功率二极管的局部剖面示意图。
S118，进行热退火，激活注入的杂质并去除光刻胶。
在本实施例中，对P型体区82、N型重掺杂区84和P+区86这三个掺杂层进行快速热退火，激活注入的杂质并去除光刻胶40。仅通过一次热退火过程完成上述三个掺杂层的杂质激活，简化了流程，并降低成本，同时不影响产品性能。在其他的实施例中，也可以在每次注入后进行一次快速热处理。图9为完成步骤S116后的功率二极管的局部剖面示意图。
S120，在第一表面和衬底的背面进行金属化处理。
在器件的整个表面先后进行氧化层刻蚀，溅射导电金属。用金属（metal）光刻板刻蚀该导电金属，形成金属引线层92，完成第一表面金属化过程。
将衬底10的背面减薄至所需要的厚度，对衬底10背面进行溅射导电金属形成背面金属引线层94，完成背面金属化过程。在进行第一表面金属化和背面金属化过程中，溅射的金属包括铝、钛、镍、银、铜等。图10为完成步骤S120后的功率二极管的局部剖面示意图。
上述制备过程中仅采用了4张光刻板，分别是终端保护环光刻板、有源区光刻板、多晶硅光刻板以及金属光刻板，比传统的制备过程省了一道光刻板，简化了流程且降低了成本。上述功率二极管的制备方法与双扩散金属氧化物半导体场效应管（Double-diffused MOSFET，DMOS）工艺完全兼容，具有普适性和不同IC生产线可移植性好等优点。
上述功率二极管的制备方法，通过步骤S112和S116中分多次注入P型离子可以获得良好的杂质分布，减小器件的反向恢复时间，提高器件的开关性能。通过在多晶硅刻蚀之前，直接利用离子注入的横向散射形成P型体区82作为MOS沟道，简化了流程并降低了成本。并且不影响产品的性能。
图11为一实施例中功率二极管的制备方法制备得到的功率二极管的剖面示意图，包括外围的终端结构（图11未示）和被终端结构包围的有源区。功率二极管的衬底为N型衬底10，衬底10的背面设背面金属引线层94。衬底10的正面设有N型的外延层20。终端结构内设有终端保护环（图11未示）。有源区的外延层20的正面（与衬底10同向的面）设有栅氧化层60，在栅氧化层60的正面（与衬底10同向的面）设有多晶硅层70。有源区的外延层20内设有P型体区（P body）82，P型体区82内设有N型重掺杂区84。在P型体区82的下方设有P+区86。在整个器件的正面（与衬底10同向的面）设有正面金属引线层92。
该功率二极管具有开启电压低、反向恢复时间短、漏电流小以及高可靠性等优越性能，可以广泛应用于AC-DC转换器、UPS不间断电源、汽车电子、便携电子、马达传动系统及其他能量转换装置。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种功率二极管的制备方法，包括以下步骤：
    提供衬底，所述衬底具有正面及与所述正面相对的背面，在所述衬底的正面生长N型层，所述N型层具有背离所述衬底的第一表面；
    在所述N型层的第一表面形成终端保护环；
    在所述N型层的第一表面形成氧化层，对所述终端保护环进行推结；
    用有源区光刻板进行光刻并刻蚀掉有源区区域的所述氧化层，并在所述有源区区域的所述N型层的第一表面形成栅氧化层；
    在所述栅氧化层上淀积形成多晶硅层；
    用多晶硅光刻板进行光刻，并以光刻胶为掩蔽层向所述N型层注入P型离子，通过离子散射在所述多晶硅层下方形成P型体区；
    以所述光刻胶作为掩蔽层刻蚀所述多晶硅层，并向被刻蚀开的区域下面的P型体区内注入N型离子，形成N型重掺杂区；
    以所述光刻胶作为掩蔽层，先后进行栅氧化层刻蚀和硅刻蚀，并通过离子注入向被刻蚀开的区域下方注入P型离子，形成P+区；
    进行热退火，激活注入的杂质并去除所述光刻胶；及
    在所述第一表面和所述衬底的背面进行金属化处理。
  2. 根据权利要求1所述的功率二极管的制备方法，其特征在于，所述在所述N型层的第一表面形成终端保护环的步骤包括：
    在所述N型层的第一表面形成薄垫氧化层，用终端保护环光刻板进行光刻，以光刻胶作为掩蔽层向所述N型层注入P型离子，在所述薄垫氧化层下方形成P型终端保护环。
  3. 根据权利要求1所述的功率二极管的制备方法，其特征在于，所述以所述光刻胶作为掩蔽层，先后进行栅氧化层刻蚀和硅刻蚀，并通过离子注入向被刻蚀开的区域下方注入P型离子，形成P+区的步骤中，被刻蚀去除的硅厚度为0.15～0.3微米。
  4. 根据权利要求1所述的功率二极管的制备方法，其特征在于，所述用多晶硅光刻板进行光刻，并以光刻胶为掩蔽层向所述N型层注入P型离子，通过离子散射在所述多晶硅层下方形成P型体区的步骤中，所述P型离子为硼离子；所述以所述光刻胶作为掩蔽层刻蚀所述多晶硅层，并向被刻蚀开的区域下面的P型体区内注入N型离子，形成N型重掺杂区的步骤中，所述N型离子为砷离子；所述以所述光刻胶作为掩蔽层，先后进行栅氧化层刻蚀和硅刻蚀，并通过离子注入向被刻蚀开的区域下方注入P型离子，形成P+区的步骤中，所述P型离子包括硼离子和BF2离子。
  5. 根据权利要求4所述的功率二极管的制备方法，其特征在于，所述用多晶硅光刻板进行光刻，并以光刻胶为掩蔽层向所述N型层注入P型离子，通过离子散射在所述多晶硅层下方形成P型体区的步骤中，所述硼离子注入能量为30～50KeV，注入剂量为1×1013～5×1013㎝-2；所述以所述光刻胶作为掩蔽层刻蚀所述多晶硅层，并向被刻蚀开的区域下面的P型体区内注入N型离子，形成N型重掺杂区的步骤中，所述砷离子注入能量为30～50KeV，注入剂量为1×1015～1×1016㎝-2；所述以所述光刻胶作为掩蔽层，先后进行栅氧化层刻蚀和硅刻蚀，并通过离子注入向被刻蚀开的区域下方注入P型离子，形成P+区的步骤中，所述硼离子注入剂量为1×1013～5×1013㎝-2，注入能量为80～100KeV，所述BF2离子注入能量为20～40KeV，注入剂量为6×1014～1×1015㎝-2。
  6. 根据权利要求1所述的功率二极管的制备方法，其特征在于，所述用多晶硅光刻板进行光刻，并以光刻胶为掩蔽层向所述N型层注入P型离子，通过离子散射在所述多晶硅层下方形成P型体区的步骤中，所述P型离子分为多次进行注入。
  7. 根据权利要求1所述的功率二极管的制备方法，其特征在于，所述推结在温度小于或等于1100摄氏度的无氧环境下进行，且推结时间为60～200分钟。
  8. 根据权利要求1所述的功率二极管的制备方法，其特征在于，所述多晶硅层的厚度为800～6000埃。
  9. 根据权利要求1所述的功率二极管的制备方法，其特征在于，所述N型层的厚度为3～20微米，电阻率为0.5～10Ω。
  10. 根据权利要求1所述的功率二极管的制备方法，其特征在于，所述衬底是晶向为100的N型硅片。
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