CN103943548A - 分立式场氧结构的半导体器件的制造方法 - Google Patents
分立式场氧结构的半导体器件的制造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 56
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims abstract description 30
- 210000003323 beak Anatomy 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims description 23
- 238000007254 oxidation reaction Methods 0.000 claims description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 238000002513 implantation Methods 0.000 claims description 13
- 238000004140 cleaning Methods 0.000 claims description 10
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 abstract description 6
- 230000008021 deposition Effects 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 abstract 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 12
- 229910052760 oxygen Inorganic materials 0.000 description 12
- 239000001301 oxygen Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000004224 protection Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000035755 proliferation Effects 0.000 description 2
- 238000002791 soaking Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
本发明公开了一种分立式场氧结构的半导体器件的制造方法,包括:在晶圆表面生长缓冲氧化层;在缓冲氧化层上通过淀积形成氮化硅层;光刻定义出场区并蚀刻,去除场区上的氮化硅;对场区进行离子注入;生长场氧化层;剥除氮化硅层;对晶圆进行湿浸,去除缓冲氧化层和部分的场氧化层;重新在晶圆表面生长缓冲氧化层及在重新生长的缓冲氧化层上通过淀积形成氮化硅层;光刻定义出漂移区并蚀刻,去除所述漂移区上的氮化硅;对漂移区进行离子注入;生长漂移区氧化层。本发明在生长场氧化层完成后剥除氮化硅层,这时可以通过调整wet dip的量来优化场氧鸟嘴的长度,解决了场氧鸟嘴过长的问题。
Description
技术领域
本发明涉及半导体器件的组件间隔离区的制作,特别是涉及一种分立式场氧结构的半导体器件的制造方法。
背景技术
现代集成电路设计中高压横向扩散漂移区MOS管(LDMOS)器件得到广泛的应用,LDMOS的耐压是利用MOS管的漏端的漂移区,通过降低表面电场(RESURF)原理来实现。这种漂移区是借由离子注入,然后通过高温热过程扩散形成。漂移区结构通常包括一定厚度的热氧化层,通过多晶硅搭在热氧化层上,改变漂移区上表面的电势分布实现漂移区的完全耗尽,达到有限漂移区长度下最极限的耐压。
通常线宽为0.35μm以上的高压工艺采用局部场氧化(LOCOS)进行隔离,漂移区上氧化层使用叠场氧是一种LOCOS方法。通常先用光刻定义出场氧区域,生长第一步场氧。再用光刻定义出漂移区,用热氧化的方式生长漂移区氧化层,同时场氧区叠加生长而实现第二步生长。漂移区热氧化层与场氧厚度可以任意搭配,可以达到多晶场板对漂移区耗尽的较佳效果,但是场氧的鸟嘴长度得不到控制,影响有源区的面积,情况严重会导致漏电,使得良率降低。
发明内容
基于此,有必要针对传统的叠场氧方法鸟嘴区域过长的问题,提供一种能够优化场氧的鸟嘴长度的分立式场氧结构的半导体器件。
一种分立式场氧结构的半导体器件的制造方法,包括下列步骤:在晶圆表面生长缓冲氧化层;在所述缓冲氧化层上通过淀积形成氮化硅层;光刻定义出场区并蚀刻,去除所述场区上的氮化硅;对所述场区进行离子注入;进行场区氧化,生长场氧化层;剥除所述氮化硅层;对所述晶圆进行湿浸,去除所述缓冲氧化层和部分的所述场氧化层,以减小所述场氧化层的鸟嘴长度;重新在晶圆表面生长缓冲氧化层及在重新生长的缓冲氧化层上通过淀积形成氮化硅层,重新淀积的所述氮化硅层将所述场氧化层完全覆盖;光刻定义出漂移区并蚀刻,去除所述漂移区上的氮化硅;对所述漂移区进行离子注入;进行漂移区氧化,生长漂移区氧化层。
在其中一个实施例中,所述光刻定义出场区并蚀刻的步骤,是涂覆光刻胶并通过曝光和显影定义出场区,用等离子蚀刻去除场区上的氮化硅,然后做去胶清洗,所述去胶清洗在所述进行场区氧化的步骤前进行;所述光刻定义出漂移区并蚀刻的步骤,是涂覆光刻胶并通过曝光和显影定义出漂移区,用等离子蚀刻去除漂移区上的氮化硅,然后再次进行去胶清洗,所述再次去胶清洗在所述进行漂移区氧化的步骤前进行。
在其中一个实施例中,所述淀积形成氮化硅层和重新淀积形成氮化硅层的步骤,是采用低压炉管的方式进行。
在其中一个实施例中,所述进行漂移区氧化,生长漂移区氧化层的步骤后还包括剥除重新淀积的所述氮化硅层的步骤。
在其中一个实施例中,所述剥除氮化硅层的步骤是用磷酸溶液进行剥除。
在其中一个实施例中,所述缓冲氧化层和重新生长的缓冲氧化层的厚度均为150埃。
在其中一个实施例中,所述对晶圆进行湿浸,去除所述缓冲氧化层和部分的所述场氧化层的步骤中,去除的所述场氧化层的厚度为200埃。
在其中一个实施例中,所述进行场区氧化,生长场氧化层的步骤中生长的场氧化层的厚度为6000埃;所述进行漂移区氧化,生长漂移区氧化层的步骤中生长的漂移区氧化层的厚度为3000埃。
在其中一个实施例中,所述半导体器件是横向扩散金属氧化物半导体场效应管。
上述分立式场氧结构的半导体器件的制造方法,在生长场氧化层完成后剥除氮化硅层,这时可以通过调整湿浸(wet dip)的量来优化场氧鸟嘴的长度,解决了场氧鸟嘴过长的问题。
附图说明
图1为一实施例中分立式场氧结构的半导体器件的制造方法的流程图;
图2A至图2F是一实施例中采用分立式场氧结构的半导体器件的制造方法在制造过程中器件的剖面示意图。
具体实施方式
为使本发明的目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。
图1是一实施例中分立式场氧结构的半导体器件的制造方法的流程图,包括下列步骤:
S110,在晶圆表面生长缓冲氧化层(PAD oxide layer)。
可以用热氧化工艺在硅衬底的表面生长缓冲氧化层。缓冲氧化层可以减缓硅与随后淀积的氮化硅层之间的应力。缓冲氧化层越厚,硅与氮化硅之间的应力越小,但对有源区形状和尺寸的影响也越大。在本实施例中,缓冲氧化层的厚度为在其它实施例中,本领域技术人员也可以根据器件的实际情况进行选择。
S120,在缓冲氧化层上通过淀积形成氮化硅层302。
图2A是一实施例中步骤S120完成后器件的剖面示意图,需要指出的是,所有附图中氮化硅层302下方的硅衬底均未画出,且缓冲氧化层因为较薄因此也未示出,本领域技术人员根据说明书和权利要求书的描述应可清楚地理解器件的结构。
在本实施例中,淀积形成氮化硅层302是采用低压炉管的方式进行。在其它实施例中,本领域技术人员也可以使用公知的其它淀积氮化硅的工艺来完成氮化硅层302的淀积。
S130,光刻定义出场区并蚀刻,去除场区上的氮化硅。
涂覆光刻胶并通过曝光和显影定义出场区,然后用等离子蚀刻去除场区上的氮化硅。在其它实施例中,也可以采用其它公知的适用于氮化硅蚀刻的干法或湿法蚀刻工艺去除氮化硅。
S140,对场区进行离子注入。
在光刻完成后,需要对光刻胶进行去胶清洗。清洗可以在离子注入之前做,也可以在离子注入完成后、步骤S150之前进行。图2B是图2A所示实施例中对场区进行离子注入的示意图。
S150,进行场区氧化,生长场氧化层304。
图2C是图2A所示实施例中步骤S150完成后器件的剖面示意图。场氧化层304可以采用热氧化工艺进行生长。
S160,剥除氮化硅层302。
在本实施例中,采用磷酸溶液去除氮化硅层302。在其它实施例中也可以采用本领域公知的去除氮化硅的方法进行剥除。图2D是图2A所示实施例中步骤S160完成后器件的剖面示意图。
S170,对晶圆进行湿浸(wet dip),去除缓冲氧化层和部分场氧化层304以减小场氧化层304的鸟嘴长度。
由于氮化硅层302被剥除,步骤S170中可以通过调整wet dip的量,实现对场氧鸟嘴的控制。在本实施例中,去除的场氧化层304的厚度为200埃。
S180,重新在晶圆表面生长缓冲氧化层,在重新生长的缓冲氧化层上通过淀积形成氮化硅层312。
生长缓冲氧化层可以用热氧化工艺进行,淀积氮化硅层312可以采用低压炉管的方式进行。氮化硅层312将场氧化层304完全覆盖。
S190,光刻定义出漂移区并蚀刻,去除漂移区上的氮化硅。
涂覆光刻胶并通过曝光和显影定义出漂移区,然后用等离子蚀刻去除漂移区上的氮化硅。
S200,对漂移区进行离子注入。
在漂移区光刻完成后,需要对光刻胶进行去胶清洗。清洗可以在漂移区离子注入之前做,也可以在离子注入完成后、步骤S210之前进行。图2E是图2A所示实施例中对漂移区进行离子注入的示意图。
S210,进行漂移区氧化,生长漂移区氧化层314。
图2F是图2A所示实施例中步骤S210完成后器件的剖面示意图。漂移区氧化层314可以采用热氧化工艺进行生长。由于氮化硅层312将场氧化层304完全覆盖,因此氮化硅层312对场氧化层304进行了保护,步骤S210中的热生长不会使得场氧化层304的厚度增加。
步骤S210完成后,可以用磷酸溶液将氮化硅层312剥除。
上述分立式场氧结构的半导体器件的制造方法,在生长场氧化层304完成后剥除氮化硅层302,这时可以通过调整湿浸(wet dip)的量来优化场氧鸟嘴的长度,解决了场氧鸟嘴过长的问题。湿浸完成后重新生长缓冲氧化层和氮化硅312,场氧化层304被氮化硅312覆盖保护。在后续生长漂移区氧化层314的步骤中,漂移区氧化层314的厚度可以自由调整,不会影响场氧化层304的厚度。
在一个实施例中,设计场氧化层304的厚度为漂移区氧化层314的厚度为可以于步骤S150中生长的场氧化层304,再于步骤S170中通过湿浸去除的场氧化层304,之后再于步骤S210中生长的漂移区氧化层314。
上述分立式场氧结构的半导体器件的制造方法,适用于横向扩散漂移区MOS管(LDMOS)器件,也可以用于制造其它采用局部场氧化(LOCOS)工艺进行隔离的半导体器件。
以上所述实施例仅表达了本发明的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对本发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。
Claims (9)
1.一种分立式场氧结构的半导体器件的制造方法,包括下列步骤:
在晶圆表面生长缓冲氧化层;
在所述缓冲氧化层上通过淀积形成氮化硅层;
光刻定义出场区并蚀刻,去除所述场区上的氮化硅;
对所述场区进行离子注入;
进行场区氧化,生长场氧化层;
剥除所述氮化硅层;
对所述晶圆进行湿浸,去除所述缓冲氧化层和部分的所述场氧化层,以减小所述场氧化层的鸟嘴长度;
重新在晶圆表面生长缓冲氧化层及在重新生长的缓冲氧化层上通过淀积形成氮化硅层,重新淀积的所述氮化硅层将所述场氧化层完全覆盖;
光刻定义出漂移区并蚀刻,去除所述漂移区上的氮化硅;
对所述漂移区进行离子注入;
进行漂移区氧化,生长漂移区氧化层。
2.根据权利要求1所述的分立式场氧结构的半导体器件的制造方法,其特征在于,所述光刻定义出场区并蚀刻的步骤,是涂覆光刻胶并通过曝光和显影定义出场区,用等离子蚀刻去除场区上的氮化硅,然后做去胶清洗,所述去胶清洗在所述进行场区氧化的步骤前进行;所述光刻定义出漂移区并蚀刻的步骤,是涂覆光刻胶并通过曝光和显影定义出漂移区,用等离子蚀刻去除漂移区上的氮化硅,然后再次进行去胶清洗,所述再次去胶清洗在所述进行漂移区氧化的步骤前进行。
3.根据权利要求1所述的分立式场氧结构的半导体器件的制造方法,其特征在于,所述淀积形成氮化硅层和重新淀积形成氮化硅层的步骤,是采用低压炉管的方式进行。
4.根据权利要求1所述的分立式场氧结构的半导体器件的制造方法,其特征在于,所述进行漂移区氧化,生长漂移区氧化层的步骤后还包括剥除重新淀积的所述氮化硅层的步骤。
5.根据权利要求1所述的分立式场氧结构的半导体器件的制造方法,其特征在于,所述剥除氮化硅层的步骤是用磷酸溶液进行剥除。
6.根据权利要求1所述的分立式场氧结构的半导体器件的制造方法,其特征在于,所述缓冲氧化层和重新生长的缓冲氧化层的厚度均为150埃。
7.根据权利要求6述的分立式场氧结构的半导体器件的制造方法,其特征在于,所述对晶圆进行湿浸,去除所述缓冲氧化层和部分的所述场氧化层的步骤中,去除的所述场氧化层的厚度为200埃。
8.根据权利要求7述的分立式场氧结构的半导体器件的制造方法,其特征在于,所述进行场区氧化,生长场氧化层的步骤中生长的场氧化层的厚度为6000埃;所述进行漂移区氧化,生长漂移区氧化层的步骤中生长的漂移区氧化层的厚度为3000埃。
9.根据权利要求1-8中任意一项所述的分立式场氧结构的半导体器件的制造方法,其特征在于,所述半导体器件是横向扩散金属氧化物半导体场效应管。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105225952A (zh) * | 2014-06-10 | 2016-01-06 | 北大方正集团有限公司 | 一种vdmos器件的制作方法及vdmos器件 |
CN105448988A (zh) * | 2014-08-22 | 2016-03-30 | 无锡华润上华半导体有限公司 | 一种ldmos器件及其制作方法 |
CN105931963A (zh) * | 2016-07-06 | 2016-09-07 | 株洲中车时代电气股份有限公司 | 一种碳化硅PiN二极管的结终端结构的制造方法 |
CN108511346A (zh) * | 2018-03-05 | 2018-09-07 | 上海华虹宏力半导体制造有限公司 | Ldmos器件的制造方法 |
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Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104517832B (zh) * | 2013-09-27 | 2017-09-29 | 无锡华润上华半导体有限公司 | 功率二极管的制备方法 |
CN104576359B (zh) * | 2013-10-23 | 2017-10-27 | 无锡华润上华科技有限公司 | 功率二极管的制备方法 |
PL3122781T3 (pl) | 2014-03-28 | 2020-06-15 | Xencor, Inc. | Dwuswoiste przeciwciała, które wiążą się z CD38 i CD3 |
US10529812B1 (en) * | 2018-10-10 | 2020-01-07 | Texas Instruments Incorporated | Locos with sidewall spacer for transistors and other devices |
CN111048420B (zh) * | 2019-12-27 | 2022-07-19 | 杰华特微电子股份有限公司 | 横向双扩散晶体管的制造方法 |
KR20230166150A (ko) | 2020-08-19 | 2023-12-06 | 젠코어 인코포레이티드 | 항-cd28 조성물 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5128274A (en) * | 1989-08-01 | 1992-07-07 | Matsushita Electric Industrial Co., Ltd. | Method for producing a semiconductor device having a LOCOS insulating film with at least two different thickness |
CN102237293A (zh) * | 2010-04-23 | 2011-11-09 | 无锡华润上华半导体有限公司 | 半导体器件及其制造方法 |
CN102593040A (zh) * | 2012-03-21 | 2012-07-18 | 无锡华润上华半导体有限公司 | Locos多层氧化层的集成制作方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5024961A (en) * | 1990-07-09 | 1991-06-18 | Micron Technology, Inc. | Blanket punchthrough and field-isolation implant for sub-micron N-channel CMOS devices |
US5397732A (en) * | 1993-07-22 | 1995-03-14 | Industrial Technology Research Institute | PBLOCOS with sandwiched thin silicon nitride layer |
TW200421560A (en) * | 2003-04-10 | 2004-10-16 | Macronix Int Co Ltd | Method for improvement of edge breakdown caused by edge electrical field at a tunnel oxide of a high-density flash memory by a shielded bird's beak |
CN101131543A (zh) * | 2006-08-23 | 2008-02-27 | 上海华虹Nec电子有限公司 | 局部硅氧化隔离的制造工艺方法 |
CN101924059A (zh) * | 2009-06-13 | 2010-12-22 | 无锡华润上华半导体有限公司 | 一种场氧化隔离制造方法 |
IT1401729B1 (it) * | 2010-06-17 | 2013-08-02 | St Microelectronics Srl | Procedimento per la fabbricazione di dispositivi integrati di potenza con corrugazioni superficiali e dispositivo integrato di potenza con corrugazioni superficiali |
-
2013
- 2013-01-23 CN CN201310025246.XA patent/CN103943548A/zh active Pending
- 2013-12-31 WO PCT/CN2013/091201 patent/WO2014114179A1/zh active Application Filing
- 2013-12-31 US US14/436,016 patent/US9252240B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5128274A (en) * | 1989-08-01 | 1992-07-07 | Matsushita Electric Industrial Co., Ltd. | Method for producing a semiconductor device having a LOCOS insulating film with at least two different thickness |
CN102237293A (zh) * | 2010-04-23 | 2011-11-09 | 无锡华润上华半导体有限公司 | 半导体器件及其制造方法 |
CN102593040A (zh) * | 2012-03-21 | 2012-07-18 | 无锡华润上华半导体有限公司 | Locos多层氧化层的集成制作方法 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105225952A (zh) * | 2014-06-10 | 2016-01-06 | 北大方正集团有限公司 | 一种vdmos器件的制作方法及vdmos器件 |
CN105225952B (zh) * | 2014-06-10 | 2018-06-15 | 北大方正集团有限公司 | 一种vdmos器件的制作方法及vdmos器件 |
CN105448988A (zh) * | 2014-08-22 | 2016-03-30 | 无锡华润上华半导体有限公司 | 一种ldmos器件及其制作方法 |
CN105931963A (zh) * | 2016-07-06 | 2016-09-07 | 株洲中车时代电气股份有限公司 | 一种碳化硅PiN二极管的结终端结构的制造方法 |
CN105931963B (zh) * | 2016-07-06 | 2019-12-03 | 株洲中车时代电气股份有限公司 | 一种碳化硅PiN二极管的结终端结构的制造方法 |
CN108511346A (zh) * | 2018-03-05 | 2018-09-07 | 上海华虹宏力半导体制造有限公司 | Ldmos器件的制造方法 |
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