WO2014206300A1 - 绝缘栅双极晶体管的制造方法 - Google Patents

绝缘栅双极晶体管的制造方法 Download PDF

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WO2014206300A1
WO2014206300A1 PCT/CN2014/080746 CN2014080746W WO2014206300A1 WO 2014206300 A1 WO2014206300 A1 WO 2014206300A1 CN 2014080746 W CN2014080746 W CN 2014080746W WO 2014206300 A1 WO2014206300 A1 WO 2014206300A1
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wafer
insulated gate
protective layer
layer
manufacturing
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PCT/CN2014/080746
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English (en)
French (fr)
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张硕
芮强
邓小社
王根毅
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无锡华润上华半导体有限公司
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Publication of WO2014206300A1 publication Critical patent/WO2014206300A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Definitions

  • the present invention relates to the field of semiconductor design and manufacturing technology, and in particular to an insulated gate bipolar transistor (Insulated Gate) Bipolar Transistor, referred to as IGBT) manufacturing method.
  • IGBT Insulated Gate Bipolar Transistor
  • IGBT is made of BJT (Bipolar Junction Composite full-voltage-driven power semiconductor device composed of Transistor, bipolar junction transistor) and MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor), combined with high input of MOSFET
  • BJT Bipolar Junction Composite full-voltage-driven power semiconductor device composed of Transistor, bipolar junction transistor
  • MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • a method for manufacturing a field-stop (FS) structure insulated gate bipolar transistor is generally performed after the front process of the silicon wafer is completely completed (that is, after the front surface process is completed to complete the front metal electrode), and then the silicon wafer is removed from the back surface.
  • ion implantation of P-type impurities is performed on the back side of the silicon wafer; then, the implanted P-type impurity ions are activated and the ion implantation damage is repaired, thereby obtaining a P+-type collector region on the back side of the silicon wafer.
  • the high-temperature annealing process is generally used to activate the implanted P-type impurity ions. Due to the limitation of the melting point of the metal electrode on the front side of the silicon wafer, the high activation rate of the P-type impurity ions cannot be achieved, thereby affecting the performance of the IGBT.
  • a method of fabricating an insulated gate bipolar transistor comprising: providing a wafer having a front side and a back side, wherein the wafer comprises a semiconductor substrate of a first conductivity type, based on the semiconductor substrate on the wafer Forming an insulated gate transistor unit on a front side; forming a protective layer on a front surface of the wafer; implanting a second conductive type impurity ion on a reverse side of the wafer; and removing protection formed on a front surface of the wafer Forming a first main electrode contact hole on the insulated gate transistor unit, and activating a second conductive type impurity ion implanted on a reverse side of the wafer by a hole injection activation thermal process to form a second conductivity type Semiconductor layer.
  • the manufacturing method further includes: covering the metal gate layer on the insulated gate transistor unit formed with the first main electrode contact hole to form the first main electrode; and covering the metal on the second conductive type semiconductor layer The layer forms a second main electrode.
  • the injection temperature and the implantation time during the hole injection activation heat process are adjusted according to the need of the second conductivity type impurity ion activation.
  • the injection temperature is 850 ° C and the injection time is 30 to 90 min.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the insulated gate transistor unit is an N-channel MOSFET unit
  • the substrate is an N-type semiconductor substrate
  • the second conductive type semiconductor layer is a P+ type collector layer
  • the first main electrode is an emitter
  • the second main electrode is a collector
  • the first The main electrode electrode contact hole is an emitter electrode contact hole.
  • the semiconductor substrate includes a first main surface on the same side as the front surface of the wafer and a second main surface on the same side as the reverse side of the wafer, the N-type groove
  • the MOSFET unit includes: a selectively formed P-base region from the first main surface of the semiconductor substrate to the N-type semiconductor substrate; and a selection from a surface of the P-base region to the P-base region a formed N+ active region; a selectively formed gate oxide layer on the first main surface of the semiconductor substrate, wherein the gate oxide layer is located at a first main surface of the edge portion of the P base region a first main surface of the semiconductor substrate on which the P-base region is not formed; a polysilicon gate electrode formed on the upper surface of the gate oxide layer; and a dielectric layer covering the exposed surface of the gate oxide layer and the polysilicon gate electrode .
  • the manufacturing method further includes: forming an emitter contact hole on the insulated gate transistor unit by a photolithography and etching process, the emitter passing through the emitter contact hole and the The N+ active region is in electrical contact with the P base region.
  • the manufacturing method further includes: simultaneously forming a protective layer on a reverse side of the wafer, wherein The protective layer includes a silicon nitride protective layer and a silicon dioxide protective layer which are successively formed.
  • the manufacturing method before injecting the second conductivity type impurity ions on the reverse side of the wafer, the manufacturing method further comprises: forming a layer of photoresist on the silicon dioxide protective layer on the front side of the wafer a protective layer; removing a silicon dioxide protective layer on a reverse side of the wafer; removing the photoresist protective layer; removing a silicon nitride protective layer on a reverse side of the wafer; etching and removing the opposite side of the wafer
  • the upper polysilicon layer is formed simultaneously when the polysilicon gate of the insulated gate transistor unit is formed on the front surface of the wafer.
  • the manufacturing method further includes: removing the silicon dioxide protective layer on the reverse side of the wafer by wet etching, and removing the opposite surface of the wafer by using a silicon nitride full stripping technique. Silicon nitride protective layer.
  • the hole injecting the thermal process after the opening step is used to inject the wafer into the wafer.
  • the second conductivity type impurity ions on the reverse side are annealed. This activation mode is not limited by the low melting point of the metal, and high-efficiency activation of the impurity ions of the second conductivity type can be realized, thereby better processing the insulated gate bipolar transistor. .
  • FIG. 1 is a flow chart showing a method of fabricating an insulated gate bipolar transistor in an embodiment
  • FIG. 2 to 13 are longitudinal cross-sectional views of the respective wafers corresponding to the respective manufacturing steps in the flowchart shown in Fig. 1.
  • FIG. 1 is a flow chart of a method 100 of fabricating an insulated gate bipolar transistor in one embodiment.
  • the method 100 of manufacturing an insulated gate bipolar transistor includes the following steps.
  • Step 110 providing a wafer having a front side and a back side, wherein the wafer includes a semiconductor substrate 10 of a first conductivity type, and an insulated gate transistor is formed on a front side of the wafer based on the semiconductor substrate 10.
  • the cell has a field stop layer 11 formed on the reverse side of the wafer.
  • the step 110 provides a semiconductor wafer as shown in FIG. 2, assuming that the first conductivity type is N-type and the second conductivity type is P-type, and the first conductivity type
  • the semiconductor substrate is an N-type semiconductor substrate 10.
  • the semiconductor substrate 10 includes a first main surface 1S1 on the same side as the front surface of the wafer and a second main surface 1S2 on the same side as the reverse side of the wafer.
  • the insulated gate transistor unit is a MOSFET having a channel of a first conductivity type (here, an N-type channel).
  • the N-channel MOSFET is DMOS (Double-diffused Metal Oxide A semiconductor, double-diffused MOS) MOSFET comprising: a P-body formed from a first main surface 1S1 of the N-semiconductor substrate 10 to selectively diffuse P-type impurities in the N-type semiconductor substrate 10.
  • a region (or referred to as a P-base region) 3; an N+ active region (or N+) formed from the surface of the P-body region 3 to selectively diffuse a high concentration of N-type impurities in the P-body region 3
  • An emitter region 4 ; a P+ active region 5 formed by diffusing a high concentration of P-type impurities from the surface portion of the P-body region 3 inside the N+ active region 4 into the P-body region 3;
  • a gate oxide layer 1 is selectively formed on the first main surface 1S1 of the N-type semiconductor substrate 10, wherein the gate oxide layer 1 is located on the first main surface 1S1 of the edge portion of the P-body region 3.
  • the portion of the P-body region 3 directly under the polysilicon gate electrode 2 is referred to as a channel region.
  • the role of the P+ active region 5 is to reduce the connection resistance of the emitter and the P-body region 3, and in other embodiments, the P+ active region 5 may not be formed.
  • the insulated gate transistor unit at this time has not yet formed the first main electrode contact hole (16 in FIG. 12) and the front surface structure formed by the subsequent front surface process, such as the first main electrode (14 in FIG. 13). And a passivation layer (not shown) or the like.
  • the N-channel MOSFET of FIG. 2 can be prepared by an existing process and will not be described herein.
  • the insulated gate transistor is a MOSFET of a DMOS structure, and in other embodiments, it may also be a trench MOSFET or a V-shaped MOSFET.
  • the gate oxide layer 1 and the polysilicon gate electrode 2 are generally grown by means of a furnace tube, a gate oxide layer 1 and a polysilicon gate of the MOSFET are formed on the first main surface 1S1 side of the semiconductor substrate 10
  • the oxide layer 21 and the polysilicon layer 22 are also sequentially formed on the second main surface 1S2 of the N-type semiconductor substrate 10. Since neither the oxide layer 21 nor the polysilicon layer 22 is intentionally formed, it is removed in a subsequent suitable step, and the process of removing the oxide layer 21 and the polysilicon layer 22 can be adjusted as needed.
  • the oxide layer 21 and the polysilicon layer 22 are not simultaneously formed, then in these implementations There are no subsequent removal steps in the example.
  • Step 120 forming a protective layer on the front and back sides of the wafer.
  • the protective layer includes a silicon nitride (SIN) protective layer 7 and a silicon dioxide (SIO2) protective layer 8 which are sequentially formed over the dielectric layer 6 of the insulated gate transistor unit, wherein the silicon nitride protection
  • the thickness of the layer 7 is based on the principle of ensuring that the dielectric layer 6 and the silicon dioxide protective layer 8 are isolated; the thickness of the silicon dioxide protective layer 8 is such that when the back polysilicon layer 22 and the back side are implanted, the front dielectric layer 6 is not damaged. For the principle.
  • a silicon nitride protective layer 7 and the silicon dioxide protective layer 8 are both formed by thermal growth, a silicon nitride protective layer 7 and a silicon dioxide protective layer 8 are formed on the front surface of the wafer. At the same time, a silicon nitride protective layer 27 and a silicon dioxide protective layer 28 are sequentially formed on the reverse side of the wafer.
  • the silicon nitride protective layer 27 nor the silicon dioxide protective layer 28 since neither the silicon nitride protective layer 27 nor the silicon dioxide protective layer 28 is intentionally formed, it may be removed in a subsequent suitable step, and the process of removing the silicon nitride protective layer 27 and the silicon dioxide protective layer 28 may be performed according to Need to adjust. In some embodiments, if the silicon nitride protective layer 27 and the silicon dioxide protective layer 28 are not formed simultaneously when the silicon nitride protective layer 7 and the silicon dioxide protective layer 8 are formed, then in these embodiments There are no subsequent removal steps.
  • Step 130 removing a protective layer formed on the reverse side of the wafer.
  • a surface of the front silicon dioxide protective layer 8 is coated with a photoresist protective layer 9; then, as shown in FIG. 5, the wet etching is used to remove the a silicon dioxide protective layer 28 on the reverse side of the wafer; subsequently, as shown in FIG. 6, the photoresist protective layer 9 is removed; finally, as shown in FIG. 7, the silicon nitride full stripping technique is used to remove the wafer.
  • Step 140 flips the front and back sides of the wafer and etches away the polysilicon layer 22 on the back side of the wafer.
  • the polysilicon layer 22 is simultaneously formed when the polysilicon gate 2 of the insulated gate transistor unit is formed on the front surface of the wafer. In some embodiments, if the polysilicon layer 22 is not formed simultaneously when the polysilicon gate electrode 2 of the MOSFET is formed, then there is no such removal step.
  • Step 150 injecting second conductivity type impurity ions 12 (such as P type impurity ions) on the reverse side of the wafer.
  • second conductivity type impurity ions 12 such as P type impurity ions
  • boron ion implantation is performed on the reverse side of the wafer, and the implantation energy is determined by the thickness of the oxide layer 21 formed on the reverse surface of the wafer to enable oxidation.
  • the layer 21 is driven into the field stop layer (N+ layer) 11 as a principle, and the injected dose is based on the principle that a good compromise between the conduction voltage drop and the turn-off loss can be achieved.
  • Step 160 removing the protective layer formed on the front side of the wafer.
  • the silicon dioxide protective layer 8 and the silicon nitride protective layer 7 on the front side of the wafer are sequentially removed. Specifically, the wafer on which the backside implantation is completed is turned upside down, the silicon dioxide protective layer 8 is first removed by wet etching, and the oxide layer 21 on the back side of the wafer is removed, and then the silicon nitride is removed by SIN full stripping technology. Protective layer 7.
  • Step 170 as shown in FIG. 12, forming a first main electrode contact hole 16 on the insulated gate transistor unit, and injecting a second conductive type impurity ion implanted on the opposite side of the wafer through an aperture injecting an activation thermal process 12 is activated to form the second conductive type semiconductor layer 13.
  • the hole injection activation heat process refers to injecting the second conductivity type impurity ions 12 into the wafer through the first main electrode contact hole 16 and in order to activate the second conductivity type impurity ions 12 on the reverse side of the wafer and from the first main electrode contact hole An annealing process of 16 implanted second conductivity type impurity ions 12.
  • the dielectric layer 6 is selectively etched by photolithography and etching to form a first main electrode contact hole 16 shorting the N+ active region 4 and the P-body region 3.
  • the injection temperature and the implantation time during the hole injection activation heat process are adjusted according to the need of the second conductivity type impurity ion activation. In one embodiment, the implantation temperature is 850 ° C and the injection time is 30 to 90 min.
  • Step 180 as shown in FIG. 13, covering a metal gate layer (for example, AL-Si-Cu) on the insulated gate transistor unit formed with the first main electrode contact hole 16 to form a first main electrode 14, at the second conductive
  • the type semiconductor layer 13 is covered with a metal layer (for example, AL-Ti-Ni-Ag) to form the second main electrode 15.
  • a metal gate layer for example, AL-Si-Cu
  • AL-Ti-Ni-Ag a metal layer
  • the hole injecting the thermal process after the opening step is used to inject the wafer into the wafer.
  • the second conductivity type impurity ions on the reverse side are annealed. This activation mode is not limited by the low melting point of the metal, and high-efficiency activation of the impurity ions of the second conductivity type can be realized, thereby better processing the insulated gate bipolar transistor. .
  • a method of manufacturing an insulated gate bipolar transistor having a field termination (FS) structure is described as an example.
  • the manufacturing method can also be applied to fabricating a non-punch-through (NPT) insulated gate bipolar transistor. It is only necessary to omit the step of manufacturing the FS layer 11.
  • the first conductivity type is N-type
  • the second conductivity type is P-type.
  • the first conductivity type may be P-type.
  • the second conductivity type is N-type.
  • a P-type semiconductor substrate 1 is used.
  • the insulated gate transistor is a P-channel MOSFET unit, and the second main electrode 15 is an emitter.
  • the first main electrode 14 For the collector, the specific structure and principle are similar to those of the above IGBT, and are not described here.

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Abstract

一种绝缘栅双极晶体管的制造方法，包括：提供具有正面和反面的晶圆，其中所述晶圆包括有第一导电类型的半导体衬底（10）,基于所述半导体衬底（10）在所述晶圆的正面侧形成有绝缘栅型晶体管单元；在所述晶圆的正面上形成保护层（7、8）；在所述晶圆的反面侧注入第二导电类型杂质离子（12）；去除形成于所述晶圆正面上的保护层（7、8）；在所述绝缘栅型晶体管单元上形成第一主电极接触孔（16），并通过孔注入激活热过程对注入所述晶圆的反面侧的第二导电类型杂质离子（12）进行激活以形成第二导电类型半导体层（13）。

Description

绝缘栅双极晶体管的制造方法
【技术领域】
本发明涉及半导体设计及制造技术领域，特别涉及一种绝缘栅双极晶体管（ Insulated Gate Bipolar Transistor ，简称 IGBT ）的制造方法。
【背景技术】
IGBT是由BJT（Bipolar Junction Transistor，双极结型晶体管）和MOSFET（Metal-Oxide-Semiconductor-Field-Effect-Transistor，金属氧化物半导体场效应晶体管）组成的复合全控型电压驱动式功率半导体器件，兼有MOSFET的高输入阻抗和BJT的低导通压降两方面的优点，具有工作频率高，控制电路简单，电流密度高，通态压低等特点，广泛应用于功率控制领域。
现有技术中，针对场终止（FS）结构绝缘栅双极晶体管的制造方法，一般是在硅片正面工艺全部完成后（即正面工艺加工至完成正面金属电极后），再将硅片从背面减薄，之后在硅片背面进行P型杂质的离子注入；然后，激活所注入的P型杂质离子并修复离子注入损伤，从而在硅片背面得到P+型集电极区。一般采用高温退火工艺激活注入的P型杂质离子，由于受硅片正面金属电极熔点的限制，无法实现P型杂质离子的高激活率，以致影响IGBT的性能。
为此，又有一种改进方案，将高温退火工艺改为激光退火（Laser annealing）工艺，其可实现仅在硅片背面一定厚度的区域内实现高温，不影响硅片正面，从而实现P型杂质离子的高效率激活。但是，激光退火工艺需要使用特殊的专用设备，成本较高。
【发明内容】
基于此，有必要针对传统的绝缘栅双极晶体管的制造方法成本较高的问题，提供一种无需采用成本较高的激光退火工艺，也可以实现掺入晶圆的反面的第二导电类型杂质的高效率激活的绝缘栅双极晶体管的制造方法。
一种绝缘栅双极晶体管的制造方法，其包括：提供具有正面和反面的晶圆，其中所述晶圆包括有第一导电类型的半导体衬底，基于所述半导体衬底在所述晶圆的正面侧形成有绝缘栅型晶体管单元；在所述晶圆的正面上形成保护层；在所述晶圆的反面侧注入第二导电类型杂质离子；去除形成于所述晶圆正面上的保护层；在所述绝缘栅型晶体管单元上形成第一主电极接触孔，并通过孔注入激活热过程对注入所述晶圆的反面侧的第二导电类型杂质离子进行激活以形成第二导电类型半导体层。
在其中一个实施例中，所述制造方法还包括：在形成有第一主电极接触孔的绝缘栅型晶体管单元上覆盖金属层以形成第一主电极；在第二导电类型半导体层上覆盖金属层以形成第二主电极。
在其中一个实施例中，所述孔注入激活热过程中的注入温度和注入时间根据所述第二导电类型杂质离子激活的需要进行调整。
在其中一个实施例中，所述注入温度为850℃，所述注入时间为30~90min。
在其中一个实施例中，所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型的半导体衬底，所述第二导电类型半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极，所述第一主电极电极接触孔为发射极电极接触孔。
在其中一个实施例中，所述半导体衬底包括与所述晶圆的正面位于同侧的第一主面和与所述晶圆的反面位于同侧的第二主面，所述N型沟道MOSFET单元包括：自所述半导体衬底的第一主面向所述N-型半导体衬底内有选择的形成的P基区；自所述P基区的表面向该P基区内有选择的形成的N+有源区；在所述半导体衬底的第一主面上有选择的形成的栅氧化层，其中，所述栅氧化层位于P基区的边缘部分的第一主面和所述半导体衬底的未形成P基区的第一主面上；在所述栅极氧化层的上表面上形成的多晶硅栅电极；覆盖所述栅极氧化层和多晶硅栅电极露出表面的介质层。
在其中一个实施例中，所述制造方法还包括：通过光刻、蚀刻工艺在所述绝缘栅型晶体管单元上形成发射极接触孔，所述发射极穿过所述发射极接触孔与所述N+有源区和所述P基区电性接触。
在其中一个实施例中，在形成有绝缘栅型晶体管单元的晶圆的正面上形成保护层时，所述制造方法还包括：同时还在所述晶圆的反面上也形成保护层，其中所述保护层包括先后形成的氮化硅保护层和二氧化硅保护层。
在其中一个实施例中，在所述晶圆的反面侧注入第二导电类型杂质离子前，所述制造方法还包括：在所述晶圆的正面的二氧化硅保护层上形成一层光胶保护层；去除所述晶圆的反面上的二氧化硅保护层；去除所述光胶保护层；去除所述晶圆的反面上的氮化硅保护层；刻蚀去除所述晶圆的反面上的多晶硅层，该多晶硅层是在所述晶圆的正面上形成所述绝缘栅型晶体管单元的多晶硅栅极时同时形成的。
在其中一个实施例中，所述制造方法还包括：采用湿法刻蚀去除所述晶圆的反面上的二氧化硅保护层，采用氮化硅全剥技术去除所述晶圆的反面上的氮化硅保护层。
与现有技术相比，根据上述绝缘栅双极晶体管的制造方法，在形成晶圆的正面的第一主电极之前，利用开孔步骤之后的孔注入激活热过程对掺入所述晶圆的反面的第二导电类型杂质离子进行退火，此种激活方式不受金属熔点低的限制，可以实现所述第二导电类型杂质离子的高效率激活，从而更好的实现绝缘栅双极晶体管的加工。
【附图说明】
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。其中：
图1为一个实施例中的绝缘栅双极晶体管的制造方法的流程图；
图2至图13为图1所示的流程图中的各个制造工序对应晶圆的纵剖面图。
【具体实施方式】
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似改进，因此本发明不受下面公开的具体实施的限制。
请参考图1所示，其为在一个实施例中的绝缘栅双极晶体管的制造方法100的流程图。所述绝缘栅双极晶体管的制造方法100包括如下步骤。
步骤110，提供具有正面和反面的晶圆，其中所述晶圆包括有第一导电类型的半导体衬底10，基于所述半导体衬底10在所述晶圆的正面侧形成有绝缘栅型晶体管单元，在所述晶圆的反面侧形成有场终止层11。
在一个实施例中，所述步骤110提供如图2所示的半导体晶圆，假设所述第一导电类型为N型，所述第二导电类型为P型，此时所述第一导电类型的半导体衬底为N-型的半导体衬底10。所述半导体衬底10包括与所述晶圆的正面位于同侧的第一主面1S1和与所述晶圆的反面位于同侧的第二主面1S2。
所述绝缘栅型晶体管单元为具有第一导电类型的沟道（在此为N型沟道）的MOSFET。具体的说，该N型沟道的MOSFET为DMOS（Double-diffused Metal Oxide Semiconductor，双扩散MOS）结构的MOSFET，其包括：自所述N-半导体衬底10的第一主面1S1向该N-型半导体衬底10内有选择的扩散P型杂质形成的P-body区（或者称为P基区）3；自所述P-body区3的表面向该P-body区3内有选择的扩散高浓度的N型杂质形成的N+有源区（或者称为N+发射极区）4；自所述N+有源区4内侧的P-body区3表面部分向该P-body区3内扩散高浓度的P型杂质形成的P+有源区5； 在所述N-型半导体衬底10的第一主面1S1上有选择的形成的栅氧化层1，其中，所述栅氧化层1位于P-body区3的边缘部分的第一主面1S1和所述N-型半导体衬底10的未形成P-body区3的第一主面1S1上；在所述栅氧化层1的上表面上形成的多晶硅栅电极2；覆盖所述栅氧化层1和多晶硅栅电极2露出表面的介质层6（例如，BPSG等）。其中，多晶硅栅电极2正下方的P-body区3的部分称为沟道区。P+有源区5的作用为减小发射极和P-body区3连接电阻，在其他实施例中，也可以不形成P+有源区5。
可以看出，此时的绝缘栅型晶体管单元还未形成第一主电极接触孔(图12中的16)以及后续正面工艺所形成的正面结构，比如第一主电极(图13中的14)和钝化层(未示出)等。图2中的所述N型沟道的MOSFET可以采用现有工艺进行制备，在此不再赘述。在图2所示的实施例中，所述绝缘栅性晶体管为DMOS结构的MOSFET，在其他实施例中，其还可以为沟槽型MOSFET或V字形的MOSFET。
此外，由于所述栅氧化层1和多晶硅栅电极2通常都是通过炉管的方式生长的，因此在所述半导体衬底10的第一主面1S1侧形成MOSFET的栅氧化层1和多晶硅栅电极2时，也会在所述N-型半导体衬底10的第二主面1S2上依次形成氧化层21和多晶硅层22。由于所述氧化层21和多晶硅层22都不是被有意形成的，因此在后续的合适步骤中会被去除，去除所述氧化层21和多晶硅层22的工序可以根据需要调整。在一些实施例中，假如在所述半导体衬底10的第一主面1S1侧形成MOSFET的栅氧化层1和多晶硅栅电极2时，没有同时形成氧化层21和多晶硅层22，那么在这些实施例中则没有后续的去除步骤。
步骤120，在所述晶圆的正面和反面上形成保护层。
如图3所示，所述保护层包括依次形成于绝缘栅型晶体管单元的介质层6上方的氮化硅（SIN）保护层7和二氧化硅（SIO2）保护层8，其中氮化硅保护层7的厚度以能够保证介质层6和二氧化硅保护层8隔离为原则；二氧化硅保护层8的厚度以保证刻蚀背面多晶硅层22和背面离子注入时，不造成正面介质层6损伤为原则。由于所述氮化硅保护层7和二氧化硅保护层8都是通过热生长的方式形成的，因此，在所述晶圆的正面上形成氮化硅保护层7和二氧化硅保护层8的同时，还会在所述晶圆的反面上依次形成氮化硅保护层27和二氧化硅保护层28。
由于氮化硅保护层27和二氧化硅保护层28都不是被有意形成的，因此在后续的合适步骤中会被去除，去除氮化硅保护层27和二氧化硅保护层28的工序可以根据需要调整。在一些实施例中，假如在形成所述氮化硅保护层7和二氧化硅保护层8时，没有同时形成氮化硅保护层27和二氧化硅保护层28，那么在这些实施例中则没有后续的去除步骤。
步骤130，去除所述晶圆的反面上形成的保护层。
在一个实施例中，首先如图4所示，在所述正面二氧化硅保护层8表面涂布一层光刻胶保护层9；然后如图5所示，采用湿法刻蚀去除所述晶圆的反面上的二氧化硅保护层28；随后如图6所示，去除所述光胶保护层9；最后，如图7所示，采用氮化硅全剥技术去除所述晶圆的反面上的氮化硅保护层27。如上文所述，在一些实施例中，假如在形成所述氮化硅保护层7和二氧化硅保护层8时，没有同时形成氮化硅保护层27和二氧化硅保护层28，则没有该去除步骤。
步骤140，如8所示，将晶圆正反面翻转，刻蚀去除所述晶圆的背面上的多晶硅层22。如上文所示，该多晶硅层22是在所述晶圆的正面上形成所述绝缘栅型晶体管单元的多晶硅栅极2时同时形成的。在一些实施例中，假如在形成MOSFET的多晶硅栅电极2时，没有同时形成多晶硅层22，那么则没有该去除步骤。
步骤150，在所述晶圆的反面侧注入第二导电类型杂质离子12(比如P型杂质离子)。
在一个实施例中，如图9所示，在所述晶圆的反面侧进行硼离子注入，注入能量由形成于所述晶圆的反面上的氧化层21的厚度决定，以能够穿过氧化层21打入场终止层(N+层)11为原则，而注入的剂量则以能够实现导通压降和关断损耗很好的折中为原则。
步骤160，去除形成于所述晶圆正面上的保护层。
在一个实施例中，如图10，图11所示，依次去除晶圆正面的二氧化硅保护层8和氮化硅保护层7。具体的，将完成背面注入的晶圆翻转为正面向上，先通过湿法腐蚀去除二氧化硅保护层8，同时去除晶圆背面的氧化层21，然后通过SIN全剥技术去除所述氮化硅保护层7。
步骤170，如图12所示，在所述绝缘栅型晶体管单元上形成第一主电极接触孔16，并通过孔注入激活热过程对注入所述晶圆的反面侧的第二导电类型杂质离子12进行激活以形成第二导电类型半导体层13。该孔注入激活热过程指通过第一主电极接触孔16将第二导电类型杂质离子12注入晶圆，并为了激活晶圆反面侧的第二导电类型杂质离子12和从第一主电极接触孔16注入的第二导电类型杂质离子12而进行的退火过程。
在一个实施例中，通过光刻、刻蚀工艺刻对所述介质层6进行选择性刻蚀形成短接N+有源区4和所述P-body区3的第一主电极接触孔16。所述孔注入激活热过程中的注入温度和注入时间根据所述第二导电类型杂质离子激活的需要进行调整。在一个实施例中，所述注入温度为850℃，所述注入时间为30~90min。
步骤180，如图13，在形成有第一主电极接触孔16的所述绝缘栅型晶体管单元上覆盖金属层(比如，AL-Si-Cu)以形成第一主电极14，在第二导电类型半导体层13上覆盖金属层(比如，AL-Ti-Ni-Ag)以形成第二主电极15。在第一导电类型为N型，第二导电类型为P型时，第一主电极14为发射极，第二主电极15为集电极，第一主电极接触孔16为发射极接触孔，所述第二导电类型半导体层13为P+集电极层。
与现有技术相比，根据上述绝缘栅双极晶体管的制造方法，在形成晶圆的正面的第一主电极之前，利用开孔步骤之后的孔注入激活热过程对掺入所述晶圆的反面的第二导电类型杂质离子进行退火，此种激活方式不受金属熔点低的限制，可以实现所述第二导电类型杂质离子的高效率激活，从而更好的实现绝缘栅双极晶体管的加工。
在上文中以场终止（FS）结构的绝缘栅双极性晶体管的制造方法为例进行介绍，很显然，该制造方法还可以适用于制造非穿通型(NPT)绝缘栅双极性晶体管，其仅需要省去制造FS层11的步骤即可。
在上述实施例中，以所述第一导电类型为N型，所述第二导电类型为P型为例进行介绍，在其他改变的实施例中，也可以使得第一导电类型为P型，所述第二导电类型为N型，此时采用P-型的半导体衬底1，所述绝缘栅型晶体管为P沟道的MOSFET单元，第二主电极15为发射极，第一主电极14为集电极，具体结构和原理与上文的中IGBT相似，这里不在赘述。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种绝缘栅双极晶体管的制造方法，包括：
    提供具有正面和反面的晶圆，其中所述晶圆包括有第一导电类型的半导体衬底，基于所述半导体衬底在所述晶圆的正面侧形成有绝缘栅型晶体管单元；
    在所述晶圆的正面上形成保护层；
    在所述晶圆的反面侧注入第二导电类型杂质离子；
    去除形成于所述晶圆正面上的保护层；及
    在所述绝缘栅型晶体管单元上形成第一主电极接触孔，并通过孔注入激活热过程对注入所述晶圆的反面侧的第二导电类型杂质离子进行激活以形成第二导电类型半导体层。
  2. 根据权利要求1所述的绝缘栅双极晶体管的制造方法，其特征在于，还包括：
    在形成有第一主电极接触孔的绝缘栅型晶体管单元上覆盖金属层以形成第一主电极；在第二导电类型半导体层上覆盖金属层以形成第二主电极。
  3. 根据权利要求1所述的绝缘栅双极晶体管的制造方法，其特征在于，所述孔注入激活热过程中的注入温度和注入时间根据所述第二导电类型杂质离子激活的需要进行调整。
  4. 根据权利要求3所述的绝缘栅双极晶体管的制造方法，其特征在于，所述注入温度为850℃，所述注入时间为30~90min。
  5. 根据权利要求2所述的绝缘栅双极晶体管的制造方法，其特征在于，
    所述第一导电类型为Ｎ型，所述第二导电类型为Ｐ型，
    所述绝缘栅型晶体管单元为N型沟道MOSFET单元，所述第一导电类型的半导体衬底为N-型的半导体衬底，所述第二导电类型半导体层为P+型集电极层，所述第一主电极为发射极，所述第二主电极为集电极，所述第一主电极电极接触孔为发射极电极接触孔。
  6. 根据权利要求5所述的绝缘栅双极晶体管的制造方法，其特征在于，所述半导体衬底包括与所述晶圆的正面位于同侧的第一主面和与所述晶圆的反面位于同侧的第二主面，所述N型沟道MOSFET单元包括：
    自所述半导体衬底的第一主面向所述N-型半导体衬底内有选择的形成的P基区；
    自所述P基区的表面向该P基区内有选择的形成的N+有源区；
    在所述半导体衬底的第一主面上有选择的形成的栅氧化层，其中，所述栅氧化层位于P基区的边缘部分的第一主面和所述半导体衬底的未形成P基区的第一主面上；
    在所述栅极氧化层的上表面上形成的多晶硅栅电极；
    覆盖所述栅极氧化层和多晶硅栅电极露出表面的介质层。
  7. 根据权利要求6所述的绝缘栅双极晶体管的制造方法，其特征在于，通过光刻、蚀刻工艺在所述绝缘栅型晶体管单元上形成发射极接触孔，所述发射极穿过所述发射极接触孔与所述N+有源区和所述P基区电性接触。
  8. 根据权利要求1所述的绝缘栅双极晶体管的制造方法，其特征在于，在形成有绝缘栅型晶体管单元的晶圆的正面上形成保护层时，同时还在所述晶圆的反面上也形成保护层，其中所述保护层包括先后形成的氮化硅保护层和二氧化硅保护层。
  9. 根据权利要求8所述的绝缘栅双极晶体管的制造方法，其特征在于，在所述晶圆的反面侧注入第二导电类型杂质离子前，所述制造方法还包括：
    在所述晶圆的正面的二氧化硅保护层上形成一层光胶保护层；
    去除所述晶圆的反面上的二氧化硅保护层；
    去除所述光胶保护层；
    去除所述晶圆的反面上的氮化硅保护层；
    刻蚀去除所述晶圆的反面上的多晶硅层，该多晶硅层是在所述晶圆的正面上形成所述绝缘栅型晶体管单元的多晶硅栅极时同时形成的。
  10. 根据权利要求9所述的绝缘栅双极晶体管的制造方法，其特征在于，采用湿法刻蚀去除所述晶圆的反面上的二氧化硅保护层，采用氮化硅全剥技术去除所述晶圆的反面上的氮化硅保护层。
PCT/CN2014/080746 2013-06-28 2014-06-25 绝缘栅双极晶体管的制造方法 WO2014206300A1 (zh)

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