CN101794734A - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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CN101794734A
CN101794734A CN201010004021A CN201010004021A CN101794734A CN 101794734 A CN101794734 A CN 101794734A CN 201010004021 A CN201010004021 A CN 201010004021A CN 201010004021 A CN201010004021 A CN 201010004021A CN 101794734 A CN101794734 A CN 101794734A
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conducting material
sidewall
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CN101794734B (zh
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G·M·格里瓦纳
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Semiconductor Components Industries LLC
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Abstract

一种半导体元件以及一种制造所述半导体元件的方法，半导体元件包括场板和半导体器件。主体区在具有主表面的半导体材料中形成。栅槽在外延层中形成，并且栅结构在栅槽上形成。源区邻近栅槽而形成并且从主表面延伸到主体区中，以及形成从外延层的主表面穿过源区并穿过主体区的场板槽。场板在场板槽中形成，其中场板与场板槽的侧壁电隔离。对源区、场板和主体区之间形成源-场板-主体接触。对栅区形成栅接触。

Description

半导体元件及其制造方法
技术领域
本发明通常涉及半导体元件，且更具体地说，涉及功率开关半导体元件。
背景技术
金属氧化物半导体场效应晶体管(“MOSFET”)是一类常见的功率开关器件。MOSFET器件包括源区、漏区、在源区和漏区之间延伸的沟道区，以及邻近沟道区设置的栅结构。栅结构包括邻近沟道区设置并靠薄的电介质层与沟道区分隔开的传导的栅电极层。当向栅结构施加足够强度的电压以将MOSFET器件置于导通状态时，在源区和漏区之间形成传导沟道区，从而允许电流流经该器件。当向栅施加的电压不足以引起沟道的形成时，不流通电流，并且MOSFET器件处于截止状态。如本领域技术人员所了解的，MOSFET可以是P沟道场效应晶体管、N沟道场效应晶体管、耗尽型器件等等。
当今的高压功率开关市场主要受两个主要因素驱动：击穿电压(“BVdss”)和导通电阻(“Rdson”)。对具体的应用场合来说，要求最低的击穿电压，并且在实际应用中，设计者通常能够满足BVdss的规格。然而，这经常是以Rdson为代价的。对高压功率开关器件的制造者和使用者来说，这种性能上的取舍是设计上的主要挑战。另一个挑战的出现是因为功率MOSFET器件在P型传导性主体区(bodyregion)和N型传导性外延区之间具有本征P-N二极管。此本征P-N二极管在一定工作条件下开启，并在P-N结上储存电荷。当向P-N二极管施加突然的反向偏压时，储存的电荷产生负电流，直到电荷完全耗尽为止。电荷耗尽的时间称为反向恢复时间(“Trr”)，且此时间使功率MOSFET器件的开关速度延迟。另外，由于峰值反向恢复电流(“Irr”)和反向恢复时间，储存的电荷(“Qrr”)同样引起开关电压电平的损耗。
一种减小Rdson并提高开关速度的技术是在同一槽中形成槽栅结构(trench gate structure)和场板(field plate)，其中在槽内槽栅结构位于场板的上方。槽栅连接到源。这种结构的缺点是采用了复杂并且昂贵的处理技术。
因此，拥有具有较低Rdson同时具有较高击穿电压和较低开关损耗，即低Qrr损耗的半导体元件以及制造此半导体元件的方法是有利的。对半导体元件来说，有成本效益的制造更加有利。
附图说明
根据下面详细的说明，结合附图将会更好地理解本发明，附图中相同的参考符号指示相同的构件，且在附图中：
图1是根据本发明的实施方式的半导体元件在早期的制造阶段的沿图18中的剖面线1-1所示区域截取的剖视图；
图2是图1的半导体元件在较后的制造阶段的剖视图；
图3是图2的半导体元件在较后的制造阶段的剖视图；
图4是图3的半导体元件在较后的制造阶段的剖视图；
图5是图4的半导体元件在较后的制造阶段的剖视图；
图6是图5的半导体元件在较后的制造阶段的剖视图；
图7是图6的半导体元件在较后的制造阶段的剖视图；
图8是图7的半导体元件在较后的制造阶段的剖视图；
图9是图8的半导体元件在较后的制造阶段的剖视图；
图10是图9的半导体元件在较后的制造阶段的剖视图；
图11是图10的半导体元件在较后的制造阶段的剖视图；
图12是图11的半导体元件在较后的制造阶段的剖视图；
图13是图12的半导体元件在较后的制造阶段的剖视图；
图14是图13的半导体元件在较后的制造阶段的剖视图；
图15是图14的半导体元件在较后的制造阶段的剖视图；
图16是图15的半导体元件在较后的制造阶段的剖视图；
图17是图16的半导体元件在较后的制造阶段的剖视图；以及
图18是图17所示的半导体元件的俯视图。
具体实施方式
主要地，本发明提供了一种半导体元件，所述半导体元件包括场板和半导体器件，所述半导体器件例如场效应晶体管或沟槽场效应晶体管(trench field effect transistor)、垂直功率场效应晶体管、功率场效应晶体管，或其组合。应注意，功率场效应晶体管也称为垂直功率器件，且垂直场效应晶体管也称为功率器件。根据一实施方式，半导体元件通过提供半导体材料而制成，所述半导体材料优选地包括具有在衬底上形成的主体区的外延层。栅槽在半导体材料中形成并延伸穿过主体区。栅结构在栅槽中形成。源区在外延层的与栅槽横向相邻的部分中形成。具有侧壁和底的分离的场板槽在半导体材料中形成，并且延伸穿过源区和主体区。导电材料在场板槽中形成，并且通过电介质材料层与场板槽的侧壁隔开。对主体区、源区以及槽场板形成自对准的结合在一起的或一体化的电接触。因为电接触是自对准的一体化结构，其减小了构成半导体元件的晶体管的尺寸。
根据另一实施方式，半导体元件包括包含栅结构的栅槽和包含场板的分离的场板槽。主体区介于栅槽和场板槽之间，而源区位于主体区中。自对准的结合在一起的或一体化的接触与主体区、源区以及场板相接触。
图1是根据本发明的实施方式的半导体元件10的一部分在制造过程中的剖视图。应注意到，图1所示的剖视图是沿图18所示的剖面线1-1所表示的区域截取的，但是处于比图18所示的更早的制造阶段。图1所示的是具有相对的表面14和16的半导体材料12。表面14也称为正面或顶面，且表面16也称为底面或背面。根据一实施方式，半导体材料12包括设置在半导体衬底18上的外延层20。优选地，衬底18是用N型掺杂剂或杂质材料重掺杂的硅，而外延层20是用N型掺杂剂轻掺杂的硅。衬底层18的电阻率可小于约0.01欧姆·厘米(Ω·cm)，而外延层20的电阻率可大于约0.1Ω·cm。衬底层18为流经功率晶体管的电流提供低电阻传导通道，并对在半导体材料12的底面16上形成的底部漏极导体(drain conductor)、顶部漏极导体或这两导体提供低电阻电连接。用N型掺杂剂掺杂的区域或层称为具有N型传导性或N传导性类型的区域，而用P型掺杂剂掺杂的区域或层称为具有P型传导性或P传导性类型的区域。N型掺杂剂也称为N型杂质材料，而P型掺杂剂也称为P型杂质材料。
电介质材料层26在外延层20上形成或由外延层20形成。根据一实施方式，电介质层26的材料是厚度在约200埃
Figure G2010100040212D00041
到约1,000范围内的二氧化硅。形成二氧化硅层26的技术是为本领域的技术人员所熟知的。注入掩模(implant mask)(未显示)在电介质层26上形成。作为举例，注入掩模是具有将电介质层26的部分暴露的开口的光刻胶。P型传导性掺杂层(未显示)在外延层20中形成。掺杂层可通过将杂质材料比如，例如硼注入到外延层20中来形成。硼可以以约1×1013离子每平方厘米(离子/cm2)到约1×1014离子/cm2范围内的剂量且在约100千电子伏特(keV)到约400keV范围内的注入能量注入。形成掺杂层的技术不限于注入技术。掩模结构被除去。
保护层28在电介质层26上形成。保护层28可以是厚度在约500
Figure G2010100040212D00043
到约2,000
Figure G2010100040212D00044
范围内的氮化硅。根据一实施方式，电介质层26具有约300的厚度，且保护层28具有约1,000
Figure G2010100040212D00046
的厚度。优选地，选择层26和层28的材料以使得保护层28限制氧扩散，并因此防止下面的层被氧化。尽管保护层28被显示为单层材料，但其也可是不同材料类型的多层结构。外延层20通过加热到在约1,000摄氏度(℃)到约1,200℃范围内的温度来退火。使外延层20退火驱使掺杂层的杂质材料形成掺杂区30，掺杂区30又称为主体区。
厚度在约1,000
Figure G2010100040212D00047
到约5,000范围内的电介质材料层32在保护层28上形成。电介质层32用作硬掩模(hardmask)。作为举例，电介质材料层32是由厚度约为2,000的原硅酸四乙酯(tetraethylorthosilicate)(TEOS)分解形成的氧化物。由TEOS分解形成的氧化物层称为TEOS层。可替换地，TEOS层32可称为硬掩模层或TEOS硬掩模层。将光刻胶层图案化(patterned)在TEOS层32上，以形成具有掩模构件34和暴露TEOS层32的部分的开口36的掩模结构33。掩模结构34又称为刻蚀掩模。除去TEOS层32的被暴露的部分，形成暴露保护层28的部分的开口38。除去掩模结构33。
现在参考图2，通过除去保护层28的被暴露的部分以及除去电介质层26的和外延层20的在保护层28的被暴露的部分下面的部分，而在外延层20中形成具有侧壁42和底44的槽40和40A。应注意，为清楚起见，将参考符号“A”附加到了与主体区30横向隔开的槽。尽管槽40A与槽40相似，但槽40A用作栅接触(gate contact)的一部分。层28、26和20的部分可采用各向异性刻蚀技术比如，例如反应离子刻蚀来除去。尽管槽40和槽40A显示为终止于外延层20，但此并不是本发明的限制。例如，槽40和40A可延伸到衬底18中。刻蚀技术、槽的个数以及在外延层20中形成的槽的形状都不是本发明的限制。TEOS层32采用，例如，湿法剥离技术(wet stripping technique)来除去。优选地，厚度在约750到约1,500
Figure G2010100040212D00052
范围内的牺牲氧化层(没有显示)在槽40和40A的侧壁42和底44上形成。作为举例，牺牲氧化层具有约1,000的厚度。使用稀释的氢氟酸溶液除去牺牲氧化层，暴露槽40和40A的侧壁42和底44。栅电介质材料在槽40和40A的侧壁42和底44上形成。优选地，栅电介质材料46是厚度在约50
Figure G2010100040212D00054
到约300
Figure G2010100040212D00055
范围内的氧化物。应注意，保护层28中的开口的宽度可在约0.2微米(μm)到约1.0μm范围内，采用箭头48表示，而保护层28中的相邻开口之间的间距或距离在约0.8μm到约3.0μm的范围内，取决于器件的理想的工作电压，用箭头50表示。
现在参考图3，导电材料层比如，例如厚度在约250到约1,000
Figure G2010100040212D00057
范围内的多晶硅52在栅氧化物层46上以及在氮化硅保护层28的剩余部分的上面形成。为清楚起见，氮化硅保护层28的剩余部分统称为氮化硅保护层28或保护层28。作为举例，多晶硅层52具有约500
Figure G2010100040212D00058
的厚度，并且用N型杂质材料，比如磷来掺杂。可替换地，多晶硅52用P型杂质材料比如，例如砷来掺杂。
现在参考图4，多晶硅层52被各向异性地刻蚀，以沿侧壁42在栅氧化物层46的部分的上面形成间隔体(spacer)54。多晶硅间隔体54和栅氧化物层46形成栅结构。厚度在约250到约1,000范围内的电介质材料层56在多晶硅间隔体54上、在栅氧化物层46的在底44上面的部分上以及在氮化硅保护层28的上面形成。根据一实施方式，电介质层56是厚度约为500的氮化硅。
现在参考图5，氮化硅层56被各向异性地刻蚀，以在多晶硅间隔体54的上面形成间隔体58。各向异性地刻蚀多晶硅和氮化硅层的技术是本领域技术人员所熟知的。厚度在约2,000
Figure G2010100040212D00064
到约10,000
Figure G2010100040212D00065
范围内的电介质材料层生长在没有氮化物保护的区域上。作为举例，电介质材料层是通过湿性环境中的氧化作用形成的氧化物，该环境加厚底44上面的电介质材料。底44上面的加厚了的氧化物层由参考符号60识别。
现在参考图6，采用选择性地除去保护层28的材料的湿法刻蚀剂(wet etchant)，亦即当保护层28是氮化硅时除去氮化硅的湿法刻蚀剂，将保护层28从氧化物层26上去除。另外，所述湿法刻蚀剂还除去氮化硅间隔体58。采用例如化学气相沉积(CVD)在槽40和40A中以及在电介质层46的上面形成低电阻材料层62。优选地，所述低电阻材料是耐火的金属硅化物比如，例如硅化钨。
现在参考图7，硅化钨层62被刻蚀掉，硅化钨插塞64留在槽40和40A中。光刻胶层图案化在硅化钨插塞64、氧化物层26以及多晶硅间隔体54和栅电介质层46的被暴露的部分的上面，以形成具有掩模构件68和将氧化物层26的部分暴露的开口70的掩模结构66。掩模结构66又称为注入掩模。然后，N型传导性的掺杂区或掺杂层72在外延层20的无掩模构件68保护的部分中，亦即外延层20的在电介质层26的由开口70所暴露的部分下面的区域中形成。根据一实施方式，掺杂区72通过注入N型传导性杂质材料比如，例如剂量在约1×1014原子/cm2到约5×1016原子/cm2范围内并且注入能量在约20keV到约500keV范围内的磷或砷而形成。掺杂区72从表面14延伸到外延层20中，延伸的垂直距离小于主体区30延伸到外延层20中的垂直距离，并且所述掺杂区72用作源区。除去掩模结构66。
现在参考图8，厚度在约1,000
Figure G2010100040212D00071
到约3,000
Figure G2010100040212D00072
范围内的电介质材料层74在氧化物层26以及栅电介质层46、多晶硅间隔体54和硅化钨插塞64的被暴露的部分的上面形成。根据一实施方式，电介质层74的材料是厚度约为2,000的TEOS。厚度在约1,000
Figure G2010100040212D00074
到约3,000
Figure G2010100040212D00075
范围内的氮化硅层76在TEOS层74上形成。优选地，氮化硅层76具有约2,000
Figure G2010100040212D00076
的厚度。光刻胶层图案化在氮化硅层76的上面，以形成具有掩模构件78和将氮化硅层76的部分暴露的开口80的掩模结构77。掩模结构77又称为刻蚀掩模。
现在参考图9，除去氮化硅层76的被暴露的部分和TEOS层74的在氮化硅层76的被暴露的部分下面的部分，以形成暴露外延层20在相邻槽40之间的部分的开口。作为举例，采用各向异性反应离子刻蚀除去氮化硅层76的部分和TEOS层74的部分。可选地，可调整各向异性刻蚀以使TEOS层74的一部分保留在开口中而用作屏蔽氧化物(screen oxide)。除去掩模结构77。根据一实施方式，通过将N型传导性杂质材料比如，例如剂量在约1×1014原子/cm2到约5×1016原子/cm2范围内，注入能量在约5keV到约30keV范围内的磷或砷注入源区72，而形成掺杂区82。掺杂区82从表面14延伸到源区72中，延伸的垂直距离小于源区72延伸到外延层20中的垂直距离，掺杂区82增加了源区72的杂质材料浓度，并用作增强型源区。
仍然参考图9，厚度在约250
Figure G2010100040212D00077
到约1,000
Figure G2010100040212D00078
范围内的氮化硅层84在外延层20的被暴露的部分上和氮化硅层76上形成。优选地，氮化硅层84具有约500
Figure G2010100040212D00079
的厚度。
现在参考图10，氮化硅层84被各向异性地刻蚀，以沿氮化硅层76和TEOS层74形成间隔体86。采用各向异性刻蚀技术比如，例如反应离子刻蚀形成延伸穿过主体区30和外延层20的具有侧壁92和底94的槽90。尽管槽90显示为延伸穿过主体区30和外延层20进入衬底18中，此并不为本发明的限制。例如，槽90可延伸穿过主体区30并终止或结束在外延层20中。优选地，槽90在相邻的槽40之间形成。因此，槽90与槽40交替相间。厚度在约500
Figure G2010100040212D00081
到约10,000
Figure G2010100040212D00082
范围内的电介质材料层98在底94上、沿侧壁92、沿氮化硅间隔体86以及在氮化硅层76上形成。厚度在约1,000
Figure G2010100040212D00083
到约3,000
Figure G2010100040212D00084
范围内的导电层100在电介质层98上形成。作为举例，槽90内的电介质层98的材料是厚度约为600
Figure G2010100040212D00085
的TEOS，而导电层100是用P型杂质材料比如硼掺杂的并且厚度约为2,000
Figure G2010100040212D00086
的多晶硅。可替换地，导电层100的材料是用N型杂质材料掺杂的多晶硅，或者其可为任何数量的其他传导性材料或传导性材料的组合。
现在参考图11，多晶硅层100被回蚀，以在槽90中形成多晶硅插塞102。应注意，多晶硅插塞102通过电介质层98与外延层20和掺杂区30、72以及82隔开，并用作场板。
现在参考图12，采用湿法刻蚀剂各向异性地刻蚀电介质层98以使电介质层98的部分凹进去，由此形成在多晶硅插塞102和掺杂区30、72以及82之间的间隙104。优选地，间隙104从表面14垂直地延伸到侧壁92的与主体区30横向相邻的部分。间隙104暴露多晶硅插塞102的侧壁和侧壁92的部分。
现在参考图13，厚度在约250
Figure G2010100040212D00087
到约1,000范围内的多晶硅层106在间隙104中、在多晶硅插塞102和氮化硅层76的上面以及邻接氮化硅间隔体86而形成。多晶硅层106可不掺杂或用N型传导性或P型传导性杂质材料掺杂。间隙104延伸到主体区30中的深度不是本发明的限制。
现在参考图14，多晶硅层106被刻蚀，指状体或部分108留在间隙104中。部分108将主体区30电连接到场板102。优选地，执行退火，使杂质材料从部分108横向扩散到主体区30中和多晶硅插塞102中。
现在参考图15，氮化硅间隔体86和邻近氮化硅间隔体86的氮化硅层76被刻蚀，以为形成交错的台阶接触区做准备。应注意，形成交错的台阶接触区是可选的。光刻胶层图案化在氮化硅层76、多晶硅插塞102、多晶硅指状体108以及交错的台阶上面，以形成具有掩模构件114和开口116的掩模结构112，开口116暴露氮化硅层76在槽40A上面的部分，即与主体区30横向隔开的槽上面的部分。掩模结构112又称为刻蚀掩模。电介质层76的被暴露的部分和电介质层74在电介质层76的被暴露的部分下面的部分被各向异性地刻蚀，以暴露槽40A中的硅化钨插塞64和多晶硅间隔体54。除去掩模结构112。
现在参考图16，耐火金属120被共形地沉积在氮化硅层76、交错台阶接触区、增强型源区82、多晶硅插塞102以及多晶硅指状体108的上面。导电材料层122在金属层120的上面形成。作为举例，耐火金属是钛-氮化钛双层(titaniu m-titanium nitride bilayer)，而导电层122可为厚度在约0.4μm到约5μm的范围内的铝合金。光刻胶层图案化在导电层122上，以形成具有掩模构件126和开口128的掩模结构124。掩模结构124又称为刻蚀掩模。因此，部分108和导电层120和122形成自对准电连接或自对准电接触，其将多晶硅插塞或场板102与主体区30和源区72电连接。
现在参考图17，导电材料122的被暴露的部分和耐火金属层120在导电材料122的被暴露的部分下面的部分被刻蚀，以将栅接触130与源-主体-场板接触(source-body-field plate contact)132电隔离。除去掩模结构124。
图18是根据本发明的实施方式的半导体元件10的俯视图。图18所示出的是与源-主体-场板接触140交替相间的栅区132。栅区132延伸到栅接触触头134。另外，图18显示出槽终止区142和边封接触区144。
至此，应认识到，提供了具有槽栅结构和形成在槽中的场板的半导体元件10和用于制造所述半导体元件的方法。槽栅结构和用于场板的槽延伸穿过主体区。因此，栅结构和场板在分离的槽中形成。此外，用于场板的槽延伸穿过源区。使用自对准的导电材料，场板电连接到主体区和源区。因为源和主体接触是在场板槽范围内自对准的，并且导电材料与场板、主体区以及源区相连，所以其又称为一体化的自对准接触、一体化自对准电接触、结合在一起的自对准接触或者结合在一起的自对准电接触。使用一体化自对准接触的优点是其在不采用复杂的或昂贵的处理步骤的情况下，允许通过形成垂直接触表面而不是横向接触表面而形成具有小几何结构的半导体元件。
尽管在此公开了一些优选的实施方式和方法，但对于本领域中的技术人员来说很明显的是，依据前述的公开，可对上述实施方式和方法做出变化和修改而不偏离本发明的主旨和范围。例如，半导体器件可以是垂直器件或者横向器件。本发明旨在只限于由所附权利要求书和适用法律的规则和法则要求的范围。

Claims (10)

1.一种用于制造半导体元件的方法，包括如下步骤：
提供具有第一主表面和第二主表面以及具有主体区的半导体材料；
在所述半导体材料中形成第一槽，所述第一槽具有至少一个侧壁；
在所述第一槽的一部分中形成栅结构；
邻近所述第一槽形成源区；
在所述半导体材料中形成第二槽，所述第二槽延伸穿过所述源区的一部分并且具有侧壁；
在所述第二槽的一部分中形成导电材料；以及
形成自对准的电连接，所述自对准的电连接将所述第二槽中的导电材料与所述源区和所述主体区电连接。
2.如权利要求1所述的方法，还包括：
在所述第二槽中形成第一电介质材料层，并在所述第一电介质材料层上面的多晶硅和所述第二槽的侧壁之间形成间隙。
3.如权利要求2所述的方法，其中形成间隙的步骤包括：除去所述第一电介质材料层的在所述第一电介质材料层上面的多晶硅和所述第二槽的侧壁之间的一部分，并在所述间隙中形成多晶硅。
4.如权利要求3所述的方法，其中用第一传导类型的杂质材料掺杂所述间隙中的多晶硅，并将所述杂质材料从所述间隙中的多晶硅横向扩散到所述半导体材料中。
5.如权利要求1所述的方法，还包括提高所述源区的一部分的掺杂浓度，并且其中形成第二槽的步骤包括：穿过所述源区中掺杂浓度提高了的所述部分而形成所述第二槽。
6.一种用于制造半导体元件的方法，其包括如下步骤：
提供半导体材料；
在所述半导体材料中形成第一槽；
在所述第一槽中形成栅结构；
在所述半导体材料的与所述第一槽相邻的一部分中形成第一传导类型的掺杂区；
邻近所述第一槽形成场板，所述场板延伸到所述掺杂区中；以及
形成到所述掺杂区和所述场板的自对准的电接触。
7.如权利要求6所述的方法，其中形成场板的步骤包括：
在所述半导体材料中形成第二槽，所述第二槽具有侧壁；
在所述第二槽的侧壁上面形成第一电介质材料层；
在所述第二槽的侧壁上面形成多晶硅；以及
还包括使所述第一电介质材料层的一部分凹进去以形成间隙。
8.如权利要求7所述的方法，还包括在所述间隙中形成多晶硅，并增加所述第一传导类型的掺杂区的浓度。
9.一种半导体元件，包括：
半导体材料，具有第一主表面和第二主表面；
栅结构，延伸到所述半导体材料中；
源区，与所述栅结构相邻；
场板，延伸穿过所述源区；以及
自对准接触，与所述场板和所述源区接触。
10.如权利要求9所述的半导体元件，其中所述栅结构包括：
第一槽，从所述第一主表面延伸到所述半导体材料中，所述第一槽具有侧壁和底；
第一电介质材料层，在所述第一槽的侧壁和底上形成；
第一导电材料，在所述第一电介质材料层上形成；以及还包括源区，所述源区与所述第一槽相邻，并且从所述第一主表面延伸到所述半导体材料中；并且其中所述场板包括：
第二槽，穿过所述源区延伸到所述半导体材料中，所述第二槽具有侧壁和底；
第二电介质材料层，在所述侧壁的部分上和所述底的上面形成；
第二导电材料，在所述第二电介质材料层的一部分上形成；
间隙，填充有第三导电材料，被填充的所述间隙在所述第二槽的侧壁的一部分和所述第二导电材料之间；以及
第四导电材料，与所述半导体材料、所述第二导电材料以及所述第三导电材料电接触。
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