WO2014048226A1 - Fs型绝缘栅型双极晶体管的制造方法 - Google Patents

Fs型绝缘栅型双极晶体管的制造方法 Download PDF

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WO2014048226A1
WO2014048226A1 PCT/CN2013/082822 CN2013082822W WO2014048226A1 WO 2014048226 A1 WO2014048226 A1 WO 2014048226A1 CN 2013082822 W CN2013082822 W CN 2013082822W WO 2014048226 A1 WO2014048226 A1 WO 2014048226A1
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substrate
layer
type
manufacturing
bipolar transistor
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PCT/CN2013/082822
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English (en)
French (fr)
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黄璇
王根毅
邓小社
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无锡华润上华半导体有限公司
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Publication of WO2014048226A1 publication Critical patent/WO2014048226A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Definitions

  • the present invention relates to the field of integrated circuit manufacturing, and more particularly to manufacturing a field stop type by using a direct bonding method.
  • Stop abbreviated as FS type
  • IGBT insulated gate bipolar transistor
  • the IGBT is a composite fully-regulated voltage-driven power semiconductor device composed of a BJT (bipolar transistor) and a MOS (insulated gate field effect transistor), which combines the high input impedance of the MOSFET and the low on-voltage drop of the GTR.
  • BJT bipolar transistor
  • MOS insulated gate field effect transistor
  • the preparation difficulty of the FS type IGBT is the preparation of the back side N + buffer layer (ie, the Field Stop layer).
  • the back side N + buffer layer is prepared by using the implantation or pre-expansion and high temperature push-trap. After that, the front structure process is prepared.
  • the wafer needs to be thinned to less than 200um before the preparation of the front structure.
  • the present invention has been made in view of the above problems, and proposes a manufacturing method of a field-stop type insulated gate bipolar transistor (i.e., FS type IGBT) which does not require a dedicated preparation apparatus, is compatible with a conventional process, and has a simple process.
  • a field-stop type insulated gate bipolar transistor i.e., FS type IGBT
  • the termination layer removal step of the termination layer is removed.
  • the prescribed thickness of the second substrate used is such that the first substrate, the second substrate, and the termination layer after the thinning step
  • the sum of the thicknesses is a conventional silicon wafer thickness.
  • the conventional silicon wafer has a thickness of 100 to 800 ⁇ m.
  • the first substrate forming step comprises the following steps in sequence:
  • a second conductive type layer is formed on a lower surface of the first conductive type layer.
  • the following steps are sequentially included:
  • the second substrate is etched by wet etching, and etching stops until the termination layer.
  • the termination layer is formed by thermal oxidation or CVD deposition or the like.
  • a termination layer having a thickness of 200 to 50,000 ⁇ is formed.
  • the drift layer of the first conductivity type is thinned to 10 to 600 ⁇ m.
  • the termination layer is removed by wet etching.
  • the termination layer is an oxide layer
  • the first conductivity type is an N type
  • the second conductivity type is a P type.
  • the FS type IGBT is manufactured by using a direct bonding method (SDB), and the thickness of the bonded silicon wafer is the same as that of the conventional silicon wafer, and therefore, Some conventional processes are compatible, and it is possible to manufacture ultra-thin FS-type IGBTs using a process line of a conventional product without a sheet device, which has the advantages of simple process, low cost, and high efficiency.
  • SDB direct bonding method
  • 1, 2, and 3 are schematic views showing the formation of the first substrate 100 in the method of fabricating the FS-type insulated gate bipolar transistor according to the embodiment of the present invention.
  • FIG 4 is a schematic view showing the formation of the termination layer 200 in the method of manufacturing the FS-type insulated gate bipolar transistor according to the embodiment of the present invention.
  • Fig. 5 is a schematic view showing the formation of the second substrate 300 in the method of manufacturing the FS-type insulated gate bipolar transistor according to the embodiment of the present invention.
  • FIG. 6 is a schematic view showing a thinning process of the first conductivity type drift layer 101 in the first substrate 100 in the method of manufacturing the FS type insulated gate bipolar transistor according to the embodiment of the present invention.
  • FIG. 7 is a schematic view showing the formation of an IGBT front surface structure on a first substrate 100 in a method of manufacturing an FS-type insulated gate bipolar transistor according to an embodiment of the present invention.
  • FIG 8 is a schematic view showing a state in which the second substrate 200 is removed in the method of manufacturing the FS-type insulated gate bipolar transistor according to the embodiment of the present invention.
  • Fig. 9 is a view showing a state in which the termination layer 300 is removed in the method of manufacturing the FS-type insulated gate bipolar transistor according to the embodiment of the present invention.
  • 1, 2, and 3 are schematic views showing the formation of the first substrate 100 in the method of fabricating the FS-type insulated gate bipolar transistor according to the embodiment of the present invention.
  • 4 is a schematic view showing the formation of the termination layer 200 in the method of manufacturing the FS-type insulated gate bipolar transistor according to the embodiment of the present invention.
  • Fig. 5 is a schematic view showing the formation of the second substrate 300 in the method of manufacturing the FS-type insulated gate bipolar transistor according to the embodiment of the present invention.
  • 6 is a schematic view showing a thinning process of the first conductivity type drift layer 101 in the first substrate 100 in the method of manufacturing the FS type insulated gate bipolar transistor according to the embodiment of the present invention.
  • FIG. 7 is a schematic view showing the formation of an IGBT front surface structure on a first substrate 100 in a method of manufacturing an FS-type insulated gate bipolar transistor according to an embodiment of the present invention.
  • 8 is a schematic view showing a state in which the second substrate 200 is removed in the method of manufacturing the FS-type insulated gate bipolar transistor according to the embodiment of the present invention.
  • Fig. 9 is a view showing a state in which the termination layer 300 is removed in the method of manufacturing the FS-type insulated gate bipolar transistor according to the embodiment of the present invention.
  • the silicon wafer on which the drift layer 101 of the first conductivity type is formed is implanted or pre-expanded to prepare the first conductivity type layer 102 described below.
  • the drift layer 101 of the first conductivity type is an N ⁇ drift layer
  • 102 is an N + layer.
  • the N + layer as the first conductive type layer 102 can be prepared by implanting P or As or the like during the implantation.
  • the second step after completing the first step shown in FIG. 2, the silicon wafer is pushed to the well, and the temperature and time of the push trap are controlled to prepare the first conductive type layer 102 having the thickness corresponding to the requirement.
  • the silicon wafer In the mode, it is an N + layer, and the N + layer serves as an electric field cutoff layer of the FS type IGBT.
  • a collector layer 103 is formed on the back surface of the silicon wafer, that is, the lower surface of the first conductive type layer 102.
  • the collector layer 103 is a P+ layer which serves as a collector of the IGBT.
  • the manner in which the collector layer 103 is formed is, for example, an implantation method or a diffusion method.
  • a silicon wafer in which the drift layer 101 of the first conductivity type, the first conductivity type layer 102, and the collector layer 103 are formed is referred to as a first substrate 100.
  • a termination layer 200 is formed on the back surface of the first substrate 100, that is, the lower surface of the collector layer 103.
  • the termination layer 200 an oxide layer is formed by thermal oxidation or CVD deposition.
  • the thickness of the termination layer 200 can be designed to be 200 to 50000 ⁇ , but this is not limited, and the thickness can be designed according to actual needs.
  • the termination layer 200 composed of an oxide will serve as an end point of the etching stop when the second substrate 300 described below is removed in the subsequent eighth step, and the termination layer 200 can be used to accurately control the corrosion thinning. thickness.
  • Step 5 As shown in Figure 5, using direct bonding (Silicon Direct) Bonding (SDB for short) bonds the first substrate 100 and the second substrate 300 together.
  • the thickness of the second substrate 300 is designed such that the thickness of the entire silicon wafer after completion of the sixth step described below is the thickness of the conventional silicon wafer (here, the conventional silicon wafer refers to a general silicon wafer, which is not ultra-thin.
  • the silicon wafer for example, a conventional silicon wafer having a thickness of 100 to 800 ⁇ m). This is because the thickness of the silicon wafer of the ultra-thin FS type IGBT is ultra-thin compared to the general IGBT.
  • the two substrates 300 are capable of temporarily converting the thinner first substrate 100 into a thicker silicon wafer, so that an ultrathin IGBT can be manufactured using a general slab (conventional silicon wafer) manufacturing apparatus without It is necessary to separately use a sheet device, and therefore, it has the advantage of being compatible with the existing conventional processes and reducing the production cost.
  • the direct bonding method means that the two silicon wafers are directly bonded together by high-temperature processing, and does not require any binder and an applied electric field, and the process is simple. This bonding technique is also called direct bonding of silicon-silicon.
  • the direct bonding process is as follows:
  • the two substrates to be bonded are treated at a high temperature for several hours in an oxygen or nitrogen atmosphere, thus forming a good bond.
  • the mechanism of direct bonding can be described by a three-stage bonding process.
  • the surface of the silicon wafer of the two substrates adsorbs OH groups, and hydrogen bonds are generated in the mutual contact regions.
  • a polymerization reaction occurs between the silicon-silicon bonds of the two silicon wafers forming hydrogen bonds, resulting in water and silicon-oxygen bonds, ie
  • the temperature is in the range of 500-800 ° C, and the water generated in the formation of the silicon-oxygen bond does not diffuse into the SiO 2 , and the OH group can break a bond of the bridging oxygen atom to transform it into a non-bridged oxygen atom.
  • the diffusion of water into SiO 2 becomes remarkable, and the diffusion amount increases exponentially with an increase in temperature.
  • the water molecules at the voids and gaps of the bonding interface can diffuse into the surrounding SiO 2 at a high temperature, thereby generating a partial vacuum, so that the silicon sheet undergoes plastic deformation to eliminate the void.
  • the viscosity of SiO 2 at this temperature is lowered, and viscous flow occurs, thereby eliminating micro-gap.
  • it exceeds 1000 ° C adjacent atoms react with each other to form a covalent bond, so that the bonding is completed.
  • the termination layer 200 ie, the oxide layer
  • the oxide layer can serve as an isolation layer to reduce impurity ions of the second substrate layer, voids and defects during bonding, etc.
  • the effect of a conductive type layer 102 therefore, by providing the termination layer 200, reduces the process requirements for direct bonding, simplifying the process steps.
  • Step 6 As shown in FIG. 6, after the direct bonding, the drift layer 101 of the first conductivity type is thinned and thinned to a thickness required for designing the FS type IGBT, for example, 10 to 600 ⁇ m. Then, the thinned first conductivity type drift layer 101 is subjected to CMP planarization to facilitate preparation of the front surface structure of the IGBT on the front side of the first substrate 100.
  • Step 7 Prepare the front structure of the IGBT on the front side of the silicon wafer.
  • the front structure of the IGBT shown in FIG. 7 includes: Pbody from bottom to top. 401, an N+ layer 402, a gate oxide layer 403, a gate electrode poly layer 404, a dielectric layer 405, and a metal layer 406.
  • the second substrate 300 is removed.
  • the specific step of removing the second substrate 300 includes: first thinning the thickness of the second substrate 300; and then removing the second substrate 300 having a reduced thickness by wet etching.
  • the termination layer 200 is used as the etching end point, so that the etching stops at the termination layer, whereby all the second substrates 300 can be accurately removed, and thus, The thickness of the corrosion can be accurately controlled using the termination layer 200.
  • the first conductivity type is an N type
  • the second conductivity type is a P type
  • the first conductivity type may be a P type
  • the second conductivity type may be an N type
  • the thickness of the silicon wafer after bonding in the manufacturing process is consistent with the thickness of the conventional silicon wafer, and therefore, Compatible with existing conventional processes, it is possible to manufacture ultra-thin FS-type IGBTs using a process line of a conventional product without a sheet device.
  • the termination layer 200 the thickness of the thinning corrosion can be accurately controlled, and the termination layer 200 can serve as an isolation layer to prevent bonding interface states, voids, and impurity ions to the first conductive type layer 102 in the direct bonding mode.
  • the method for manufacturing the field-stopping insulated gate bipolar transistor of the present invention has the advantages of simple process, low cost, and high efficiency.

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Abstract

提供一种FS型绝缘栅双极晶体管（IGBT）的制造方法，该方法依次具备下述步骤：形成第一衬底（100）的第一衬底形成步骤；在所述第一衬底（100）的背面形成终止层（200）的终止层形成步骤；将所述第一衬底（100）通过所述终止层（200）与规定厚度的第二衬底（300）利用直接键合方式键合在一起的键合步骤；将所述第一衬底（100）的厚度减薄的减薄步骤；以及在所属第一衬底（100）形成IGBT的正面结构的正面结构形成步骤；以所述终止层（200）为终点去除所述第二衬底（300）的第二衬底去除步骤；去除所述终止层（200）的终止层去除步骤。根据上述方法，能与现有的常规工艺兼容，工艺简单，效率高，无需专用的设备，能够重复降低工艺成本。

Description

FS 型绝缘栅型双极晶体管的制造方法
【技术领域】
本发明涉及集成电路制造领域，尤其涉及一种利用直接键合方式制造场中止型（Field Stop，简称为FS型）绝缘栅型双极晶体管（Insulated Gate Bipolar Transistor，简称为IGBT）的制造方法。
【背景技术】
IGBT是由BJT(双极型三极管)和MOS(绝缘栅型场效应管)组成的复合全控型电压驱动式功率半导体器件，兼有MOSFET的高输入阻抗和GTR的低导通压降两方面的优点。GTR饱和压降低，载流密度大，但驱动电流较大；MOSFET驱动功率很小，开关速度快，但导通压降大，载流密度小。IGBT综合了以上两种器件的优点，驱动功率小而饱和压降低。
在IGBT中，有一种可以有效降低产品的导通压降和应用温度的FS（Field Stop，场中止）型IGBT。FS型IGBT的制备难点为背面N+ 缓冲层（即Field Stop层）的制备，现有制备方法有两种：第一种，先利用注入或预扩和高温推阱制备背面N+ 缓冲层层之后再制备正面结构工艺，对于低压IGBT（1700V以下）正面结构制备前就需要将圆片减薄到200um以下，这就要求生产线有薄片通线能力，因此需要专用的薄片流通设备；第二种，先完成正面结构制备再完成背面N+ 缓冲层，而这需要专用的高能离子注入设备或特殊元素注入，这种设备注入能量高达1~8Mev。
不论上述哪种方式都需要价格高昂的专用设备，增加了FS型IGBT 的工艺制造成本。
【发明内容】
本发明鉴于上述问题提出一种无需专用的制备设备、能够与常规工艺兼容且工艺简单的制造场中止型绝缘栅型双极晶体管（即，FS型IGBT）的制造方法。
本发明的FS型绝缘栅型双极晶体管的制造方法，其特征在于，依次具备下述步骤：
形成第一衬底的第一衬底形成步骤；
在所述第一衬底的背面形成终止层的终止层形成步骤；
将所述第一衬底通过所述终止层与规定厚度的第二衬底利用直接键合方式键合在一起的键合步骤；
将所述第一衬底的厚度减薄的减薄步骤；以及
在所述第一衬底形成IGBT的正面结构的正面结构形成步骤；
以所述终止层为重点去除所述第二衬底的第二衬底去除步骤；
去除所述终止层的终止层去除步骤。
优选地，在所述键合步骤中，所采用的第二衬底的规定厚度为使得在所述减薄步骤之后的所述第一衬底、所述第二衬底、所述终止层的厚度总和为常规的硅片厚度。
优选地，所述常规的硅片厚度为100～800μm。
优选地，所述第一衬底形成步骤依次包括下述步骤：
在第一导电类型的衬底背面形成第一导电类型的漂移层；
在所述第一导电类型的漂移层下表面形成第一导电类型层；以及
在第一导电类型层的下表面形成第二导电类型层。
优选地，在所述第二衬底去除步骤中依次包括下述步骤：
将所述第二衬底减薄；
利用湿法腐蚀所述第二衬底，腐蚀停止到所述终止层为止。
优选地，在所述终止层形成步骤中，利用热氧化或者CVD淀积等的方式形成终止层。
优选地，在所述终止层形成步骤中，形成厚度为200～50000Å的终止层。
优选地，在所述减薄步骤中，将所述第一导电类型的漂移层减薄到10～600μm。
优选地，在所述终止层去除步骤中，利用湿法腐蚀去除所述终止层。
优选地，所述终止层是氧化物层，所述第一导电类型是N型，所述第二导电类型是P型。
根据上述本发明的FS型绝缘栅型双极晶体管的制造方法，通过采用直接键合方式（SDB）制造FS型IGBT，键合的硅片厚度与常规的硅片厚度一致，因此，能够与现有的常规工艺兼容，不需要薄片设备就能够采用常规产品的工艺线来制造超薄的FS型的IGBT，具有工艺简单、成本低、效率高的优点。
【附图说明】
图1、图2、图3表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中形成第一衬底100的示意图。
图4是表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中形成了终止层200的示意图。
图5是表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中形成了第二衬底300的示意图。
图6是表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中对第一衬底100中的第一导电类型的漂移层101进行了减薄处理后的示意图。
图7是表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中在第一衬底100形成IGBT正面结构的示意图。
图8是表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中去除了第二衬底200后的示意图。
图9是表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中去除了终止层300后的示意图。
【具体实施方式】
下面介绍的是本发明的多个实施例中的一些，旨在提供对本发明的基本了解。并不旨在确认本发明的关键或决定性的要素或限定所要保护的范围。
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明作进一步的详细描述。
图1、图2、图3表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中形成第一衬底100的示意图。图4是表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中形成了终止层200的示意图。图5是表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中形成了第二衬底300的示意图。图6是表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中对第一衬底100中的第一导电类型的漂移层101进行了减薄处理后的示意图。图7是表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中在第一衬底100形成IGBT正面结构的示意图。图8是表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中去除了第二衬底200后的示意图。图9是表示本发明实施例的FS型绝缘栅型双极晶体管的制造方法中去除了终止层300后的示意图。
下面参照图1～图9对于本发明的FS型绝缘栅型双极晶体管的制造方法进行具体说明。
第一步：如图1所示，对形成有第一导电类型的漂移层101的硅片进行注入或预扩，制备下述的第一导电类型层102。在本实施方式中，第一导电类型的漂移层101为N－漂移层，102为N+层。在注入过程中可以通过注入P或As等来制备作为第一导电类型层102的N+层。
第二步：如图2所示在完成图1所示的第一步后，对硅片进行推阱，控制推阱温度及时间制备出厚度符合需求的第一导电类型层102，在本实施方式中为N+层，N+层作为FS型IGBT的电场截止层。
第三步：如图3所示，在硅片的背面，即第一导电类型层102的下表面形成集电极层103。在本实施方式中，集电极层103是P＋层，它作为IGBT的集电极。形成集电极层103的方式有例如注入方式或是扩散方式。在本发明中将形成有第一导电类型的漂移层101、第一导电类型层102、集电极层103的硅片称作为第一衬底100。
第四步：如图4所示，在第一衬底100的背面，即集电极层103的下表面形成终止层200。在本发明中，作为终止层200，利用热氧化或是CVD淀积方式形成一层氧化物层。终止层200的厚度可以设计为200~50000Å，但对此不做限定，可以按实际需求来设计其厚度。在本发明中，由氧化物构成的终止层200将在后续的第八步中作为去除下述的第二衬底300时的腐蚀停止终点，利用该终止层200能够准确地控制腐蚀减薄的厚度。
第五步：如图5所示，利用直接键合方式（Silicon Direct Bonding，简称SDB）把第一衬底100和第二衬底300键合在一起。这里，第二衬底300的厚度设计为，要使得在下述的第六步完成后的整个硅片的厚度为常规硅片的厚度（这里的常规硅片是指一般的硅片，非超薄的硅片，例如，常规的硅片厚度为100～800μm）。这是因为超薄的FS型IGBT相比于一般的IGBT，其硅片的厚度是超薄的，因此一般制造FS型IGBT是需要特殊的薄片设备才能完成，而在本发明中通过键合第二衬底300，能够暂时将较薄的第一衬底100变换成较厚的硅片，这样，就能够利用一般厚片（常规硅片）的制造设备来制造超薄型的IGBT，而不需要另行采用薄片设备，因此，具有能够与现有的常规工艺兼容、降低生产成本的优点。
直接键合方式是指两硅片通过高温处理直接键合在一起，不需要任何粘结剂和外加电场、工艺简单，这种键合技术也称为硅-硅直接键合。
直接键合的工艺如下：
（1）将两枚衬底（在本发明中是形成有终止层200的第一衬底100以及第二衬底300）经含OH的溶液浸泡处理；
（2）在室温下将两枚衬底贴合在一起；
（3）将贴合好的两枚衬底在氧气或氮气环境中经数小时的高温处理，这样就形成了良好的键合。
直接键合的机理可用三个阶段的键合过程加以描述。
第一阶段，从室温到200°C，两衬底的硅片表面吸附OH团，在相互接触区产生氢键。在200°C时，形成氢键的两硅片的硅醇键之间发生聚合反应，产生水及硅氧键，即
　　Si-OH+HO-Si→ Si-O-Si+H2O。
到400°C时，聚合反应基本完成。
第二阶段温度在500~800°C范围内，在形成硅氧键时产生的水向SiO2中的扩散不明显，而OH团可以破坏桥接氧原子的一个键使其转变为非桥接氧原子，即：
HOH+Si-O-Si=2 +2Si- 。
第三阶段，温度高于800°C后，水向SiO2中扩散变得显著，而且随温度的升高扩散量成指数增大。键合界面的空洞和间隙处的水分子可在高温下扩散进入四周SiO2中，从而产生局部真空，这样硅片会发生塑性变形使空洞消除。同时，此温度下的SiO2粘度降低，会发生粘滞流动，从而消除了微间隙。超过1000°C时，邻近原子间相互反应产生共价键，使键合得以完成。
另外，在一般的直接键合工艺中，要求对两枚键合衬底的键合面做平整化处理以保证在键合面不会产生空洞、凹凸等问题。而在本发明中，由于形成有终止层200（即氧化层），在直接键合时，该氧化层能够作为隔离层降低第二衬底层的杂质离子、键合时产生空洞及缺陷等对第一导电类型层102的影响，因此，通过设置终止层200，降低了对直接键合的工艺要求，简化了工艺步骤。
第六步：如图6所示，在直接键合之后，对第一导电类型的漂移层101进行减薄，减薄到设计FS型IGBT所需要的厚度，例如10～600μm。然后，对该减薄后的第一导电类型的漂移层101进行CMP平坦化，以方便在第一衬底100正面制备IGBT的正面结构。
第七步：在硅片的正面制备IGBT的正面结构。作为IGBT的正面结构的一个示例，如图7所示IGBT的正面结构从下至上包括：Pbody 401、N＋层402、栅极氧化层403、栅电极poly层404、介质层405以及金属层406。
第八步：在形成了IGBT的正面结构之后，如图8所示，去除第二衬底300。去除第二衬底300的具体步骤包括：先将第二衬底300的厚度减薄；再将厚度减薄后的第二衬底300用湿法腐蚀方式进行去除。在用湿法腐蚀方式去除的第二衬底300的过程中，以终止层200为腐蚀终点，使得腐蚀停止于该终止层，由此，能够精确地去除全部的第二衬底300，因此，能够利用终止层200准确地控制腐蚀的厚度。
第九步：在去除了第二衬底300之后，如图9所示，利用湿法腐蚀去除背面的终止层200，从而得到完成的FS型IGBT。
另外，在本实施方式中，第一导电类型是N型，第二导电类型是P型，作为其他变换实施方式，也可以是第一导电类型是P型，第二导电类型是N型。
根据上述本发明的FS型绝缘栅型双极晶体管的制造方法，通过采用直接键合方式制造FS型IGBT，在制造过程中键合之后的硅片厚度与常规的硅片厚度一致，因此，能够与现有的常规工艺兼容，不需要薄片设备就能够采用常规产品的工艺线来制造超薄的FS型的IGBT。而且，通过形成终止层200，能够准确地控制减薄腐蚀的厚度，该终止层200在直接键合方式中能够作为隔离层防止键合的界面态、空洞、杂质离子对第一导电类型层102的负面影响，并且能够降低直接键合中对需要键合的硅片的键合面的要求。基于以上内容，本发明的场中止型绝缘栅型双极晶体管的制造方法具有工艺简单、成本低、效率高的优点。
以上例子主要说明了本发明利用直接键合方式制造FS型IGBT的制造方法。尽管只对其中一些本发明的具体实施方式进行了描述，但是本领域普通技术人员应当了解，本发明可以在不偏离其主旨与范围内以许多其他的形式实施。因此，所展示的例子与实施方式被视为示意性的而非限制性的，在不脱离如所附各权利要求所定义的本发明精神及范围的情况下，本发明可能涵盖各种的修改与替换。

Claims (11)

  1. 一种FS型绝缘栅型双极晶体管的制造方法，其特征在于，依次具备下述步骤：
    形成第一衬底的第一衬底形成步骤；
    在所述第一衬底的背面形成终止层的终止层形成步骤；
    将所述第一衬底通过所述终止层与规定厚度的第二衬底利用直接键合方式键合在一起的键合步骤；
    将所述第一衬底的厚度减薄的减薄步骤；以及
    在所述第一衬底形成IGBT的正面结构的正面结构形成步骤；
    以所述终止层为重点去除所述第二衬底的第二衬底去除步骤；
    去除所述终止层的终止层去除步骤。
  2. 如权利要求1所述的FS型绝缘栅型双极晶体管的制造方法，其特征在于，
    在所述键合步骤中，所采用的第二衬底的规定厚度为使得在所述减薄步骤之后的所述第一衬底、所述第二衬底、所述终止层的厚度总和为常规的硅片厚度。
  3. 如权利要求2所述的FS型绝缘栅型双极晶体管的制造方法，其特征在于，
    所述常规的硅片厚度为100～800μm。
  4. 如权利要求2所述的FS型绝缘栅型双极晶体管的制造方法，其特征在于，
    所述第一衬底形成步骤依次包括下述步骤：
    在第一导电类型的衬底背面形成第一导电类型的漂移层；
    在所述第一导电类型的漂移层下表面形成第一导电类型层；以及
    在第一导电类型层的下表面形成第二导电类型层。
  5. 如权利要求2所述的FS型绝缘栅型双极晶体管的制造方法，其特征在于，
    在所述第二衬底去除步骤中依次包括下述步骤：
    将所述第二衬底减薄；
    利用湿法腐蚀所述第二衬底，腐蚀停止到所述终止层为止。
  6. 如权利要求2所述的FS型绝缘栅型双极晶体管的制造方法，其特征在于，
    在所述终止层形成步骤中，利用热氧化或者CVD淀积的方式形成终止层。
  7. 如权利要求2所述的FS型绝缘栅型双极晶体管的制造方法，其特征在于，
    在所述终止层形成步骤中，形成厚度为200～50000Å的终止层。
  8. 如权利要求4所述的FS型绝缘栅型双极晶体管的制造方法，其特征在于，
    在所述减薄步骤中，将所述第一导电类型的漂移层减薄到10～600μm。
  9. 如权利要求2所述的FS型绝缘栅型双极晶体管的制造方法，其特征在于，
    在所述终止层去除步骤中，利用湿法腐蚀去除所述终止层。
  10. 如权利要求1～9中任意一项所述的FS型绝缘栅型双极晶体管的制造方法，其特征在于，
    所述终止层是氧化物层。
  11. 如权利要求4所述的FS型绝缘栅型双极晶体管的制造方法，其特征在于，所述第一导电类型是N型，所述第二导电类型是P型。
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