WO2016107234A1 - 横向绝缘栅双极型晶体管的制造方法 - Google Patents

横向绝缘栅双极型晶体管的制造方法 Download PDF

Info

Publication number
WO2016107234A1
WO2016107234A1 PCT/CN2015/090965 CN2015090965W WO2016107234A1 WO 2016107234 A1 WO2016107234 A1 WO 2016107234A1 CN 2015090965 W CN2015090965 W CN 2015090965W WO 2016107234 A1 WO2016107234 A1 WO 2016107234A1
Authority
WO
WIPO (PCT)
Prior art keywords
well
oxide layer
mini
layer
wafer
Prior art date
Application number
PCT/CN2015/090965
Other languages
English (en)
French (fr)
Inventor
黄枫
韩广涛
孙贵鹏
林峰
赵龙杰
林华堂
赵兵
刘理想
平梁良
陈凤英
Original Assignee
无锡华润上华半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润上华半导体有限公司 filed Critical 无锡华润上华半导体有限公司
Priority to US15/541,155 priority Critical patent/US9865702B2/en
Priority to JP2017535429A priority patent/JP6555552B2/ja
Publication of WO2016107234A1 publication Critical patent/WO2016107234A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Definitions

  • the present invention relates to semiconductor processes, and more particularly to a method of fabricating a laterally insulated gate bipolar transistor.
  • the lateral insulated gate bipolar transistor can increase the LDMOS area without adding SiOMOS area after adding a silicon dioxide mini-oxide structure to the drain side of the channel region.
  • the degradation problem of Idlin (linear leakage current) / Rdson (on-resistance) after the current and voltage test is solved.
  • the traditional process uses silicon nitride as a hard mask (hard Mask), growing silica through a furnace tube in a specific area (ie, LOCOS process).
  • silicon nitride can be used as a hard mask
  • lithography defines a region where a mini-oxide needs to be formed
  • silicon nitride in the region is etched away
  • silicon dioxide is grown in the furnace tube
  • silicon nitride is finally passed through phosphoric acid. Stripping.
  • this process has the following disadvantages: as shown in FIG. 1, a large amount of dislocation occurs at the edge of the active region of the device, which affects the reliability of the product.
  • a method for fabricating a laterally insulated gate bipolar transistor comprising the steps of: providing a shallow trench isolation structure formed on an N-type buried layer, an N-type buried layer, a first N-well on the N-type buried layer, and an N-type buried layer a first P-well wafer; a high-temperature oxide film is deposited on the first N-well, and the deposition temperature is 750-850 degrees Celsius; Performing a thermal push on the wafer, and photolithography and etching the high temperature oxide film to form a mini oxide layer; performing photolithography and ion implantation to form a second N well in the first N well And forming a second P well in the first N well and the first P well; Forming a gate oxide layer and a polysilicon gate in sequence, the gate oxide layer and the polysilicon gate extending to one end of the second P well in the first N well and the other end extending to the mini oxide layer on the second N well; Photolithography is performed to implant N-type ions between
  • the above method for manufacturing a laterally insulated gate bipolar transistor uses a high-temperature oxide film (HTO) process with a lower stress than a LOCOS process using a silicon nitride mask as a mask to reduce the electric field of the LDMOS surface. Edges do not generate dislocation.
  • HTO high-temperature oxide film
  • the HTO is densified, the wet etching rate of the high temperature oxide film is greatly reduced, and the high temperature oxide film etching is ensured.
  • the amount of corrosion of the retained mini-oxide in the subsequent cleaning process can be stably controlled, ensuring the stability of mass production and can be used for mass production.
  • Figure 1 is a photomicrograph of a misalignment at the edge of the active region
  • FIG. 2 is a flow chart showing a method of fabricating a laterally insulated gate bipolar transistor in an embodiment
  • FIG. 3 is a schematic cross-sectional structural view of a lateral insulated gate bipolar transistor after completion
  • step S110 is a flow chart of a specific implementation of step S110 in an embodiment.
  • the inventors have found through experiments that the traditional process of fabricating mini-oxides with LOCOS produces a large amount of dislocation at the edge of the active region because the mini-oxide is formed after the STI, while the LOCOS process deposits silicon nitride because Silicon nitride has different HDP stresses on the active and trench regions, thus creating a dislocation at the edge of the active region.
  • FIG. 2 is a flow chart showing a method of fabricating a laterally insulated gate bipolar transistor in an embodiment, including the following steps:
  • S110 providing a wafer formed with an N-type buried layer, a shallow trench isolation structure, a first N well, and a first P well.
  • step S110 can also be completed by a method known to those skilled in the art.
  • a high temperature oxide is formed by depositing silicon dioxide at a temperature of 750 to 850 degrees Celsius (which may simultaneously produce other valence silicon oxides) using a low temperature furnace tube, using SiH 2 Cl. 2 and N 2 O are used as reaction gases.
  • SiH 2 Cl. 2 and N 2 O are used as reaction gases.
  • silane or the like may be used instead of SiH 2 Cl 2 .
  • the first N well and the first P well formed in the step S110 are extended, and the purpose is to make the high temperature oxide film dense by the high temperature process while pushing the well. Due to the wet etching/cleaning step in the subsequent process, the ordinary high temperature oxide film is not suitable as a mini-oxide due to a large amount of corrosion.
  • the high temperature oxide film is densified by thermally pushing the wafer in step S130, the wet etching rate of the high temperature oxide film is greatly reduced, and the high temperature oxide film is ensured.
  • the amount of corrosion of the mini-oxide retained after the etch can be stably controlled during the subsequent cleaning process, ensuring the stability of mass production and can be used for mass production. Since it is completed in the same step as the first N well and the first P well push well, it is also possible to save costs.
  • the temperature of the hot push trap is 1000 degrees Celsius or more and the time is 60 minutes or more, which has a significant effect on the densification of the mini-oxide.
  • the push trap is carried out in an inert gas atmosphere, such as a nitrogen atmosphere, to ensure that the wafer does not generate unwanted chemical reactions with the gases in the furnace during the push-pull process.
  • a specific area where the HTO needs to be left is defined by photolithography, and then the other areas are etched away, leaving the HTO as a mini-oxide.
  • the high temperature oxide film may be photolithographically etched and then thermally pushed. The location where the mini-oxide layer is formed requires reference to the drain and gate locations, as described below.
  • a second N well is formed in the first N well by photolithography and ion implantation, and a second P well is formed in the first N well and the first P well.
  • the mini oxide layer is located directly above it, that is, the left and right ends of the mini oxide layer are located within the range of the second N well.
  • the mini oxide layer and the second P-well leave a certain distance A as an accumulation region, ensuring that the channel of the device can be opened without risk of breakage.
  • the value of A is from 0.2 microns to 1.5 microns.
  • the oxide layer is thermally oxidized on the surface of the wafer, and then polysilicon is deposited on the oxide layer. Finally, the excess oxide layer and polysilicon are removed by photolithography and etching to form a gate oxide layer and a polysilicon gate.
  • the gate oxide layer and the polysilicon gate extend to one end of the second P well in the first N well and the other end to the mini oxide layer on the second N well.
  • Diffusion may be performed after implantation to form a drain between the second N-well, the mini-oxide layer and the shallow trench isolation structure adjacent to the mini-oxide layer, while forming a source in the second P-well.
  • the distance B between the formed N+ drain and the polysilicon gate can be 0 (ie, a self-aligned gate implantation process can be used), and the specific value of B depends on the withstand voltage requirement of the device and the thickness of the mini oxide layer. If the demand for withstand voltage is low, then B can be zero. If the demand for withstand voltage is high, a certain distance needs to be left between the N+ drain and the gate. Similarly, if the mini oxide layer is thick enough, B can Zero, the mini oxide layer is thinner, so there needs to be a certain distance between the N+ drain and the gate.
  • step S170 photolithography is performed, P-type ions are implanted, and a P-type heavily doped region is formed between the two sources and in the second P-well.
  • Fig. 3 is a cross-sectional structural view showing the LDMOS device manufactured by the above-described method for manufacturing a laterally insulated gate bipolar transistor. Since the figure is a left-right symmetric structure, the reference numerals are only indicated on one side.
  • the lateral insulated gate bipolar transistor includes an N-type buried layer 10, a first N well 22, a first P well 24, a second N well 32, a second P well 34, a shallow trench isolation structure 40, a source 51, and a drain 53.
  • the thickness of the mini-oxide layer 60 is related to the withstand voltage required for the device.
  • B an oxide layer having a thickness of 400 angstroms can ensure a withstand voltage of 25 volts, and an oxide layer having a thickness of 1200 angstroms can withstand a withstand voltage of 40 volts.
  • a 1200 angstrom oxide layer can increase the device withstand voltage to 80 volts.
  • the above method for manufacturing a laterally insulated gate bipolar transistor uses a HTO having a lower stress than silicon nitride to reduce the electric field of the LDMOS surface, and the dislocation of the active region edge does not occur.
  • the stepping of the first N well and the first P well by step S130 makes the HTO dense, greatly reducing the wet etching rate of the high temperature oxide film, and ensuring that the mini-oxide remaining after the high temperature oxide film is etched
  • the amount of corrosion during the cleaning process can be stably controlled, ensuring the stability of mass production and can be used for mass production. For example, it is usually necessary to form a thin oxide layer on the front side of the wafer as a barrier layer before performing step S150.
  • the barrier layer needs to be removed before S160. If the HTO is not densified by pushing the trap, the wet etching is very fast and the mini-oxide is also etched away. After the densification treatment, the barrier layer can be removed relatively cleanly. If there are other cleaning steps, the mini-oxide will remain better.
  • the barrier layer is formed by thermal oxidation, for example, may be 70 angstroms to 90 angstroms at 850-900 degrees Celsius, and is etched at room temperature with 1:100 hydrofluoric acid before cleaning in step S160. second.
  • FIG. 4 is a flowchart of a specific implementation of step S110 in an embodiment, including the following steps:
  • a wafer which is a silicon substrate.
  • epitaxial layer is epitaxially formed on the N-type buried layer.
  • An epitaxial layer of silicon is epitaxially layered on the N-type buried layer.
  • the STI structure can be fabricated in the epitaxial layer using processes well known to those skilled in the art.
  • the first N well and the first P well are a high voltage N-well (HV Nwell) and a high voltage P-well (HV Pwell).

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

本发明涉及一种横向绝缘栅双极型晶体管的制造方法，包括：提供衬底往上依次形成有N型埋层（10）、STI（40）、第一N阱（22）/第一P阱（24）的晶圆；在晶圆第一N阱（22）上淀积形成高温氧化膜；对晶圆进行热推阱并对高温氧化膜进行光刻和刻蚀，形成迷你氧化层（60）；进行光刻和离子注入，从而在第一N阱（22）内形成第二N阱（32），以及在第一N阱（22）和第一P阱（24）内形成第二P阱（34）；在依次形成栅氧化层和多晶硅栅（72），栅氧化层和多晶硅栅（72）一端延伸至第一N阱（22）内的第二P阱（34）上，另一端延伸至第二N阱（32）上的迷你氧化层（60）上；光刻并迷你氧化层（60）、与迷你氧化层（60）相邻的STI（40）间注入N型离子，形成漏极，同时在第二P阱（34）内形成源极（51）。

Description

横向绝缘栅双极型晶体管的制造方法
【技术领域】
本发明涉及半导体工艺，特别是涉及一种横向绝缘栅双极型晶体管的制造方法。
【背景技术】
对于0.18微米BCD工艺平台，横向绝缘栅双极型晶体管（LDMOS）在沟道区靠近漏端（drain）一侧增加一块二氧化硅材质的mini-oxide结构后，可以在不增加LDMOS面积的情况下，大幅度降低LDMOS表面电场，解决Idlin（线性漏电流）/Rdson（导通电阻）在电流电压测试后发生的退化问题。
对于这个mini-oxide，传统的工艺是利用氮化硅作为硬掩膜（hard mask），在特定区域内通过炉管生长二氧化硅（即LOCOS工艺）。具体可以是利用氮化硅作为硬掩膜，光刻定义出需要形成mini-oxide的区域，刻蚀掉该区域的氮化硅，器件在炉管内生长二氧化硅，最后通过磷酸把氮化硅剥除。但该工艺存在以下缺点：如图1所示，器件的有源区边缘出现大量错位（dislocation），影响产品的可靠性。
【发明内容】
基于此，有必要提供一种能够解决mini-oxide结构引起的有源区边缘错位现象的横向绝缘栅双极型晶体管。
一种横向绝缘栅双极型晶体管的制造方法，包括步骤：提供形成有N型埋层、N型埋层上的浅槽隔离结构、N型埋层上的第一N阱以及N型埋层上的第一P阱的晶圆；在第一N阱上淀积形成高温氧化膜，淀积温度为750~850摄氏度； 对所述晶圆进行热推阱，并对所述高温氧化膜进行光刻和刻蚀，形成迷你氧化层；进行光刻和离子注入，从而在所述第一N阱内形成第二N阱，以及在所述第一N阱和第一P阱内形成第二P阱； 依次形成栅氧化层和多晶硅栅，所述栅氧化层和多晶硅栅一端延伸至第一N阱内的第二P阱上，另一端延伸至所述第二N阱上的迷你氧化层上；以及光刻并向所述迷你氧化层、与迷你氧化层相邻的浅槽隔离结构之间注入N型离子，形成漏极，同时在所述第二P阱内形成源极。
上述横向绝缘栅双极型晶体管的制造方法，利用与氮化硅做掩膜的LOCOS工艺相比应力较小的高温氧化膜（HTO）工艺来做降低LDMOS表面电场的mini-oxide，有源区边缘不会产生dislocation。通过将对第一N阱和第一P阱的推阱步骤放在淀积HTO的步骤之后，使得HTO变致密，极大地降低了高温氧化膜的湿法腐蚀速率，保证了高温氧化膜刻蚀后保留下来的mini-oxide在后续清洗过程中的腐蚀量可以得到稳定的控制，确保了量产的稳定性，可以用于批量生产。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是有源区边缘出现错位的显微镜照片；
图2是一实施例中横向绝缘栅双极型晶体管的制造方法的流程图；
图3是横向绝缘栅双极型晶体管完成后的剖面结构示意图；
图4是一实施例中步骤S110的一种具体实现方式的流程图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
发明人经实验研究发现，传统用LOCOS制作mini-oxide的工艺在有源区边缘产生大量的错位（dislocation）的原因是mini-oxide形成于STI之后，而LOCOS工艺淀积氮化硅时，因为氮化硅对有源区和沟槽区域的HDP应力不同，因此在有源区边缘产生了dislocation。
图2是一实施例中横向绝缘栅双极型晶体管的制造方法的流程图，包括下列步骤：
S110，提供形成有N型埋层、浅槽隔离结构、第一N阱以及第一P阱的晶圆。
浅槽隔离结构、第一N阱以及第一P阱形成于N型埋层上方。本步骤的具体方法在后文中进行介绍，也可以采用本领域技术人员习知的方法来完成步骤S110。
S120，在第一N阱上淀积形成高温氧化膜。
在本实施例中，高温氧化膜（High Temperature Oxide, HTO）是采用低温炉管在750~850摄氏度淀积形成二氧化硅（可能会同时生产其他价态的硅氧化物），采用SiH2Cl2和N2O作为反应气体。在其他实施例中也可以用硅烷等代替SiH2Cl2。
S130，进行热推阱。
本步骤是将步骤S110中形成的第一N阱和第一P阱的推阱延后，其目的是在推阱的同时通过这一个高温过程使得高温氧化膜变致密。由于后续制程中会有湿法腐蚀/清洗的步骤，普通的高温氧化膜由于会被大量腐蚀而不适合作为mini-oxide。本发明的横向绝缘栅双极型晶体管的制造方法，通过步骤S130对晶圆进行热推阱使得高温氧化膜变致密，极大地降低了高温氧化膜的湿法腐蚀速率，保证了高温氧化膜刻蚀后保留下来的mini-oxide在后续清洗过程中的腐蚀量可以得到稳定的控制，确保了量产的稳定性，可以用于批量生产。由于是与第一N阱和第一P阱的推阱在同一步骤中完成，因此还可以节省成本。
在本实施例中，热推阱的温度为1000摄氏度以上，时间为60分钟以上，这样对mini-oxide的增密有较显著的效果。推阱在惰性气体环境中进行，例如氮气环境中进行，以保证推阱过程中晶圆不会与炉内的气体产生不需要的化学反应。
S140，对高温氧化膜进行光刻和刻蚀，形成迷你氧化层。
通过光刻定义出特定的需要保留下HTO的区域，然后刻蚀掉其他区域，留下的HTO作为迷你氧化层（mini-oxide）。在其他实施例中，也可以先光刻并刻蚀高温氧化膜后再进行热推阱。迷你氧化层形成的位置需要参考漏极和栅极的位置，下文会再进行介绍。
S150，在第一N阱内形成第二N阱，并在第一N阱和第一P阱内形成第二P阱。
通过光刻和离子注入在第一N阱内形成第二N阱，以及在第一N阱和第一P阱内形成第二P阱。第二N阱形成后，迷你氧化层位于其正上方，即迷你氧化层的左右两端都位于第二N阱的范围内。迷你氧化层与第二P阱留出一定距离A作为积累区，保证器件沟道可开启、无断沟风险。在其中一个实施例中，A的值为0.2微米~1.5微米。
S160，依次形成栅氧化层和多晶硅栅。
本实施例中是在晶圆表面热氧化生长氧化层，然后在氧化层上淀积多晶硅，最后光刻并刻蚀去掉多余的氧化层和多晶硅，形成栅氧化层和多晶硅栅。栅氧化层和多晶硅栅一端延伸至第一N阱内的第二P阱上，另一端延伸至第二N阱上的迷你氧化层上。
S170，光刻并注入N型离子，形成漏极和源极。
注入后可以进行扩散，从而在第二N阱内、迷你氧化层和与迷你氧化层相邻的浅槽隔离结构间形成漏极，同时在第二P阱内形成源极。形成的N+漏极与多晶硅栅的距离B最小可为0（即可采用自对准栅极注入工艺），B的具体取值取决于器件的耐压需求和迷你氧化层的厚度，器件如果对耐压的需求较低，则B可以为零，如果对耐压的需求较高，则N+漏极与栅极之间需要留出一定的距离；同理，迷你氧化层若足够厚则B可以为零，迷你氧化层较薄则N+漏极与栅极之间需要留出一定的距离。
步骤S170完后之后再光刻、注入P型离子，在两个源极之间、以及第二P阱内形成P型重掺杂区。
图3是采用上述横向绝缘栅双极型晶体管的制造方法制造的LDMOS器件完成后的剖面结构示意图，由于图中为左右对称结构，故只在一边标出了标号。横向绝缘栅双极型晶体管包括N型埋层10、第一N阱22、第一P阱24、第二N阱32、第二P阱34、浅槽隔离结构40、源极51、漏极53、P型重掺杂区54、迷你氧化层60以及多晶硅栅72。迷你氧化层60的一端延伸至漏极53，另一端延伸至多晶硅栅72下方。迷你氧化层60的厚度与器件所需要的耐压有关。在B=0的实施例中，厚度为400埃的氧化层可以保证25伏特的耐压，厚度为1200埃的氧化层可以保证40伏特的耐压。在适当增大B的取值的情况下，1200埃的氧化层可以将器件耐压增至80伏特。
上述横向绝缘栅双极型晶体管的制造方法，利用与氮化硅相比应力较小的HTO来做降低LDMOS表面电场的mini-oxide，有源区边缘不会产生dislocation。通过步骤S130对第一N阱和第一P阱的推阱使得HTO变致密，极大地降低了高温氧化膜的湿法腐蚀速率，保证了高温氧化膜刻蚀后保留下来的mini-oxide在后续清洗过程中的腐蚀量可以得到稳定的控制，确保了量产的稳定性，可以用于批量生产。例如执行步骤S150之前通常需要在晶圆正面形成一层薄氧化层作为阻挡层。步骤S150注入完成之后，S160之前需要将该阻挡层去除。如果没有通过推阱使得HTO变致密，则湿法腐蚀的速度非常快，该mini-oxide也会被腐蚀掉。而进行了致密处理后，就可以将该阻挡层去除得较干净。后续如有其它清洗步骤，mini-oxide也会保留得比较好。在其中一个实施例中，该阻挡层是采用热氧化法生成，例如可以在850~900摄氏度下长70埃~90埃，步骤S160前清洗时采用1：100的氢氟酸在常温下腐蚀120秒。
图4是一实施例中步骤S110的一种具体实现方式的流程图，包括下列步骤：
S101，提供衬底。
本实施例中是提供硅衬底的晶圆。
S103，在衬底上形成N型埋层。
光刻并注入N型离子，形成N型埋层。
S105，在N型埋层上外延形成外延层。
在N型埋层上在外延一层硅外延层。
S107，形成浅槽隔离结构。
可以采用本领域技术人员习知的工艺在外延层中制造STI结构。
S109，光刻并离子注入形成第一N阱和第一P阱。
第一N阱和第一P阱是高压N阱（HV Nwell）和高压P阱（HV Pwell）。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (6)

  1. 一种横向绝缘栅双极型晶体管的制造方法，包括步骤：
    提供形成有N型埋层、N型埋层上的浅槽隔离结构、N型埋层上的第一N阱以及N型埋层上的第一P阱的晶圆；
    在第一N阱上淀积形成高温氧化膜，淀积温度为750~850摄氏度；
    对所述晶圆进行热推阱，并对所述高温氧化膜进行光刻和刻蚀，形成迷你氧化层；
    进行光刻和离子注入，从而在所述第一N阱内形成第二N阱，以及在所述第一N阱和第一P阱内形成第二P阱；
    依次形成栅氧化层和多晶硅栅，所述栅氧化层和多晶硅栅一端延伸至第一N阱内的第二P阱上，另一端延伸至所述第二N阱上的迷你氧化层上；以及
    光刻并向所述迷你氧化层、与迷你氧化层相邻的浅槽隔离结构之间注入N型离子，形成漏极，同时在所述第二P阱内形成源极。
  2. 根据权利要求1所述的方法，其特征在于，所述进行热推阱步骤的温度为1000摄氏度以上，时间为60分钟以上。
  3. 根据权利要求2所述的方法，其特征在于，所述进行热推阱步骤是在惰性气体环境中进行。
  4. 根据权利要求1所述的方法，其特征在于，在所述晶圆表面淀积形成高温氧化膜的步骤的反应气体是N2O和SiH2Cl2。
  5. 根据权利要求1-4中任意一项所述的方法，其特征在于，所述提供晶圆的步骤包括：
    提供衬底；
    在衬底上形成N型埋层；
    在所述N型埋层上外延形成外延层；
    在所述外延层中形成浅槽隔离结构；
    在所述晶圆的正面进行光刻并离子注入形成所述N型埋层上的第一N阱和第一P阱。
  6. 一种根据权利要求1-5中任意一项所述的方法制造的横向绝缘栅双极型晶体管。
PCT/CN2015/090965 2014-12-30 2015-09-28 横向绝缘栅双极型晶体管的制造方法 WO2016107234A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US15/541,155 US9865702B2 (en) 2014-12-30 2015-09-28 Method for manufacturing laterally insulated-gate bipolar transistor
JP2017535429A JP6555552B2 (ja) 2014-12-30 2015-09-28 横型絶縁ゲートバイポーラトランジスタの製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410849111.X 2014-12-30
CN201410849111.XA CN105810583B (zh) 2014-12-30 2014-12-30 横向绝缘栅双极型晶体管的制造方法

Publications (1)

Publication Number Publication Date
WO2016107234A1 true WO2016107234A1 (zh) 2016-07-07

Family

ID=56284146

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/090965 WO2016107234A1 (zh) 2014-12-30 2015-09-28 横向绝缘栅双极型晶体管的制造方法

Country Status (4)

Country Link
US (1) US9865702B2 (zh)
JP (1) JP6555552B2 (zh)
CN (1) CN105810583B (zh)
WO (1) WO2016107234A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158957B (zh) * 2015-04-10 2019-05-17 无锡华润上华科技有限公司 横向扩散金属氧化物半导体场效应管及其制造方法
CN107946296A (zh) * 2017-10-23 2018-04-20 深圳震有科技股份有限公司 一种静电保护用lemds_scr器件
CN112053953B (zh) * 2020-09-29 2024-03-22 上海华虹宏力半导体制造有限公司 绝缘栅双极型晶体管及其制造方法
CN114300581B (zh) * 2021-12-31 2024-05-17 北海惠科半导体科技有限公司 光敏元件的制备方法及半导体器件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1330837A1 (en) * 2000-11-03 2003-07-30 Telefonaktiebolaget Lm Ericsson Integration of high voltage self-aligned mos components
US20090096022A1 (en) * 2007-10-15 2009-04-16 Fitipower Integrated Technology, Inc. Lateral diffused metal oxide semiconductor device
CN101488525A (zh) * 2009-02-27 2009-07-22 东南大学 P型绝缘体上硅的横向双扩散金属氧化物半导体晶体管
CN101924131A (zh) * 2009-06-11 2010-12-22 上海华虹Nec电子有限公司 横向扩散mos器件及其制备方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0969494A (ja) * 1995-08-31 1997-03-11 Texas Instr Japan Ltd 半導体装置の製造方法
US7667268B2 (en) * 2002-08-14 2010-02-23 Advanced Analogic Technologies, Inc. Isolated transistor
CN100447982C (zh) * 2002-12-31 2008-12-31 上海贝岭股份有限公司 制造高压半导体器件的工艺
JP4845410B2 (ja) * 2005-03-31 2011-12-28 株式会社リコー 半導体装置
JP2010056216A (ja) * 2008-08-27 2010-03-11 Sharp Corp 半導体装置およびその製造方法
JP2010212423A (ja) * 2009-03-10 2010-09-24 Asahi Kasei Electronics Co Ltd 半導体装置及びその製造方法
US8507988B2 (en) * 2009-10-02 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage devices, systems, and methods for forming the high voltage devices
JP5524103B2 (ja) * 2011-02-07 2014-06-18 株式会社東芝 半導体装置
US8866252B2 (en) * 2011-09-15 2014-10-21 Cambridge Semiconductor Limited Power semiconductor devices and fabrication methods
JP6011136B2 (ja) * 2012-08-09 2016-10-19 富士電機株式会社 半導体装置
US9698024B2 (en) * 2012-12-06 2017-07-04 Taiwan Semiconductor Manufacturing Co., Ltd. Partial SOI on power device for breakdown voltage improvement
US9111898B2 (en) * 2013-02-19 2015-08-18 Taiwan Semiconductor Manufacturing Company. Ltd. Multiple layer substrate
JP5920407B2 (ja) * 2013-07-16 2016-05-18 株式会社デンソー 半導体装置
US8952744B1 (en) * 2013-07-31 2015-02-10 Macronix International Co., Ltd. Semiconductor device and operating method for the same
US9647065B2 (en) * 2013-10-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bipolar transistor structure having split collector region and method of making the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1330837A1 (en) * 2000-11-03 2003-07-30 Telefonaktiebolaget Lm Ericsson Integration of high voltage self-aligned mos components
US20090096022A1 (en) * 2007-10-15 2009-04-16 Fitipower Integrated Technology, Inc. Lateral diffused metal oxide semiconductor device
CN101488525A (zh) * 2009-02-27 2009-07-22 东南大学 P型绝缘体上硅的横向双扩散金属氧化物半导体晶体管
CN101924131A (zh) * 2009-06-11 2010-12-22 上海华虹Nec电子有限公司 横向扩散mos器件及其制备方法

Also Published As

Publication number Publication date
CN105810583B (zh) 2019-03-15
JP6555552B2 (ja) 2019-08-07
JP2018505552A (ja) 2018-02-22
CN105810583A (zh) 2016-07-27
US20170358657A1 (en) 2017-12-14
US9865702B2 (en) 2018-01-09

Similar Documents

Publication Publication Date Title
JP7279277B2 (ja) 複数遮蔽トレンチゲートｆｅｔ
US9466700B2 (en) Semiconductor device and method of fabricating same
JP3831602B2 (ja) 半導体装置の製造方法
WO2016161842A1 (zh) 横向扩散金属氧化物半导体场效应管及其制造方法
WO2011143836A1 (zh) 一种具有厚绝缘底部的沟槽及其半导体器件的制造方法
WO2016107234A1 (zh) 横向绝缘栅双极型晶体管的制造方法
US9034709B2 (en) Method for manufacturing semiconductor device
CN108550623A (zh) 集成有增强型和耗尽型vdmos的器件及其制造方法
WO2020094044A1 (zh) 一种半导体器件及其制造方法
JP2021153163A (ja) 半導体装置の製造方法、および半導体装置
KR20100020688A (ko) Ｌｄｍｏｓ 반도체 소자와 그 제조 방법
US8669616B2 (en) Method for forming N-shaped bottom stress liner
CN102054698B (zh) 提高半导体器件阈值电压的方法
JPH0621451A (ja) 半導体装置の製造方法
KR101289121B1 (ko) 반도체 소자 및 이의 제조방법
CN117316772A (zh) Ldmos器件的制备方法以及ldmos器件
CN114429983A (zh) 高压横向双扩散金属氧化物半导体场效应管及其制作方法
CN116631874A (zh) 一种半导体器件及其制备方法
KR100850074B1 (ko) 반도체 소자의 제조방법
CN103426761A (zh) 一种mosfet器件以及制备方法
CN114023651A (zh) Nmos晶体管的制备方法
KR20070090052A (ko) 반도체 소자 및 그 제조 방법
JPS61220372A (ja) 半導体装置の製造方法
JPH01270272A (ja) Ｍｉｓ形半導体装置の製造方法
JPH01243446A (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15874919

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2017535429

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 15541155

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15874919

Country of ref document: EP

Kind code of ref document: A1