WO2012071986A1 - Method for manufacturing dual-gate oxide semiconductor devices - Google Patents

Method for manufacturing dual-gate oxide semiconductor devices Download PDF

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Publication number
WO2012071986A1
WO2012071986A1 PCT/CN2011/082395 CN2011082395W WO2012071986A1 WO 2012071986 A1 WO2012071986 A1 WO 2012071986A1 CN 2011082395 W CN2011082395 W CN 2011082395W WO 2012071986 A1 WO2012071986 A1 WO 2012071986A1
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oxide layer
gate oxide
forming
region
layer
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PCT/CN2011/082395
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French (fr)
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Le Wang
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Csmc Technologies Fab1 Co., Ltd
Csmc Technologies Fab2 Co., Ltd.
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Publication of WO2012071986A1 publication Critical patent/WO2012071986A1/en

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
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    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28238—Making the insulator with sacrificial oxide

Definitions

  • the present invention generally relates to the field of semiconductor manufacturing and, more particularly, to the methods and processes for manufacturing dual-gate oxide semiconductor devices .
  • a dual-gate oxide semiconductor device generally includes a source, a drain and two gates, and the two gates are mutually independent. Gate oxide layers respectively under the two gates are of different thickness, so as to meet the need of different applications. For example, a thicker gate oxide layer is used in a high voltage device for input or output; while a thinner gate oxide layer is used in a low voltage device for digital logic operation. These characteristics make it possible to use the dual-gate oxide semiconductor device as a high-frequency amplifier, a mixer, a demodulator, a gain control amplifier and so on. Therefore, dual-gate oxide semiconductor devices are widely used in large scale integrated circuits.
  • An existing process for manufacturing dual-gate oxide semiconductor devices usually includes: forming a thick gate oxide layer on a surface of a semiconductor substrate by a thermal oxidation process; forming a photoresist pattern of a thick gate oxide layer region on the surface of the thick gate oxide layer region by performing steps of applying photoresist, exposure, developing and so on sequentially; removing the thick gate oxide layer in a thin gate oxide layer region through an etching process using the photoresist pattern of the thick gate oxide layer region as a mask; and forming, by another thermal oxidation process, a thin gate oxide layer in the region where the thick gate oxide layer is removed.
  • the disclosed methods and systems are directed to solve one or more problems set forth above and other problems.
  • One aspect of the present disclosure includes a method for manufacturing a dual-gate oxide semiconductor device.
  • the method includes providing a substrate including a first gate oxide layer region and a second gate oxide layer region, and forming a photoresist pattern of the second gate oxide layer region on a surface of the substrate.
  • the method also includes implanting nitrogen atoms into the first gate oxide layer region by an ion implantation process using the photoresist pattern of the second gate oxide layer region as a mask to form a nitrogen implantation layer.
  • the method includes removing the photoresist pattern on the surface of the substrate to expose the second gate oxide layer region, and forming a first gate oxide layer and a second gate oxide layer on the surface of the substrate at same time by a single thermal oxidation process.
  • the first gate oxide layer has a first thickness and the second gate oxide layer has a second thickness, which is different from the first thickness.
  • Figure 1 illustrates an exemplary flow diagram of a method of manufacturing a dual-gate oxide semiconductor device consistent with the disclosed embodiments
  • Figure 2 illustrates a dual-gate oxide semiconductor device after forming a photoresist pattern of a thick gate oxide layer
  • Figure 3 illustrates a dual-gate oxide semiconductor device after forming a nitrogen implantation layer
  • Figure 4 illustrates a dual-gate oxide semiconductor device after removing photoresist on a surface of a semiconductor substrate
  • Figure 5 illustrates a dual-gate oxide semiconductor device after forming a gate oxide layer
  • Figure 6 illustrates a semiconductor device after forming a silicon oxide layer on the surface consistent with the disclosed embodiments
  • Figure 7 illustrates a dual-gate oxide semiconductor device including a silicon oxide layer during forming a nitrogen implantation layer
  • Figure 8 illustrates a dual-gate oxide semiconductor device after forming a well region
  • Figure 9 illustrates a dual-gate oxide semiconductor device after forming a silicon nitride layer consistent with the disclosed embodiments ;
  • Figure 10 illustrates a dual-gate oxide semiconductor device after forming a pattern of a local field oxidation isolation region
  • Figure 11 illustrates a dual-gate oxide semiconductor device after forming a local field oxidation isolation region
  • Figure 12 illustrates a dual-gate oxide semiconductor device consistent with the disclosed embodiments.
  • Figure 1 illustrates an exemplary flow diagram of a method of manufacturing a dual-gate oxide semiconductor device consistent with the disclosed embodiments .
  • Figure 2 illustrates a corresponding dual-gate oxide semiconductor device 200.
  • device 200 may include a substrate 201, a predetermined thin gate oxide layer region 204 (i.e., a first gate oxide layer region), a predetermined thick gate oxide layer region 205 (i.e., a second gate oxide layer region), and an isolation region 202 between the thin gate oxide layer region 204 and the thick gate oxide layer region 205.
  • a predetermined thin gate oxide layer region 204 i.e., a first gate oxide layer region
  • a predetermined thick gate oxide layer region 205 i.e., a second gate oxide layer region
  • isolation region 202 between the thin gate oxide layer region 204 and the thick gate oxide layer region 205.
  • Substrate 201 may be provided first as the base for the dual-gate oxide semiconductor device 200 .
  • the substrate 201 may include any appropriate material for making double-gate structures.
  • the substrate 201 may include a semiconductor structure, e.g., silicon, silicon germanium (SiGe) with a monocrystalline, polycrystalline, or amorphous structure.
  • the substrate 201 may also include a hybrid semiconductor structure, e.g., carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductor, or a combination thereof.
  • the substrate 201 may include a silicon-on-insulator (SOI) structure.
  • the substrate 201 may also include other materials, such as a multi-layered structure of epitaxial layer or buried layer. Other materials may also be used.
  • the thin gate oxide layer region 204 may be used to form a first gate oxide layer with a first thickness (i.e., a thin gate oxide layer); and the thick gate oxide layer region 205 may be used to form a second gate oxide layer with a second thickness (i.e., a thick gate oxide layer).
  • the first thickness is different from the second thickness and, more specifically, the first thickness may be less than the second thickness.
  • the degree of difference may be depending on particular dual-gate oxide semiconductor device, and the thin gate oxide layer and the thick gate oxide layer may be formed at the same time as a single gate oxide layer with corresponding different thicknesses.
  • a photoresist pattern of the thick gate oxide layer region may be formed on a surface of the semiconductor substrate 201 (S101).
  • the photoresist pattern may be formed by performing steps such as applying photoresist, exposure and developing sequentially.
  • Figure 2 shows the photoresist pattern 203 of the thick gate oxide layer region 205. After a photoresist layer is developed, the surface of the thin gate oxide layer region 204 is not covered with any photoresist and the surface of the thick gate oxide layer region 205 is covered with photoresist pattern 203.
  • the thick gate oxide layer region and the thin gate oxide layer region are regions before a gate oxide layer is formed.
  • nitrogen atoms are implanted into the thin gate oxide layer region 204 to form a nitrogen implantation layer (S102).
  • the nitrogen atoms may be implanted through an ion implantation process using the photoresist pattern 203 of the thick gate oxide layer region 205 as a mask.
  • Figure 3 shows the corresponding dual-gate oxide semiconductor device 200 after forming the nitrogen implantation layer.
  • a nitrogen implantation layer 206 is formed in the thin gate oxide layer region 204.
  • the shape (not shown) of the nitrogen implantation layer 206 may also coincide with the shape of the thin gate oxide layer region 204. Any appropriate shape or any appropriate number of regions may be used.
  • parameters of the ion implantation such as the concentration of ion (e.g., nitrogen atoms), may be predetermined based on desired thickness of the thin gate oxide layer and/or the thick gate oxide layer, as further described in the disclosed embodiments. Thus, the ion implantation can be controlled according to the predetermined ion implantation parameters during the manufacturing process.
  • the photoresist on the surface of the semiconductor substrate 201 is removed (S103). That is, the photoresist pattern located on the surface of the semiconductor substrate 201 and corresponding to the thick gate oxide layer region 205 is removed.
  • Figure 4 shows the corresponding dual-gate oxide semiconductor device 200 after removing photoresist on the surface of the semiconductor substrate 201. As shown in Figure 4, both the thin gate oxide layer region 204 and the thick gate oxide layer region 205 are exposed, with the nitrogen implantation layer 206 in the thin gate oxide layer region 204.
  • a thick gate oxide layer and a thin gate oxide layer are formed on the surface of the semiconductor substrate 201 at same time by a thermal oxidation process (S104). Other processes may also be used.
  • the nitrogen implantation layer 206 may reduce the oxidation speed of the surface of the semiconductor substrate.
  • the oxidation speed of the surface of the semiconductor substrate without the nitrogen implantation layer 206 is normal.
  • only one single thermal oxidation process can be used to form the thin gate oxide layer on the surface of the semiconductor substrate in the thin gate oxide layer region with the nitrogen implantation layer 206, and to form the thick gate oxide layer on the surface of the semiconductor substrate in the thick gate oxide layer region without the nitrogen implantation layer 206.
  • the nitrogen implantation layer 206 in the thin gate oxide layer region 204 may reduce the oxidation speed of the surface of the semiconductor substrate 201, while the oxidation speed is normal at the surface of the semiconductor substrate corresponding to the thick gate oxide layer region 205 without a nitrogen implantation layer. Further, the oxidation speed at the surface of the semiconductor substrate corresponding to the nitrogen implantation layer 206 can be controlled by controlling the nitrogen atom concentration and thickness of the nitrogen implantation layer 206. Thus, the thickness of the thin gate oxide layer formed by thermal oxidation process can be controlled with desired precision to produce substantial thin gate oxide layers.
  • Figure 5 shows the corresponding dual-gate oxide semiconductor device 200 after forming a gate oxide layer.
  • a thin gate oxide layer 207 is formed in the thin gate oxide layer region 204, and a thick gate oxide layer 208 is formed in the thick gate oxide layer region 205.
  • a silicon oxide layer may be formed on the surface of the semiconductor substrate.
  • a silicon oxide layer 209 is formed on the surface of the device 200. That is, the silicon oxide layer 209 is formed on substrate 201.
  • the silicon oxide layer 209 may be formed by, for example, a deposition process. In subsequent processes, such as forming a well region or a nitrogen implantation layer, the silicon oxide layer 209 may be used as a blocking and protective layer to control depth and concentration of the ion or atom implantation and to prevent the semiconductor substrate from being excessively damaged during the implantation process. Further, the thickness of the silicon oxide layer 209 may be in a range of approximately 150-300 ⁇ .
  • Figure 7 shows the dual-gate oxide semiconductor device 200 including a silicon oxide layer 209 after forming a nitrogen implantation layer.
  • a nitrogen implantation layer 206 may be formed in the thin gate oxide layer region 204 on the surface of the substrate 201, covered by the silicon oxide layer 209 so as to protect and/or control the formation of the nitrogen implantation layer 206.
  • the silicon oxide layer 209 may be removed after the nitrogen implantation layer 206 is formed.
  • a well region may also be formed on the surface of substrate 201 after forming the silicon oxide layer 209.
  • Figure 8 shows the dual-gate oxide semiconductor device 200 after forming a well region.
  • a well region 210 is formed on the surface of substrate 201 and covered by the silicon oxide layer 209.
  • the well region 210 may be an n-well or a p-well according to the conduction type of device 200. Further, the well region 210 may be formed by an ion implantation process. More specifically, the process of forming the well region 210 may include forming a photoresist pattern of a well region by applying photoresist, exposure and developing sequentially on the surface of the silicon oxide layer 209; and performing ion implantation using the photoresist pattern of the well region as a mask. During the formation of the well region 210, the silicon oxide layer 209 may be used as a blocking and protective layer to control depth and concentration of the ion implantation.
  • isolation region may be a local field oxidation isolation or a shallow trench isolation. Other type of isolation region may also be used.
  • a silicon nitride layer is deposited on the surface of the silicon oxide layer 209.
  • Figure 9 shows the dual-gate oxide semiconductor device 200 after forming the silicon nitride layer.
  • a silicon nitride layer 211 is formed on the silicon oxide layer 209.
  • the silicon nitride layer 211 may be a layer of firm mask material which may protect an active region of the semiconductor substrate 201 during the formation of the local field oxidation isolation and may be used as blocking material during polishing process.
  • a pattern of a local field oxidation isolation region is formed in the silicon nitride layer 211.
  • Figure 10 shows the dual-gate oxide semiconductor device 200 after forming the pattern of the local field oxidation isolation region. As shown in Figure 10, a pattern of the local field oxidation isolation region 212 is formed in the silicon nitride layer 211.
  • FIG. 11 shows the dual-gate oxide semiconductor device 200 after forming the local field oxidation isolation.
  • local field oxidation isolation 202 is formed between the thin gate oxide layer region 204 and the thick gate oxide layer region 205.
  • the local field oxidation isolation 202 may be formed through an oxidation process using the silicon nitride layer 211 as a mask, so as to separate the thin gate oxide layer region 204 and the thick gate oxide layer region 205.
  • local field oxidation isolation 202 is formed in a local field oxidation isolation region.
  • the thick gate oxide layer region may be provided at one side of the local field oxidation isolation 202, and a thin gate oxide layer region may be provided at the other side of the local field oxidation isolation 202. Since there is insulating silicon oxide in the local field oxidation isolation region, the isolation between the thin gate oxide layer region 204 and the thick gate oxide layer region 205 can be realized.
  • Figure 12 shows the dual-gate oxide semiconductor device 200 after removing the silicon nitride layer 211 and other steps.
  • thin gate oxide layer 207 is formed in the thin gate oxide layer region 204
  • thick gate oxide layer 208 is formed in the thick gate oxide layer region 205.
  • the thin gate oxide layer 207 and the thick gate oxide layer 208 are separated by local field oxidation isolation 202.
  • a shallow trench isolation may be formed instead of the local field oxidation isolation 202. Because the shallow trench isolation forming process is similar to the process of forming the local field oxidation isolation 202, only brief description is provided for the illustrative purposes.
  • a silicon nitride layer 211 is deposited on the surface of the silicon oxide layer 209. A pattern of a shallow trench isolation region may then be formed in the silicon nitride layer 211.
  • a shallow trench isolation is formed through an etching process using the silicon nitride layer 211 as a mask, so as to separate the thick gate oxide layer region 205 and the thin gate oxide layer region 204.
  • the shallow trench isolation may then be filled with an insulating material, and the silicon nitride layer 211 is removed afterwards.
  • the shallow trench isolation region may occupy smaller area and may have a better isolation effect than the local field oxidation isolation region.
  • the shallow trench isolation region may be suitable for small-sized dual-gate oxide semiconductor devices.
  • the gate oxide layer of the dual-gate oxide semiconductor device can be formed on the surface of the semiconductor substrate by a single thermal oxidation process, which simplifies the process flow, reduces the production cost, and improves the production efficiency of the manufacturing of the dual-gate oxide semiconductor device.

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Abstract

A method is provided for manufacturing a dual-gate oxide semiconductor device. The method includes providing a substrate including a first gate oxide layer region and a second gate oxide layer region, and forming a photoresist pattern of the second gate oxide layer region on a surface of the substrate (S101). The method also includes implanting nitrogen atoms into the first gate oxide layer region by an ion implantation process using the photoresist pattern of the second gate oxide layer region as a mask to form a nitrogen implantation layer (S102). Further, the method includes removing the photoresist pattern on the surface of the substrate to expose the second gate oxide layer region (S103), and forming a first gate oxide layer and a second gate oxide layer on the surface of the substrate at the same time by a single thermal oxidation process (S104). Furthermore, the first gate oxide layer has a first thickness and the second gate oxide layer has a second thickness, which is different from the first thickness.

Description

METHOD FOR MANUFACTURING DUAL-GATE OXIDE SEMICONDUCTOR DEVICES
FIELD OF THE INVENTION
The present invention generally relates to the field of semiconductor manufacturing and, more particularly, to the methods and processes for manufacturing dual-gate oxide semiconductor devices .
BACKGROUND
A dual-gate oxide semiconductor device generally includes a source, a drain and two gates, and the two gates are mutually independent. Gate oxide layers respectively under the two gates are of different thickness, so as to meet the need of different applications. For example, a thicker gate oxide layer is used in a high voltage device for input or output; while a thinner gate oxide layer is used in a low voltage device for digital logic operation. These characteristics make it possible to use the dual-gate oxide semiconductor device as a high-frequency amplifier, a mixer, a demodulator, a gain control amplifier and so on. Therefore, dual-gate oxide semiconductor devices are widely used in large scale integrated circuits.
An existing process for manufacturing dual-gate oxide semiconductor devices usually includes: forming a thick gate oxide layer on a surface of a semiconductor substrate by a thermal oxidation process; forming a photoresist pattern of a thick gate oxide layer region on the surface of the thick gate oxide layer region by performing steps of applying photoresist, exposure, developing and so on sequentially; removing the thick gate oxide layer in a thin gate oxide layer region through an etching process using the photoresist pattern of the thick gate oxide layer region as a mask; and forming, by another thermal oxidation process, a thin gate oxide layer in the region where the thick gate oxide layer is removed.
However, there are certain disadvantages in the existing process for manufacturing the dual-gate oxide semiconductor device. To form the thick gate oxide layer and the thin gate oxide layer, respectively, the thermal oxidation process has to be performed twice. Therefore, the process flow is complicated, leading to higher production cost and lower production efficiency when manufacturing dual-gate oxide semiconductor devices.
The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.
BRIEF SUMMARY OF THE DISCLOSURE
One aspect of the present disclosure includes a method for manufacturing a dual-gate oxide semiconductor device. The method includes providing a substrate including a first gate oxide layer region and a second gate oxide layer region, and forming a photoresist pattern of the second gate oxide layer region on a surface of the substrate. The method also includes implanting nitrogen atoms into the first gate oxide layer region by an ion implantation process using the photoresist pattern of the second gate oxide layer region as a mask to form a nitrogen implantation layer. Further, the method includes removing the photoresist pattern on the surface of the substrate to expose the second gate oxide layer region, and forming a first gate oxide layer and a second gate oxide layer on the surface of the substrate at same time by a single thermal oxidation process. Furthermore, the first gate oxide layer has a first thickness and the second gate oxide layer has a second thickness, which is different from the first thickness.
Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 illustrates an exemplary flow diagram of a method of manufacturing a dual-gate oxide semiconductor device consistent with the disclosed embodiments;
Figure 2 illustrates a dual-gate oxide semiconductor device after forming a photoresist pattern of a thick gate oxide layer;
Figure 3 illustrates a dual-gate oxide semiconductor device after forming a nitrogen implantation layer;
Figure 4 illustrates a dual-gate oxide semiconductor device after removing photoresist on a surface of a semiconductor substrate;
Figure 5 illustrates a dual-gate oxide semiconductor device after forming a gate oxide layer;
Figure 6 illustrates a semiconductor device after forming a silicon oxide layer on the surface consistent with the disclosed embodiments;
Figure 7 illustrates a dual-gate oxide semiconductor device including a silicon oxide layer during forming a nitrogen implantation layer;
Figure 8 illustrates a dual-gate oxide semiconductor device after forming a well region;
Figure 9 illustrates a dual-gate oxide semiconductor device after forming a silicon nitride layer consistent with the disclosed embodiments ；
Figure 10 illustrates a dual-gate oxide semiconductor device after forming a pattern of a local field oxidation isolation region;
Figure 11 illustrates a dual-gate oxide semiconductor device after forming a local field oxidation isolation region; and
Figure 12 illustrates a dual-gate oxide semiconductor device consistent with the disclosed embodiments.
DETAILED DESCRIPTION
Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
Figure 1 illustrates an exemplary flow diagram of a method of manufacturing a dual-gate oxide semiconductor device consistent with the disclosed embodiments . Figure 2 illustrates a corresponding dual-gate oxide semiconductor device 200.
As shown in Figure 2, device 200 may include a substrate 201, a predetermined thin gate oxide layer region 204 (i.e., a first gate oxide layer region), a predetermined thick gate oxide layer region 205 (i.e., a second gate oxide layer region), and an isolation region 202 between the thin gate oxide layer region 204 and the thick gate oxide layer region 205.
Substrate 201 may be provided first as the base for the dual-gate oxide semiconductor device 200 . The substrate 201 may include any appropriate material for making double-gate structures. For example, the substrate 201 may include a semiconductor structure, e.g., silicon, silicon germanium (SiGe) with a monocrystalline, polycrystalline, or amorphous structure. The substrate 201 may also include a hybrid semiconductor structure, e.g., carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductor, or a combination thereof. Further, the substrate 201 may include a silicon-on-insulator (SOI) structure. In addition, the substrate 201 may also include other materials, such as a multi-layered structure of epitaxial layer or buried layer. Other materials may also be used.
Further, the thin gate oxide layer region 204 may be used to form a first gate oxide layer with a first thickness (i.e., a thin gate oxide layer); and the thick gate oxide layer region 205 may be used to form a second gate oxide layer with a second thickness (i.e., a thick gate oxide layer). The first thickness is different from the second thickness and, more specifically, the first thickness may be less than the second thickness. However, the degree of difference may be depending on particular dual-gate oxide semiconductor device, and the thin gate oxide layer and the thick gate oxide layer may be formed at the same time as a single gate oxide layer with corresponding different thicknesses.
As shown in Figure 1, after the substrate 201 is provided, a photoresist pattern of the thick gate oxide layer region may be formed on a surface of the semiconductor substrate 201 (S101). The photoresist pattern may be formed by performing steps such as applying photoresist, exposure and developing sequentially.
Figure 2 shows the photoresist pattern 203 of the thick gate oxide layer region 205. After a photoresist layer is developed, the surface of the thin gate oxide layer region 204 is not covered with any photoresist and the surface of the thick gate oxide layer region 205 is covered with photoresist pattern 203. The thick gate oxide layer region and the thin gate oxide layer region are regions before a gate oxide layer is formed.
Returning to Figure 1, after forming the photoresist pattern 203 (S101), nitrogen atoms are implanted into the thin gate oxide layer region 204 to form a nitrogen implantation layer (S102). The nitrogen atoms may be implanted through an ion implantation process using the photoresist pattern 203 of the thick gate oxide layer region 205 as a mask. Figure 3 shows the corresponding dual-gate oxide semiconductor device 200 after forming the nitrogen implantation layer.
As shown in Figure 3, a nitrogen implantation layer 206 is formed in the thin gate oxide layer region 204. The shape (not shown) of the nitrogen implantation layer 206 may also coincide with the shape of the thin gate oxide layer region 204. Any appropriate shape or any appropriate number of regions may be used. Further, parameters of the ion implantation, such as the concentration of ion (e.g., nitrogen atoms), may be predetermined based on desired thickness of the thin gate oxide layer and/or the thick gate oxide layer, as further described in the disclosed embodiments. Thus, the ion implantation can be controlled according to the predetermined ion implantation parameters during the manufacturing process.
Returning to Figure 1, after forming the nitrogen implantation layer 206, the photoresist on the surface of the semiconductor substrate 201 is removed (S103). That is, the photoresist pattern located on the surface of the semiconductor substrate 201 and corresponding to the thick gate oxide layer region 205 is removed.
Figure 4 shows the corresponding dual-gate oxide semiconductor device 200 after removing photoresist on the surface of the semiconductor substrate 201. As shown in Figure 4, both the thin gate oxide layer region 204 and the thick gate oxide layer region 205 are exposed, with the nitrogen implantation layer 206 in the thin gate oxide layer region 204.
Returning to Figure 1, after removing the photoresist on the surface of the semiconductor substrate 201 (S103), a thick gate oxide layer and a thin gate oxide layer are formed on the surface of the semiconductor substrate 201 at same time by a thermal oxidation process (S104). Other processes may also be used.
That is, during the process of forming the gate oxide layer (i.e., the thick gate oxide layer and the thin gate oxide layer) on the surface of the semiconductor substrate 201 by a single thermal oxidation process, the nitrogen implantation layer 206 may reduce the oxidation speed of the surface of the semiconductor substrate. On the other hand, the oxidation speed of the surface of the semiconductor substrate without the nitrogen implantation layer 206 is normal. Thus, only one single thermal oxidation process can be used to form the thin gate oxide layer on the surface of the semiconductor substrate in the thin gate oxide layer region with the nitrogen implantation layer 206, and to form the thick gate oxide layer on the surface of the semiconductor substrate in the thick gate oxide layer region without the nitrogen implantation layer 206.
More specifically, the nitrogen implantation layer 206 in the thin gate oxide layer region 204 may reduce the oxidation speed of the surface of the semiconductor substrate 201, while the oxidation speed is normal at the surface of the semiconductor substrate corresponding to the thick gate oxide layer region 205 without a nitrogen implantation layer. Further, the oxidation speed at the surface of the semiconductor substrate corresponding to the nitrogen implantation layer 206 can be controlled by controlling the nitrogen atom concentration and thickness of the nitrogen implantation layer 206. Thus, the thickness of the thin gate oxide layer formed by thermal oxidation process can be controlled with desired precision to produce substantial thin gate oxide layers.
Figure 5 shows the corresponding dual-gate oxide semiconductor device 200 after forming a gate oxide layer. As shown in Figure 5, a thin gate oxide layer 207 is formed in the thin gate oxide layer region 204, and a thick gate oxide layer 208 is formed in the thick gate oxide layer region 205.
Additionally or optionally, other processes may also be performed together with the above processes for manufacturing the dual-gate oxide semiconductor device 200. For example, before forming the photoresist pattern of the thick gate oxide layer region 205 (e.g., before applying photoresist), a silicon oxide layer may be formed on the surface of the semiconductor substrate.
As shown in Figure 6, a silicon oxide layer 209 is formed on the surface of the device 200. That is, the silicon oxide layer 209 is formed on substrate 201. The silicon oxide layer 209 may be formed by, for example, a deposition process. In subsequent processes, such as forming a well region or a nitrogen implantation layer, the silicon oxide layer 209 may be used as a blocking and protective layer to control depth and concentration of the ion or atom implantation and to prevent the semiconductor substrate from being excessively damaged during the implantation process. Further, the thickness of the silicon oxide layer 209 may be in a range of approximately 150-300 Å.
Figure 7 shows the dual-gate oxide semiconductor device 200 including a silicon oxide layer 209 after forming a nitrogen implantation layer. As shown in Figure 7, similar to Figure 3, a nitrogen implantation layer 206 may be formed in the thin gate oxide layer region 204 on the surface of the substrate 201, covered by the silicon oxide layer 209 so as to protect and/or control the formation of the nitrogen implantation layer 206. Moreover, the silicon oxide layer 209 may be removed after the nitrogen implantation layer 206 is formed.
Additionally or optionally, a well region may also be formed on the surface of substrate 201 after forming the silicon oxide layer 209. Figure 8 shows the dual-gate oxide semiconductor device 200 after forming a well region.
As shown in Figure 8, a well region 210 is formed on the surface of substrate 201 and covered by the silicon oxide layer 209. The well region 210 may be an n-well or a p-well according to the conduction type of device 200. Further, the well region 210 may be formed by an ion implantation process. More specifically, the process of forming the well region 210 may include forming a photoresist pattern of a well region by applying photoresist, exposure and developing sequentially on the surface of the silicon oxide layer 209; and performing ion implantation using the photoresist pattern of the well region as a mask. During the formation of the well region 210, the silicon oxide layer 209 may be used as a blocking and protective layer to control depth and concentration of the ion implantation.
Further, processes may be performed to form an isolation region between a thin gate oxide layer and a thick gate oxide layer of the dual-gate oxide semiconductor device 200. The isolation region may be a local field oxidation isolation or a shallow trench isolation. Other type of isolation region may also be used.
More particularly, after forming the silicon oxide layer 209 and/or well region 210, but before applying photoresist for forming thick gate oxide region pattern, a silicon nitride layer is deposited on the surface of the silicon oxide layer 209.
Figure 9 shows the dual-gate oxide semiconductor device 200 after forming the silicon nitride layer. As shown in Figure 9, a silicon nitride layer 211 is formed on the silicon oxide layer 209. The silicon nitride layer 211 may be a layer of firm mask material which may protect an active region of the semiconductor substrate 201 during the formation of the local field oxidation isolation and may be used as blocking material during polishing process.
Further, a pattern of a local field oxidation isolation region is formed in the silicon nitride layer 211. Figure 10 shows the dual-gate oxide semiconductor device 200 after forming the pattern of the local field oxidation isolation region. As shown in Figure 10, a pattern of the local field oxidation isolation region 212 is formed in the silicon nitride layer 211.
After forming the pattern of the local field oxidation isolation region 212, a local field oxidation isolation is formed between the thin gate oxide layer region and the thick gate oxide layer region. Figure 11 shows the dual-gate oxide semiconductor device 200 after forming the local field oxidation isolation.
As shown in Figure 11, local field oxidation isolation 202 is formed between the thin gate oxide layer region 204 and the thick gate oxide layer region 205. The local field oxidation isolation 202 may be formed through an oxidation process using the silicon nitride layer 211 as a mask, so as to separate the thin gate oxide layer region 204 and the thick gate oxide layer region 205.
That is, local field oxidation isolation 202 is formed in a local field oxidation isolation region. The thick gate oxide layer region may be provided at one side of the local field oxidation isolation 202, and a thin gate oxide layer region may be provided at the other side of the local field oxidation isolation 202. Since there is insulating silicon oxide in the local field oxidation isolation region, the isolation between the thin gate oxide layer region 204 and the thick gate oxide layer region 205 can be realized.
Further, the silicon nitride layer 211 is removed and other steps for forming the gate oxide layer may also be applied. Figure 12 shows the dual-gate oxide semiconductor device 200 after removing the silicon nitride layer 211 and other steps. As shown in Figure 12, similar to Figure 5, thin gate oxide layer 207 is formed in the thin gate oxide layer region 204, and thick gate oxide layer 208 is formed in the thick gate oxide layer region 205. The thin gate oxide layer 207 and the thick gate oxide layer 208 are separated by local field oxidation isolation 202.
Additionally or alternatively, a shallow trench isolation may be formed instead of the local field oxidation isolation 202. Because the shallow trench isolation forming process is similar to the process of forming the local field oxidation isolation 202, only brief description is provided for the illustrative purposes.
After forming the silicon oxide layer 209 and before applying the photoresist for forming thick gate oxide region pattern, a silicon nitride layer 211 is deposited on the surface of the silicon oxide layer 209. A pattern of a shallow trench isolation region may then be formed in the silicon nitride layer 211.
Further, a shallow trench isolation is formed through an etching process using the silicon nitride layer 211 as a mask, so as to separate the thick gate oxide layer region 205 and the thin gate oxide layer region 204. The shallow trench isolation may then be filled with an insulating material, and the silicon nitride layer 211 is removed afterwards.
Compared to the local field oxidation isolation region, the shallow trench isolation region may occupy smaller area and may have a better isolation effect than the local field oxidation isolation region. Thus, the shallow trench isolation region may be suitable for small-sized dual-gate oxide semiconductor devices.
By using the disclosed methods and processes, the gate oxide layer of the dual-gate oxide semiconductor device can be formed on the surface of the semiconductor substrate by a single thermal oxidation process, which simplifies the process flow, reduces the production cost, and improves the production efficiency of the manufacturing of the dual-gate oxide semiconductor device.
It is understood that the disclosed embodiments may be applied to any dual-gate semiconductor devices, and can also be extended to the manufacturing of multi-gate and other types of semiconductor devices. Various alternations, modifications, or equivalents to the technical solutions of the disclosed embodiments can be obvious to those skilled in the art.

Claims (13)

  1. A method for manufacturing a dual-gate oxide semiconductor device , comprising:
    providing a substrate including a first gate oxide layer region and a second gate oxide layer region ;
    forming a photoresist pattern of the second gate oxide layer region on a surface of the substrate ;
    implanting nitrogen atoms into the first gate oxide layer region by an ion implantation process using the photoresist pattern of the second gate oxide layer region as a mask to form a nitrogen implantation layer;
    removing the photoresist pattern on the surface of the substrate to expose the second gate oxide layer region ; and
    forming a first gate oxide layer and a second gate oxide layer on the surface of the substrate at same time by a single thermal oxidation process,
    wherein the first gate oxide layer has a first thickness and the second gate oxide layer has a second thickness, different from the first thickness.
  2. The method according to claim 1, wherein:
    the first thickness is less than the second thickness;
    the first gate oxide layer is a thin gate oxide layer; and
    the second gate oxide layer is a thick gate oxide layer.
  3. The method according to claim 1, wherein:
    the nitrogen implantation layer is configured to control the different thicknesses of the first gate oxide layer and the second gate oxide layer during the single thermal oxidation process.
  4. The method according to claim 1, wherein:
    the implantation parameters are determined based on a thickness difference between the first gate oxide layer and the second gate oxide layer.
  5. The method according to claim 1, wherein forming the photoresist pattern includes :
    performing steps of applying photoresist, exposure, and developing sequentially on the surface of the substrate.
  6. The method according to claim 5, further including:
    before applying the photoresist, forming a silicon oxide layer on the surface of the substrate; and
    before forming the first gate oxide layer and the second and gate oxide layer, removing the silicon oxide layer.
  7. The method according to claim 6, wherein
    the silicon oxide layer is formed by a deposition process.
  8. The method according to claim 6, wherein
    the thickness of the silicon oxide layer is in a range of approximately 150-300 Å.
  9. The method according to claim 6, wherein:
    after forming the silicon oxide layer and before applying the photoresist, forming a well region in the substrate by an ion implantation process.
  10. The method according to claim 6, wherein
    the first gate oxide layer and the second gate oxide layer are separated by a local field oxidation isolation.
  11. The method according to claim 10, wherein the local field oxidation isolation is formed by :
    after forming the silicon oxide layer and before applying the photoresist, depositing a silicon nitride layer on the surface of the silicon oxide layer;
    forming a pattern of a local field oxidation isolation region in the silicon nitride layer;
    forming a local field oxidation isolation through an oxidization process using the silicon nitride layer as a mask; and
    removing the silicon nitride layer.
  12. The method according to claim 6, wherein
    the first gate oxide layer and the second gate oxide layer are separated by a shallow trench isolation.
  13. The method according to claim 12, wherein the shallow trench isolation is formed by :
    after forming the silicon oxide layer and before applying the photoresist, depositing a silicon nitride layer on the surface of the silicon oxide layer;
    forming a pattern of a shallow trench isolation region in the silicon nitride layer;
    forming the shallow trench isolation through an etching process using the silicon nitride layer as a mask;
    filling the shallow trench isolation with an insulating material; and
    removing the silicon nitride layer.
PCT/CN2011/082395 2010-11-29 2011-11-18 Method for manufacturing dual-gate oxide semiconductor devices WO2012071986A1 (en)

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