CN112382572B - Ono屏蔽栅的sgt结构及其制造方法 - Google Patents

Ono屏蔽栅的sgt结构及其制造方法 Download PDF

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CN112382572B
CN112382572B CN202110055819.8A CN202110055819A CN112382572B CN 112382572 B CN112382572 B CN 112382572B CN 202110055819 A CN202110055819 A CN 202110055819A CN 112382572 B CN112382572 B CN 112382572B
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杨乐
李铁生
楼颖颖
李恩求
刘琦
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Longteng Semiconductor Co ltd
Xi'an Longxiang Semiconductor Co ltd
Xusi Semiconductor Shanghai Co ltd
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Abstract

本发明涉及ONO屏蔽栅的SGT结构及其制造方法，在Si衬底片表面生长N型外延层，在外延层表面形成硬掩膜；刻蚀出深沟槽，内填硼硅玻璃BSG；将沟槽内BSG腐蚀至沟槽指定位置，进行第二层氮化硅淀积和厚氧化层淀积；沟槽内回填源极多晶硅并回刻；去除露出的厚氧化层；将沟槽内源极多晶硅刻蚀至沟槽指定位置；形成源极多晶硅氧化层，同时使硼硅玻璃BSG中硼Boron扩散至深沟槽外围的Si材料中形成P柱；去除露出的氮氧化物、薄氧化物；形成栅极氧化层,回填栅极多晶硅并回刻，形成器件的栅极；开接触孔和金属布线。本发明在暴露的硼硅玻璃上方淀积了高密度氮化硅，能有效阻止硼在后续的高温炉管工艺过程中析出。

Description

ONO屏蔽栅的SGT结构及其制造方法
技术领域
本发明属于半导体功率器件技术领域，具体涉及一种氧化硅-氮化硅-氧化硅（ONO）屏蔽栅的屏蔽栅极沟槽（Shield-Gate-Trench，SGT）结构及其制造方法。
背景技术
SGT结构因其具有电荷耦合效应，在传统沟槽金属-氧化物半导体场效应晶体管（Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET）垂直耗尽（P-Body/N-Epi结）基础上引入了水平耗尽，将器件电场由三角形分布改变为近似矩形分布。在采用同样掺杂浓度的外延规格情况下，器件可以获得更高的击穿电压，该结构在中低压功率器件领域得到广泛应用。
图14为现有的三段式SGT结构，在制造过程中，硼硅玻璃（Borosilicate glass，BSG）回刻蚀后，暴露的硼硅玻璃进入了前段工艺的炉管设备，硼硅玻璃在高温下会析出硼并扩散至炉管，沾污炉管设备，进而影响到其他进入该炉管设备的产品。另外此结构制造方法还需要使用工艺复杂的高密度等离子淀积工艺和高成本的化学机械研磨工艺，工艺成本稍高。
发明内容
本发明的目的是提供一种ONO屏蔽栅的SGT结构及其制造方法，SGT结构的屏蔽栅由ONO膜包围，克服现有技术的缺陷。
本发明所采用的技术方案为：
一种ONO屏蔽栅的SGT结构的制造方法，其特征在于：
所述SGT的屏蔽栅由ONO包围，所述方法包括以下步骤：
步骤一：在Si衬底片表面生长N型外延层；
步骤二：在外延层表面依次形成薄氧化层、薄氮化硅、厚氧化层，组成硬掩膜；
步骤三：利用沟槽光刻版进行光刻工艺，对沟槽位置曝光，再通过干法刻蚀，将曝光位置刻蚀出深沟槽；
步骤四：利用化学气相积淀（Chemical Vapor Deposition，CVD）工艺在深沟槽内填满硼硅玻璃，并通过回流工艺使表面平坦化；
步骤五：利用干法腐蚀将沟槽内硼硅玻璃腐蚀至沟槽指定位置；
步骤六：进行第二层氮化硅淀积；
步骤七：进行厚氧化层淀积；
步骤八：沟槽内回填源极多晶硅并回刻蚀至沟槽指定位置；
步骤九：使用湿法刻蚀将露出的厚氧化层去除；
步骤十：使用各向同性刻蚀，再次将沟槽内源极多晶硅刻蚀至沟槽指定位置；
步骤十一：使用热氧化工艺形成源极多晶硅氧化层，同时使硼硅玻璃材料中硼扩散至深沟槽外围的Si材料中，形成P柱；
步骤十二：使用湿法去除露出的氮氧化物、薄氧化物；
步骤十三：使用热氧化工艺形成栅极氧化层,回填栅极多晶硅并回刻蚀至沟槽指定位置，形成器件的栅极；然后与常规MOSFET的制程一样，直到开接触孔和金属布线。
步骤一中，外延层厚度为5微米至20微米。
步骤五中，利用干法腐蚀将沟槽内硼硅玻璃腐蚀至Si表面以下2微米至17微米。
步骤六：第二层氮化硅淀积厚度为0.05微米至1微米。
步骤七中，厚氧化层淀积厚度为0.1微米至1微米。
步骤八中，沟槽内回填源极多晶硅并回刻蚀，回刻蚀深度为1微米至1.5微米。
步骤十中，将沟槽内源极多晶硅刻蚀至厚氧化层下0.05微米至0.15微米。
一种如所述的方法制造的ONO屏蔽栅的SGT结构。
本发明具有以下优点：
本发明的方法在深沟槽内填充硼硅玻璃材料并回刻后，淀积氮化硅和厚氧化层，沟槽内回填多晶硅并回刻蚀，然后将露出的厚氧化层去除，接着将源极多晶硅回刻蚀，然后进行源极多晶硅氧化，同时使硼硅玻璃材料中硼扩散至深沟槽外围的Si材料中形成P柱，接着将露出的氮化硅层、薄氧化层去除,生长栅极氧化层后，回填多晶硅并回刻蚀形成栅极，最后经过一系列普通MOSFET工艺步骤形成最终三段式氧化层屏蔽栅沟槽MOSFET。采用该SGT MOSFET结构及工艺制造方法，在暴露的硼硅玻璃上方淀积了高密度氮化硅，阻止了硼硅玻璃中的硼在后续的高温炉管工艺过程中析出，同时该层氮化硅可以在源极多晶硅氧化层形成过程中对侧壁硅进行氧气隔绝，阻止侧壁硅的氧化，使源极多晶硅氧化层厚度更加可控，省去了原有的高密度等离子淀积工艺和化学机械研磨工艺，降低制造成本，增强市场竞争力。
附图说明
图1为本发明步骤一的示意图；
图2为本发明步骤二的示意图；
图3为本发明步骤三的示意图；
图4为本发明步骤四的示意图；
图5为本发明步骤五的示意图；
图6为本发明步骤六的示意图；
图7为本发明步骤七的示意图；
图8为本发明步骤八的示意图；
图9为本发明步骤九的示意图；
图10为本发明步骤十的示意图；
图11为本发明步骤十一的示意图；
图12为本发明步骤十二的示意图；
图13为本发明结构示意图；
图14为现有的三段式氧化层SGT结构示意图。
具体实施方式
下面结合具体实施方式对本发明进行详细的说明。
本发明涉及一种ONO屏蔽栅的SGT结构的制造方法，所述SGT的屏蔽栅由ONO包围，所述方法包括以下步骤：
步骤一：在Si衬底片表面生长N型外延层；
步骤二：在外延层表面依次形成薄氧化层、薄氮化硅、厚氧化层，组成硬掩膜；
步骤三：利用沟槽光刻版进行光刻工艺，对沟槽位置曝光，再通过干法刻蚀，将曝光位置刻蚀出深沟槽；
步骤四：利用CVD工艺在深沟槽内填满硼硅玻璃，并通过回流工艺使表面平坦化；
步骤五：利用干法腐蚀将沟槽内BSG腐蚀至沟槽指定位置；
步骤六：进行第二层氮化硅淀积；
步骤七：进行厚氧化层淀积；
步骤八：沟槽内回填源极多晶硅并回刻蚀至沟槽指定位置；
步骤九：使用湿法刻蚀将露出的厚氧化层去除；
步骤十：使用各向同性刻蚀，再次将沟槽内源极多晶硅刻蚀至沟槽指定位置；
步骤十一：使用热氧化工艺形成源极多晶硅氧化层，同时使硼硅玻璃材料中硼扩散至深沟槽外围的Si材料中，形成P柱；
步骤十二：使用湿法去除露出的氮氧化物、薄氧化物；
步骤十三：使用热氧化工艺形成栅极氧化层,回填栅极多晶硅并回刻蚀至沟槽指定位置，形成器件的栅极；然后与常规MOSFET的制程一样，直到开接触孔和金属布线。
采用本发明所述方法制作的SGT MOSFET，可以在传统SGT MOSFET基础上实现较小的器件尺寸的同时，植入的硼硅玻璃可以灵活调节P柱的宽度和浓度，有利于增加电荷平衡区域，降低外延电阻率，极大的降低芯片单位面积导通电阻，优化器件参数和性能。第二层氮化硅的使用可以阻止BSG材料中硼在后续的炉管工艺中扩散，沾污炉管设备，工艺更安全可控。同时第二层氮化硅可以在生长源极多晶硅氧化层过程中，阻止侧壁硅的氧化，使源极多晶硅氧化层厚度更加可控。
以下结合附图对本发明的制造步骤进行进一步详细的说明：
步骤一：在Si衬底片表面生长N型外延层，外延层厚度根据器件所需源漏耐压制定，范围从5微米至20微米，如图1所示。
步骤二：形成ONO膜为硬掩膜。如图2所示。
步骤三：利用沟槽光刻版进行光刻工艺，需要挖沟槽的位置曝光，无光刻胶掩蔽，其余部分用光刻胶掩蔽，然后通过干法刻蚀，将无光刻胶掩蔽位置刻蚀出深沟槽，然后去除光刻胶，如图3所示。
步骤四：利用CVD工艺在深沟槽内填充BSG材料，并进行回流，保证将深沟槽内填满并且表面平整，如图4所示。
步骤五：利用干法腐蚀将沟槽内BSG腐蚀至Si表面以下2微米至17微米，如图5所示。
步骤六：进行第二层氮化硅淀积，厚度约0.05微米至1微米。如图6所示。
步骤七：进行厚氧化层淀积，厚度约0.1微米至1微米，厚度根据器件所需漏源耐压制定，如图7所示。
步骤八：沟槽内回填源极多晶硅并回刻蚀，深度1微米至1.5微米，如图8所示。
步骤九：使用湿法刻蚀将露出的厚氧化层去除，如图9所示。
步骤十：使用各向同性刻蚀，再次将沟槽内源极多晶硅刻蚀至厚氧化层下0.05微米至0.15微米，如图10所示。
步骤十一：使用热氧化工艺形成源极多晶硅氧化层，同时使硼硅玻璃材料中硼扩散至深沟槽外围的Si材料中，形成P柱，如图11所示。
步骤十二：使用湿法去除露出的氮氧化物、薄氧化物，如图12所示。
步骤十三：使用热氧化工艺形成栅极氧化层，回填栅极多晶硅并回刻蚀至沟槽指定位置，形成器件的栅极；然后与常规MOSFET的制程一样，直到开接触孔和金属布线，完成后最终器件结构如图13所示。
本发明的内容不限于实施例所列举，本领域普通技术人员通过阅读本发明说明书而对本发明技术方案采取的任何等效的变换，均为本发明的权利要求所涵盖。

Claims (8)

1.一种ONO屏蔽栅的SGT结构的制造方法，其特征在于：
所述SGT的屏蔽栅由ONO包围，所述方法包括以下步骤：
步骤一：在Si衬底片表面生长N型外延层；
步骤二：在外延层表面依次形成薄氧化层、薄氮化硅、厚氧化层，组成硬掩膜；
步骤三：利用沟槽光刻版进行光刻工艺，对沟槽位置曝光，再通过干法刻蚀，将曝光位置刻蚀出深沟槽；
步骤四：利用CVD工艺在深沟槽内填满硼硅玻璃，并通过回流工艺使表面平坦化；
步骤五：利用干法腐蚀将沟槽内硼硅玻璃腐蚀至沟槽指定位置；
步骤六：进行第二层氮化硅淀积；
步骤七：进行厚氧化层淀积；
步骤八：沟槽内回填源极多晶硅并回刻蚀至沟槽指定位置；
步骤九：使用湿法刻蚀将露出的厚氧化层去除；
步骤十：使用各向同性刻蚀，再次将沟槽内源极多晶硅刻蚀至沟槽指定位置；
步骤十一：使用热氧化工艺形成源极多晶硅氧化层，同时使硼硅玻璃材料中硼扩散至深沟槽外围的Si材料中，形成P柱；
步骤十二：使用湿法去除露出的氮氧化物、薄氧化物；
步骤十三：使用热氧化工艺形成栅极氧化层,回填栅极多晶硅并回刻蚀至沟槽指定位置，形成器件的栅极；然后与常规MOSFET的制程一样，直到开接触孔和金属布线。
2.根据权利要求1所述的ONO屏蔽栅的SGT结构的制造方法，其特征在于：
步骤一中，外延层厚度为5微米至20微米。
3.根据权利要求2所述的ONO屏蔽栅的SGT结构的制造方法，其特征在于：
步骤五中，利用干法腐蚀将沟槽内硼硅玻璃腐蚀至Si表面以下2微米至17微米。
4.根据权利要求3所述的ONO屏蔽栅的SGT结构的制造方法，其特征在于：
步骤六：第二层氮化硅淀积厚度为0.05微米至1微米。
5.根据权利要求4所述的ONO屏蔽栅的SGT结构的制造方法，其特征在于：
步骤七中，厚氧化层淀积厚度为0.1微米至1微米。
6.根据权利要求5所述的ONO屏蔽栅的SGT结构的制造方法，其特征在于：
步骤八中，沟槽内回填源极多晶硅并回刻蚀，回刻蚀深度为1微米至1.5微米。
7.根据权利要求6所述的ONO屏蔽栅的SGT结构的制造方法，其特征在于：
步骤十中，将沟槽内源极多晶硅刻蚀至厚氧化层下0.05微米至0.15微米。
8.一种如权利要求7所述的方法制造的ONO屏蔽栅的SGT结构。
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