CN102214561A - 超级结半导体器件及其制造方法 - Google Patents

超级结半导体器件及其制造方法 Download PDF

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CN102214561A
CN102214561A CN2010101410645A CN201010141064A CN102214561A CN 102214561 A CN102214561 A CN 102214561A CN 2010101410645 A CN2010101410645 A CN 2010101410645A CN 201010141064 A CN201010141064 A CN 201010141064A CN 102214561 A CN102214561 A CN 102214561A
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肖胜安
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

本发明公开了一种超级结半导体器件的制造方法，包括步骤：在N型硅外延层上生长一介质膜，利用光刻和刻蚀工艺形成沟槽；在沟槽侧壁淀积一含碳硅层；在沟槽中淀积一P型半导体薄层填满所述沟槽；将N型外延层表面的P型半导体薄层、含碳硅层以及介质膜去除。本发明公开了另一种超级结半导体器件的制造方法，和第一种方法不同的是步骤二为在沟槽侧壁通过扩散形成一碳薄层。本发明还公开了一种超级结半导体器件。本发明能抑制超级结半导体器件中的P型半导体薄层的P型杂质在后续热过程中扩散到N型半导体薄层中，减少N型半导体薄层被补偿的N型载流子数，从而减少器件的比抵抗电阻，提高器件的性能。

Description

超级结半导体器件及其制造方法
技术领域
本发明涉及半导体集成电路制造领域，特别是涉及一种超级结半导体器件，本发明还涉及该超级结半导体器件制造方法。
背景技术
超级结MOSFET采用新的耐压层结构，利用一系列的交替排列的P型半导体薄层和N型半导体薄层来在截止状态下在较低电压下就将所述P型半导体薄层和N型半导体薄层耗尽，实现电荷相互补偿，从而使P型半导体薄层和N型半导体薄层在高掺杂浓度下能实现高的击穿电压，从而同时获得低导通电阻和高击穿电压，打破传统功率MOSFET理论极限。超级结半导体器件的结构和制造方法可分为两大类，第一类是利用多次光刻、外延成长和注入工艺来获得交替的P型掺杂区和N型掺杂区；第二类是在N型硅外延层上开沟槽，往该沟槽中填入P型多晶硅，或倾斜注入P型杂质，或填入P型外延层。上述第一类制造方法不仅工艺复杂，实现难度大，而且成本很高。第二类工艺中，利用P型外延层填满沟槽的方法虽然工艺难度较大，但由于其拥有成本低的特点，很有应用前景。
以上方法中，不论那一类，在交替的P型半导体薄层和N型半导体薄层形成后，还有后续长时间的高温工艺，如栅氧生成工艺、推阱工艺、源漏注入后的高温退火工艺和BPSG回流工艺，这些工艺会使P型半导体薄层如P型外延层中的B扩散到N型半导体薄层中，从而将所述N型半导体薄层中部分N型载流子中和掉，使所述超级结半导体器件的比导通电阻提高。为了减少这种效应，一种方法是将推阱工艺提到P型半导体薄层形成之前进行，但一方面该方法只能在部分工艺中实现；另一方面，即使不考虑所述推阱工艺，其它的热过程工艺如栅氧生成工艺，源漏注入后的高温退火工艺和BPSG回流工艺对B扩散的作用也不小；特别是，在所述超级结半导体器件工艺被用于中压如源漏击穿电压(BVDS)为200V及其之下时，由于每个薄层的厚度在减少，这一效应的影响就越不可以不考虑。
发明内容
本发明所要解决的技术问题是提供一种超级结半导体器件的制造方法，能抑制超级结半导体器件中的P型半导体薄层的P型杂质在后续热过程中扩散到N型半导体薄层中，减少N型半导体薄层被补偿的N型载流子数，从而减少器件的比抵抗电阻，提高器件的性能；本发明还提供一种超级结半导体器件。
为解决上述技术问题，本发明提供的一种超级结半导体器件的制造方法，形成所述超级结半导体器件的交替型P型半导体薄层和N型半导体薄层时包括如下步骤：
步骤一、在一N+硅基片上生长一层N型硅外延层，在所述N型硅外延层上生长一介质膜，利用光刻和刻蚀工艺形成沟槽。
步骤二、在所述沟槽侧壁淀积一层含碳硅层，所述含碳硅层能为N型、或P型、或本征型。
步骤三、在所述沟槽中淀积一P型半导体薄层填满所述沟槽，所述P型半导体薄层能为一P型硅层、或一P型硅层加一介质层、或一P型硅层加一不掺杂硅层。所述P型硅层能为P型单晶硅、或P型多晶硅、或P型不定型硅。所述P型单晶硅的生长温度能为650℃到1200℃。所述P型多晶硅的生长温度能为580℃到650℃。所述P型不定型硅的生长温度能为510℃到579℃。
步骤四、利用回刻或化学机械研磨将所述N型外延层表面的所述P型半导体薄层、所述含碳硅层以及所述介质膜去除。
本发明提供的一种超级结半导体器件，包含交替型P型半导体薄层和N型半导体薄层，在所述P型半导体薄层和所述N型半导体薄层之间含有一层含碳硅层。
本发明提供的另一种超级结半导体器件的制造方法，形成所述超级结半导体器件的交替型P型半导体薄层和N型半导体薄层时包括如下步骤：
步骤一、在一N+硅基片上生长一层N型硅外延层，在所述N型硅外延层上生长一介质膜，利用光刻和刻蚀工艺形成沟槽。
步骤二、在所述沟槽侧壁通过扩散工艺形成一层碳薄层。
步骤三、在所述沟槽中淀积一P型半导体薄层填满所述沟槽，所述P型半导体薄层能为一P型硅层、或一P型硅层加一介质层、或一P型硅层加一不掺杂硅层。所述P型硅层能为P型单晶硅、或P型多晶硅、或P型不定型硅。所述P型单晶硅的生长温度能为650℃到1200℃。所述P型多晶硅的生长温度能为580℃到650℃。所述P型不定型硅的生长温度能为510℃到579℃。
步骤四、利用回刻或化学机械研磨将所述N型外延层表面的所述P型半导体薄层以及所述介质膜去除。
本发明提供的另一种超级结半导体器件，包含交替型P型半导体薄层和N型半导体薄层，在所述P型半导体薄层和所述N型半导体薄层之间含有一层碳薄层。
本发明制造方法所得到的所述超级结半导体器件，在所述P型半导体薄层和所述N型半导体薄层之间含有一层含碳硅层或一碳薄层，所述含碳硅层或碳薄层能抑制P型半导体薄层中的硼(B)在后续工艺的热过程中扩散到N型半导体薄层中，通过这一扩散的抑制使N型杂质层的被补偿(或中和)N型载流子减少，从而减小器件的比抵抗电阻，提高器件的性能。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1A-图1D是本发明实施例一超级结半导体器件的制造方法的各步骤中器件的截面图；
图2是本发明实施例一超级结半导体器件的结构示意图；
图3A-图3D是本发明实施例二超级结半导体器件的制造方法的各步骤中器件的截面图。
具体实施方式
如图1A-图1D所示，是本发明实施例一超级结半导体器件的制造方法的各步骤中器件的截面图，形成所述超级结半导体器件的交替型P型半导体薄层和N型半导体薄层时包括如下步骤：
步骤一、如图1A所示，在一N+硅基片1上生长一层N型硅外延层2；所述N+硅基片1的电阻率在0.001欧姆·厘米～0.003欧姆·厘米；所述N型硅外延层2的厚度和电阻率是按照器件设计的要求来确定的，如对源漏击穿电压(BVDS)为600V的器件，所述N型硅外延层2的电阻率选取在2欧姆·厘米～10欧姆·厘米、厚度选取40微米～55微米。在所述N型硅外延层2上生长一层氧化硅膜3，所述氧化硅膜3能做为后续沟槽刻蚀工艺的掩膜、也能做为化学机械研磨时阻挡层。通过光刻工艺和刻蚀工艺得到沟槽的图形，所述沟槽的深度能穿过所述N型硅外延层2到达所述N+硅基片1、也能只停留在所述N型硅外延层2中。所述氧化硅膜3能采用热氧化工艺生长、也能采用化学气象淀积(CVD)工艺来实现。所述沟槽的刻蚀工艺能利用所述氧化硅膜3做为掩膜、也能利用光刻胶做为掩膜，刻蚀后的所述氧化硅膜厚度要在1000埃以上。
步骤二、如图1B所示，在所述沟槽侧壁生长一层含碳硅层41，所述含碳硅层41能为N型、或P型、或本征型。所述含碳硅层41的厚度小于3000埃，掺碳浓度要比其后填的P型半导体薄层42中硼浓度高，最好要求高一个数量级以上。所述含碳硅层41是P型时，那么其P型杂质浓度要与P型半导体薄层42中的硼浓度在同一数量级上；如果所述含碳硅层41是N型的，那么其N型杂质浓度要与所述硅外延层2中的N型杂质浓度在同一数量级上。
步骤三、如图1C所示，在所述沟槽中淀积一P型半导体薄层42填满所述沟槽，所述P型半导体薄层能为一P型硅层、或一P型硅层加一介质层、或一P型硅层加一不掺杂硅层。所述P型硅层中的杂质用于平衡相邻的N型半导体薄层中的N型杂质，为了得到理想的器件特性，P型半导体薄层中的P型杂质总量要与N型半导体薄层中的N型杂质总量相同，如果所述含碳硅层41是P型或N型时，其中的杂质也要考虑。为了得到无缝的填充并减少工艺难度，P型半导体薄层42中能先填充一P型硅层，之后再填充介质膜如BPSG，利用BPSG的流动性将沟槽完好填充；也能先填一层P型硅层后，再填一层不掺杂硅层，利用不掺杂硅层中即使有空洞也不会有大的漏电的特性来得到好的器件特性。这里的所述P型硅层能为单晶硅、多晶硅或不定型硅；所述P型单晶硅的生长温度在650℃到1200℃之间，所述P型多晶硅的生长温度能在580℃到650℃之间，所述P型不定型硅的生长温度能在510℃到579℃之间。
步骤四、如图1D所示，利用化学机械研磨或回刻将所述硅外延层2表面的所述含碳硅层41和所述P型半导体薄层42去除，之后再将表面的介质膜即所述氧化硅膜3去掉。当进行化学机械研磨时，为了保证研磨中不对所述氧化硅膜3下的硅造成损伤，建议研磨完成后残留的所述氧化硅膜3厚度要大于500埃。
利用以上步骤一到四，就得到了一种交替的P型和N型半导体薄层，其特征是P型层和N型层之间有一层含碳的硅。
之后，利用成熟的纵向双扩散金属氧化物半导体(VDMOS，verticaldouble-diffusion metal-oxide-semiconductor)加工工艺得到对应的超级结NMOS器件单元结构，如图2所示，包括步骤：位于所述N硅外延层2上端的栅氧5和多晶硅栅6的形成；P阱7，N+源8的形成；包覆所述多晶硅栅6的层间介质膜9、接触孔10的形成，P+接触注入层11的形成；金属源极12形成和栅极形成；背面金属漏电极14。
如图3A-图3D所示，是本发明实施例二超级结半导体器件的制造方法的各步骤中器件的截面图，本发明实施例二超级结半导体器件的制造方法和本发明实施例一超级结半导体器件的制造方法的步骤一、三、四相同，其中步骤二不同，不同之处为：在步骤二中不是淀积一层含碳硅层41，而是利用扩散工艺在所述沟槽的硅表面吸附一个碳薄层43，所述碳薄层43的碳浓度建议在经过后续热过程之后能比步骤三中形成的半导体薄层44中的P型杂质浓度高，一般建议高出一个数量级以上。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (13)

1.一种超级结半导体器件的制造方法，其特征在于，形成所述超级结半导体器件的交替型P型半导体薄层和N型半导体薄层时包括如下步骤：
步骤一、在一N+硅基片上生长一层N型硅外延层，在所述N型硅外延层上生长一介质膜，利用光刻和刻蚀工艺形成沟槽；
步骤二、在所述沟槽侧壁淀积一层含碳硅层；
步骤三、在所述沟槽中淀积一P型半导体薄层填满所述沟槽，所述P型半导体薄层能为一P型硅层、或一P型硅层加一介质层、或一P型硅层加一不掺杂硅层；
步骤四、利用回刻或化学机械研磨将所述N型外延层表面的所述P型半导体薄层、所述含碳硅层以及所述介质膜去除。
2.如权利要求1所述的超级结半导体器件的制造方法，其特征在于：步骤二中所述含碳硅层能为N型、或P型、或本征型。
3.如权利要求1所述的超级结半导体器件的制造方法，其特征在于：步骤三中所述P型硅层能为P型单晶硅、或P型多晶硅、或P型不定型硅。
4.如权利要求5所述的超级结半导体器件的制造方法，其特征在于：所述P型单晶硅的生长温度为650℃到1200℃。
5.如权利要求5所述的超级结半导体器件的制造方法，其特征在于：所述P型多晶硅的生长温度为580℃到650℃。
6.如权利要求5所述的超级结半导体器件的制造方法，其特征在于：所述P型不定型硅的生长温度为510℃到579℃。
7.一种超级结半导体器件，包含交替型P型半导体薄层和N型半导体薄层，其特征在于：在所述P型半导体薄层和所述N型半导体薄层之间含有一层含碳硅层。
8.一种超级结半导体器件的制造方法，其特征在于，形成所述超级结半导体器件的交替型P型半导体薄层和N型半导体薄层时包括如下步骤：
步骤一、在一N+硅基片上生长一层N型硅外延层，在所述N型硅外延层上生长一介质膜，利用光刻和刻蚀工艺形成沟槽；
步骤二、在所述沟槽侧壁通过扩散工艺形成一层碳薄层；
步骤三、在所述沟槽中淀积一P型半导体薄层填满所述沟槽，所述P型半导体薄层能为一P型硅层、或一P型硅层加一介质层、或一P型硅层加一不掺杂硅层；
步骤四、利用回刻或化学机械研磨将所述N型外延层表面的所述P型半导体薄层以及所述介质膜去除。
9.如权利要求8所述的超级结半导体器件的制造方法，其特征在于：步骤三中所述P型硅层能为P型单晶硅、或P型多晶硅、或P型不定型硅。
10.如权利要求9所述的超级结半导体器件的制造方法，其特征在于：所述P型单晶硅的生长温度为650℃到1200℃。
11.如权利要求9所述的超级结半导体器件的制造方法，其特征在于：所述P型多晶硅的生长温度为580℃到650℃。
12.如权利要求9所述的超级结半导体器件的制造方法，其特征在于：所述P型不定型硅的生长温度为510℃到579℃。
13.一种超级结半导体器件，包含交替型P型半导体薄层和N型半导体薄层，其特征在于：在所述P型半导体薄层和所述N型半导体薄层之间含有一层碳薄层。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103633137A (zh) * 2012-08-21 2014-03-12 朱江 一种具有底部隔离电荷补偿结构半导体晶片及其制备方法
CN105321819A (zh) * 2014-07-15 2016-02-10 富士电机株式会社 半导体装置的制造方法
CN105679809A (zh) * 2016-01-15 2016-06-15 上海华虹宏力半导体制造有限公司 沟槽型超级结的制造方法
CN109817700A (zh) * 2019-01-15 2019-05-28 上海华虹宏力半导体制造有限公司 超级结深沟槽填充方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030025154A1 (en) * 2001-08-02 2003-02-06 Haynie Sheldon D. LDMOS high voltage structure compatible with VLSI CMOS processes
CN1885557A (zh) * 2005-06-21 2006-12-27 台湾积体电路制造股份有限公司 半导体元件及形成半导体元件的方法
CN101060132A (zh) * 2006-04-19 2007-10-24 丰田自动车株式会社 半导体器件及其制造方法
CN101308875A (zh) * 2007-05-14 2008-11-19 株式会社电装 具有超结结构的半导体器件及其制造方法
CN101506940A (zh) * 2006-08-25 2009-08-12 飞思卡尔半导体公司 超结沟槽器件及方法
CN101640171A (zh) * 2008-08-01 2010-02-03 富士电机电子技术株式会社 半导体器件制造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7507631B2 (en) * 2006-07-06 2009-03-24 International Business Machines Corporation Epitaxial filled deep trench structures
US8187955B2 (en) * 2009-08-24 2012-05-29 International Business Machines Corporation Graphene growth on a carbon-containing semiconductor layer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030025154A1 (en) * 2001-08-02 2003-02-06 Haynie Sheldon D. LDMOS high voltage structure compatible with VLSI CMOS processes
CN1885557A (zh) * 2005-06-21 2006-12-27 台湾积体电路制造股份有限公司 半导体元件及形成半导体元件的方法
CN101060132A (zh) * 2006-04-19 2007-10-24 丰田自动车株式会社 半导体器件及其制造方法
CN101506940A (zh) * 2006-08-25 2009-08-12 飞思卡尔半导体公司 超结沟槽器件及方法
CN101308875A (zh) * 2007-05-14 2008-11-19 株式会社电装 具有超结结构的半导体器件及其制造方法
CN101640171A (zh) * 2008-08-01 2010-02-03 富士电机电子技术株式会社 半导体器件制造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103633137A (zh) * 2012-08-21 2014-03-12 朱江 一种具有底部隔离电荷补偿结构半导体晶片及其制备方法
CN105321819A (zh) * 2014-07-15 2016-02-10 富士电机株式会社 半导体装置的制造方法
CN105321819B (zh) * 2014-07-15 2019-07-26 富士电机株式会社 半导体装置的制造方法
CN105679809A (zh) * 2016-01-15 2016-06-15 上海华虹宏力半导体制造有限公司 沟槽型超级结的制造方法
CN109817700A (zh) * 2019-01-15 2019-05-28 上海华虹宏力半导体制造有限公司 超级结深沟槽填充方法

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