CN112635331B - 一种超级结功率器件的制备方法 - Google Patents

一种超级结功率器件的制备方法 Download PDF

Info

Publication number
CN112635331B
CN112635331B CN202110076522.XA CN202110076522A CN112635331B CN 112635331 B CN112635331 B CN 112635331B CN 202110076522 A CN202110076522 A CN 202110076522A CN 112635331 B CN112635331 B CN 112635331B
Authority
CN
China
Prior art keywords
layer
gate
super junction
grid
epitaxial layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110076522.XA
Other languages
English (en)
Other versions
CN112635331A (zh
Inventor
金宰年
叶宏伦
钟其龙
刘芝韧
刘崇志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Changlong Zhixin Semiconductor Co ltd
Original Assignee
Beijing Libaosheng Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Libaosheng Technology Co ltd filed Critical Beijing Libaosheng Technology Co ltd
Priority to CN202110076522.XA priority Critical patent/CN112635331B/zh
Publication of CN112635331A publication Critical patent/CN112635331A/zh
Application granted granted Critical
Publication of CN112635331B publication Critical patent/CN112635331B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明公开了一种超级结功率器件的制备方法，其通过热扩散工艺将第二外延层的掺杂质扩散进入第一外延层中，从而得到超级结；本发明能有效提高超级结功率器件的耐压值并降低导通电阻。

Description

一种超级结功率器件的制备方法
技术领域
本发明涉及半导体技术领域，特别是指一种超级结功率器件的制备方法。
背景技术
超级结功率器件是一种发展迅速、应用广泛的新型功率半导体器件。它是在普通双扩撒金属氧化物半导体(DMOS)的基础上引入超级结(SuperJunction)结构；除了具备DMOS输入阻抗高、开关速度快、工作频率高、易电压控制、热稳定好、驱动电路简单、易于集成等特点外，还克服了DMOS的导通电阻随着击穿电压成2.5次方关系增加的缺点。目前超级结DMOS已广泛应用于面向个人电脑、笔记本电脑、上网本、手机、照明(高压气体放电灯)产品以及电视机(液晶或等离子电视机)和游戏机等消费电子产品的电源或适配器。
目前超级结功率器件的制造方法主要分成两大类，第一类是利用多次外延和注入的方式在N型外延衬底上形成P型柱；第二类是采用深沟槽蚀刻加P型柱填充的方式形成。但是第一类制造方法存在电子不均与扩散的情况，局限了掺杂质浓度；而第二类制造方法中，蚀刻深度和氧化膜厚度也受限于垂直方向的气流强度；因此现有的超级结功率器件的电气性能还有待改善。
发明内容
本发明的目的在于提供一种超级结功率器件的制备方法，其能有效改善超级结功率器件的电气性能。
为了达成上述目的，本发明的解决方案是：
一种超级结功率器件的制备方法，其包括如下步骤：
步骤1：提供具有高掺杂浓度且具有N型导电类型的半导体衬底，并在该半导体衬底正面形成具有N型导电类型的第一外延层；
步骤2：对第一外延层正面进行蚀刻以形成若干个栅极沟槽，并在第一外延层上生长防护层，防护层覆盖第一外延层的顶面和各栅极沟槽；
步骤3：蚀刻移除防护层处于各栅极沟槽底部的部分，并对第一外延层处于各栅极沟槽底部的部分进行蚀刻，以形成位于栅极沟槽下方的超级结沟槽；
步骤4：沉积具有P型导电类型的第二外延层，该第二外延层覆盖防护层以及各超级结沟槽；
步骤5：通过热扩散工艺，使得第二外延层中覆盖超级结沟槽的部分中的具有P型导电类型的掺杂质扩散进入第一外延层中而使得第一外延层中形成具有P型导电类型的第二导电区，而第一外延层中处于相邻第二导电区之间的部分则构成具有N型导电类型的第一导电区，第一导电区和第二导电区交替排列形成超级结；与此同时，第二外延层中覆盖超级结沟槽的部分则形成覆盖第二导电区的厚氧化层；
步骤6：在超级结沟槽中填充浮动栅极；
步骤7：将全部的防护层移除，然后再生成栅极氧化层，该栅极氧化层覆盖浮动栅极、第一外延层的顶面以及各栅极沟槽；
步骤8：在栅极沟槽中填充栅极，然后再形成覆盖栅极氧化层和栅极的保护层；
步骤9：对保护层和栅极氧化层进行蚀刻，以去除栅极氧化层和保护层处于各栅极沟槽两侧的上方的部分以及部分去除保护层处于栅极上方的部分，从而得到包覆栅极的栅极保护层；
步骤10：先将离子注入第一外延层处于各栅极沟槽两侧的部分而形成处于各栅极沟槽两侧的通道；然后沉积覆盖通道的N型源区和P型源区；最后沉积源极金属和漏极金属，源极金属覆盖N型源区、P型源区和栅极保护层，漏极金属覆盖半导体衬底背面。
所述第二外延层的掺杂质为硼或铝或镓或铟。
所述半导体衬底、浮动栅极和栅极均为多晶硅；或者，所述半导体衬底、浮动栅极和栅极均为多晶碳化硅。
在所述步骤6中，在超级结沟槽中填充浮动栅极的方法包括：
步骤6.1：沉积浮动栅极层，该浮动栅极层覆盖防护层并填满栅极沟槽和超级结沟槽；
步骤6.2：蚀刻浮动栅极层而将浮动栅极层中覆盖防护层和填充在栅极沟槽中的部分移除，浮动栅极层保留在超级结沟槽中的部分则构成所述浮动栅极。
在所述步骤8中，在栅极沟槽中填充栅极的方法包括：
步骤8.1：沉积栅极层，该栅极层覆盖栅极氧化膜并填满栅极沟槽；
步骤8.2：蚀刻栅极层而将栅极层覆盖栅极氧化膜的部分移除，栅极层保留在栅极沟槽中的部分则构成所述栅极。
所述防护层包括依次生长的基础防护层和钝化层；所述基础防护层为氮化膜或氧化膜。
采用上述方案后，本发明具有以下特点：
1、通过本发明制备的超级结功率器件具有耐压值高、导通电阻低的优点；
2、本发明通过设置栅极保护层能保护通道，防止其他掺杂质渗入通道，从而防止超级结功率器件的晶格结构被破坏和出现漏电情况，使得超级结功率器件的电气性能好。
附图说明
图1为本发明步骤1的示意图；
图2为本发明步骤2的示意图；
图3为本发明步骤3的示意图；
图4为本发明步骤4的示意图；
图5为本发明步骤5的示意图；
图6为本发明步骤6的示意图；
图7为本发明步骤7的示意图；
图8为本发明步骤8的示意图；
图9为本发明步骤9的示意图；
图10为本发明步骤10的示意图；
标号说明：
半导体衬底1，
第一外延层2，栅极沟槽21，超级结沟槽22，第一导电区23，第二导电区24，
防护层3，基础防护层31，钝化层32，
第二外延层4，
厚氧化层5，
浮动栅极层6，浮动栅极61，
栅极保护层7，栅极氧化层71，保护层72，
栅极层8，栅极81，
保护层9，
通道9，N型源区10，P型源区11，源极金属12，漏极金属13。
具体实施方式
为了进一步解释本发明的技术方案，下面通过具体实施例来对本发明进行详细阐述。
如图1至图10所示，本发明揭示了一种超级结功率器件的制备方法，其包括如下步骤：
步骤1：提供具有高掺杂浓度且具有N型导电类型的半导体衬底1，并在该N型半导体衬底1正面形成具有N型导电类型的第一外延层2；
步骤2：对第一外延层2正面进行蚀刻以形成若干个栅极沟槽21，并在第一外延层2上生长防护层3，防护层3覆盖第一外延层2的顶面和各栅极沟槽21；所述防护层3可包括依次生长的基础防护层31和钝化层32，基础防护层31为氮化膜或氧化膜。
步骤3：蚀刻移除防护层3处于各栅极沟槽21底部的部分，并第一外延层2处于各栅极沟槽21底部的部分进行蚀刻，以形成位于栅极沟槽21下方的超级结沟槽22；
步骤4：沉积具有P型导电类型的第二外延层4，该第二外延层4覆盖防护层3以及各超级结沟槽22；
步骤5：通过热扩散工艺，使得第二外延层4中覆盖超级结沟槽22的部分中的P型导电类型掺杂质扩散进入第一外延层2中而使得第一外延层2中形成具有P型导电类型的第二导电区24，而第一外延层2中处于相邻第二导电区24之间的部分则构成具有N型导电类型的第一导电区23，第一导电区23和第二导电区24交替排列形成超级结；与此同时，第二外延层4中覆盖超级结沟槽的部分则形成覆盖第二导电区24的厚氧化层5；
步骤6：在超级结沟槽22中填充浮动栅极61；
步骤7：将全部的防护层3移除，然后再生成栅极氧化层71，栅极氧化层71覆盖浮动栅极、第一外延层2的顶面以及各栅极沟槽21；
步骤8：在栅极沟槽21中填充栅极81，然后再形成覆盖栅极氧化层71和栅极81的保护层72；
步骤9：对保护层71和栅极氧化层72进行蚀刻，以去除栅极氧化层71和保护层72处于各栅极沟槽21两侧的上方的部分以及部分去除保护层72处于栅极81上方的部分，从而得到包覆栅极81的栅极保护层7；该栅极保护层7由保护层71和栅极氧化层72蚀刻剩下的部分组合而成；
步骤10：先将离子注入第一外延层2处于各栅极沟槽21两侧的部分而形成处于各栅极沟槽21两侧的通道9；然后沉积覆盖通道9的N型源区10和P型源区11；最后沉积源极金属12和漏极金属13，源极金属12覆盖N型源区10、P型源区11和栅极保护层7，漏极金属13覆盖半导体衬底1背面。
在本发明的步骤3中，由于防护层3的存在，本发明在成型超级结沟槽时，不会扩宽栅极沟槽21，有助于能改善超级结功率器件电气性能。
在本发明中，在所述步骤4中，沉积具有P型导电类型的第二外延层4的方法包括：
步骤4.1：沉积一层第二外延层薄膜，该第二外延层薄膜覆盖防护层3以及各超级结沟槽22；第二外延层薄膜可以为碳化硅薄膜或硅薄膜；
步骤4.2：通过离子注入工艺将具有P型导电类型的第二外延层离子注入第二外延层薄膜；
步骤4.3：在第二外延层薄膜上沉积一层硼硅玻璃或硼磷硅玻璃，从而形成第二外延层4；
而在所述步骤5中，通过热扩散工艺，在高温作用下，第二外延层4中覆盖超级结沟槽的部分中的掺杂质都进入第一外延层2而剩下氧化硅，剩下的氧化硅即形成厚氧化层5；
在本发明中，在所述步骤6中，在超级结沟槽22中填充浮动栅极61的方法包括：
步骤6.1：沉积浮动栅极层6，该浮动栅极层6覆盖防护层3并填满栅极沟槽21和超级结沟槽22；
步骤6.2：蚀刻浮动栅极层6而将浮动栅极层6覆盖防护层3和填充在栅极沟槽21中的部分移除，浮动栅极层6保留在超级结沟槽22中的部分则构成所述浮动栅极61。
在本发明中，在所述步骤8中，在栅极沟槽21中填充栅极81的方法包括：
步骤8.1：沉积栅极层8，该栅极层8覆盖栅极氧化膜7并填满栅极沟槽21；
步骤8.2：蚀刻栅极层8而将栅极层8覆盖栅极氧化膜7的部分移除，栅极层8保留在栅极沟槽21中的部分则构成所述栅极81；其中蚀刻栅极层8可以采用湿式蚀刻法或干式蚀刻法。
在本发明中，所述第二外延层4的掺杂质可以选用硼或铝或镓或铟。
在本发明中，所述半导体衬底1、浮动栅极61和栅极81均为多晶硅，这样本发明制备的超级结功率器件为纯硅功率器件；在本发明中，所述半导体衬底1、浮动栅极61和栅极82也可以均为多晶碳化硅，这样本发明制备的超级结功率器件为碳化硅功率器件。
在本发明中，通过本发明制备的超级结功率器件能形成超级结，而且还能形成垂直水平方向的垂直电场，因此通过本发明制备的超级结功率器件具有具有耐压值高、导通电阻低的优点；另外本发明通过设置栅极保护层7能保护通道9，防止其他掺杂质渗入通道9，从而防止超级结功率器件的晶格结构被破坏和出现漏电情况，使得超级结功率器件的电气性能好。
上述实施例和图式并非限定本发明的产品形态和式样，任何所属技术领域的普通技术人员对其所做的适当变化或修饰，皆应视为不脱离本发明的专利范畴。

Claims (6)

1.一种超级结功率器件的制备方法，其特征在于：包括如下步骤：
步骤1：提供具有高掺杂浓度且具有N型导电类型的半导体衬底，并在该半导体衬底正面形成具有N型导电类型的第一外延层；
步骤2：对第一外延层正面进行蚀刻以形成若干个栅极沟槽，并在第一外延层上生长防护层，防护层覆盖第一外延层的顶面和各栅极沟槽；
步骤3：蚀刻移除防护层处于各栅极沟槽底部的部分，并对第一外延层处于各栅极沟槽底部的部分进行蚀刻，以形成位于栅极沟槽下方的超级结沟槽；
步骤4：沉积具有P型导电类型的第二外延层，该第二外延层覆盖防护层以及各超级结沟槽；
步骤5：通过热扩散工艺，使得第二外延层中覆盖超级结沟槽的部分中的具有P型导电类型的掺杂质扩散进入第一外延层中而使得第一外延层中形成具有P型导电类型的第二导电区，而第一外延层中处于相邻第二导电区之间的部分则构成具有N型导电类型的第一导电区，第一导电区和第二导电区交替排列形成超级结；与此同时，第二外延层中覆盖超级结沟槽的部分则形成覆盖第二导电区的厚氧化层；
步骤6：在超级结沟槽中填充浮动栅极；
步骤7：将全部的防护层移除，然后再生成栅极氧化层，该栅极氧化层覆盖浮动栅极、第一外延层的顶面以及各栅极沟槽；
步骤8：在栅极沟槽中填充栅极，然后再形成覆盖栅极氧化层和栅极的保护层；
步骤9：对保护层和栅极氧化层进行蚀刻，以去除栅极氧化层和保护层处于各栅极沟槽两侧的上方的部分以及部分去除保护层处于栅极上方的部分，从而得到包覆栅极的栅极保护层；
步骤10：先将离子注入第一外延层处于各栅极沟槽两侧的部分而形成处于各栅极沟槽两侧的通道；然后沉积覆盖通道的N型源区和P型源区；最后沉积源极金属和漏极金属，源极金属覆盖N型源区、P型源区和栅极保护层，漏极金属覆盖半导体衬底背面。
2.如权利要求1所述的一种超级结功率器件的制备方法，其特征在于：所述第二外延层的掺杂质为硼或铝或镓或铟。
3.如权利要求1所述的一种超级结功率器件的制备方法，其特征在于：所述半导体衬底、浮动栅极和栅极均为多晶硅；或者，所述半导体衬底、浮动栅极和栅极均为多晶碳化硅。
4.如权利要求1或3所述的一种超级结功率器件的制备方法，其特征在于：在所述步骤6中，在超级结沟槽中填充浮动栅极的方法包括：
步骤6.1：沉积浮动栅极层，该浮动栅极层覆盖防护层并填满栅极沟槽和超级结沟槽；
步骤6.2：蚀刻浮动栅极层而将浮动栅极层中覆盖防护层和填充在栅极沟槽中的部分移除，浮动栅极层保留在超级结沟槽中的部分则构成所述浮动栅极。
5.如权利要求1或3所述的一种超级结功率器件的制备方法，其特征在于：在所述步骤8中，在栅极沟槽中填充栅极的方法包括：
步骤8.1：沉积栅极层，该栅极层覆盖栅极氧化膜并填满栅极沟槽；
步骤8.2：蚀刻栅极层而将栅极层覆盖栅极氧化膜的部分移除，栅极层保留在栅极沟槽中的部分则构成所述栅极。
6.如权利要求1所述的一种超级结功率器件的制备方法，其特征在于：所述防护层包括依次生长的基础防护层和钝化层；所述基础防护层为氮化膜或氧化膜。
CN202110076522.XA 2021-01-20 2021-01-20 一种超级结功率器件的制备方法 Active CN112635331B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110076522.XA CN112635331B (zh) 2021-01-20 2021-01-20 一种超级结功率器件的制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110076522.XA CN112635331B (zh) 2021-01-20 2021-01-20 一种超级结功率器件的制备方法

Publications (2)

Publication Number Publication Date
CN112635331A CN112635331A (zh) 2021-04-09
CN112635331B true CN112635331B (zh) 2022-06-21

Family

ID=75294892

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110076522.XA Active CN112635331B (zh) 2021-01-20 2021-01-20 一种超级结功率器件的制备方法

Country Status (1)

Country Link
CN (1) CN112635331B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990757B (zh) * 2021-10-27 2024-03-26 电子科技大学 一种mos器件结构及制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035721A (zh) * 2012-09-05 2013-04-10 上海华虹Nec电子有限公司 超级结器件及其制造方法
CN107910374A (zh) * 2017-12-13 2018-04-13 深圳市晶特智造科技有限公司 超结器件及其制造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9024383B2 (en) * 2013-05-01 2015-05-05 Infineon Technologies Austria Ag Semiconductor device with a super junction structure with one, two or more pairs of compensation layers

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035721A (zh) * 2012-09-05 2013-04-10 上海华虹Nec电子有限公司 超级结器件及其制造方法
CN107910374A (zh) * 2017-12-13 2018-04-13 深圳市晶特智造科技有限公司 超结器件及其制造方法

Also Published As

Publication number Publication date
CN112635331A (zh) 2021-04-09

Similar Documents

Publication Publication Date Title
EP2955758B1 (en) Trench gate mos semiconductor device and method for manufacturing same
CN103247681B (zh) 沟槽底部氧化物屏蔽以及三维p-本体接触区的纳米mosfet
CN102769037B (zh) 减少表面电场的结构及横向扩散金氧半导体元件
CN107342326B (zh) 一种降低导通电阻的功率半导体器件及制造方法
CN109166922B (zh) 一种沟槽型超结功率终端结构及其制备方法
TW202006956A (zh) 具有整合的偽肖特基二極體於源極接觸溝槽之功率金屬氧化物半導體場效電晶體
JP2008103683A (ja) 省スペース型のエッジ構造を有する半導体素子
CN102479805A (zh) 一种超级结半导体元件及其制造方法
US11888022B2 (en) SOI lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof
CN108091685A (zh) 一种提高耐压的半超结mosfet结构及其制备方法
CN115148826B (zh) 一种深沟槽碳化硅jfet结构的制作方法
CN111384153A (zh) 一种具有接地p型区的sgt器件及其制备方法
CN114038914A (zh) 双重耐压半导体功率器件及其制备方法
CN105655402A (zh) 低压超结mosfet终端结构及其制造方法
CN117038455A (zh) Mosfet结构及工艺方法
CN113838914A (zh) 具有分离栅结构的ret igbt器件结构及制作方法
CN111933714A (zh) 三段式氧化层屏蔽栅沟槽mosfet结构的制造方法
CN109037071A (zh) 一种屏蔽栅功率器件的制备方法
CN108074963B (zh) 超结器件及其制造方法
CN118099191A (zh) 沟槽型分栅碳化硅场效应晶体管及其制备方法
CN112635331B (zh) 一种超级结功率器件的制备方法
CN107342226B (zh) 超小单元尺寸纵向超结半导体器件的制造方法
CN102157377B (zh) 超结vdmos器件及其制造方法
CN102214561A (zh) 超级结半导体器件及其制造方法
CN102522338B (zh) 高压超结mosfet结构及p型漂移区形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20211207

Address after: 102600 935, floor 9, building 2, yard 38, Kechuang Fifth Street, Beijing Economic and Technological Development Zone, Daxing District, Beijing

Applicant after: Beijing libaosheng Technology Co.,Ltd.

Address before: Room 501, 5th floor, 3749 Erhuan East Road, Licheng District, Jinan City, Shandong Province

Applicant before: XINCAN semiconductor technology (Shandong) Co.,Ltd.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20240411

Address after: 101300 North Wenhuaying Village, Shunyi District, Beijing (No. 1, Shunchuang Second Road)

Patentee after: Beijing Changlong Zhixin Semiconductor Co.,Ltd.

Country or region after: China

Address before: 102600 935, floor 9, building 2, yard 38, Kechuang Fifth Street, Beijing Economic and Technological Development Zone, Daxing District, Beijing

Patentee before: Beijing libaosheng Technology Co.,Ltd.

Country or region before: China

TR01 Transfer of patent right