CN109037071A - 一种屏蔽栅功率器件的制备方法 - Google Patents

一种屏蔽栅功率器件的制备方法 Download PDF

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CN109037071A
CN109037071A CN201810794418.2A CN201810794418A CN109037071A CN 109037071 A CN109037071 A CN 109037071A CN 201810794418 A CN201810794418 A CN 201810794418A CN 109037071 A CN109037071 A CN 109037071A
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layer
grid
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gate oxide
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张军亮
陈利
陈译
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Xiamen Core 1 Integrated Circuit Co Ltd
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Abstract

本发明的目的是提供一种屏蔽栅功率器件的制备方法。本发明采用双层不同电阻率外延，下层为低阻外延，比均一高阻外延层在相同的耐压情况下具有更小的通态电阻，以减小器件静态功率损耗，栅极氧化物向漏端纵向扩展，利用Resurf技术优化上层高阻层横向电场分布，提高器件的反向耐压；本专利屏蔽栅极为PN掺杂多晶硅，可减小屏蔽栅极与漏极之间的电容，以减小屏蔽栅功率MOSFET的开关功率损耗。

Description

一种屏蔽栅功率器件的制备方法
技术领域
本发明涉及一种功率器件制备方法，特别提供一种屏蔽栅功率器件的制备方法。
背景技术
自功率MOS技术发明以来，该技术已取得了很多重要的发展和进步。近年来，功率MOS技术的新器件结构和新制造工艺不断的涌现，以达到两个最基本的目标：最大的功率处理能力，最小的功率损耗。
现有结构多采用单层均一电阻率外延，因其通态电阻较大，静态功率损耗大；屏蔽栅极为均一N型掺杂多晶硅，屏蔽栅极与漏极之间的电容比较大，屏蔽栅功率MOSFET的开关功率损耗较大。
发明内容
为了解决上述问题，本发明的目的是提供一种双外延结构、屏蔽栅极采用PN掺杂结构的功率器件制备方法。
为达到上述目的，本发明的技术方案如下：一种屏蔽栅功率器件的制备方法，包括如下步骤：
步骤一、提供一N型重掺杂半导体衬底（10），在所述N型重掺杂半导体衬底（10）上生长第一外延层和第二外延层，所述第一外延层为低阻层（20），第二外延层为高阻层（30）。栅极氧化物向漏端纵向扩展，利用Resurf技术优化上层高阻层（30）的横向电场分布，以提高器件的反向耐压，下方采用低阻层（20）外延，以减小器件的通态电阻；
步骤二、刻蚀高阻层（30）形成沟槽（301），所述沟槽（301）底部伸入低阻层（20）上表面；
步骤三、在所述沟槽（301）表面热生长一层屏蔽栅氧化物（302）；
步骤四、淀积多晶硅层（303），所述多晶硅层（303）覆盖在所述屏蔽栅氧化物（302）上方，且充满整个沟槽（301）；
步骤五、对所述多晶硅层（303）和屏蔽栅氧化物（302）采用化学机械抛光技术，使多晶硅层（303）和屏蔽栅氧化物（302）平坦至所述高阻层（30）上表面的同一高度；
步骤六、先后分别刻蚀平坦后的多晶硅层（303）和屏蔽栅氧化物（302），使多晶硅层（303）和屏蔽栅氧化物（302）的上表面高度一致；
步骤七、淀积氮化硅层，所述氮化硅层覆盖在刻蚀平坦后的多晶硅层（303）和屏蔽栅氧化层（302）后露出沟槽表面的高阻层（30）上，之后进行各项异性刻蚀氮化硅层，移除覆盖在多晶硅层（303）、屏蔽栅氧化物（302）和高阻层（30）之上的氮化硅层，保留沟槽侧壁的氮化硅层（40）；
步骤八、在多晶硅层（303）中注入P型掺杂，形成上部为P型掺杂多晶硅（304），下部为N型掺杂多晶硅的PN掺杂屏蔽栅；
步骤九、热氧化生长控制栅极与屏蔽栅极极间氧化物（302-1）和表面氧化物（302-2），所述极间氧化物（302-1）覆盖在屏蔽栅氧化物（302）和P型掺杂多晶硅（304）的上方；所述表面氧化物（302-2）覆盖在沟槽两侧的高阻层（30）上表面；
步骤十、腐蚀移除氮化硅层（40），之后热氧化生长控制栅极氧化层（50）；
步骤十一、淀积多晶硅层（60），且多晶硅层填充满整个沟槽上部，并化学机械抛光多晶硅层（60）；
步骤十二、刻蚀多晶硅层（60）形成控制栅极，刻蚀高阻层表面氧化物（302-2）；
步骤十三、注入P型杂质并推进，形成P体区（70）；
步骤十四、注入N型杂质，热退火形成重掺杂的源区（80）；
步骤十五、淀积层间介质层（90），之后进行化学机械抛光，并刻蚀接触孔，其中屏蔽栅极和控制栅极接触孔位于终端区域，并且屏蔽栅极通过后续金属溅射及刻蚀工艺与源极相连；
步骤十六、刻蚀硅形成源区接触沟槽，且沟槽深度大于N型重掺杂源区结深度，之后注入P型杂质形成源区P型重掺杂接触区（110）；
步骤十七、钨塞填充接触孔，溅射金属并刻蚀，其他后道工艺。
本发明的有益效果是：（1）本发明采用双层不同电阻率外延，下层为低阻外延，比均一高阻外延层在相同的耐压情况下具有更小的通态电阻，以减小器件静态功率损耗，栅极氧化物向漏端纵向扩展，利用Resurf技术优化上层高阻层横向电场分布，提高器件的反向耐压；（2）本专利屏蔽栅极为PN掺杂多晶硅，可减小屏蔽栅极与漏极之间的电容，以减小屏蔽栅功率MOSFET的开关功率损耗。
附图说明
图1为本发明结构原理图；图2~18为本发明工艺流程示意图。
具体实施方式
下面结合附图详细描述本发明的具体实施方式。
如图所示，一种屏蔽栅功率器件的制备方法，包括如下步骤：
步骤一、提供一N型重掺杂半导体衬底（10），在所述N型重掺杂半导体衬底（10）上生长第一外延层和第二外延层，所述第一外延层为低阻层（20），第二外延层为高阻层（30）。栅极氧化物向漏端纵向扩展，利用Resurf技术优化上层高阻层（30）的横向电场分布，以提高器件的反向耐压，下方采用低阻层（20）外延，以减小器件的通态电阻；
步骤二、刻蚀高阻层（30）形成沟槽（301），所述沟槽（301）底部伸入低阻层（20）上表面；
步骤三、在所述沟槽（301）表面热生长一层屏蔽栅氧化物（302）；
步骤四、淀积多晶硅层（303），所述多晶硅层（303）覆盖在所述屏蔽栅氧化物（302）上方，且充满整个沟槽（301）；
步骤五、对所述多晶硅层（303）和屏蔽栅氧化物（302）采用化学机械抛光技术，使多晶硅层（303）和屏蔽栅氧化物（302）平坦至所述高阻层（30）上表面的同一高度；
步骤六、先后分别刻蚀平坦后的多晶硅层（303）和屏蔽栅氧化物（302），使多晶硅层（303）和屏蔽栅氧化物（302）的上表面高度一致；
步骤七、淀积氮化硅层，所述氮化硅层覆盖在刻蚀平坦后的多晶硅层（303）和屏蔽栅氧化层（302）后露出沟槽表面的高阻层（30）上，之后进行各项异性刻蚀氮化硅层，移除覆盖在多晶硅层（303）、屏蔽栅氧化物（302）和高阻层（30）之上的氮化硅层，保留沟槽侧壁的氮化硅层（40）；
步骤八、在多晶硅层（303）中注入P型掺杂，形成上部为P型掺杂多晶硅（304），下部为N型掺杂多晶硅的PN掺杂屏蔽栅；
步骤九、热氧化生长控制栅极与屏蔽栅极极间氧化物（302-1）和表面氧化物（302-2），所述极间氧化物（302-1）覆盖在屏蔽栅氧化物（302）和P型掺杂多晶硅（304）的上方；所述表面氧化物（302-2）覆盖在沟槽两侧的高阻层（30）上表面；
步骤十、腐蚀移除氮化硅层（40），之后热氧化生长控制栅极氧化层（50）；
步骤十一、淀积多晶硅层（60），且多晶硅层填充满整个沟槽上部，并化学机械抛光多晶硅层（60）；
步骤十二、刻蚀多晶硅层（60）形成控制栅极，刻蚀高阻层表面氧化物（302-2）；
步骤十三、注入P型杂质并推进，形成P体区（70）；
步骤十四、注入N型杂质，热退火形成重掺杂的源区（80）；
步骤十五、淀积层间介质层（90），之后进行化学机械抛光，并刻蚀接触孔，其中屏蔽栅极和控制栅极接触孔位于终端区域，并且屏蔽栅极通过后续金属溅射及刻蚀工艺与源极相连；
步骤十六、刻蚀硅形成源区接触沟槽，且沟槽深度大于N型重掺杂源区结深度，之后注入P型杂质形成源区P型重掺杂接触区（110）；
步骤十七、钨塞填充接触孔，溅射金属并刻蚀，其他后道工艺。
屏蔽栅功率MOSFET的输出电容为栅漏电容CGD和栅源电容CGS之和：COSS=CGD+CDS。较大的输出电容会引起瞬态响应下较长的关断时间，引起较高的开关损耗，因此输出电容成为了限制器件工作频率和开关损耗的主要因素之一，必须设法减小SGT的输出电容COSS。本发明通过引入PN掺杂Poly的屏蔽栅极结构，屏蔽栅功率MOSFET工作在反偏状态下时，由于漏端电压高于源端，屏蔽栅极PN掺杂Poly形成的二极管处于反偏状态，利用其反偏状态下的耗尽电容，与屏蔽栅极与漏极的之间的电容并联，因此可以减小屏蔽栅功率MOSFET的漏源电容CDS，进而减小屏蔽栅的输出电容Coss达到减小其开关损耗的目的。
以上是对本发明的较佳实施进行了具体说明，但本发明创造并不限于所述实施例，熟悉本领域的技术人员在不违背本发明精神的前提下还可作出种种的等同变形或替换，这些等同的变形或替换均包含在本申请权利要求所限定的范围内。

Claims (1)

1.一种屏蔽栅功率器件的制备方法，其特征在于：包括如下步骤：
步骤一、提供一N型重掺杂半导体衬底（10），在所述N型重掺杂半导体衬底（10）上生长第一外延层和第二外延层，所述第一外延层为低阻层（20），第二外延层为高阻层（30）；栅极氧化物向漏端纵向扩展，利用Resurf技术优化上层高阻层（30）的横向电场分布，以提高器件的反向耐压，下方采用低阻层（20）外延，以减小器件的通态电阻；
步骤二、刻蚀高阻层（30）形成沟槽（301），所述沟槽（301）底部伸入低阻层（20）上表面；
步骤三、在所述沟槽（301）表面热生长一层屏蔽栅氧化物（302）；
步骤四、淀积多晶硅层（303），所述多晶硅层（303）覆盖在所述屏蔽栅氧化物（302）上方，且充满整个沟槽（301）；
步骤五、对所述多晶硅层（303）和屏蔽栅氧化物（302）采用化学机械抛光技术，使多晶硅层（303）和屏蔽栅氧化物（302）平坦至所述高阻层（30）上表面的同一高度；
步骤六、先后分别刻蚀平坦后的多晶硅层（303）和屏蔽栅氧化物（302），使多晶硅层（303）和屏蔽栅氧化物（302）的上表面高度一致；
步骤七、淀积氮化硅层，所述氮化硅层覆盖在刻蚀平坦后的多晶硅层（303）和屏蔽栅氧化层（302）后露出沟槽表面的高阻层（30）上，之后进行各项异性刻蚀氮化硅层，移除覆盖在多晶硅层（303）、屏蔽栅氧化物（302）和高阻层（30）之上的氮化硅层，保留沟槽侧壁的氮化硅层（40）；
步骤八、在多晶硅层（303）中注入P型掺杂，形成上部为P型掺杂多晶硅（304），下部为N型掺杂多晶硅的PN掺杂屏蔽栅；
步骤九、热氧化生长控制栅极与屏蔽栅极极间氧化物（302-1）和表面氧化物（302-2），所述极间氧化物（302-1）覆盖在屏蔽栅氧化物（302）和P型掺杂多晶硅（304）的上方；所述表面氧化物（302-2）覆盖在沟槽两侧的高阻层（30）上表面；
步骤十、腐蚀移除氮化硅层（40），之后热氧化生长控制栅极氧化层（50）；
步骤十一、淀积多晶硅层（60），且多晶硅层填充满整个沟槽上部，并化学机械抛光多晶硅层（60）；
步骤十二、刻蚀多晶硅层（60）形成控制栅极，刻蚀高阻层表面氧化物（302-2）；
步骤十三、注入P型杂质并推进，形成P体区（70）；
步骤十四、注入N型杂质，热退火形成重掺杂的源区（80）；
步骤十五、淀积层间介质层（90），之后进行化学机械抛光，并刻蚀接触孔，其中屏蔽栅极和控制栅极接触孔位于终端区域，并且屏蔽栅极通过后续金属溅射及刻蚀工艺与源极相连；
步骤十六、刻蚀硅形成源区接触沟槽，且沟槽深度大于N型重掺杂源区结深度，之后注入P型杂质形成源区P型重掺杂接触区（110）；
步骤十七、钨塞填充接触孔，溅射金属并刻蚀，其他后道工艺。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020199706A1 (zh) * 2019-04-03 2020-10-08 杭州士兰微电子股份有限公司 双向功率器件及其制造方法
CN112201687A (zh) * 2020-10-30 2021-01-08 深圳市威兆半导体有限公司 一种npn三明治栅结构的沟槽mosfet器件
CN112382572A (zh) * 2021-01-15 2021-02-19 龙腾半导体股份有限公司 Ono屏蔽栅的sgt结构及其制造方法
CN117936581A (zh) * 2023-12-22 2024-04-26 西安龙飞电气技术有限公司 一种改进型沟槽型碳化硅mosfet器件及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579320A (zh) * 2012-07-31 2014-02-12 上海华虹Nec电子有限公司 沟槽型栅极及制造方法
CN105529256A (zh) * 2014-10-21 2016-04-27 英飞凌科技奥地利有限公司 半导体器件和使用对准层制造半导体器件的方法
US20160149034A1 (en) * 2014-11-26 2016-05-26 Sinopower Semiconductor, Inc. Power semiconductor device having low on-state resistance

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579320A (zh) * 2012-07-31 2014-02-12 上海华虹Nec电子有限公司 沟槽型栅极及制造方法
CN105529256A (zh) * 2014-10-21 2016-04-27 英飞凌科技奥地利有限公司 半导体器件和使用对准层制造半导体器件的方法
US20160149034A1 (en) * 2014-11-26 2016-05-26 Sinopower Semiconductor, Inc. Power semiconductor device having low on-state resistance

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020199706A1 (zh) * 2019-04-03 2020-10-08 杭州士兰微电子股份有限公司 双向功率器件及其制造方法
TWI747226B (zh) * 2019-04-03 2021-11-21 大陸商杭州士蘭微電子股份有限公司 雙向功率器件及其製造方法
CN112201687A (zh) * 2020-10-30 2021-01-08 深圳市威兆半导体有限公司 一种npn三明治栅结构的沟槽mosfet器件
WO2022088925A1 (zh) * 2020-10-30 2022-05-05 深圳市威兆半导体有限公司 一种npn三明治栅结构的沟槽mosfet器件
CN112382572A (zh) * 2021-01-15 2021-02-19 龙腾半导体股份有限公司 Ono屏蔽栅的sgt结构及其制造方法
CN112382572B (zh) * 2021-01-15 2021-11-02 龙腾半导体股份有限公司 Ono屏蔽栅的sgt结构及其制造方法
CN117936581A (zh) * 2023-12-22 2024-04-26 西安龙飞电气技术有限公司 一种改进型沟槽型碳化硅mosfet器件及其制造方法

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