WO2022088925A1 - 一种npn三明治栅结构的沟槽mosfet器件 - Google Patents
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- the existing structure will convert the gate-drain capacitance into the source-drain capacitance, resulting in an increase in the input capacitance of the device; secondly, the electric field distribution in the drift region of the structure still has a certain inhomogeneity, which leads to the improvement of the on-resistance of the structure. The effect is weakened; at the same time, the structure needs to be deposited many times of oxide layers during the process preparation, which increases a certain process complexity.
- the N+Poly gate, the P-type lightly doped region, and the N-type source contact region together constitute the NPN sandwich structure in the trench, which can further reduce the gate electrode while enhancing the assistance to the depletion of the drift region. and the shielding of the drain, thereby reducing the gate-to-drain capacitance of the device.
- FIG. 1 is a schematic diagram of a lateral cross-sectional structure of an existing shielded gate trench MOSFET device
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Abstract
本申请公开一种NPN三明治栅结构的沟槽MOSFET器件,包括元胞结构,元胞结构包括漏极金属、N+衬底、N型漂移区、源极金属;N型漂移区的上表面一侧形成从上至下依次设置的N+Poly栅极、P型轻掺杂区、N型源极接触区;N型漂移区的上表面另一侧设有紧邻沟槽栅极结构的P型基区、N型重掺杂区和P型重掺杂区。
Description
本申请要求于2020年10月30日提交中国专利局、申请号为202011192757.7、申请名称为“一种NPN三明治栅结构的沟槽MOSFET器件”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本申请涉及功率半导体器件技术领域,尤其涉及一种NPN三明治栅结构的沟槽MOSFET器件。
随着电力电子系统的发展,功率半导体器件被广泛应用于交通运输、军事防御、能源转换等重要领域,逐渐成为学界重要的研究热点。功率MOS器件是功率半导体器件的重要组成部分,因其具有输入阻抗高、开关速度快、瞬态损耗低等优势,故功率MOS器件在低压功率开关电路中占有主导地位。而由于应用的需求,低压应用下的功率MOSFET器件逐渐开始沿着降低器件开关功耗、提高器件电流能力以及增强器件可靠性的趋势发展。
为了提高器件的耐压,功率MOSFET器件经历了从横向结构到纵向结构、从平面结构到沟槽结构的不断发展。沟槽结构主要经历了从传统槽栅MOSFET器件到降低表面电场的阶梯氧化层槽栅 MOSFET(Resurf Stepped Oxide Trench MOSFET,RSO MOSFET),再到屏蔽栅沟槽MOSFET(Split-Gate Trench MOSFET,SGT MOSFET)的发展。传统槽栅MOSFET器件主要通过深槽刻蚀和多晶硅淀积形成栅电极,其相较于传统平面栅可有效减小器件的导通电阻并提高器件的击穿电压。RSO MOSFET器件在传统槽栅MOSFET的基础上通过将槽伸至外延层漂移区内的方式对传统槽栅MOSFET器件进行进一步的优化,伸入漂移区的栅电极起到体内场板的作用,对漂移区的载流子进行辅助耗尽从而有效地优化漂移区电场,保证了在相同击穿电压的前提下RSO MOSFET器件可以实现更高的漂移区浓度,从而具有更低的比导通电阻。但是尽管RSO MOSFET可以实现更低的静态损耗,由于其栅面积较大RSO MOSFET具有极大的栅电容,导致其在应用于开关电路时具有较大的开关功率损耗。
为进一步优化槽栅MOSFET的性能,在传统槽栅MOSFET和RSO MOSFET的基础上提出了SGT MOSFET器件,该结构示意图如图1所示。相较于传统槽栅MOSFET,SGT MOSFET的沟槽更深;对比RSO MOSFET,SGT MOSFET的栅极和屏蔽栅通过介质隔离,同时器件的屏蔽栅电极通过版图在三维前后方向上实现与源极电极的短接。SGT MOSFET结构相较于上述提到的两种结构有如下两种方向的改进:一方面,屏蔽栅可作为埋于体内的体内场板,对漂移区的载流子进行辅助耗尽,有效地提高了器件漂移区的耗尽能力,优化漂移区的电场分布,从而保证在相同击穿电压的前提下SGT MOSFET具有更低的比导通电阻;另一方面,器件栅极漏极之间的 交叠面积由于屏蔽栅的存在而大大减小,因此可以有效地将栅极和漏极的极间电容屏蔽,极大地降低了器件的栅漏电容,从而在一定程度上提高功率MOSFET器件的开关速度,并降低了器件的开关损耗。但是现有的该结构会将栅漏电容转化为源漏电容,导致器件的输入电容增大;其次,该结构漂移区的电场分布仍然存在一定的不均一性,导致该结构对导通电阻的改善效果减弱;同时该结构在工艺制备中需要进行多次氧化层的淀积,增加了一定的工艺复杂性。
现有的该结构会将栅漏电容转化为源漏电容,导致器件的输入电容增大;其次,该结构漂移区的电场分布仍然存在一定的不均一性,导致该结构对导通电阻的改善效果减弱;同时该结构在工艺制备中需要进行多次氧化层的淀积,增加了一定的工艺复杂性。
本申请的目的是提供一种NPN三明治栅结构的沟槽MOSFET器件,在SGT MOSFET的基础上改进,进一步改善功率MOSFET器件的开关特性。
为实现上述目的,采用以下技术方案:
一种NPN三明治栅结构的沟槽MOSFET器件,包括元胞结构,所述元胞结构包括从下至上依次层叠的漏极金属、N+衬底、N型漂移区、源极金属;所述N型漂移区的上表面一侧形成沟槽栅极结构, 沟槽栅极结构包括从上至下依次设置的N+Poly栅极、P型轻掺杂区、N型源极接触区;所述N型漂移区的上表面另一侧设有紧邻沟槽栅极结构的P型基区;所述P型基区的上表面设有相互接触的N型重掺杂区和P型重掺杂区,且N型重掺杂区紧邻沟槽栅极结构设置;所述沟槽栅极结构的下表面、侧面以及上表面均设有氧化层,用于隔离N型漂移区、P型基区、N型重掺杂区以及源极金属。
较佳地,所述P型轻掺杂区、N型源极接触区的侧面与N型漂移区之间的氧化层为厚氧化层,N+Poly栅极侧面的氧化层为薄氧化层。
较佳地,所述N型源极接触区与源极金属相连接。
本申请中的N+Poly栅极、P型轻掺杂区、N型源极接触区共同构成沟槽中的NPN三明治结构,在增强对漂移区耗尽的辅助的同时,可进一步降低栅极和漏极的屏蔽之间的影响,从而降低器件的栅漏电容。
本申请相较于传统屏蔽栅沟槽MOSFET,有效地减少了槽栅中的氧化层淀积次数,简化了器件的版图设计步骤,提高了设计效率。
本申请提供的上述一个或多个技术方案,可以具有如下优点或至少实现了如下技术效果:
本申请在传统屏蔽栅沟槽MOSFET结构的基础上,提出了一种NPN三明治栅结构的沟槽MOSFET器件,利用槽栅中的NPN三明 治结构:一方面可以帮助漂移区实现耗尽,确保了在耐压不受影响的情况下实现更高的掺杂浓度,从而降低器件的比导通电阻以及静态损耗;另一方面,该结构还可以减小栅极和漏极之间的交叠,从而减小栅漏电容,同时也可以为位移电流提供其他的电流通路,从而减小位移电流对栅极的充电影响,有效地减少了栅电荷的充电现象,实现更快的开关速度以及更小的开关损耗。
为了更清楚地说明本申请实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据提供的这些附图获得其他的附图。
图1为现有的屏蔽栅沟槽MOSFET器件的横向截面结构示意图;
图2为本申请的横向截面结构示意图;
其中,附图标识说明:
1—N型重掺杂区,2—P型重掺杂区,
3—P型基区,4—N型漂移区,
5—N+衬底,6—漏极金属,
7—源极金属,8—N+Poly栅极,
9—P型轻掺杂区,10—N型源极接触区,
11—氧化层。
本申请的实施方式
以下通过特定的具体实例说明本申请的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本申请的其他优点与功效。本申请还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本申请的精神下进行各种修饰或改变。
为了进一步改善器件的静态特性、开关特性并减小工艺的复杂度,本申请基于现有SGT MOSFET结构,提出了一种NPN三明治栅结构的沟槽MOSFET器件,如图2所示。该结构的主要改进在于:在沟槽中实现NPN三明治结构,一方面利用槽栅内的PN结耗尽进一步辅助漂移区的耗尽,优化漂移区内部的电场分布;另一方面则利用PN结的结电容将栅极和漏极进一步屏蔽实现更小的栅漏电容,从而提高器件的开关速度并减小器件的开关损耗。
下面结合附图,详细描述本申请的技术方案:
参照图2所示,本申请提供一种NPN三明治栅结构的沟槽MOSFET器件,包括元胞结构,所述元胞结构包括从下至上依次层叠的漏极金属6、N+衬底5、N型漂移区4、源极金属7;所述N型漂移区4的上表面一侧形成沟槽栅极结构,沟槽栅极结构包括从上至下依次设置的N+Poly栅极8、P型轻掺杂区9、N型源极接触区10;所述N型漂移区4的上表面另一侧设有紧邻沟槽栅极结构的P型基区3;所述P型基区3的上表面设有相互接触的N型重掺杂区1和P 型重掺杂区2,且N型重掺杂区1紧邻沟槽栅极结构设置;所述沟槽栅极结构的下表面、侧面以及上表面均设有氧化层11,用于隔离N型漂移区4、P型基区3、N型重掺杂区1以及源极金属7,其中,所述漏极金属6的材料包括钽、钨、氮化钽或氮化钛的至少一种,所述源极金属7的材料包括铜、铝以及钼的至少一种。
其中,所述P型轻掺杂区9包括依次设置在所述N型源极接触区上的第一掺杂区和第二掺杂区,所述第一掺杂区的P离子浓度大于所述第二掺杂区的P离子。
其中,所述N+Poly栅极8的厚度大于所述P型轻掺杂区9的厚度,所述P型轻掺杂区9的厚度大于所述N型源极接触区10。
其中,所述P型轻掺杂区9、N型源极接触区10的侧面与N型漂移区4之间的氧化层11为厚氧化层,N+Poly栅极8侧面的氧化层11为薄氧化层。所述N型源极接触区10与源极金属7相连接。
本申请的原理如下:在SGT MOSFET结构的基础上,在沟槽中设置NPN三明治结构进一步优化屏蔽栅的效果,其中NPN结构中的N型重掺杂区1作为poly栅极引出,而N型轻掺杂区浮空,N型源极接触区10则与源极连接。具有NPN三明治栅结构的沟槽MOSFET器件(Split-Gate Trench MOSFET with NPN Sandwich,SSGT MOSFET)相较于传统SGT MOSFET器件,增强了对栅极和漏极间的屏蔽效果,极大地减小了器件的栅漏电容,同时由于新结构中槽栅NPN三明治结构中的较小结电容的存在,使得新结构的源漏电容远远小于传统SGT MOSFET器件的源漏电容,NPN三明治结构对栅漏电容以及源 漏电容的改进使得新结构的输出电容远远小于传统结构的输出电容,从而有效地改善了器件的开关速度以及开关损耗。同时,槽栅中NPN三明治结构的存在实现了从体内阻场板到体内结场板的改进,可增强沟槽结构对耗尽的辅助作用,从而实现对漂移区内部电场以及导通电阻的进一步优化。
综上所述,在传统的屏蔽栅沟槽MOSFET结构基础上,在沟槽中设置NPN三明治结构实现的具有NPN三明治栅结构的沟槽MOSFET器件(Split-Gate Trench MOSFET with NPN Sandwich,SSGT MOSFET),在减小器件的栅漏电容以及源漏电容的同时可进一步优化体内漂移区的电场以及比导通电阻,从而实现更快的开关速度以及更低的静态损耗和开关损耗。
以上仅为本申请的较佳实施例而已,并不用于限制本申请,凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本申请的保护范围之内。
Claims (7)
- 一种NPN三明治栅结构的沟槽MOSFET器件,包括元胞结构,其中,所述元胞结构包括从下至上依次层叠的漏极金属、N+衬底、N型漂移区、源极金属;所述N型漂移区的上表面一侧形成沟槽栅极结构,沟槽栅极结构包括从上至下依次设置的N+Poly栅极、P型轻掺杂区、N型源极接触区;所述N型漂移区的上表面另一侧设有紧邻沟槽栅极结构的P型基区;所述P型基区的上表面设有相互接触的N型重掺杂区和P型重掺杂区,且N型重掺杂区紧邻沟槽栅极结构设置;所述沟槽栅极结构的下表面、侧面以及上表面均设有氧化层,用于隔离N型漂移区、P型基区、N型重掺杂区以及源极金属。
- 根据权利要求1所述的NPN三明治栅结构的沟槽MOSFET器件,其中,所述P型轻掺杂区、N型源极接触区的侧面与N型漂移区之间的氧化层为厚氧化层,N+Poly栅极侧面的氧化层为薄氧化层。
- 根据权利要求2所述的NPN三明治栅结构的沟槽MOSFET器件,其中,所述P型轻掺杂区包括依次设置在所述N型源极接触区上的第一掺杂区和第二掺杂区,所述第一掺杂区的P离子浓度大于所述第二掺杂区的P离子。
- 根据权利要求2所述的NPN三明治栅结构的沟槽MOSFET器件,其中,所述N+Poly栅极的厚度大于所述P型轻掺杂区的厚度,所述P型轻掺杂区的厚度大于所述N型源极接触区。
- 根据权利要求1所述的NPN三明治栅结构的沟槽MOSFET器件,其中,所述N型源极接触区与源极金属相连接。
- 根据权利要求1所述的NPN三明治栅结构的沟槽MOSFET器件,其中,所述源极金属的材料包括铜、铝以及钼的至少一种。
- 根据权利要求1所述的NPN三明治栅结构的沟槽MOSFET器件,其中,所述漏极金属的材料包括钽、钨、氮化钽或氮化钛的至少一种。
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