JP2008103683A - 省スペース型のエッジ構造を有する半導体素子 - Google Patents
省スペース型のエッジ構造を有する半導体素子 Download PDFInfo
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Abstract
【解決手段】半導体基材100を備えた半導体素子であって、半導体基材は、第1の面101、第2の面102、内部領域105と、内部領域隣接したエッジ領域106と、内部領域およびエッジ領域にわたって延設され、且つ第1導電型の第1の半導体層103とを有しており、さらに、第1導電型に対して相補的な第2導電型であって、且つ第1の半導体層内の内部領域内に位置する少なくとも1つの能動素子ゾーン12と、エッジ領域内に位置するエッジ構造とを備えている。
【選択図】図1
Description
本発明は、内部領域内にpn接合部を備え、エッジ領域内にはエッジ構造を備えた半導体基材を有する半導体素子、特にパワートランジスタに関する。
本発明に係る半導体素子の一例としては、半導体基材を備えた半導体素子であって、上記半導体基材は、第1の面と、第2の面と、内部領域と、該内部領域の該半導体基材側方側に隣接したエッジ領域と、該内部領域および該エッジ領域にわたって延設されており、且つ第1導電型の基本ドーピングが施された第1の半導体層とを有しており、上記半導体素子は、さらに、上記第1導電型に対して相補的な第2導電型であって、且つ上記第1の半導体層内の上記内部領域内に位置する少なくとも1つの能動素子ゾーンと、上記エッジ領域内に位置するエッジ構造とを備えている。このエッジ構造は、上記第1の面から半導体基材内部へ向けて延設された少なくとも1つのトレンチと、該トレンチ内に位置するエッジ電極と、該トレンチ内に位置し、且つエッジ電極と半導体基材との間に位置する絶縁層と、該トレンチに隣接するとともに、少なくとも一部分が該トレンチの下方に配置され、且つ上記第2導電型である第1のエッジゾーンとを有している。
本発明の実施例について、図面を参照しながら以下に説明する。これらの図面では、別段の記載がない限りは、同一の符号は、同一の意味を有する同一の素子領域を示している。
図1は、本発明の一実施例による半導体素子の一部の断面図を示している。この半導体素子は、以下では表面として示されている第1の面101と、以下では裏面として示されている第2の面102とを有する半導体基材100を備えている。裏面102は、半導体基材100の垂直方向において、第1の面101の反対側に配置されている。半導体基材100は、例えば基本nドーピング(basic n-doping)などの第1導電型の基本ドーピング(basic doping)が施された第1の半導体層103を有している。半導体基材100の表面101と隣接している第1の半導体層103は、例えば、第2の半導体層104上に配置されたエピタキシャル層103である。第2の半導体層104は、例えば半導体基板である。図1に示されている第1の半導体層103および第2の半導体層104の垂直方向の寸法は、互いに相対的な縮小とはなっていない。通常、第1の半導体層103をエピタキシャル層として基板104上に形成する際は、半導体基材103の垂直方向におけるエピタキシャル層103の寸法は、半導体基板104の寸法よりも大幅に小さい。
Claims (26)
- 半導体基材(100)を備えた半導体素子であって、
上記半導体基材(100)は、第1の面(101)と、第2の面(102)と、内部領域(105)と、該内部領域(105)の該半導体基材(100)側方側に隣接したエッジ領域(106)と、該内部領域および該エッジ領域にわたって延設されており、且つ第1導電型の基本ドーピングが施された第1の半導体層(103)とを有しており、
上記半導体素子は、さらに、
上記第1導電型に対して相補的な第2導電型であって、且つ上記第1の半導体層(103)内の上記内部領域(105)内に位置する少なくとも1つの能動素子ゾーン(12)と、
上記エッジ領域(106)内に位置するエッジ構造とを備えており、
上記エッジ構造は、上記第1の面(101)から半導体基材(100)内部へ向けて延設された少なくとも1つのトレンチ(25)と、該トレンチ内に位置するエッジ電極(23)と、該トレンチ内に位置し、且つエッジ電極(23)と半導体基材(100)との間に位置する絶縁層(24)と、該トレンチ(25)に隣接するとともに、少なくとも一部分が該トレンチ(25)の下方に配置され、且つ上記第2導電型である第1のエッジゾーン(21)とを有している、ことを特徴とする半導体素子。 - 上記第1のエッジゾーンとは離間して配置されており、且つ少なくとも1つのトレンチ(15)と側方において隣接するとともに、第1の面(101)と隣接する第2のエッジゾーン(22)を備えていることを特徴とする請求項1に記載の半導体素子。
- 上記第1のエッジゾーン(21)は、完全に空乏化されるように、あるいは、側方における上記エッジトレンチ(25)の幅よりも寸法が小さい領域以外が空乏化されていることを特徴とする請求項1または2に記載の半導体素子。
- MOSトランジスタとして形成され、
上記半導体基材(100)の上記内部領域(105)内に、
第1導電型であるソースゾーン(11)、該第1導電型であるドリフトゾーン(13)、及び該ソースゾーン(11)と該ドリフトゾーン13との間に配置されている上記第2導電型であるボディゾーン(12)を備えており、
さらに、
ゲート絶縁膜(16)によってボディゾーン(12)から絶縁されたかたちでボディゾーン(12)と隣り合って配置されているゲート電極(15)を少なくとも1つ備えていることを特徴とする請求項1から3までの何れか1項に記載の半導体素子。 - 上記ゲート電極(15)は、上記第1の面(101)から半導体基材(100)内部へ向けて延設された少なくとも1つのトレンチ内に配置されていることを特徴とする請求項4に記載の半導体素子。
- 上記ゲート電極(15)が設けられた上記トレンチ(19)内にフィールド電極(17)配置されており、
上記フィールド電極(17)は、上記ゲート電極(15)よりも、上記半導体基材(100)内部へ深く延びていることを特徴とする請求項5に記載の半導体素子。 - 上記エッジ電極(23)は、上記ソースゾーン(11)と電気的に結合していることを特徴とする請求項4から6までの何れか1項に記載の半導体素子。
- 上記ゲート電極(15)は、半導体ゾーン(22、26)と電気的に結合しており、
上記能動素子ゾーン(12)は、上記第1の半導体層(103)の基本ドーピングに対して相補的なドーピングが施されており、且つ上記トレンチ(25)と上記内部領域(105)との間に配置されていることを特徴とする請求項1から6までの何れか1項に記載の半導体素子。 - 上記半導体ゾーン(22、26)は、上記基本ドーピングに対して相補的にドーピングされており、上記エッジトレンチ(25)に隣接していることを特徴とする請求項8に記載の半導体素子。
- 上記半導体素子は、さらに、
上記エッジ電極(23)を備えた少なくとも2つのトレンチ(25)と、該トレンチ(25)の数に対応する数の第1のエッジゾーン(21)とを備えており、
上記トレンチ(25)は、各々が、半導体基材(100)における側方方向に離間して配置されていることを特徴とする請求項1から9までの何れか1項に記載の半導体素子。 - 上記半導体素子は、さらに
上記トレンチ(25)の数に対応する数の第2のエッジゾーン(22)を備えており、
上記第2のエッジゾーン(22)は、各々、各トレンチ(25)の内部領域(105)側とは反対側に配置されており、該トレンチ(25)と隣接していることを特徴とする請求項10に記載の半導体素子。 - 上記第2のエッジゾーン(26)の各々は、2つのトレンチ(25)の間に配置されており、一方のトレンチから他方のトレンチまでを側方に向けて延びていることを特徴とする請求項11に記載の半導体素子。
- 半導体基材(100)を備えた半導体素子であって、
上記半導体基材(100)は、第1の面(101)と、第2の面(102)と、内部領域(105)と、該内部領域(105)の該半導体基材(100)側方側に隣接したエッジ領域(106)と、該内部領域および該エッジ領域にわたって延設されており、且つ第1導電型の基本ドーピングが施された第1の半導体層(103)とを有しており、
上記半導体素子は、さらに、
上記第1導電型に対して相補的な第2導電型であって、且つ上記第1の半導体層(103)内の上記内部領域(105)内に位置する少なくとも1つの能動素子ゾーン(12)と、
上記エッジ領域(106)内に位置するエッジ構造とを備えており、
上記エッジ構造は、上記第1の面(101)から半導体基材(100)内部へ向けて延設された少なくとも1つのトレンチ(25)と、該トレンチ(25)を充填する絶縁層(24)と、該トレンチ(25)に隣接するとともに、少なくとも一部分が該トレンチ(25)の下方に配置され、且つ上記第2導電型である第1のエッジゾーン(21)とを有しており、
上記第1のエッジゾーン(21)は、上記能動素子ゾーン(12)と、上記基本ドーピングが施された上記第1の半導体層(103)との間に形成された半導体接合部に対して遮断電圧がアプライされる際に、完全に空乏化されるように、あるいは、側方方向におけるエッジトレンチ(25)の幅よりも寸法が小さい領域以外が空乏化されるように選択されたドーピングが施されていることを特徴とする半導体素子。 - 上記第1のエッジゾーン(21)とは離間して配置されており、且つ少なくとも1つのトレンチと側方において隣接するとともに、第1の面(101)と隣接する第2のエッジゾーン(22)を備えていることを特徴とする請求項13に記載の半導体素子。
- MOSトランジスタとして形成され、
上記半導体基材(100)の上記内部領域(105)内に、
第1導電型であるソースゾーン(11)、該第1導電型であるドリフトゾーン(13)、及び該ソースゾーン(11)と該ドリフトゾーン13との間に配置されている上記第2導電型であるボディゾーン(12)を備えており、
さらに、
ゲート絶縁膜(16)によってボディゾーン(12)から絶縁されたかたちでボディゾーン(12)と隣り合って配置されているゲート電極(15)を少なくとも1つ備えていることを特徴とする請求項13または14に記載の半導体素子。 - 上記ゲート電極(15)は、上記第1の面(101)から半導体基材(100)内部へ向けて延設された少なくとも1つのトレンチ内に配置されていることを特徴とする請求項15に記載の半導体素子。
- 上記ゲート電極(15)が設けられた上記トレンチ(19)内にフィールド電極(17)配置されており、
上記フィールド電極(17)は、上記ゲート電極(15)よりも、上記半導体基材(100)内部へ深く延びていることを特徴とする請求項16に記載の半導体素子。 - 上記半導体素子は、さらに、少なくとも2つのトレンチ(25)と、該トレンチ(25)の数に対応する数の第1のエッジゾーン(21)とを備えており、
上記トレンチ(25)は、各々が、側方方向に離間して配置されており、絶縁層によって充填されていることを特徴とする請求項14から17までの何れか1項に記載の半導体素子。 - 上記半導体素子は、さらに、上記トレンチの数に対応する数の第2のエッジゾーン(22)を備えていることを特徴とする請求項18に記載の半導体素子。
- 上記第2のエッジゾーン(26)の各々は、2つのトレンチ(25)の間に配置されており、一方のトレンチから他方のトレンチまでを側方に向けて延びていることを特徴とする請求項19に記載の半導体素子。
- 上記エッジトレンチ(25)の、半導体基材(100)の垂直方向の深さは、上記フィールド電極(17)が配置されたトレンチ(19)のそれよりも深いことを特徴とする請求項17から20までの何れか1項に記載の半導体素子。
- 上記第2のエッジゾーン(22)は、完全な空乏化はなされていないことを特徴とする請求項1から21までの何れか1項に記載の半導体素子。
- 上記第1の半導体層(103)は、第1の部分層(103’)と、該第1の部分層103’よりも低い濃度でドーピングされた第2の部分層(103’’)とを有しており、
少なくとも1つの上記エッジトレンチ(25)は、上記第2の部分層(103’’)内に延びていることを特徴とする請求項1から22までの何れか1項に記載の半導体素子。 - 上記フィールド電極(17)が配置されたトレンチ(19)は、上記第2の部分層(103’’)内に延びていることを特徴とする請求項23に記載の半導体素子。
- 上記第1の半導体層(103)は、第1の部分層(103’)と、該第1の部分層103’よりも低い濃度でドーピングされた第2の部分層(103’’)とを有しており、
上記第1のエッジゾーン(21)は、全体が上記第2の部分層(103’’)内に位置していることを特徴とする請求項1から24までの何れか1項に記載の半導体素子。 - 上記エッジトレンチ(25)の、半導体基材(100)の垂直方向の深さは、上記フィールド電極(17)が配置されたトレンチ(19)のそれよりも深いことを特徴とする請求項6または17に記載の半導体素子。
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US8080858B2 (en) | 2011-12-20 |
JP5089284B2 (ja) | 2012-12-05 |
DE102006036347B4 (de) | 2012-01-12 |
US20080042172A1 (en) | 2008-02-21 |
DE102006036347A1 (de) | 2008-04-17 |
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