CN110797412A - Sgt mosfet结构及其工艺制造方法 - Google Patents

Sgt mosfet结构及其工艺制造方法 Download PDF

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CN110797412A
CN110797412A CN201911005962.5A CN201911005962A CN110797412A CN 110797412 A CN110797412 A CN 110797412A CN 201911005962 A CN201911005962 A CN 201911005962A CN 110797412 A CN110797412 A CN 110797412A
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groove
bsg
mosfet
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mosfet structure
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陈桥梁
刘挺
王新
楼颖颖
杨乐
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Longteng Semiconductor Co Ltd
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Abstract

本发明涉及一种SGT MOSFET结构及其工艺制造方法。本发明SGT MOSFET通过在栅极沟槽下方植入P柱构成,通过在Si衬底片表面生长N型外延层,然后刻蚀深沟槽,接着在深沟槽内填充BSG材料并回刻,再通过各向同性腐蚀形成栅极沟槽,接着栅极沟槽内回填HDP并回刻,最后高温退火回流使BSG材料中Boron扩散至深沟槽外围的Si材料中形成P柱。采用本发明所述方法制作的SGT MOSFET,可以在实现较小的器件尺寸的同时,灵活调节P柱的宽度和浓度,有利于实现电荷平衡,优化器件参数和性能,工艺可控性强。

Description

SGT MOSFET结构及其工艺制造方法
技术领域
本发明属于半导体功率器件技术领域,具体涉及一种SGT MOSFET结构及其工艺制造方法。
背景技术
SGT(Split-Gate-Trench,分裂栅极沟槽)结构因其具有电荷耦合效应,在传统沟槽MOSFET垂直耗尽(P-Body/N-Epi结)基础上引入了水平耗尽,将器件电场由三角形分布改变为近似矩形分布。在采用同样掺杂浓度的外延规格情况下,器件可以获得更高的击穿电压,该结构在中低压功率器件领域得到广泛应用。
图1为传统的SGT(Split-Gate-Trench,分裂栅极沟槽)结构,先通过一道刻蚀形成沟槽,然后在沟槽内生长屏蔽电极介质层,通常为厚氧化层来实现电荷平衡。这种结构的SGT其源漏击穿电压受控于该氧化层厚度,击穿电压越高,需要氧化层厚度越厚,对于100V器件该氧化层厚度已经达到6000A左右。因而,在器件设计时需要将沟槽CD定义的比较宽(100V器件沟槽CD需要1um以上)。而目前SGT器件设计的一个主流方向是为了获得更低的Rsp(单位面积导通电阻),需要尽可能缩小单位元胞的尺寸,传统的SGT结构特点显然阻碍了其自身发展。
发明内容
本发明的目的是提供一种SGT MOSFET结构及其工艺制造方法,该结构通过CVD工艺在沟槽内填充BSG(硼硅玻璃)材料,再经退火使Boron自动扩散到沟槽外围的硅材料中形成P柱,改变BSG浓度和退火温度可以有效调节P柱的宽度及浓度,实现与N型外延层的电荷平衡。
本发明所采用的技术方案为:
SGT MOSFET结构,其特征在于:
该MOSFET结构位于外延衬底上,其栅极沟槽下方有一区域,该区域内填满与外延反型的材料来实现电荷平衡。
MOSFET的栅极沟槽下方区域为一深沟槽。
MOSFET栅极沟槽下方的深沟槽中填充的材料为与外延反型的掺杂氧化物。
MOSFET的外延材料为N型,其栅极沟槽下方的深沟槽内填充物为P型氧化膜:硼硅玻璃BSG。
MOSFET栅极沟槽与其下方深沟槽自对准。
深沟槽的深度小于MOSFET所在外延的厚度。
SGT MOSFET结构的工艺制造方法,其特征在于:
包括以下步骤:
步骤一:在Si衬底片表面生长N型外延层;
步骤二:利用沟槽光刻版进行光刻工艺,对沟槽位置曝光,再通过干法刻蚀,将曝光位置刻蚀出深沟槽;
步骤三:利用CVD工艺在深沟槽内填满硼硅玻璃BSG;
步骤四:通过CMP工艺将Si表面多余硼硅玻璃BSG研磨去除,并利用湿法腐蚀将沟槽内BSG腐蚀至Si表面以下;
步骤五:利用各项同性刻蚀将沟槽宽度扩大,形成栅极沟槽;
步骤六:栅极沟槽内回填HDP 氧化物;
步骤七:利用高温退火使硼硅玻璃BSG材料中硼Boron扩散至深沟槽外围的Si材料中,形成P柱;
步骤八:栅极沟槽内HDP OX回刻;
之后步骤与常规MOSFET工艺相同。
所述步骤二中,干法刻蚀形成的沟槽其深度在5微米至20微米之间,宽度在0.2微米至2微米之间。
所述步骤四中,湿法腐蚀BSG至Si表面以下深度在1微米至1.5微米之间。
所述步骤七中,硼硅玻璃BSG高温退火的温度在800C至1000C之间,退火过程只通入氮气,或按比例通入氮气与氧气的混合气体,通入氮气与氧气的比例在10:1至20:1之间。
本发明具有以下优点:
采用本发明涉及的SGT MOSFET结构及工艺制造方法,因其不需要在沟槽内生长厚的屏蔽电极介质层,同时BSG具有良好的高温回流特性,具备良好的沟槽填充能力,可以将沟槽CD极大程度缩小,因而可以缩小单位元胞尺寸,采用更高掺杂浓度的外延片实现同样的击穿电压,降低器件Rsp,增强市场竞争力。
同时,本发明的制造方法考虑到BSG易扩散的特点,将填充在深沟槽下部的BSG,先用厚氧化物将其完全密封在沟槽内,再进行高温退火,完全规避了BSG扩散可能引起的沟道和栅氧化的沾污,实现与现有常规集成电路制程的完全兼容。
附图说明
图1为传统SGT结构示意图;
图2为本发明步骤一的示意图;
图3为本发明步骤二的示意图;
图4为本发明步骤三的示意图;
图5为本发明步骤四的示意图;
图6为本发明步骤五的示意图;
图7为本发明步骤六的示意图;
图8为本发明步骤七的示意图;
图9为本发明步骤八的示意图;
图10为本发明步骤九的示意图。
具体实施方式
下面结合具体实施方式对本发明进行详细的说明。
本发明涉及一种SGT结构MOSFET及其工艺制造方法,所述方法由以下步骤实现:
步骤一:在Si衬底片1表面生长N型外延层2,外延层厚度根据器件所
需源漏耐压制定,范围从5微米至20微米,如图2所示。
步骤二:以ONO(氧化硅3-氮化硅4-氧化硅5)膜为硬掩膜,利用沟槽光刻版进行光刻工艺,需要挖沟槽的位置曝光,无光刻胶掩蔽,其余部分用光刻胶掩蔽。然后通过干法刻蚀,将无光刻胶掩蔽位置刻蚀出深沟槽6,然后去除光刻胶,如图3所示。
步骤三:利用CVD工艺在深沟槽内填充BSG材料7,保证将深沟槽内填满,如图4所示。
步骤四:通过CMP工艺将Si表面多余BSG研磨去除,并利用湿法腐蚀将沟槽内BSG腐蚀至Si表面以下1微米至1.5微米,如图5所示。
步骤五:利用各向同性刻蚀将沟槽宽度扩大,形成栅极沟槽8,然后去除表面硬掩模,如图6所示。
步骤六:栅极沟槽内回填HDP 氧化物 9,如图7所示。
步骤七:利用炉管高温退火回流使BSG材料中Boron扩散至深沟槽外围的Si材料中,即可形成P柱10,退火温度范围800℃至1000℃之间。退火回流的气体可以是纯氮气,也可以是氮气与氧气的混合气体,其气流比例在10:1至20:1之间,如图8所示。
步骤八:栅极沟槽内HDP 氧化物回刻至与BSG顶端间距剩余2000~5000A左右,作为BSG与栅极POLY间的隔离层,如图9所示。
步骤九:栅极氧化层至最终metal层次与常规MOSFET工艺相同,完成后最终器件结构如图10所示。
通过上述方法得到的SGT MOSFET结构,该MOSFET结构位于外延衬底上,其栅极沟槽下方有一区域,该区域内填满与外延反型的材料来实现电荷平衡。MOSFET的栅极沟槽下方区域为一深沟槽。MOSFET栅极沟槽下方的深沟槽中填充的材料为与外延反型的掺杂氧化物。所述MOSFET的外延材料为N型,其栅极沟槽下方的深沟槽内填充物为P型氧化膜:硼硅玻璃BSG。MOSFET栅极沟槽与其下方深沟槽自对准。所述深沟槽的深度小于所述MOSFET所在外延的厚度。
以上所述,仅为本发明的较佳实施例而已,并非用于限定本发明的保护范围。
本发明所述的SGT MOSFET是通过在沟槽内填充BSG材料,再由炉管高温退火,使Boron扩散至沟槽外围形成P柱,实现与N型外延的电荷平衡,而非通过厚氧化层的电荷耦合效应。采用本发明所述的工艺制造方法制作的SGT MOSFET可以在实现较小的器件尺寸的同时,灵活调节P柱的宽度和浓度,有利于优化器件参数和性能,工艺可控性强。且,本发明的制造方法考虑到BSG易扩散的特点,将填充在深沟槽下部的BSG,先用厚氧化物将其完全密封在沟槽内,再进行高温退火,完全规避了BSG扩散可能引起的沟道和栅氧化的沾污,实现与现有常规集成电路制程的完全兼容。
本发明的内容不限于实施例所列举,本领域普通技术人员通过阅读本发明说明书而对本发明技术方案采取的任何等效的变换,均为本发明的权利要求所涵盖。

Claims (10)

1.SGT MOSFET结构,其特征在于:
该MOSFET结构位于外延衬底上,其栅极沟槽下方有一区域,该区域内填满与外延反型的材料来实现电荷平衡。
2.根据权利要求1所述的SGT MOSFET结构,其特征在于:
MOSFET的栅极沟槽下方区域为一深沟槽。
3.根据权利要求2所述的SGT MOSFET结构,其特征在于:
MOSFET栅极沟槽下方的深沟槽中填充的材料为与外延反型的掺杂氧化物。
4.根据权利要求3所述的SGT MOSFET结构,其特征在于:
MOSFET的外延材料为N型,其栅极沟槽下方的深沟槽内填充物为P型氧化膜:硼硅玻璃BSG。
5.根据权利要求4所述的SGT MOSFET结构,其特征在于:
MOSFET栅极沟槽与其下方深沟槽自对准。
6.根据权利要求5所述的SGT MOSFET结构,其特征在于:
深沟槽的深度小于MOSFET所在外延的厚度。
7.SGT MOSFET结构的工艺制造方法,其特征在于:
包括以下步骤:
步骤一:在Si衬底片表面生长N型外延层;
步骤二:利用沟槽光刻版进行光刻工艺,对沟槽位置曝光,再通过干法刻蚀,将曝光位置刻蚀出深沟槽;
步骤三:利用CVD工艺在深沟槽内填满硼硅玻璃BSG;
步骤四:通过CMP工艺将Si表面多余硼硅玻璃BSG研磨去除,并利用湿法腐蚀将沟槽内BSG腐蚀至Si表面以下;
步骤五:利用各项同性刻蚀将沟槽宽度扩大,形成栅极沟槽;
步骤六:栅极沟槽内回填HDP 氧化物;
步骤七:利用高温退火使硼硅玻璃BSG材料中硼Boron扩散至深沟槽外围的Si材料中,形成P柱;
步骤八:栅极沟槽内HDP OX回刻;
之后步骤与常规MOSFET工艺相同。
8.根据权利要求7所述的SGT MOSFET结构的工艺制造方法,其特征在于:
所述步骤二中,干法刻蚀形成的沟槽其深度在5微米至20微米之间,宽度在0.2微米至2微米之间。
9.根据权利要求8所述的SGT MOSFET结构的工艺制造方法,其特征在于:
所述步骤四中,湿法腐蚀BSG至Si表面以下深度在1微米至1.5微米之间。
10.根据权利要求9所述的SGT MOSFET结构的工艺制造方法,其特征在于:
所述步骤七中,硼硅玻璃BSG高温退火的温度在800C至1000C之间,退火过程只通入氮气,或按比例通入氮气与氧气的混合气体,通入氮气与氧气的比例在10:1至20:1之间。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111933714A (zh) * 2020-09-25 2020-11-13 龙腾半导体股份有限公司 三段式氧化层屏蔽栅沟槽mosfet结构的制造方法
CN112349780A (zh) * 2020-09-25 2021-02-09 龙腾半导体股份有限公司 三段式氧化层屏蔽栅沟槽mosfet结构
CN112382572A (zh) * 2021-01-15 2021-02-19 龙腾半导体股份有限公司 Ono屏蔽栅的sgt结构及其制造方法
CN113628969A (zh) * 2020-05-06 2021-11-09 苏州东微半导体股份有限公司 半导体超结器件的制造方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07183247A (ja) * 1992-04-21 1995-07-21 Seiko Instr Inc 半導体装置及び半導体装置の製造方法及び半導体装置の評価方法及び半導体製造装置
JP2007158275A (ja) * 2005-12-08 2007-06-21 Toyota Motor Corp 絶縁ゲート型半導体装置およびその製造方法
US20070158755A1 (en) * 2006-01-12 2007-07-12 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a buried conductive region
JP2008251732A (ja) * 2007-03-29 2008-10-16 Toshiba Corp 半導体装置およびその製造方法
US20100155840A1 (en) * 2008-12-19 2010-06-24 Kou-Way Tu Power mosfet and fabricating method thereof
CN101814436A (zh) * 2009-11-05 2010-08-25 苏州博创集成电路设计有限公司 纵向高压深槽半导体管的制备方法
JP2011054809A (ja) * 2009-09-03 2011-03-17 Mitsubishi Electric Corp 窒化物半導体装置およびその製造方法
US20110272759A1 (en) * 2010-05-06 2011-11-10 International Rectifier Corporation Vertical LDMOS device and method for fabricating same
US20170077292A1 (en) * 2015-09-10 2017-03-16 Kabushiki Kaisha Toyota Jidoshokki Trench-gate semiconductor device and manufacturing method thereof

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07183247A (ja) * 1992-04-21 1995-07-21 Seiko Instr Inc 半導体装置及び半導体装置の製造方法及び半導体装置の評価方法及び半導体製造装置
JP2007158275A (ja) * 2005-12-08 2007-06-21 Toyota Motor Corp 絶縁ゲート型半導体装置およびその製造方法
US20070158755A1 (en) * 2006-01-12 2007-07-12 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a buried conductive region
JP2008251732A (ja) * 2007-03-29 2008-10-16 Toshiba Corp 半導体装置およびその製造方法
US20100155840A1 (en) * 2008-12-19 2010-06-24 Kou-Way Tu Power mosfet and fabricating method thereof
JP2011054809A (ja) * 2009-09-03 2011-03-17 Mitsubishi Electric Corp 窒化物半導体装置およびその製造方法
CN101814436A (zh) * 2009-11-05 2010-08-25 苏州博创集成电路设计有限公司 纵向高压深槽半导体管的制备方法
US20110272759A1 (en) * 2010-05-06 2011-11-10 International Rectifier Corporation Vertical LDMOS device and method for fabricating same
US20170077292A1 (en) * 2015-09-10 2017-03-16 Kabushiki Kaisha Toyota Jidoshokki Trench-gate semiconductor device and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113628969A (zh) * 2020-05-06 2021-11-09 苏州东微半导体股份有限公司 半导体超结器件的制造方法
CN113628969B (zh) * 2020-05-06 2022-06-24 苏州东微半导体股份有限公司 半导体超结器件的制造方法
CN111933714A (zh) * 2020-09-25 2020-11-13 龙腾半导体股份有限公司 三段式氧化层屏蔽栅沟槽mosfet结构的制造方法
CN112349780A (zh) * 2020-09-25 2021-02-09 龙腾半导体股份有限公司 三段式氧化层屏蔽栅沟槽mosfet结构
CN112382572A (zh) * 2021-01-15 2021-02-19 龙腾半导体股份有限公司 Ono屏蔽栅的sgt结构及其制造方法
CN112382572B (zh) * 2021-01-15 2021-11-02 龙腾半导体股份有限公司 Ono屏蔽栅的sgt结构及其制造方法

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