CN107833914A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN107833914A
CN107833914A CN201710749648.2A CN201710749648A CN107833914A CN 107833914 A CN107833914 A CN 107833914A CN 201710749648 A CN201710749648 A CN 201710749648A CN 107833914 A CN107833914 A CN 107833914A
Authority
CN
China
Prior art keywords
portions
semiconductor device
ttransistor
igbt
fly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710749648.2A
Other languages
English (en)
Other versions
CN107833914B (zh
Inventor
白川彻
田中裕之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of CN107833914A publication Critical patent/CN107833914A/zh
Application granted granted Critical
Publication of CN107833914B publication Critical patent/CN107833914B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明公开了一种半导体装置。RC‑IGBT与具有IGBT部但不具有FWD部的半导体芯片相比，设置FWD部的部分使得半导体芯片的芯片面积变大。寻求缩小RC‑IGBT的半导体芯片的芯片面积。本发明的半导体装置具备：晶体管部，具有多个晶体管；续流二极管部，在俯视晶体管部的情况下，续流二极管部至少与晶体管部的一边对置，且设置于晶体管部的外侧；以及栅流道部和栅衬垫部，在俯视晶体管部的情况下，栅流道部和栅衬垫部与晶体管部接触地设置，并且不包围晶体管部的整个外侧。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
已知有将IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极型晶体管)和FWD(Free Wheeling Diode：续流二极管)设置于一个半导体基板而成的RC-IGBT(ReverseConducting-IGBT：反向导通IGBT)。以往，以在俯视半导体装置时，使IGBT部与FWD部交替地呈条纹状，或者，IGBT部包围多个FWD部的方式，设置IGBT部和FWD部(例如，参照专利文献1)。另外，以包围IGBT部的周围的方式设置有栅流道(gate runner)(例如，参照专利文献2)。
现有技术文献
专利文献
专利文献1：日本特开2016-96222号公报
专利文献2：日本特开2004-363328号公报
发明内容
技术问题
RC-IGBT与具有IGBT部但不具有FWD部的半导体芯片相比，设置FWD部的部分使半导体芯片的芯片面积变大。谋求缩小RC-IGBT的半导体芯片的芯片面积。
技术方案
本发明的第一方式中，提供一种半导体装置。半导体装置可以具备晶体管部、续流二极管部、栅流道部和栅衬垫部。晶体管部可以具有多个晶体管。在俯视晶体管部的情况下，续流二极管部可以至少与晶体管部的一边对置，并且设置于晶体管部的外侧。在俯视晶体管部的情况下，栅流道部和栅衬垫部可以与晶体管部接触地设置，并且不包围晶体管部的整个外侧。
在俯视晶体管部的情况下，续流二极管部可以不设置于晶体管部的内侧。
在俯视晶体管部的情况下，续流二极管部可以连续地设置于晶体管部的外侧、栅流道部的外侧和栅衬垫部的外侧。
续流二极管部可以为对矩形环状的四边之中的一边进行切口而成的形状。
续流二极管部可以设置为包围晶体管部的整个外侧。
半导体装置还可以具备边缘终端部。在俯视晶体管部的情况下，边缘终端部可以位于续流二极管部的外侧。续流二极管部可以具有发射沟槽部，该发射沟槽部的至少一部分与从边缘终端部延伸的绝缘膜重叠。
半导体装置还可以具备布线部。布线部可以与半导体装置的外部电导通。在俯视晶体管部的情况下，布线部可以设置在晶体管部的内侧。
半导体装置还可以具备半导体基板和焊料层。晶体管部和续流二极管部可以设置于半导体基板。焊料层可以与背面电极和半导体基板的侧面直接接触地设置。背面电极可以设置于半导体基板的背面。半导体基板的厚度W与半导体基板的侧面处的半导体基板的背面上的焊料层的高度T可以满足W/2＜T的关系。
在俯视晶体管部的情况下，焊料层从半导体基板的侧面向外侧突出的突出长度X与焊料层的高度T可以满足T＜X的关系。
续流二极管部可以具有延伸至边缘终端部为止的n型阴极层。
边缘终端部可以具有p型集电层，该p型集电层的宽度比边缘终端部的宽度小。
边缘终端部中的p型集电层的宽度可以小于设有晶体管部和续流二极管部的半导体基板的厚度。
晶体管部与续流二极管部的交界区的总计长度可以为半导体装置的一边的长度的3.0倍以下。
应予说明，上述的发明内容并非列举了本发明的全部特征。此外，这些特征组的再组合也可另外成为发明。
附图说明
图1是第一实施方式中的半导体装置500的俯视图。
图2是图1中的区域A的放大图。
图3A是图2中的B-B’的剖视图。
图3B是栅流道部36被设置为包围IGBT部100的整个外侧的第一比较例的剖视图。
图4是图2中的C-C’的剖视图。
图5是图2中的D-D’的剖视图。
图6A是说明IGBT部100和FWD部200交替地设置而成的第二比较例的图。
图6B是说明第一实施方式的IGBT部100和FWD部200的图。
图6C是图6A的俯视图。
图7的(A)是说明未将发射沟槽部40设置于FWD部200的第三比较例的图。图7的(B)是说明将发射沟槽部40设置于FWD部200的第一实施方式的图。
图8是说明焊料层400的高度T和突出长度X的图。
图9是说明第二实施方式中的边缘终端部300的宽度S和边缘终端部300的集电层360的宽度Y的图。
图10A是第三实施方式中的半导体装置500的俯视图。
图10B是示出第三实施方式的第一变形例的图。
图10C是示出第三实施方式的第二变形例的图。
图10D是示出第三实施方式的第三变形例的图。
图11A是示出第四实施方式中的半导体装置500的俯视图。
图11B是示出第四实施方式的第一变形例的图。
图11C是示出第四实施方式的第二变形例的图。
图11D是示出第四实施方式的第三变形例的图。
图12A是示出第五实施方式中的半导体装置600的俯视图。
图12B是示出第五实施方式的第一变形例的图。
图12C是示出第五实施方式的第二变形例的图。
图12D是示出第五实施方式的第三变形例的图。
符号说明
10…半导体基板，12…正面，14…背面，16…侧面，20…基区，21…沟道形成区域，22…发射区，23…p+型阱区，24…接触区，25…漂移区，26…FS层，30…栅沟槽部，31…栅极端子，32…栅电极，34…栅绝缘膜，36…栅流道部，38…栅衬垫部，39…p+型阱区，40…发射沟槽部，41…发射极端子，42…沟槽电极，44…沟槽绝缘膜，46…发射电极，47…发射电极外周端，50…层间绝缘膜，52…开口，54…插塞，60…集电层，61…集电极端子，66…集电电极，80…边，85…中心，90…布线区，94…开口，95…钝化膜，98…布线部，100…IGBT部，150…交界区，200…FWD部，260…阴极层，300…边缘终端部，310…保护环结构，322…保护环，324…沟道阻止区，340…多晶硅层，346…电极层，348…电极层，350…绝缘膜，360…集电层，400…焊料层，500、600…半导体装置
具体实施方式
以下，通过发明的实施方式来说明本发明，但以下的实施方式并不限定权利要求所涉及的发明。另外，在实施方式之中所说明的特征的全部组合不限于是发明的技术方案所必须的。
图1是第一实施方式中的半导体装置500的俯视图。应予说明，俯视半导体装置500与俯视IGBT部100所得的情况相当。在图1中，为了说明构成物的相互位置关系，适当地除去了设置于半导体基板10的正面上的膜、层和电极等。应予说明，在图2的说明中对开口94进行描述，在图6A等的说明中对标号“B”、“L”进行描述。
在本例中，x方向与y方向是彼此垂直的方向，z方向是垂直于x-y平面的方向。x方向、y方向和z方向构成通常所说的右手系。本例的半导体基板10在+z方向的端部具有正面，在-z方向端部具有背面。应予说明，在本例中，上和下不过是说明相对的位置关系的方便起见的表达而已。z方向并不一定表示重力方向或者垂直于地面的方向。
半导体装置500设置于半导体基板10。本例的半导体装置500具备IGBT部100、续流二极管部(以下，简写为FWD部)200、栅流道部36、栅衬垫部38和边缘终端部300。
在俯视半导体装置500时，IGBT部100为矩形形状。本例的矩形形状具有四边80a～80d。本例的边80a和边80c为平行于x方向的边80。另外，本例的边80b和边80d为平行于y方向的边80。在IGBT部100，邻接的两边80构成的角也可以不是直角。在本例中，边80a与边80b不形成直角，而通过平滑的曲线彼此连接。边80b和边80c也是同样。
本例的IGBT部100是晶体管部的一例。IGBT部100具有多个IGBT。应予说明，对于IGBT的单位构成将在后面进行描述。应予说明，也可以使用MOSFET(Metal OxideSemiconductor Field Effect Transistor：金属氧化物半导体场效应晶体管)部来取代IGBT部100。MOSFET部可以具有多个MOSFET。IGBT部100和MOSFET部可以是供电流沿z方向流通的通常所说的纵型晶体管。
本例的FWD部200设置于IGBT部100的外侧。应予说明，在本例中，外侧表示相对于半导体基板10的矩形的x-y平面的中心85，位于相对远的位置。相对于此，内侧表示相对于中心85位于相对近的位置。在本例中，FWD部200不设置于IGBT部100的内侧。
FWD部200可以至少与IGBT部100的一边80对置。本例的FWD部200被设置为与IGBT部100的不同的四边80对置而包围IGBT部100的整个外侧。本例的FWD部200与IGBT部100的三边80a、80b和80c接触。FWD部200与IGBT部100接触的交界区150用粗线进行图示。另外，本例的FWD部200连续地设置于IGBT部100的外侧、栅流道部36的外侧和栅衬垫部38的外侧。
栅流道部36和栅衬垫部38与IGBT部100接触而设置。本例的栅流道部36和栅衬垫部38不包围IGBT部100的整个外侧。本例的栅流道部36和栅衬垫部38设置于IGBT部100的边80d与FWD部200之间。
需要将包括栅沟槽的p型阱区或者p型半导体层设置于栅流道部36和栅衬垫部38正下方的区域。对此，在本例中，栅流道部36和栅衬垫部38未设置为包围IGBT部100的整个外侧，因此能够将不包括栅沟槽部的p型阱区或者p型半导体层用作FWD部200。因此，与栅流道部36和栅衬垫部38包围IGBT部100的整个外侧的情况相比，能够缩小半导体装置500的芯片面积。
边缘终端部300可以设置为包围FWD部200的整个外侧。边缘终端部300位于从FWD部200的最外侧至半导体基板10的端部为止。另外，边缘终端部300可以具有保护环结构和沟道阻止部等耐压结构。
IGBT部100在半导体基板10的正面的整个上方具有发射电极。本例的发射电极在内侧具有布线区90。本例的布线区90为圆形，但布线区90也可以为与FWD部200的外形相似的形状。布线区90的中心可以位于中心85。在布线区90设有与半导体装置500的外部电导通的布线部98。布线部98可以是一条或者多条键合线，也可以是一个或者多个引线框架。本例的键合线和引线框架包括导电性和导热性优异的金属材料。另外，本例的发射电极可以如图1所示地具备发射电极外周端47。
本例的FWD部200被设置为矩形环状。因此，在FWD部200动作时产生的热能够向内侧和外侧传递。在本例中，将布线区90设置于包括中心85的位置，因此能够使在FWD部200产生的热从导热性高的布线部98均匀地进行散热。因此，能够使设为矩形环状的FWD部200的散热在四边均匀地进行。由此，能够防止FWD部200的热阻不均。因此，与存在热阻不均的情况相比，本例在半导体装置500的故障率降低方面和半导体装置500的寿命延长方面有利。
图2是图1中的区域A的放大图。IGBT部100具有多个栅沟槽部30。本例的栅沟槽部30具有沿x方向延伸的长边部。栅沟槽部30的长边部作为IGBT的栅极而起作用。两个长边部在栅流道部36和栅衬垫部38正下方可以为U字形，也可以以直线形状封端。应予说明，栅沟槽部30还位于栅流道部36和栅衬垫部38的下方。
在栅流道部36的周边可以形成有比栅沟槽部30深的p+型阱区39。对p+型阱区39而言，通过p+型阱区39覆盖栅沟槽部30的U字形部分的沟槽底部或者直线状终端部的沟槽底部。由此，在U字形部分和直线状终端部不形成耗尽层，因此防止电场集中。
在栅沟槽部30与栅流道部36之间以及栅沟槽部30与栅衬垫部38之间设有层间绝缘膜。层间绝缘膜具有多个开口52。开口52可以具有与栅沟槽部30的U字形部分对应的形状。本例的开口52具有与栅沟槽部30的U字形部分相似并且比该U字形部分小的形状。栅沟槽部30与栅流道部36以及栅沟槽部30与栅衬垫部38之间可以通过设置于开口52的金属的插塞电导通。
栅流道部36可以为多晶硅膜和其上部的铝-硅合金膜的双层结构。栅流道部36的多晶硅膜通过开口52而与栅沟槽部30的内部的多晶硅连接。或者，栅流道部36可以为铝-硅合金膜的单层结构。在该单层结构的情况下，栅沟槽部30的内部的多晶硅与栅流道部36的铝-硅合金膜可以通过开口52直接连接。
在半导体基板10的正面上设有发射电极46。但是，发射电极46不设置在栅流道部36和栅衬垫部38上。FWD部200上部的发射电极46与IGBT部100上部的发射电极46可以连续。在本例中，发射电极46以包围栅流道部36的方式配置，发射电极46连续地形成于FWD部200与IGBT部100的交界。
在半导体基板10的最上面设有钝化膜95。钝化膜95可以覆盖IGBT部100、FWD部200、边缘终端部300、栅流道部36，还可以局部覆盖栅衬垫部38的周边部。本例的钝化膜95为聚酰亚胺膜。
为了确保半导体装置500与外部的导通，钝化膜9具有多个开口94。为了用于栅电极，本例的钝化膜95在栅衬垫部38上具有开口94，该开口94的x-y平面上的面积比栅衬垫部38的x-y平面上的面积小。应予说明，本例的钝化膜95在栅流道部36上不具有开口94。另外，钝化膜95至少在与布线区90对应的位置也具有用于发射电极46的开口94。在本例中，用于发射电极46的开口94为矩形。
FWD部200可以具有多个发射沟槽部40，也可以不具有多个发射沟槽部40。本例的各个发射沟槽部40以包围IGBT部100的整个外侧的方式连续地设置。俯视发射沟槽部40所得的形状可以与俯视FWD部200所得的外形相似。本例的各个发射沟槽部40在俯视下为矩形环状。应予说明，对于发射沟槽部40的详细情况在后面进行描述。
本例的边缘终端部300具有保护环结构310。保护环结构310包括多个保护环322。另外，本例的边缘终端部300在比保护环结构310更靠向外侧的位置具有沟道阻止区324。
图3A为图2中的B-B’的剖视图。半导体基板10在IGBT部100、FWD部200和边缘终端部300是共通的。在本例中，将半导体基板10的一个主面称为正面12。另外，将半导体基板10的另一个主面称为背面14。本例的半导体基板10为硅基板。但是，在其它示例中，半导体基板10也可以为碳化硅(SiC)基板、氮化镓(GaN)基板、氧化镓(GaO)基板。
本例的半导体基板10在从正面12至预定的深度位置为止具有p型的基区20。本例的基区20设置于IGBT部100和FWD部200。另外，本例的半导体基板10在IGBT部100和FWD部200，从基区20至预定的深度位置为止具有n-型的漂移区25。另外，本例的半导体基板10在边缘终端部300，从正面12至预定的深度位置为止具有漂移区25。
在本例中，n或者p分别表示电子或者空穴为多数载流子。另外，关于记载于n或者p的右上方的+或者-，+表示载流子浓度比+未记载于n或者p的载流子浓度高，-表示载流子浓度比-未记载于n或者p的载流子浓度低。
在IGBT部100和FWD部200，栅沟槽部30和发射沟槽部40贯穿基区20而设置。即，栅沟槽部30和发射沟槽部40的前端到达漂移区25。
在栅沟槽部30上设有层间绝缘膜50。另外，在基区20上设有发射电极46。层间绝缘膜50使栅沟槽部30的栅电极与发射电极46电分离。栅极端子31通过栅衬垫部38电连接于栅沟槽部30。关于栅沟槽部30的详细情况在后面进行描述。另外，发射极端子41通过布线区90电连接于发射电极46。图1所示的布线部98为发射极端子41的一例。
在FWD部200，也在基区20上设有发射电极46。FWD部200的发射电极46作为阳极电极而起作用。FWD部200具有通过p型的基区20与n-型的漂移区25的pn结而形成的FWD。FWD部200的FWD与IGBT部100的IGBT反向并联连接，在IGBT截止时使回流电流流通。
边缘终端部300的保护环结构310可以具有使在IGBT部100和FWD部200产生的耗尽层向半导体基板10的端部扩展的功能。由此，能够防止半导体基板10内部的电场集中。由此，与不设置保护环结构310的情况相比，能够提高半导体装置500的耐压。
本例的p+型的保护环322通过多晶硅层340而与电极层346电连接。多个保护环322彼此通过绝缘膜350互相电绝缘。n+型的沟道阻止区324通过绝缘膜350的开口而电连接于电极层348。应予说明，沟道阻止区324也可以是p型的半导体区。沟道阻止区324具有使从保护环322向半导体基板10的端部扩展的耗尽层封端的功能。
p+型的保护环322的底部的深度可以与p+型阱区39的底部的深度相等。另外，p+型的保护环322的底部的深度可以比栅沟槽部30的底部的深度或者发射沟槽部40的底部的深度深。本例的p+型阱区39的底部的深度比栅沟槽部30的底部的深度和发射沟槽部40的底部的深度深。
在本例中，发射电极46、电极层346和电极层348均可以是铝和硅的合金(例如，Al-Si合金或者Al-Si-Cu合金)。另外，绝缘膜350可以是二氧化硅膜，也可以在二氧化硅上进一步具有包括其他材料的层间绝缘膜(例如，BPSG膜)。
本例的半导体基板10在漂移区25的下方具有FS(Field Stop：场截止)层26。FS层26可以是n型的半导体层。本例的FS层26共通地设置于IGBT部100、FWD部200和边缘终端部300。
本例的半导体基板10在FS层26的下方具有集电层60、阴极层260和集电层360。在本例中，集电层60、阴极层260和集电层360分别设置于IGBT部100、FWD部200和边缘终端部300。集电层60和集电层360为p+型的半导体层。与此相对地，阴极层260为n+型的半导体层。
半导体装置500在背面14的下方具有作为背面电极的集电电极66。集电电极66共通地设置于IGBT部100、FWD部200和边缘终端部300。应予说明，在FWD部200，集电电极66作为阴极电极而起作用。集电极端子61可以电连接到集电电极66。
图3B是栅流道部36被设置为包围IGBT部100的整个外侧的第一比较例的剖视图。第一比较例具有p+型阱区23，该p+型阱区23在正上方具有栅流道部36和栅衬垫部38。在p+型阱区23的正上方设有包括多晶硅的栅电极。该栅电极电连接到栅沟槽部30的栅电极。
与此相对地，在图3A(即第一实施方式)，栅流道部36不包围IGBT部100的整个外侧。在第一实施方式中，栅流道部36和栅衬垫部38仅设置于IGBT部100的一边80d与FWD部200之间。因此，在图3A中，也可以将图3B的第一比较例中的p+型阱区23用作FWD部200。
图4是图2中的C-C’的剖视图。在图4中，对IGBT的单位构成进行说明。栅沟槽部30在沟槽内具有栅绝缘膜34和栅电极32。栅绝缘膜34与沟槽的内壁直接接触地设置。内壁可以包括底面和侧面。栅电极32与栅绝缘膜34直接接触地设置。即，沟槽的内部被栅绝缘膜34和栅电极32填充。
n+型的发射区22和p+型的接触区24以在正面12露出的方式设置。发射区22和接触区24设置于栅沟槽部30的x方向的两侧。发射区22与栅沟槽部30的两侧直接接触地设置。相对于此，接触区24与栅沟槽部30分离。基区20之中，与栅沟槽部30接触的区域作为沟道形成区域21而起作用。
图5是图2中的D-D’的剖视图。在图5中，栅沟槽部30的栅电极32和栅流道部36与在层间绝缘膜50的开口52设置的插塞54直接连接。由此，栅电极32和栅流道部36彼此电连接。本例的插塞54优选包括钨。但是，栅电极32和栅流道部36也可以不通过插塞54而彼此电连接。应予说明，栅沟槽部30与栅衬垫部38也是同样，通过设置于开口52的插塞54彼此电连接。栅电极32可以包括多晶硅。
图6A是说明IGBT部100和FWD部200交替地设置而成的第二比较例的图。图6B是说明第一实施方式的IGBT部100和FWD部200的图。在图6A和图6B中，对IGBT在从导通状态转移到截止状态之后紧接着的两者的差异进行说明。应予说明，在图6A和图6B的FWD部200，设有发射沟槽部40，该发射沟槽部40具有沟槽电极42和沟槽绝缘膜44。另外，在图6A和图6B中，在圆形标记的内部记载有“e-”的部分示意性地表示电子，同样地，在圆形标记的内部记载有“e+”的部分表示空穴。图6C为图6A的俯视图。在图6C中，考虑到附图的便于观察性，仅示出IGBT部100、交界区150、FWD部200和边缘终端部300。
应予说明，在本实施方式和比较例中，各个接地电位和预定的正电位施加于发射电极46和集电电极66。在本实施方式和比较例中，将通过使预定的正电位施加于栅电极32而使沟道形成于沟道形成区域21的状态称为IGBT部100的导通状态。将通过使接地电位或者预定的负电位施加于栅电极32而使沟道形成区域21的沟道消除了的状态称为IGBT部100的截止状态。应予说明，也将IGBT部100为导通状态时和IGBT部100为截止状态时分别简称为导通时和截止时。
在IGBT部100，导通时使电流从集电电极66流到发射电极46。与此相对地，在IGBT部100截止时，在IGBT部100使电流不流通，而在FWD部使电流从发射电极46流到集电电极66。换言之，在IGBT部100的栅极导通时，电子从IGBT部100的发射电极46流到集电电极66，而空穴从集电电极66流到发射电极46。另一方面，在IGBT部100的栅极截止时，回流电流在半导体装置500中流通的情况下，电子从FWD部200的集电电极66流到发射电极46，空穴从发射电极46流到集电电极66。
回流电流在半导体装置500中流通时，存在IGBT部100的栅极保持导通(即，残存有沟道形成区域21)的情况。在图6A和图6B中，用虚线表示残存的沟道形成区域21。在FWD部200流通的与IGBT部100最相邻的电子可能进入到残存的沟道形成区域21。与图6B所示第一实施方式相比，在图6A所示的第二比较例中，IGBT部100与FWD部200的交界部分多，因此进入到残存的沟道形成区域21的电子变多。
由此，产生图6A的FWD部200的正向电压(以下，为Vf)变得比图6B的FWD部200的Vf高的现象。Vf变高的部分使得电流难以在FWD部200流通。FWD部200中的电流的流通难度成为FWD部200中的导通损耗。与此相对地，在图6B的第一实施方式中，FWD部200以仅包围IGBT部100的外侧的方式设置。因此，与以将IGBT部100和FWD部200交替地设置为条纹状，或者，使IGBT部100包围多个FWD部200的方式设置IGBT部100和FWD部200的情况相比，IGBT部100与FWD部200的交界区150变小。因此，与图6A所示的第二比较例相比，在图6B所示的第一实施方式中，能够降低Vf。
在本实施方式的示例中，将平面观察(俯视)半导体装置500而得的形状设为大致正方形。将作为该正方形的半导体装置500的一边的长度设为L。另一方面，在半导体装置500，IGBT部100与FWD部200的交界区150设为一个以上，例如n个。该交界区150之中，如果将第i个(i为1～n中的任一个)交界区150设为Bi，将全部Bi的总计长度设为β(β＝B1+B2+…+Bi+…+Bn)，则长度β可以为长度L的3.0倍以下(即，β≤3.0L)。
关于第二比较例，例如图6C所示，在半导体装置中，将IGBT部100设为六个，将与IGBT部100接触的FWD部200设为五个。此时，IGBT部和FWD部的交界区150的数量共计为十个。如果将IGBT部100和FWD部200的各条长边方向的长度设为例如0.7L，则IGBT部100和FWD部200的交界区150的长度Bi全部相同为B＝0.7L。而且，交界区150的总计长度α为α＝10×B＝7.0L。
另一方面，在图1所示的本实施方式的示例中，例如IGBT部100与FWD部200相邻之处为四处。在此，对于隔着栅流道部36而相邻的IGBT部100与FWD部200而言，由于通过栅流道部36使得IGBT部100与FWD部200充分远离，因此交界区150视为不存在。因此，本例的IGBT部100与FWD部200的交界区150的数量为三个。本例的交界区150也可以换言之为IGBT部100与FWD部200直接相邻的直线部分的数量。如果分别将三个交界区150的长度设为B，且B＝0.7L，则交界区150的总计长度α为α＝3×B＝2.1L。
IGBT部100和FWD部200的形状和/或配置可以进行适当调整。因此，相对于半导体装置500的一边的长度L，IGBT部100与FWD部200的各交界区150的长度Bi不限于0.7L，也可以为0.5L以上且0.9L以下。如此即使IGBT部100与FWD部200的各交界区150的长度Bi为预定的范围，只要α小于L的3.0倍，就可以获得降低Vf的效果，因此也是优选的。进一步地，α还可以为L的2.5倍以下、L的2.0倍以下、L的1.5倍以下、L的1.0倍以下。
应予说明，也可以认为在IGBT部100与FWD部200的交界为仅一条的情况下，交界区150的长度B1为0.5L左右时为交界区150的总计长度α的下限值。即，α可以为L的0.5倍以上。
应予说明，在本实施方式的示例中，将俯视半导体装置500所得的形状设为大致正方形，但半导体装置500可以为长方形。在半导体装置的形状为长方形的情况下，例如，将半导体装置的长边和与该长边垂直地相邻的短边的各自长度之和除以2而得的值设为L。
图7的(A)为说明在FWD部200不设置发射沟槽部40的第三比较例的图。与此相对地，图7的(B)为说明在FWD部200设置有发射沟槽部40的第一实施方式的图。在图7的(A)和图7的(B)中，示出FWD部200与边缘终端部300的交界附近处的FWD部200的放大图。
在图7的(A)和图7的(B)中，绝缘膜350从边缘终端部300延伸至FWD部200的位置P1为止。位置P1为绝缘膜350与发射区22以遍及x方向的预定长度的方式重叠的区域的x方向端部。位置P1位于正面12。应予说明，发射电极46在从位置P1起算+x方向的预定范围内，与正面12直接接触。
如图7的(A)所示的那样，IGBT部100为导通状态时，存在从边缘终端部300的集电电极66流到FWD部200的发射电极46的电流I(用箭头表示)。该电流I从基区20的端部的正面12附近进入到FWD部200。为了进行说明，以位于比位置P1更靠近IGBT部100(内侧)的位置P2为例。如果将位置P1与位置P2进行比较，则对电流I而言，在基区20流到位置P2之后进入到发射电极46的情况下的电阻高于在基区20流到位置P1之后进入到发射电极46的情况下的电阻。因此，电流I必然通过置P1。由此，电流I集中于位置P1。
另外，在IGBT部100导通时，在发射区22的底部处的x方向端部区域(即，角部R1)，电场特别集中。产生电场集中的区域R1与产生电流集中的位置P1之间的距离L越小，雪崩击穿越容易发生。
相对于此，图7的(B)的FWD部200具有与绝缘膜350在z方向上重叠的发射沟槽部40。发射沟槽部40的至少一部分在正面12被绝缘膜350覆盖即可。在本例的发射沟槽部40，最靠近边缘终端部300的发射沟槽部40的沟槽绝缘膜44在位置P1处与绝缘膜350在z方向上重叠。因此，在图7的(B)的本例中，对电流I而言，通过位置P1的情况成为高电阻。由此，在图7的(B)中，电流I成为不在位置P1，而通过发射沟槽部40之间。因此，与图7的(A)相比，在图7的(B)中，能够增大区域R1与位置P1之间的距离L，因此变得难以发生雪崩击穿。
应予说明，位于最外周的发射沟槽部40可以形成于绝缘膜350的下部，并且可以与发射电极46绝缘。在该情况下，位置P1可以位于相邻的发射沟槽部40之间。如果位于最外周的发射沟槽部40形成于绝缘膜350的下部，则位于最外周的发射沟槽部40成为壁垒，电流I无法集中于位置P1。与位于最外周的发射沟槽部40相邻并且与发射电极46绝缘的发射沟槽部40也可以是多个。
接着，对第一实施方式的半导体装置500的制造方法的一例进行说明。但是，半导体装置500的制造方法不限于本例。首先，准备与漂移区25相同的n型杂质浓度的半导体基板10。漂移区25的n型杂质浓度可以为2E+13cm-3以上且5E+14cm-3以下。
接着，通过热氧化，形成左右的热氧化膜。接着，蚀刻除去预定区域的热氧化膜，使半导体基板10露出。接着，对半导体基板10实施选择性的杂质掺杂和热扩散，而形成保护环322和沟道阻止区324。p+型的保护环322可以具有5.5E+18cm-3以上且5.0E+19cm-3以下的p型杂质，n+型的沟道阻止区324可以具有1.0E+19cm-3以上且1.0E+20cm-3以下的n型杂质。在热处理中，可以在1150℃下对半导体基板10进行加热2小时。另外，在热处理中，也可以同时形成左右的热氧化膜。
接着，对半导体基板10进行蚀刻，形成栅沟槽部30和发射沟槽部40的外形。接着，对半导体基板10实施选择性的杂质掺杂和热扩散，而形成p型的基区20、n+型的发射区22和p+型的接触区24。
首先，为了形成基区20，注入1.5E+13cm-2以上且3.5E+13cm-2以下的p型杂质，在1100℃下进行热处理2小时。接着，为了形成接触区24，注入1.0E+15cm-2以上且3.0E+15cm-2以下的p型杂质。接着，为了形成发射区22，注入1.0E+15cm-2以上且5.0E+15cm-2以下的n型杂质。然后，在900℃以上且1050℃以下对半导体基板10进行热处理0.5小时。应予说明，可以将在热处理时形成的二氧化硅膜用作栅绝缘膜34和沟槽绝缘膜44。二氧化硅膜可以形成为约1.2μm的厚度。
接着，通过CVD(chemical vapor deposition：化学气相沉积)和蚀刻工艺等形成栅电极32、沟槽电极42和多晶硅层340。在本例中，栅电极32和沟槽电极42也包括多晶硅。
接着，通过CVD和蚀刻工艺等形成绝缘膜350和层间绝缘膜50。绝缘膜350可以包括二氧化硅，层间绝缘膜50可以包括BPSG。开口52也通过蚀刻层间绝缘膜50来形成。接着，通过溅射钨，蚀刻成形而使插塞54成形。
接着，通过CVD和蚀刻工艺等形成栅流道部36、栅衬垫部38和多晶硅层340。在本例中，栅流道部36、栅衬垫部38和多晶硅层340均包括多晶硅。接着，通过溅射和蚀刻工艺等，形成发射电极46、电极层346和电极层348。本例的发射电极46、电极层346和电极层348包括Al-Si合金。
接着，从下方研磨半导体基板10，而将半导体基板10的厚度调整为预定的厚度。可以根据半导体装置500的耐压来确定半导体基板10的厚度。接着，涂布形成钝化膜95。钝化膜95也可以是厚度为5μm以上且15μm以下的聚酰亚胺膜。
接着，从半导体基板10的背面14掺杂n型杂质而形成n+型的FS层26。例如，从半导体基板10的背面14以1.0E+12cm-2以上且5.0E+14cm-2以下的程度并以不同质子的剂量进行多次离子注入。接着，在300℃～400℃程度的温度下进行热处理，形成VOH缺陷，该VOH缺陷通过注入质子所注入的氢与半导体基板10中的氧和空穴而引起。该VOH缺陷成为施主(氢施主)。该氢施主成为n+型的FS层26。
接着，从半导体基板10的背面14掺杂p型杂质而形成p+型的集电层60。例如，从半导体基板10的背面14以例如5.0E+12cm-2以上且4.0E+13cm-2以下的剂量以离子方式注入p型杂质。然后，使用背面图案化技术，以离子方式注入1.0E+15cm-2以上且5.0E+15cm-2以下的n型杂质。再然后，对注入面进行激光退火，使n型杂质和p型杂质活化。最后，在半导体基板10的背面14形成集电电极66。应予说明，集电电极66也作为FWD部200的阴极电极而发挥作用。
图8是说明焊料层400的高度T和突出长度X的图。本例的FWD部200包围IGBT部100的整个外侧，因此在FWD部200产生的热也易于传递到半导体基板10的侧面16。另外，本例的FWD部200的电流密度是IGBT部100的电流密度的约3倍。因此，FWD部200中的单位时间的发热量变得比IGBT部100高。
因此，本例的半导体装置500在半导体基板10的侧面16具备焊料层400。在本例中，在进行形成直到集电电极66为止之后，将半导体基板10载置于焊料层400上。由此，焊料层400与集电电极66和半导体基板10的侧面16直接接触地设置。
在本例中，将半导体基板10的厚度设为W。本例的厚度W为从正面12至背面14为止的半导体基板10的z方向上的最短距离。另外，在本例中，在半导体基板10的侧面16处的焊料层400，将背面14上的焊料层400的高度设为T。本例的高度T为从与背面14相同的z方向位置至+z方向上的焊料层400的上端为止的最短直线长度。焊料层400的高度T可以满足W/2＜T的关系通过将焊料层400的高度T设为大于半导体基板10的厚度W的一半，能够使在FWD部200产生的热通过侧面16高效地释放。
另外，将在俯视半导体装置500的情况下从半导体基板10的侧面16向外侧突出的焊料层400的突出长度设为X。本例的突出长度X为从侧面16至-x方向上的焊料层400的端部为止的最短直线长度。焊料层400的高度T可以满足T＜X的关系。本例的高度T满足T＜X≤W。即，高度T小于突出长度X，突出长度X为厚度W以下。通过使高度T小于厚度W，能够防止发射电极46与集电电极66之间的短路。
图9是说明第二实施方式中的边缘终端部300的宽度S和边缘终端部300的集电层360的宽度Y的图。在第二实施方式中，阴极层260和集电层360的形状与第一实施方式不同。其他方面可以与第一实施方式相同。
在本例中，FWD部200的阴极层260延伸至边缘终端部300。另外，本例的边缘终端部300的集电层360的宽度Y与边缘终端部300的宽度S相比小相当于阴极层260延伸出来的量。例如，集电层360的宽度Y小于边缘终端部300的宽度S的一半(即，Y＜S/2)。
应予说明，在本例中，边缘终端部300的宽度S是指正面12上的从半导体基板10的侧面16至最内侧的保护环322的内侧端部为止的最短直线长度。另外，在本例中，集电层360的宽度Y是指从半导体基板10的侧面16至集电层360与阴极层260的交界为止的最短直线长度。
在本例中，集电层360的宽度Y小于半导体基板10的厚度W(即，Y＜W)。应予说明，本例的厚度W小于边缘终端部300的宽度S的一半(即，W＜S/2)。总之，在本例中，满足Y＜W＜S/2的关系。
在从保护环322至阴极层260，存在雪崩电流流通的情况。如第一实施方式那样，在集电层360存在于从侧面16至FWD部200与边缘终端部300的交界部分的情况下，存在雪崩电流急剧偏向内侧的情况(用虚线表示该状况)。因此，由于雪崩电流集中于FWD部200与边缘终端部300的交界部分处的阴极层260，因此存在元件结构被局部破坏的可能性。与此相对地，在本例中，由于减小了集电层360的宽度Y，因此雪崩电流大致均匀地向阴极层260流入。因此，与第一实施方式相比，在本例中，能够防止元件结构的局部破坏。
图10A是示出第三实施方式中的半导体装置500的俯视图。应予说明，在图10A以后，考虑到附图的易观察性，省略发射电极外周端47和开口94。本例的FWD部200仅与IGBT部100的不同方向的二边80对置。本例在相关方面与第一实施方式不同。但是，其他方面可以与第一实施方式相同，也可以组合本例与第二实施方式。在俯视半导体装置500的情况下，本例的FWD部200仅与IGBT部100的边80a和边80d对置。在本例中，IGBT部100与FWD部200的交界区150仅成为一边。如上所述，在隔着栅流道部36的情况下，视为交界区150不存在。
图10B是示出第三实施方式的第一变形例的图。在俯视半导体装置500的情况下，本例的FWD部200仅IGBT部100的边80d和边80c对置。在本例中，IGBT部100与FWD部200的交界区150成为一边。
图10C是示出第三实施方式的第二变形例的图。在俯视半导体装置500的情况下，本例的FWD部200仅与IGBT部100的边80c和边80b对置。在本例中，IGBT部100与FWD部200的交界区150成为两边。
图10D是示出第三实施方式的第三变形例的图。在俯视半导体装置500的情况下，本例的FWD部200仅与IGBT部100的边80b和边80a对置。在本例中，IGBT部100与FWD部200的交界区150成为两边。
图11A是第四实施方式中的半导体装置500的俯视图。本例的FWD部200为将矩形环状的四边之中的一边切口而成的形状。本例在相关方面与第一实施方式不同。但是，其他方面可以与第一实施方式相同，也可以组合本例与第二实施方式。在俯视半导体装置500的情况下，本例的FWD部200仅与IGBT部100的边80a、边80c和边80d对置。在本例中，IGBT部100与FWD部200的交界区150成为两边。
图11B是示出第四实施方式的第一变形例的图。在俯视半导体装置500的情况下，本例的FWD部200仅与IGBT部100的边80b、边80c和边80d对置。在本例中，IGBT部100与FWD部200的交界区150成为两边。
图11C是示出第四实施方式的第二变形例的图。在俯视半导体装置500的情况下，本例的FWD部200仅与IGBT部100的边80a、边80b和边80c对置。在本例中，IGBT部100与FWD部200的交界区150成为三边。
图11D是示出第四实施方式的第三变形例的图。在俯视半导体装置500的情况下，本例的FWD部200仅与IGBT部100的边80a、边80b和边80d对置。在本例中，IGBT部100与FWD部200的交界区150成为两边。
图12A是第五实施方式中的半导体装置600的俯视图。本例的FWD部200为直线形状。本例在相关方面与第一实施方式不同。但是，其他方面可以与第一实施方式相同，也可以组合本例与第二实施方式。在俯视半导体装置500的情况下，本例的FWD部200仅与IGBT部100的边80a对置。在本例中，IGBT部100与FWD部200的交界区150成为一边。
图12B是示出第五实施方式的第一变形例的图。在俯视半导体装置500的情况下，本例的FWD部200仅与IGBT部100的边80d对置。在本例中，没有IGBT部100与FWD部200的交界区150。
图12C是示出第五实施方式的第二变形例的图。在俯视半导体装置500的情况下，本例的FWD部200仅与IGBT部100的边80c对置。在本例中，IGBT部100与FWD部200的交界区150成为一边。
图12D是示出第五实施方式的第三变形例的图。在俯视半导体装置500的情况下，本例的FWD部200仅与IGBT部100的边80b对置。在本例中，IGBT部100与FWD部200的交界区150成为一边。
以上，使用实施方式对本发明进行了说明，但本发明的技术范围不限于上述实施方式中记载的范围。本领域技术人员明确知晓可以对上述实施方式进行多种变更或改进。由权利要求书的记载可以明确，进行了这样的变更或改进的实施方式也包含在本发明的技术范围内。
应当注意的是，只要权利要求书、说明书和附图中示出的装置、系统、程序和方法中的动作、次序、步骤和阶段等各处理的执行顺序并未特别明示“此前”、“事先”等并且未在后续处理中使用之前处理的结果，就可以以任意的顺序来实现。对于权利要求书、说明书和附图中的动作流程，即使为方便起见而使用“首先”、“其次”等来进行了说明，也不表示必须以该顺序来实施。

Claims (13)

1.一种半导体装置，具备：
晶体管部，具有多个晶体管；
续流二极管部，在俯视所述晶体管部的情况下，所述续流二极管部至少与所述晶体管部的一边对置，并且设置于所述晶体管部的外侧；以及
栅流道部和栅衬垫部，在俯视所述晶体管部的情况下，所述栅流道部和栅衬垫部与所述晶体管部接触地设置，并且不包围所述晶体管部的整个外侧。
2.根据权利要求1所述的半导体装置，其特征在于，在俯视所述晶体管部的情况下，所述续流二极管部不设置于所述晶体管部的内侧。
3.根据权利要求1或2所述的半导体装置，其特征在于，在俯视所述晶体管部的情况下，所述续流二极管部连续地设置于所述晶体管部的外侧、所述栅流道部的外侧和所述栅衬垫部的外侧。
4.根据权利要求3所述的半导体装置，其特征在于，所述续流二极管部为对矩形环状的四边之中的一边切口而成的形状。
5.根据权利要求3所述的半导体装置，其特征在于，所述续流二极管部被设置为包围所述晶体管部的整个外侧。
6.根据权利要求1至5中任一项所述的半导体装置，其特征在于，所述半导体装置还具备边缘终端部，在俯视所述晶体管部的情况下，所述边缘终端部位于所述续流二极管部的外侧，
所述续流二极管部具有发射沟槽部，所述发射沟槽部的至少一部分与从所述边缘终端部延伸的绝缘膜重叠。
7.根据权利要求1至6中任一项所述的半导体装置，其特征在于，所述半导体装置还具备布线部，所述布线部与所述半导体装置的外部电导通，并且在俯视所述晶体管部的情况下，所述布线部设置于所述晶体管部的内侧。
8.根据权利要求1至7中任一项所述的半导体装置，其特征在于，所述半导体装置还具备：
半导体基板，设置有所述晶体管部和所述续流二极管部；以及
焊料层，与设置于所述半导体基板的背面的背面电极和所述半导体基板的侧面直接接触地设置，
所述半导体基板的厚度W与所述半导体基板的所述侧面处的所述半导体基板的背面上的所述焊料层的高度T满足W/2＜T的关系。
9.根据权利要求8所述的半导体装置，其特征在于，在俯视所述晶体管部的情况下，所述焊料层从所述半导体基板的所述侧面向外侧突出的突出长度X与所述焊料层的高度T满足T＜X的关系。
10.根据权利要求6所述的半导体装置，其特征在于，所述续流二极管部具有延伸至所述边缘终端部为止的n型阴极层。
11.根据权利要求10所述的半导体装置，其特征在于，所述边缘终端部具有p型集电层，所述p型集电层的宽度比所述边缘终端部的宽度小。
12.根据权利要求10或11所述的半导体装置，其特征在于，所述边缘终端部中的p型集电层的宽度小于设有所述晶体管部和所述续流二极管部的半导体基板的厚度。
13.根据权利要求1至12中任一项所述的半导体装置，其特征在于，所述晶体管部与所述续流二极管部的交界区的总计长度为所述半导体装置的一边的长度的3.0倍以下。
CN201710749648.2A 2016-09-15 2017-08-28 半导体装置 Active CN107833914B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016180640A JP6801324B2 (ja) 2016-09-15 2016-09-15 半導体装置
JP2016-180640 2016-09-15

Publications (2)

Publication Number Publication Date
CN107833914A true CN107833914A (zh) 2018-03-23
CN107833914B CN107833914B (zh) 2022-04-15

Family

ID=61560375

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710749648.2A Active CN107833914B (zh) 2016-09-15 2017-08-28 半导体装置

Country Status (3)

Country Link
US (1) US10128230B2 (zh)
JP (1) JP6801324B2 (zh)
CN (1) CN107833914B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110504167A (zh) * 2018-05-17 2019-11-26 上海先进半导体制造股份有限公司 绝缘栅双极型晶体管及其制造方法
CN111463270A (zh) * 2020-03-23 2020-07-28 珠海格力电器股份有限公司 一种igbt结构及其制备方法
CN113169226A (zh) * 2018-12-19 2021-07-23 三菱电机株式会社 半导体装置

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016125879B3 (de) * 2016-12-29 2018-06-21 Infineon Technologies Ag Halbleitervorrichtung mit einer IGBT-Region und einer nicht schaltbaren Diodenregion
JP6854654B2 (ja) * 2017-01-26 2021-04-07 ローム株式会社 半導体装置
JP6804379B2 (ja) * 2017-04-24 2020-12-23 三菱電機株式会社 半導体装置
CN109671773B (zh) * 2017-10-16 2020-05-05 苏州能讯高能半导体有限公司 半导体器件及其制造方法
US10361276B1 (en) * 2018-03-17 2019-07-23 Littelfuse, Inc. Embedded field plate field effect transistor
JP7106981B2 (ja) * 2018-05-18 2022-07-27 富士電機株式会社 逆導通型半導体装置
CN109192774A (zh) * 2018-09-06 2019-01-11 江苏中科君芯科技有限公司 栅极双箝位的igbt器件
CN112543993A (zh) * 2019-02-07 2021-03-23 富士电机株式会社 半导体装置
JP7192968B2 (ja) 2019-04-01 2022-12-20 三菱電機株式会社 半導体装置
JP7061983B2 (ja) * 2019-04-26 2022-05-02 三菱電機株式会社 半導体装置
JP7404702B2 (ja) 2019-08-09 2023-12-26 富士電機株式会社 半導体装置
US20220344328A1 (en) * 2019-09-27 2022-10-27 Rohm Co., Ltd. Semiconductor device
JP7319754B2 (ja) 2020-08-19 2023-08-02 株式会社東芝 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008294172A (ja) * 2007-05-24 2008-12-04 Panasonic Corp リードフレームおよび半導体装置ならびに半導体装置の製造方法
CN102822968A (zh) * 2010-04-02 2012-12-12 丰田自动车株式会社 具备具有二极管区和绝缘栅双极性晶体管区的半导体基板的半导体装置
US20150349051A1 (en) * 2014-05-28 2015-12-03 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device and manufacturing method thereof
CN105706238A (zh) * 2013-11-05 2016-06-22 丰田自动车株式会社 半导体装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1140822A (ja) 1997-07-15 1999-02-12 Nissan Motor Co Ltd 半導体装置
EP1263045A1 (en) * 2001-06-01 2002-12-04 ABB Schweiz AG High power semiconductor module
JP4403366B2 (ja) 2003-06-04 2010-01-27 富士電機デバイステクノロジー株式会社 半導体装置およびその製造方法
US20050280053A1 (en) * 2004-06-22 2005-12-22 Hayes Monty B Semiconductor device with diagonal gate signal distribution runner
JP5582102B2 (ja) * 2010-07-01 2014-09-03 株式会社デンソー 半導体装置
JP5321669B2 (ja) * 2010-11-25 2013-10-23 株式会社デンソー 半導体装置
JP5818099B2 (ja) * 2012-04-27 2015-11-18 国立研究開発法人産業技術総合研究所 半導体装置
WO2015050262A1 (ja) * 2013-10-04 2015-04-09 富士電機株式会社 半導体装置
JP5967065B2 (ja) 2013-12-17 2016-08-10 トヨタ自動車株式会社 半導体装置
CN106463541B (zh) * 2014-05-23 2019-05-21 松下知识产权经营株式会社 碳化硅半导体装置
JP6260515B2 (ja) 2014-11-13 2018-01-17 三菱電機株式会社 半導体装置
JP6597102B2 (ja) * 2015-09-16 2019-10-30 富士電機株式会社 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008294172A (ja) * 2007-05-24 2008-12-04 Panasonic Corp リードフレームおよび半導体装置ならびに半導体装置の製造方法
CN102822968A (zh) * 2010-04-02 2012-12-12 丰田自动车株式会社 具备具有二极管区和绝缘栅双极性晶体管区的半导体基板的半导体装置
CN105706238A (zh) * 2013-11-05 2016-06-22 丰田自动车株式会社 半导体装置
US20150349051A1 (en) * 2014-05-28 2015-12-03 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110504167A (zh) * 2018-05-17 2019-11-26 上海先进半导体制造股份有限公司 绝缘栅双极型晶体管及其制造方法
CN113169226A (zh) * 2018-12-19 2021-07-23 三菱电机株式会社 半导体装置
CN111463270A (zh) * 2020-03-23 2020-07-28 珠海格力电器股份有限公司 一种igbt结构及其制备方法

Also Published As

Publication number Publication date
US20180076193A1 (en) 2018-03-15
JP2018046187A (ja) 2018-03-22
US10128230B2 (en) 2018-11-13
JP6801324B2 (ja) 2020-12-16
CN107833914B (zh) 2022-04-15

Similar Documents

Publication Publication Date Title
CN107833914A (zh) 半导体装置
US11094810B2 (en) Semiconductor device and manufacturing method of semiconductor device
CN105210187B (zh) 半导体装置
CN107039419B (zh) 半导体装置
US11393812B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP3467381B2 (ja) 炭化けい素ダイオード
JP2017103400A (ja) 半導体装置
JP3338185B2 (ja) 半導体装置
CN104332495B (zh) 一种绝缘栅双极晶体管及其制造方法
US11462615B2 (en) Semiconductor device
JPWO2020149354A1 (ja) 半導体装置および半導体装置の製造方法
CN102916042A (zh) 逆导igbt器件结构及制造方法
CN106129110A (zh) 一种双通道rc‑igbt器件及其制备方法
CN110838522B (zh) 半导体装置
US11482615B2 (en) Super-junction power MOSFET device with improved ruggedness, and method of manufacturing
CN104253152A (zh) 一种igbt及其制造方法
US11094787B2 (en) Method of manufacturing semiconductor device and semiconductor device
US20080265277A1 (en) Semiconductor device and method for producing it
US20160336409A1 (en) Semiconductor Device Having an Impurity Concentration and Method of Manufacturing Thereof
CN109564939B (zh) 半导体装置
CN104253154A (zh) 一种具有内置二极管的igbt及其制造方法
CN106486475A (zh) 半导体装置
CN114388612A (zh) 半导体装置及半导体装置的制造方法
JP2008053610A (ja) 絶縁ゲート型バイポーラトランジスタ
US20230402533A1 (en) Semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant