WO2015000226A1 - 制造esd器件的方法、esd器件和显示面板 - Google Patents

制造esd器件的方法、esd器件和显示面板 Download PDF

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Publication number
WO2015000226A1
WO2015000226A1 PCT/CN2013/084186 CN2013084186W WO2015000226A1 WO 2015000226 A1 WO2015000226 A1 WO 2015000226A1 CN 2013084186 W CN2013084186 W CN 2013084186W WO 2015000226 A1 WO2015000226 A1 WO 2015000226A1
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Prior art keywords
lead
segments
esd device
disconnected
gate
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PCT/CN2013/084186
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English (en)
French (fr)
Inventor
蔡振飞
郝昭慧
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US14/368,913 priority Critical patent/US9443884B2/en
Publication of WO2015000226A1 publication Critical patent/WO2015000226A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a method of manufacturing an ESD (Electrostatic Discharge) device, an ESD device, and a display panel.
  • ESD Electrostatic Discharge
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • Electrostatic breakdown can cause abnormal pixel circuits on the array substrate in the display device. In severe cases, the pixel circuits on the array substrate are short-circuited, and the array substrate cannot work normally. Therefore, it is necessary to form an anti-static device on the array substrate and discharge static electricity to prevent electrostatic damage of the array substrate.
  • an antistatic device is formed by one or several thin film transistors TFT and leads functioning as a switch, and different leads in the antistatic device are respectively used as an input end and an output end of the static electricity, and the static electricity is output from the input terminal through the TFT to the output. End, or statically attenuate the static electricity on the lead to achieve the purpose of releasing static electricity.
  • static electricity is inevitably present. Since the ESD device is not formed at this time, it cannot function to discharge static electricity, so the electrostatic charge accumulated on the glass substrate may strike. The weaker portion of the array substrate is worn, so that the accumulated electrostatic charge will break down the antistatic device before the antistatic device is formed, resulting in damage to the antistatic device and failure to discharge static electricity.
  • the embodiments of the present disclosure provide a method for manufacturing an antistatic breakdown ESD device, an array substrate, and a display panel, which can better solve the damage of an electrostatic charge accumulated on the array substrate to an unformed ESD device, and improve the quality of the array substrate. rate.
  • a method of fabricating an antistatic breakdown ESD device comprising: In the manufacturing process of the ESD device, a thin film transistor, a first lead connected to the gate and source of the thin film transistor, and a second lead connected to the gate and drain of the thin film transistor are formed on the substrate by a patterning process
  • the first lead includes at least two broken lead segments, or the second lead includes at least two broken lead segments; and a passivation film is deposited on the substrate forming the first lead or the second lead Forming, on the passivation layer film, a via hole for connecting at least two broken lead segments of the first lead, or at least two segments for connecting the second lead to be disconnected by a patterning process a via hole of the lead segment; depositing a transparent conductive film layer on the substrate on which the via hole is formed, the transparent conductive film layer electrically connecting between the lead segments of at least two segments of the first lead through the via hole, or At least two of the disconnected lead segments of the second lead are electrically connected.
  • the first lead includes at least two broken lead segments, or the second lead includes at least two broken lead segments; forming a first lead or a second Depositing a passivation layer film on the substrate of the lead, and etching a via hole for connecting at least two broken lead segments of the first lead on the passivation layer film by a patterning process, or for connecting a via hole of at least two broken lead segments of the second lead; a transparent conductive film layer deposited on the substrate on which the via is formed, the transparent conductive film layer passing at least two segments of the first lead through the via Conducting between the disconnected lead segments or between the disconnected segments of the at least two segments of the second lead.
  • an ESD device fabricated by the above method, comprising a thin film transistor TFT formed on a substrate, wherein: a source and a gate of the TFT are connected to a first lead, a gate of the TFT a pole and a drain connected to the second lead, the first lead comprising at least two broken lead segments, or the second lead comprising at least two broken lead segments; wherein the at least two segments are disconnected
  • the lead segments are electrically connected by a transparent conductive film layer.
  • a display panel including the above-described ESD device.
  • a thin film transistor, a first lead connected to the gate and the source of the thin film transistor, and a gate connected to the gate and the drain of the thin film transistor are sequentially formed on the substrate by a patterning process.
  • the first lead includes at least two broken lead segments, or the second lead includes at least two broken lead segments; on the substrate forming the first lead or the second lead, deposition passivation a via film on the passivation layer film, through a patterning process, a via for connecting at least two broken lead segments of the first lead, or at least two segments for connecting the second lead a via hole of the opened lead segment; depositing a transparent conductive on the substrate on which the via is formed a film layer, the transparent conductive film layer is electrically connected between the lead segments of the first lead that are disconnected by at least two segments, or between the lead segments that disconnect at least two of the second leads Turn on. In this way,
  • the static electricity accumulated on the TFT substrate will not damage the unformed ESD device, and when the transparent conductive film layer is deposited through the via hole, the lead segment is turned on, and the ESD device can exert its function of releasing static electricity.
  • the transparent conductive film layer in the pixel electrode is formed at the same time as the transparent conductive film layer in the present disclosure during the fabrication of the TFT substrate, so that the electrostatic charges accumulated on the array substrate are not contacted before the transparent conductive film is formed.
  • the ESD device can exert the function of releasing static electricity, so that the electrostatic charge accumulated on the array substrate can be better solved for the destruction of the unformed ESD device, and the yield of the array substrate is improved.
  • FIG. 1 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view showing an array substrate formed by a patterning process according to an embodiment of the present disclosure
  • FIG. 3 is a top plan view of the formed antistatic device proposed in the embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of an ESD device according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram showing the structure of a first lead structure in an ESD device according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural view of forming a TFT structure according to an embodiment of the present disclosure.
  • the electrostatic charge accumulated on the glass substrate will break through the weaker portion of the array substrate, so the accumulated electrostatic charge will break down the antistatic device before the antistatic device is formed, resulting in prevention
  • the electrostatic device is damaged and cannot function to discharge static electricity.
  • the lead of the ESD device is disconnected before the ESD device is formed, and finally, after deposition of the passivation layer film, deposition is performed.
  • the transparent conductive film layer electrically connects the broken leads.
  • the static electricity accumulated on the TFT substrate does not damage the unformed ESD device, and when the transparent conductive film layer is formed, the ESD device can exert its function of releasing static electricity, and the ESD device is guided.
  • the transparent conductive film layer of the lead wire segment is formed at the same time as the transparent conductive film layer required for fabricating the array substrate, so that damage of the EDS device by electrostatic charge can be avoided in time, and the yield of the array substrate can be improved.
  • the embodiment of the present disclosure provides a method for manufacturing an array substrate. As shown in FIG. 1, the specific processing flow is as follows:
  • Step 11 in the manufacturing process of the ESD device, forming a thin film transistor on the substrate, a first lead connected to the gate and the source of the thin film transistor, and a second lead connected to the gate and the drain of the thin film transistor by a patterning process,
  • the first lead includes at least two broken lead segments, or the second lead includes at least two broken lead segments.
  • a gate of a thin film transistor, a gate insulating layer, an active layer, a source and a drain, and a gate and a source are sequentially formed.
  • a lead, and a second lead connected to the gate and the drain.
  • the leads may be connected to the gate and the source when forming the leads.
  • the leads can also be connected to the gate and drain.
  • the lead wire connected to the gate and the source is referred to as a first lead
  • the lead connected to the gate and the drain is referred to as a second lead in the embodiment of the present disclosure.
  • the broken lead segments may be formed by etching to form the completed first or second leads after etching to form a complete first or second lead.
  • the broken lead segments can be on the same horizontal line or offset by a certain angle.
  • the width of the formed lead segments may be the same or different.
  • the formed lead segments are on the same horizontal line, and the formed lead segments have the same width.
  • the formed first lead including at least two lead segments may be formed simultaneously with the gate, or the formed first lead including at least two lead segments may be formed simultaneously with the source.
  • the formed second lead including at least two lead segments may be formed simultaneously with the gate, or the formed second lead including at least two lead segments may be formed simultaneously with the drain.
  • the first method is as follows:
  • the specific forming process is as follows: As shown in FIG. 2, a gate metal film is deposited on the substrate 600 to form a gate metal layer 601. A first lead and a gate are formed by a patterning process, wherein the first lead is connected to the gate.
  • the formed first lead includes at least two broken lead segments.
  • the broken lead segment can be a direct formation formed during the mask process.
  • the line segment may also be after the formation of the complete first lead, the first lead is broken by an etching process to form a first lead including at least two lead segments.
  • a gate insulating layer (not shown in FIG.
  • an active layer 602 and a source/drain metal layer 603 are sequentially formed by a patterning process.
  • a via hole is formed by a patterning process, and a source and a gate are connected through the formed via hole.
  • the specific implementation principle is the same as that for the first lead formed simultaneously with the gate, as shown in FIG. 2, specifically: depositing a gate metal film on the substrate 600 , a gate metal layer 601 is formed.
  • a second lead and a gate are formed by a patterning process, wherein the second lead is connected to the gate, and the formed second lead includes at least two broken lead segments.
  • the broken lead segment may be a lead segment formed directly during the mask process, or after the complete second lead is formed, the second lead may be broken by an etching process to form a lead including at least two lead segments.
  • the second lead On the substrate on which the gate metal layer 601 is formed, a gate insulating layer (not shown in Fig.
  • an active layer 602 and a source/drain metal layer 603 are sequentially formed by a patterning process.
  • a source/drain metal layer 603 is sequentially formed by a patterning process.
  • via holes are formed by a patterning process, and the drain and the gate are connected through the formed via holes.
  • the distance between the two lead segments included in the first lead or the second lead may be 15-30 microns.
  • the distance between the two lead segments can be 20 microns.
  • the second method for the first lead formed at the same time as the source, the specific forming process is as follows: As shown in FIG. 2, a gate metal film is deposited on the substrate 600 to form a gate metal layer 601. After the gate metal layer 601 is formed, a gate electrode is formed by an etching process. On the substrate on which the gate metal layer 601 is formed, a gate insulating layer (not shown in Fig. 2), an active layer 602, and a metal layer 603 are sequentially formed by a patterning process. A via is formed by a patterning process, and a source and a gate are connected through the formed via. On the formed source/drain metal layer 603, a first lead connected to the source is simultaneously formed in the process of forming the source and the drain.
  • the formed first lead includes at least two broken lead segments.
  • the broken lead segment may be a lead segment formed directly during the mask process, or after the complete first lead is formed, the first lead is disconnected by an etching process to form a lead including at least two lead segments. The first lead.
  • the specific implementation principle is the same as the first lead formed simultaneously with the source, specifically: for the second lead formed simultaneously with the drain, the specific forming process is As shown in FIG. 2, a gate metal film is deposited on the substrate 600 to form a gate metal layer 601. A gate electrode is formed on the gate metal layer 601 by an etching process. On the substrate on which the gate metal layer 601 is formed, a gate insulating layer (not shown in FIG. 2), an active layer 602, and a source/drain metal layer 603 are sequentially formed by a patterning process.
  • a via is formed by a patterning process, and the drain and the gate are connected through the formed via.
  • a second lead connected to the drain is simultaneously formed in the process of forming the source and the drain.
  • the second lead formed includes at least two broken lead segments.
  • the broken lead segment may be a lead segment formed directly during the mask process, or after the complete second lead is formed, the second lead may be broken by an etching process to form a lead including at least two lead segments. The second lead.
  • the distance between the two lead segments included in the first lead or the second lead may be 15-30 microns.
  • the distance between the two lead segments can be 20 microns.
  • Step 12 depositing a passivation layer film on the substrate on which the first lead or the second lead is formed, and forming a via hole for connecting the lead segments on the passivation layer film by a patterning process.
  • Step 13 depositing a transparent conductive film layer on the substrate on which the via hole is formed, and the transparent conductive film layer is electrically connected between the line segments of at least two segments of the first lead through the via hole, or the second portion At least two segments of the lead are disconnected between the lead segments.
  • the material of the transparent conductive film layer is the same as the material of the pixel electrode layer formed when the array substrate is formed.
  • FIG. 3 A top view of the formed antistatic device of the array substrate comprising the antistatic device produced by the above process is shown in Fig. 3.
  • the first antistatic device fabricated by the above process, as shown in Fig. 4, includes a region of the pixel array 102 formed on the substrate 101, and at least one row of the antistatic device 103 located in the peripheral region of the pixel array.
  • the antistatic device 103 includes at least one TFT 201.
  • a bidirectional TFT is taken as an example for detailed explanation.
  • the source 2011 and the gate 2013 of the TFT 201 are connected to the first lead 202.
  • the first lead 202 is composed of two lead segments 301, and the lead segments 301 are electrically connected by a conductive film layer 302.
  • the metal film layer forming the first wiring 202 is a gate metal layer or a source/drain metal layer.
  • a first lead 202 connected to the source 2011 and the gate 2013 of the TFT 201, and a second lead 203 connected to the gate 2013 and the drain 2012 of the TFT 201 are part of an ESD device, an array
  • the electrostatic charge accumulated on the substrate is introduced through the first lead. If the current is large, the TFT 201 in the ESD device is turned on, the TFT 201 operates, and the electrostatic charge is discharged, thereby functioning as an antistatic. If it is the normal working voltage of the TFT, the ESD device cannot be operated. Thus, the ESD device does not affect the normal display of the TFT substrate.
  • the first lead 202 is composed of two lead segments. In the fabrication of an ESD device, since the first lead 202 is composed of two broken lead segments, the electrostatic charge generated during the fabrication of the array substrate does not cause damage to the ESD device that has not been formed before the ESD device is formed.
  • the first lead is taken as an example for detailed explanation.
  • the first lead 202 is comprised of two lengths of lead segments, a lead segment 3011 and a lead segment 3012, respectively, which are not in communication between the lead segment 3011 and the lead segment 3012 prior to formation of the ESD device.
  • the electrostatic charge is concentrated more, it flows into the lead segment 3011 in the first lead 202.
  • the lead segment 3011 and the lead segment 3012 are not in communication, the electrostatic charge cannot flow into the TFT 201, so that the unformed ESD device is not damaged, and the electrostatic charge is conducted in the lead segment 3011. Therefore, the resistance of the lead segment 3011 can also consume all or part of the electrostatic charge.
  • the TFT 201 includes a protective layer 401 covering the TFT 201.
  • the conductive film layer 302 is disposed on the protective layer 401, and the lead segments 3011 and the lead segments 3012 in FIG. 3 are electrically connected through the vias 402. sexual connection. Thereby, the lead segments 3011 and the lead segments 3012 are turned on to form the final ESD device.
  • the distance between the lead segment 3011 and the lead segment 3012 is 15-30 microns.
  • the distance between lead segment 3011 and lead segment 3012 can be 20 microns.
  • the antistatic device includes a plurality of TFTs 201, and the TFTs 201 may be connected to each other in series; or the TFTs 201 are connected in parallel with each other.
  • the electrostatic charge may accumulate in the pixel array region or the common electrode region, and the ESD device on the array substrate cannot be used until the pixel electrode is completed. It acts to discharge static electricity, and on the array substrate, when the ESD device is set, the structure of the ESD itself is relatively compact, so that the electrostatic charge accumulated on the array substrate is broken down before the ESD device is formed, and the device is broken down by the static electricity. Can not play the role of releasing static electricity, thus failing.
  • the pixel array region The static electricity generated by the domain or the common electrode Vcom region will not be released, and the unreleased static electricity will break down the pixel.
  • the ESD device can be better prevented from failing before formation.
  • the second array substrate comprising the antistatic device produced by the above process, as shown in FIG. 4, includes at least one row of antistatic devices 103 located in the peripheral region of the pixel array in the pixel array 102 region formed on the substrate 101.
  • the antistatic device 103 includes at least one TFT 201.
  • the bidirectional TFT is still taken as an example for detailed explanation. Specifically, as shown in FIG. 5, the gate 2013 and the drain 2012 of the TFT 201 are connected to the second lead 203.
  • the second lead 203 is composed of two lead segments 301, and the lead segments 301 are electrically connected through the conductive film layer 302.
  • the metal film layer forming the second wiring 203 is a gate metal layer or a source/drain metal layer.
  • the second lead 203 connected to the gate electrode 2013 and the drain 2012 of the TFT 201 is a part of the ESD device, and the electrostatic charge accumulated on the array substrate is introduced through the first lead or the second lead, if
  • the TFT 201 in the ESD device is turned on, the TFT 201 operates, and the electrostatic charge is derived, thereby functioning as an antistatic.
  • the electrostatic charge is consumed in the first lead and the second lead, so that it can also function as an antistatic.
  • the ESD device before the formation of the ESD device, a large amount of electrostatic charge is accumulated on the array substrate. At this time, since the ESD device is not completely formed, it cannot function as an electrostatic discharge, and more electrostatic charges may cause the formation of an electrostatic charge. ESD device breakdown.
  • at least one of the second leads 203 is composed of two lead segments. In the fabrication of the ESD device, since the second lead 203 is composed of two broken lead segments, the electrostatic charge generated during the fabrication of the array substrate does not cause damage to the ESD device that has not been formed before the ESD device is formed.
  • the distance between the lead segments and the lead segments is 15-30 microns.
  • the distance between the lead segments and the lead segments can be 20 microns.
  • the antistatic device includes a plurality of TFTs 201.
  • a bidirectional TFT is taken as an example for detailed description.
  • Each of the TFTs 201 is connected in series to each other, or each of the TFTs 201 is connected in parallel with each other.
  • embodiments of the present disclosure also provide a display panel including the above-described ESD device.
  • the static electricity accumulated on the TFT substrate does not damage the unformed ESD device before the formation of the ESD device, and after the transparent conductive film layer is formed
  • the ESD device can also exert its function of releasing static electricity, and the transparent conductive film layer of the pixel electrode is formed at the same time as the transparent conductive film layer in the present disclosure during the fabrication of the TFT substrate, so that the array substrate is formed before the transparent conductive film is formed.
  • the electrostatic charge accumulated on the upper surface does not contact the ESD device, and the ESD device can play the role of releasing static electricity after the transparent conductive film is formed, so that the electrostatic charge accumulated on the array substrate can be better solved for the destruction of the unformed ESD device. Improve the yield of the array substrate.

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Abstract

公开了一种制造ESD器件的方法、ESD器件和显示面板，能够较好地解决阵列基板上积聚的静电电荷对未形成的ESD器件的破坏，提高阵列基板的良品率。该方法包括在ESD器件的制造过程中，通过构图工艺在基板上形成薄膜晶体管、与所述薄膜晶体管栅极和源极连接的第一引线、以及与所述栅极和漏极连接的第二引线，所述第一引线包括至少两段断开的引线段，或者所述第二引线包括至少两段断开的引线段；在形成第一引线或第二引线的基板上，沉积钝化层薄膜，通过构图工艺在所述钝化层薄膜上形成用于连接所述第一引线的引线段的过孔、或用于连接所述第二引线的引线段的过孔；在形成过孔的基板上沉积透明导电膜层，所述透明导电膜层通过过孔将所述引线段之间导通。

Description

制造 ESD器件的方法、 ESD器件和显示面板 技术领域
本公开涉及显示技术领域，特别是涉及一种制造防静电击穿 ESD ( ESD, Electro Static Discharge ) 器件的方法、 ESD器件和显示面板。 背景技术
在平板显示装置中， 薄膜晶体管液晶显示器 （TFT-LCD , Thin Film Transistor Liquid Crystal Display )具有体积小、 功耗氐、 制造成本相对较低和 无辐射等特点， 在当前的平板显示器市场占据了主导地位。 有机发光二极管 ( OLED, Organic Light-Emitting Diode ) , 其显示技术与传统的 LCD显示方 式不同， 无需背光灯， 而采用非常薄的有机材料涂层和玻璃基板， 当有电流 流过时， 这些有机材料就会发光， 因此具备轻薄、 省电等特性。
在所述平板显示装置的制作过程中， 静电击穿现象经常发生。 静电击穿 会导致显示装置中的阵列基板上的像素电路异常， 严重时会导致阵列基板上 的像素电路短路， 阵列基板无法正常工作。 因此需要在阵列基板上形成防静 电器件以及时释放静电， 防止阵列基板发生静电损伤。
一般地，通过一个或者若干个起开关作用的薄膜晶体管 TFT和引线组成 防静电器件， 防静电器件中的不同引线分别作为静电的输入端和输出端， 通 过将静电从输入端经过 TFT导出到输出端、 或者使静电在引线上逐渐衰减， 达到释放静电的目的。 但是在制作防静电器件的 TFT和引线的过程中， 不可 避免地存在静电， 由于此时 ESD器件还未形成， 因此不能够起到释放静电的 作用， 因此玻璃基板上积聚的静电电荷可能会击穿阵列基板中较薄弱的部分， 因此积聚的静电电荷会在防静电器件形成之前将该防静电器件击穿， 导致防 静电器件损伤， 不能够起到释放静电的作用。 发明内容
本公开实施例提供了一种制造防静电击穿 ESD器件的方法、阵列基板和 显示面板， 能够较好地解决阵列基板上积聚的静电电荷对未形成的 ESD器件 的破坏， 提高阵列基板的良品率。
根据本公开实施例，提供了一种制造防静电击穿 ESD器件的方法，包括： 在 ESD器件的制造过程中， 通过构图工艺在基板上形成薄膜晶体管、 与所述 薄膜晶体管栅极和源极连接的第一引线、 以及与所述薄膜晶体管栅极和漏极 连接的第二引线， 所述第一引线包括至少两段断开的引线段， 或者所述第二 引线包括至少两段断开的引线段； 在形成第一引线或第二引线的基板上， 沉 积钝化层薄膜， 通过构图工艺在所述钝化层薄膜上形成用于连接所述第一引 线的至少两段断开的引线段的过孔、 或用于连接所述第二引线的至少两段断 开的引线段的过孔； 在形成过孔的基板上沉积透明导电膜层， 所述透明导电 膜层通过过孔将所述第一引线的至少两段断开的引线段之间导通、 或将所述 第二引线的至少两段断开的引线段之间导通。
作为示例， 在 ESD器件的制造过程中， 通过构图工艺在基板上依次形成 栅极、 有源层， 源极和漏极， 与所述栅极和源极连接的第一引线， 以及与所 述栅极和漏极连接的第二引线， 所述第一引线包括至少两段断开的引线段， 或者所述第二引线包括至少两段断开的引线段； 在形成第一引线或第二引线 的基板上， 沉积钝化层薄膜， 通过构图工艺在所述钝化层薄膜上刻蚀出用于 连接所述第一引线的至少两段断开的引线段的过孔、 或用于连接所述第二引 线的至少两段断开的引线段的过孔；在形成过孔的基板上沉积透明导电膜层， 所述透明导电膜层通过过孔将所述第一引线的至少两段断开的引线段之间导 通、 或将所述第二引线的所述至少两段断开的 ^ I线段之间导通。
根据本公开实施例， 提供了一种通过上述方法制作的 ESD器件， 包括形 成在基板上的薄膜晶体管 TFT, 其中： 所述 TFT的源极和栅极与第一引线相 连， 所述 TFT的栅极和漏极与第二引线相连， 所述第一引线包含至少两段断 开的引线段， 或所述第二引线包含至少两段断开的引线段； 其中所述至少两 段断开的引线段之间通过透明导电膜层电性相连。
根据本公开实施例， 提供了一种显示面板， 包括上述的 ESD器件。
采用上述技术方案， 在 ESD器件的制造过程中， 通过构图工艺在基板上 依次形成薄膜晶体管， 与薄膜晶体管栅极和源极连接的第一引线， 以及与薄 膜晶体管栅极和漏极连接的第二引线， 所述第一引线包括至少两段断开的引 线段， 或者所述第二引线包括至少两段断开的引线段； 在形成第一引线或第 二引线的基板上， 沉积钝化层薄膜， 通过构图工艺在所述钝化层薄膜上形成 用于连接所述第一引线的至少两段断开的引线段的过孔、 或用于连接所述第 二引线的至少两段断开的引线段的过孔； 在形成过孔的基板上沉积透明导电 膜层， 所述透明导电膜层通过过孔将所述第一引线的至少两段断开的引线段 之间导通、 或将所述第二引线的至少两段断开的引线段之间导通。 这样， 在
ESD器件形成之前， TFT基板上积聚的静电就不会损伤到未成形的 ESD器件， 而当透明导电膜层通过过孔沉积之后， 将引线段导通， ESD器件又可以发挥 其释放静电的作用， 并且在 TFT基板的制作过程中像素电极中的透明导电膜 层与本公开中的透明导电膜层在同一时间形成，这样在透明导电膜形成之前， 阵列基板上聚集的静电电荷都不会接触到 ESD器件， 而透明导电膜形成后 ESD器件已经可以发挥释放静电的作用， 从而能够较好地解决阵列基板上积 聚的静电电荷对未形成的 ESD器件的破坏， 提高阵列基板的良品率。 附图说明
图 1为本公开实施例中提出的制造阵列基板的方法流程图；
图 2为本公开实施例中提出的通过构图工艺形成阵列基板的剖面示意 图；
图 3为本公开实施例中提出的形成的防静电器件的俯视图；
图 4为本公开实施例中提出的阵列基板结构组成示意图；
图 5为本公开实施例中提出的 ESD器件结构组成示意图；
图 6为本公开实施例中提出的 ESD器件中第一引线结构组成示意图； 图 7为本公开实施例中提出的形成 TFT结构组成示意图。 具体实施方式
针对现有技术中存在的以下问题： 玻璃基板上积聚的静电电荷会击穿阵 列基板中较薄弱的部分， 因此积聚的静电电荷会在防静电器件形成之前将该 防静电器件击穿， 导致防静电器件损伤， 不能够起到释放静电的作用， 本公 开实施例这里提出的技术方案中， 在未形成 ESD器件之前， 将 ESD器件的 引线断开， 最后在沉积钝化层薄膜之后， 通过沉积的透明导电膜层将断开的 引线电性相连。 这样， 在 ESD器件形成之前， TFT基板上积聚的静电就不会 损伤到未成形的 ESD器件， 而当透明导电膜层形成之后， ESD器件又可以发 挥其释放静电的作用， 并且 ESD器件中导通引线段的透明导电膜层与制作阵 列基板时需要的透明导电膜层在同时形成， 这样在时间上可以避免静电电荷 对 EDS器件的损伤， 提高阵列基板的良品率。 下面将结合各个附图对本公开实施例技术方案的主要实现原理、 具体实 施方式及其对应能够达到的有益效果进行详细地阐述。
本公开实施例提出一种制造阵列基板的方法， 如图 1所示， 其具体处理 流程如下述：
步骤 11 , 在 ESD器件的制造过程中， 通过构图工艺在基板上形成薄膜 晶体管， 与薄膜晶体管栅极和源极连接的第一引线， 以及与薄膜晶体管栅极 和漏极连接的第二引线， 所述第一引线包括至少两段断开的引线段， 或者所 述第二引线包括至少两段断开的引线段。
在 ESD器件的制造过程中， 通过构图工艺在基板上形成薄膜晶体管时， 依次形成薄膜晶体管的栅极、 栅绝缘层、 有源层、 源极和漏极， 与栅极和源 极连接的第一引线， 以及与栅极和漏极连接的第二引线。
其中， 在 ESD器件的制造过程中， 在形成引线时， 引线可以与栅极和源 极连接。 引线还可以与栅极和漏极连接。 为便于阐述， 本公开实施例中将与 栅极和源极连接的引线称之为第一引线， 将与栅极和漏极连接的引线称之为 第二引线。
在制造 ESD器件的过程中，断开的引线段可以是在形成完整的第一引线 或第二引线后， 通过刻蚀， 将形成的完整的第一引线或第二引线断开。 可替 代地， 还可以是在形成第一引线或第二引线的时候， 直接形成至少两段断开 的引线段。 断开的引线段可以在同一水平线上， 也可以错开一定的角度。 形 成的引线段的宽度可以相同也可以不相同。
较佳地， 本公开实施例这里提出的技术方案中， 形成的引线段在同一水 平线上， 并且形成的引线段的宽度相同。
在形成第一引线的时候， 形成的包含至少两段引线段的第一引线可以和 栅极同时形成， 或形成的包含至少两段引线段的第一引线可以和源极同时形 成。 同样地， 对于第二引线来说， 形成的包含至少两段引线段的第二引线可 以和栅极同时形成， 或形成的包含至少两段引线段的第二引线可以和漏极同 时形成。 下面就第一引线或第二引线的不同设置方法来分别进行详细阐述。
第一种方式： 对于和栅极同时形成的第一引线， 其具体形成过程为： 如 图 2所示， 在基板 600上沉积一层栅金属薄膜， 形成栅金属层 601。 通过构 图工艺形成第一引线和栅极， 其中第一引线和栅极相连。 形成的第一引线包 含至少两个断开的引线段。 断开的引线段可以是在掩膜过程中直接形成的引 线段， 也可以是在形成完整的第一引线之后， 采用刻蚀工艺将第一引线断开， 从而形成包含至少两个引线段的第一引线。 在形成栅金属层 601的基板上， 通过构图工艺依次形成栅绝缘层（图 2中未示出）、有源层 602以及源漏金属 层 603。 在形成的源漏金属层 603上， 通过构图工艺形成过孔， 并通过形成 的过孔， 将源极和栅极连接。
同样地， 对于和栅极同时形成的第二引线， 其具体实施原理和对于和栅 极同时形成的第一引线相同， 如图 2所示， 具体为： 在基板 600上沉积一层 栅金属薄膜， 形成栅金属层 601。 通过构图工艺形成第二引线和栅极， 其中 第二引线和栅极相连， 形成的第二引线包含至少两个断开的引线段。 断开的 引线段可以是在掩膜过程中直接形成的引线段， 也可以是在形成完整的第二 引线之后， 采用刻蚀工艺将第二引线断开， 从而形成包含至少两个引线段的 第二引线。 在形成栅金属层 601的基板上， 通过构图工艺依次形成栅绝缘层 (图 2中未示出）、有源层 602以及源漏金属层 603。在形成的源漏金属层 603 上， 通过构图工艺形成过孔， 并通过形成的过孔， 将漏极和栅极连接。
具体地，第一引线或第二引线包含的两段引线段之间的距离可以为 15-30 微米。 较佳地， 两段引线段之间的距离可以为 20微米。
第二种方式： 对于与源极同时形成的第一引线， 其具体形成过程为： 如 图 2所示， 在基板 600上沉积一层栅金属薄膜， 形成栅金属层 601。 在形成 栅金属层 601之后， 通过刻蚀工艺形成栅极。 在形成栅金属层 601的基板上， 通过构图工艺依次形成栅绝缘层（图 2中未示出）、 有源层 602以及金属层 603。 通过构图工艺形成过孔， 并通过形成的过孔， 将源极和栅极连接。 在形 成的源漏金属层 603上， 在形成源极和漏极的过程中， 同时形成和源极连接 的第一引线。 形成的第一引线包含至少两个断开的引线段。 断开的引线段可 以是在掩膜过程中直接形成的引线段，也可以是在形成完整的第一引线之后， 采用刻蚀工艺将第一引线断开， 从而形成包含至少两个引线段的第一引线。
同样地， 对于与漏极同时形成的第二引线， 其具体实施原理和对于与源 极同时形成的第一引线相同， 具体为： 对于与漏极同时形成的第二引线， 其 具体形成过程为： 如图 2所示， 在基板 600上沉积一层栅金属薄膜， 形成栅 金属层 601。 通过刻蚀工艺， 在栅金属层 601上形成栅极。 在形成栅金属层 601的基板上，通过构图工艺依次形成栅绝缘层（图 2中未示出）、有源层 602 以及源漏金属层 603。 通过构图工艺在源漏金属层 603上形成源极和漏极， 通过构图工艺形成过孔， 并通过形成的过孔， 将漏极和栅极连接。 在形成的 源漏金属层 603上， 在形成源极和漏极的过程中， 同时形成和漏极连接的第 二引线。 形成的第二引线包含至少两个断开的引线段。 断开的引线段可以是 在掩膜过程中直接形成的引线段， 也可以是在形成完整的第二引线之后， 采 用刻蚀工艺将第二引线断开， 从而形成包含至少两个引线段的第二引线。
具体地，第一引线或第二引线包含的两段引线段之间的距离可以为 15-30 微米。 较佳地， 两段引线段之间的距离可以为 20微米。
步骤 12, 在形成第一引线或第二引线的基板上， 沉积钝化层薄膜， 通过 构图工艺在所述钝化层薄膜上形成用于连接引线段的过孔。
步骤 13, 在形成过孔的基板上沉积透明导电膜层， 透明导电膜层通过过 孔将所述第一引线的至少两段断开的 ^ )线段之间导通、 或将所述第二引线的 至少两段断开的引线段之间导通。
具体地， 透明导电膜层的材质和制造阵列基时形成的像素电极层的材质 相同。 在形成过孔的基板上沉积与像素电极材质相同的 ITO层薄膜 605, 沉 积的 ITO薄膜 605通过过孔 606将断开的引线段导通， 形成完整的第一引线 或第二引线， 第一引线或第二引线恢复导电功能。
由上述过程制作的包含防静电器件的阵列基板， 形成的防静电器件的俯 视图如图 3所示。
由上述过程制作的第一种防静电器件，如图 4所示，包括形成在基板 101 上的像素阵列 102区域， 位于像素阵列外围区域的至少一行防静电器件 103。 防静电器件 103包括至少一个 TFT 201。 这里以双向 TFT为例来进行详细阐 述。
具体如图 5所示， TFT 201的源极 2011和栅极 2013与第一引线 202相 连。 其中， 第一引线 202由两段引线段 301组成， 引线段 301之间通过导电 膜层 302电性相连。 具体地， 形成第一引线 202的金属膜层是栅金属层或源 漏金属层。
如图 5所示， 与 TFT 201的源极 2011和栅极 2013连接的第一引线 202, 与 TFT 201的栅极 2013和漏极 2012连接的第二引线 203, 是组成 ESD器件 的一部分， 阵列基板上积聚的静电电荷， 通过第一引线导入， 如果电流较大 的情况下， 会使 ESD器件中 TFT 201打开， TFT 201工作， 静电电荷会导出， 从而起到防静电的作用。如果是 TFT的正常工作电压，不能使 ESD器件工作， 这样 ESD器件就不会影响 TFT基板的正常显示。
但是， 在 ESD器件形成之前， 阵列基板上也会聚集较多的静电电荷， 此 时由于 ESD器件未完全形成， 所以不能够起到静电释放的作用， 较多的静电 电荷， 会使得尚未形成的 ESD器件击穿。 本公开实施例提出的技术方案中， 第一引线 202由两段引线段组成。 在制作 ESD器件时， 由于第一引线 202是 由两段断开的引线段组成的， 因此在 ESD器件形成之前， 阵列基板制造过程 中产生的静电电荷不会对尚未形成的 ESD器件造成损伤。 下面以第一引线为 例来进行详细阐述。
如图 6所示， 第一引线 202由两段引线段组成， 分别是引线段 3011和引 线段 3012,在 ESD器件形成之前， 引线段 3011和引线段 3012之间是不连通 的。 在 ESD器件形成之前， 当阵列基板上聚集较多的静电电荷时， 假设在图 6中所示的 A区域， 静电电荷聚集的较多时， 会流入第一引线 202中的引线 段 3011中， 此时引线段 3011和引线段 3012之间是不连通的， 因此静电电荷 不能够流入到 TFT 201中， 因此不会对未形成的 ESD器件造成损伤， 并且静 电电荷是在引线段 3011中进行传导， 因此引线段 3011的电阻也可以将静电 电荷全部或部分消耗掉。
较佳地， 如图 7所示， TFT 201包括覆盖该 TFT 201的保护层 401 , 导电 膜层 302位于保护层 401之上，通过过孔 402将图 3中的引线段 3011和引线 段 3012电性相连。 从而实现将引线段 3011和引线段 3012导通， 形成最终的 ESD器件。
具体地， 引线段 3011和引线段 3012之间的距离为 15-30微米。
一种较佳地实现方式， 引线段 3011和引线段 3012之间的距离可以为 20 微米。
本公开实施例提出的防静电器件中，所述防静电器件包括多个 TFT 201 , 各 TFT 201之间可以相互串联连接； 或各 TFT201之间相互并联连接。
在阵列基板的制造过程中， 由于像素阵列区域或者公共电极区域经常接 触静电来源， 静电电荷会在像素阵列区域或公共电极区域积聚， 在像素电极 未完成前， 阵列基板上的 ESD器件还不能够起到释放静电的作用， 并且在阵 列基板上， ESD器件设置时， ESD自身的结构又比较紧凑， 因此会在 ESD器 件形成之前被阵列基板上积聚的静电电荷击穿， 被静电击穿的器件不能起到 释放静电的作用， 从而失效。 在后续的制造阵列基板的过程中， 像素阵列区 域或者公共电极 Vcom区域产生的静电将不能得到释放， 则未被释放的静电 会击穿像素， 采用本公开实施提出的技术方案， 可以较好地避免 ESD器件在 形成之前失效。
由上述过程制作的第二种包含防静电器件的阵列基板， 如图 4所示， 包 括形成在基板 101上的像素阵列 102区域， 位于像素阵列外围区域的至少一 行防静电器件 103。 防静电器件 103包括至少一个 TFT 201。 仍然以双向 TFT 为例来进行详细阐述。 具体如图 5所示， TFT 201的栅极 2013和漏极 2012 与第二引线 203相连。 其中， 第二引线 203中由两段引线段 301组成， 引线 段 301之间通过导电膜层 302电性相连。 具体地， 形成第二引线 203的金属 膜层是栅金属层或源漏金属层。
如图 5所示， 与 TFT 201的栅极 2013和漏极 2012连接的第二引线 203, 是组成 ESD器件的一部分， 阵列基板上积聚的静电电荷， 通过第一引线或第 二引线导入，如果静电比较强的情况下，会使 ESD器件中 TFT 201打开， TFT 201工作， 静电电荷会导出， 从而起到防静电的作用。 如果是静电比较弱的 情况下， 静电电荷会在第一引线和第二引线中消耗， 从而也能够起到防静电 的作用。
但是， 在 ESD器件形成之前， 阵列基板上也会聚集较多的静电电荷， 此 时由于 ESD器件未完全形成， 所以不能够起到静电释放的作用， 较多的静电 电荷， 会使得尚未形成的 ESD器件击穿。 本公开实施例这里提出的技术方案 中，第二引线 203中的至少一条引线由两段引线段组成。在制作 ESD器件时， 由于第二引线 203是由两段断开的引线段组成的，因此在 ESD器件形成之前， 阵列基板制造过程中产生的静电电荷不会对尚未形成的 ESD器件造成损伤。
具体地， 引线段和引线段之间的距离为 15-30微米。
一种较佳地实现方式， 引线段和引线段之间的距离可以为 20微米。
本公开实施例这里提出的阵列基板中， 防静电器件中包括多个 TFT 201 , 本公开实施例一这里提出的技术方案中， 是以双向 TFT为例来进行详细阐述 的。 各 TFT 201之间相互串联连接， 或各 TFT201之间相互并联连接。
相应地， 本公开实施例这里还提出一种显示面板， 包含上述提出的 ESD 器件。
本公开实施例上述提出的技术方案中， 在 ESD器件形成之前， TFT基板 上积聚的静电就不会损伤到未成形的 ESD器件，而当透明导电膜层形成之后， ESD器件又可以发挥其释放静电的作用， 并且在 TFT基板的制作过程中像素 电极的透明导电膜层与本公开中的透明导电膜层在同一时间形成， 这样在透 明导电膜形成之前， 阵列基板上聚集的静电电荷都不会接触到 ESD器件， 而 透明导电膜形成后 ESD器件已经可以发挥释放静电的作用，从而能够较好地 解决阵列基板上积聚的静电电荷对未形成的 ESD器件的破坏，提高阵列基板 的良品率。
尽管已描述了本公开的优选实施例， 但本领域内的技术人员一旦得知了 基本创造性概念， 则可对这些实施例作出另外的变更和修改。 所以， 所附权 利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。 公开的精神和范围。 这样， 倘若本公开的这些修改和变型属于本公开权利要 求及其等同技术的范围之内， 则本公开也意图包含这些改动和变型在内。

Claims

权 利 要 求 书
1、 一种制造防静电击穿 ESD器件的方法， 包括：
在 ESD器件的制造过程中， 通过构图工艺在基板上形成薄膜晶体管、 与 所述薄膜晶体管栅极和源极连接的第一引线、 以及与所述薄膜晶体管栅极和 漏极连接的第二引线， 其中， 所述第一引线包括至少两段断开的引线段； 或 所述第二引线包括至少两段断开的引线段；
在形成第一引线或第二引线的基板上， 沉积钝化层薄膜， 通过构图工艺 在所述钝化层薄膜上形成用于连接所述第一引线的至少两段断开的引线段的 过孔、 或用于连接所述第二引线的至少两段断开的引线段的过孔；
在形成过孔的基板上沉积透明导电膜层， 所述透明导电膜层通过过孔将 所述第一引线的至少两段断开的引线段之间导通、 或将所述第二引线的至少 两段断开的引线段之间导通。
2、 如权利要求 1所述的方法， 其中，
形成的包括至少两段断开的引线段的第一引线和栅极同时形成； 或 形成的包括至少两段断开的引线段的第一引线和源极、 漏极同时形成。
3、 如权利要求 1所述的方法， 其中，
形成的包括至少两段断开的 ^ I线段的第二引线和栅极同时形成； 或 形成的包括至少两段断开的引线段的第二引线和源极、 漏极同时形成。
4、如权利要求 1所述的方法， 其中， 所述透明导电膜层的材质和制造阵 列基板时形成的像素电极层的材质相同。
5、 根据权利要求 1所述的方法， 其中， 所述两段引线段之间的距离为 15-30微米。
6、根据权利要求 5所述的方法， 其中， 所述两段断开的引线段之间的距 离为 20微米。
7、 一种通过权利要求 1~6任一方法制作的 ESD器件， 其特征在于， 包 括形成在基板上的薄膜晶体管 TFT, 其中：
所述 TFT的源极和栅极与第一引线相连，所述 TFT的栅极和漏极与第二 引线相连， 其中， 所述第一引线包含至少两段断开的引线段， 或所述第二引 线包含至少两段断开的引线段；
其中所述至少两段断开的引线段之间通过透明导电膜层电性相连。 、 一种显示面板， 其特征在于， 包括权利要求 7所述的 ESD器件。
PCT/CN2013/084186 2013-07-05 2013-09-25 制造esd器件的方法、esd器件和显示面板 WO2015000226A1 (zh)

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104112742B (zh) 2014-06-30 2017-05-10 京东方科技集团股份有限公司 一种柔性基板、柔性显示面板和柔性显示装置
CN105097847B (zh) 2015-09-15 2018-10-23 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN105633097B (zh) * 2016-01-08 2018-07-17 京东方科技集团股份有限公司 一种阵列基板、显示面板和显示装置
CN205452280U (zh) 2016-03-30 2016-08-10 京东方科技集团股份有限公司 静电防护结构、阵列基板及显示装置
KR102526508B1 (ko) 2016-06-30 2023-04-26 티씨엘 차이나 스타 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 액정 표시 장치
CN112859455A (zh) * 2021-03-03 2021-05-28 Tcl华星光电技术有限公司 显示面板及显示装置
CN115188906A (zh) * 2021-04-02 2022-10-14 华为技术有限公司 显示面板和显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201876644U (zh) * 2010-11-23 2011-06-22 北京京东方光电科技有限公司 一种薄膜晶体管液晶显示面板及液晶显示器
CN103022052A (zh) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 一种阵列基板及显示装置
KR20130044405A (ko) * 2011-10-24 2013-05-03 주식회사 루셈 외부 정전기로부터 칩을 보호하기 위한 절연테이프를 구비한 칩 패키지

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3647542B2 (ja) * 1996-02-20 2005-05-11 株式会社半導体エネルギー研究所 液晶表示装置
JPH10198292A (ja) * 1996-12-30 1998-07-31 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
TW440736B (en) * 1997-10-14 2001-06-16 Samsung Electronics Co Ltd Liquid crystal displays and manufacturing methods thereof
KR100386849B1 (ko) * 2001-07-10 2003-06-09 엘지.필립스 엘시디 주식회사 박막 트랜지스터 표시장치의 정전방전 방지회로
KR100883769B1 (ko) * 2002-11-08 2009-02-18 엘지디스플레이 주식회사 액정표시장치용 어레이기판 제조방법
KR100528697B1 (ko) * 2003-05-06 2005-11-16 엘지.필립스 엘시디 주식회사 액정표시장치의 검사방법 및 장치
JP4574158B2 (ja) * 2003-10-28 2010-11-04 株式会社半導体エネルギー研究所 半導体表示装置及びその作製方法
JP2006065021A (ja) * 2004-08-27 2006-03-09 Seiko Epson Corp アクティブマトリクス基板の製造方法、アクティブマトリクス基板、電気光学装置並びに電子機器
US7332360B2 (en) * 2004-10-25 2008-02-19 Applied Materials, Inc. Early detection of metal wiring reliability using a noise spectrum
US7636135B2 (en) * 2006-09-11 2009-12-22 Beijing Boe Optoelectronics Technology Co., Ltd TFT-LCD array substrate and method for manufacturing the same
US7852446B2 (en) * 2006-09-18 2010-12-14 Samsung Electronics Co., Ltd. Liquid crystal display and method of driving the same
US7456432B2 (en) * 2006-11-20 2008-11-25 Tpo Displays Corp. System having electrostatic discharge protection structure and method for manufacturing the same
CN101504499B (zh) * 2008-02-04 2011-08-31 北京京东方光电科技有限公司 Tft-lcd的数据线引线区的结构及其制作方法
CN101719493B (zh) * 2008-10-08 2014-05-14 株式会社半导体能源研究所 显示装置
CN101847648B (zh) * 2009-03-23 2012-11-21 北京京东方光电科技有限公司 有源矩阵有机发光二极管像素结构及其制造方法
US10014068B2 (en) 2011-10-07 2018-07-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
TWI493685B (zh) * 2012-02-10 2015-07-21 E Ink Holdings Inc 主動陣列基板上之靜電防護結構
US9166054B2 (en) * 2012-04-13 2015-10-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201876644U (zh) * 2010-11-23 2011-06-22 北京京东方光电科技有限公司 一种薄膜晶体管液晶显示面板及液晶显示器
KR20130044405A (ko) * 2011-10-24 2013-05-03 주식회사 루셈 외부 정전기로부터 칩을 보호하기 위한 절연테이프를 구비한 칩 패키지
CN103022052A (zh) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 一种阵列基板及显示装置

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