WO2021088824A1 - 阵列基板、显示装置和静电保护单元 - Google Patents
阵列基板、显示装置和静电保护单元 Download PDFInfo
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- WO2021088824A1 WO2021088824A1 PCT/CN2020/126247 CN2020126247W WO2021088824A1 WO 2021088824 A1 WO2021088824 A1 WO 2021088824A1 CN 2020126247 W CN2020126247 W CN 2020126247W WO 2021088824 A1 WO2021088824 A1 WO 2021088824A1
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- film transistor
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Definitions
- the present disclosure relates to the field of display technology, and in particular to an array substrate, a display device and an electrostatic protection unit.
- AMOLED Active-matrix organic light-emitting diode
- LCD liquid crystal displays
- ESD Electro-Static Discharge
- the present disclosure provides an array substrate, a display device, and an electrostatic protection unit.
- An embodiment of the present disclosure provides an array substrate, including: a first wire, a second wire, and a first electrostatic protection unit, the first electrostatic protection unit including a first thin film transistor and a first capacitor, the first thin film transistor The gate of the first thin film transistor is suspended, the gate of the first thin film transistor is connected to the first electrode of the first thin film transistor through the first capacitor, and the first electrode of the thin film transistor is connected to the first wire , The second electrode of the first thin film transistor is connected to the second wire.
- the first electrostatic protection unit further includes a second capacitor, and the gate of the first thin film transistor is connected to the second electrode of the first thin film transistor through the second capacitor.
- the first electrostatic protection unit further includes a second thin film transistor and a third capacitor, the gate of the second thin film transistor is suspended, and the gate of the second thin film transistor passes through the third capacitor.
- the first electrode of the second thin film transistor Connected to the first electrode of the second thin film transistor, the first electrode of the second thin film transistor is connected to the second electrode of the first thin film transistor, and the second electrode of the second thin film transistor is connected to the first electrode of the first thin film transistor. Two wires are connected, so that the second electrode of the first thin film transistor is connected to the second wire through the second thin film transistor.
- the first electrostatic protection unit further includes a fourth capacitor, and the gate of the second thin film transistor is connected to the second electrode of the second thin film transistor through the fourth capacitor.
- the first electrostatic protection unit further includes: a second thin film transistor, a fourth capacitor, a fifth capacitor, and a sixth capacitor, and the first pole of the first thin film transistor is connected to the all through the sixth capacitor.
- the second electrode of the first thin film transistor is connected to the first electrode of the second thin film transistor, the gate of the second thin film transistor is suspended, and the gate of the second thin film transistor passes through the fourth
- the capacitor is connected to the second electrode of the second thin film transistor, and the first electrode of the second thin film transistor is connected to the second electrode of the second thin film transistor through the fifth capacitor.
- the array substrate includes: a substrate and a semiconductor layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source and drain layer sequentially stacked on the substrate,
- the active layer of the first thin film transistor is located on the semiconductor layer, the gate of the first thin film transistor is located on the gate layer, and the first electrode and the second electrode of the first thin film transistor are located on the source Drain layer,
- the first electrode of the first thin film transistor has a first overlap portion that overlaps the gate of the first thin film transistor, and the first overlap portion and the gate of the first thin film transistor constitute the first capacitor ,
- the first electrode of the first thin film transistor is connected to the active layer of the first thin film transistor through a first via hole, and the second electrode of the first thin film transistor is connected to the first thin film transistor through a second via hole.
- the active layer of the transistor is connected, and the first via hole and the second via hole pass through the interlayer insulating layer and the gate insulating layer.
- the second electrode of the first thin film transistor has a second overlapping portion that overlaps with the gate of the first thin film transistor, and the second overlapping portion and the gate of the first thin film transistor constitute a Mentioned second capacitor.
- the array substrate includes: a substrate and a semiconductor layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source and drain layer sequentially stacked on the substrate,
- the active layer of the first thin film transistor and the active layer of the second thin film transistor are located on the semiconductor layer, and the gate of the first thin film transistor and the gate of the second thin film transistor are located on the gate.
- An electrode layer, the first electrode and the second electrode of the first thin film transistor and the first electrode and the second electrode of the second thin film transistor are located in the source and drain layer,
- the first electrode of the first thin film transistor has a first overlap portion that overlaps the gate of the first thin film transistor, and the first overlap portion and the gate of the first thin film transistor constitute the first capacitor ,
- the first electrode of the first thin film transistor is connected to the active layer of the first thin film transistor through a first via hole, and the second electrode of the first thin film transistor is connected to the first thin film transistor through a fourth via hole.
- the first electrode of the second thin film transistor has a third overlapping portion overlapping the gate of the second thin film transistor, and the third overlapping portion and the gate of the second thin film transistor constitute the third capacitor ,
- the first electrode of the second thin film transistor is connected to the active layer of the second thin film transistor through the fourth via hole, and the second electrode of the second thin film transistor is connected to the first electrode through the second via hole.
- the first via hole, the second via hole and the fourth via hole pass through the interlayer insulating layer and the gate insulating layer.
- the second electrode of the first thin film transistor has a second overlapping portion that overlaps the gate of the first thin film transistor, and the second overlapping portion and the gate of the first thin film transistor constitute a first Two capacitors; and/or, the second electrode of the second thin film transistor has a fourth overlap portion that overlaps the gate of the second thin film transistor, and the fourth overlap portion and the gate of the second thin film transistor The pole constitutes the fourth capacitor.
- the array substrate includes: a substrate and a semiconductor layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source and drain layer sequentially stacked on the substrate,
- the active layer of the first thin film transistor and the active layer of the second thin film transistor are located on the semiconductor layer, and the active layer of the first thin film transistor and the active layer of the second thin film transistor are integrated Structure, and the one-piece structure has a metallized area, the gate of the first thin film transistor and the gate of the second thin film transistor are located in the gate layer, and the first electrode of the first thin film transistor is The second electrode of the second thin film transistor is located in the source and drain layer, and the second electrode of the first thin film transistor and the first electrode of the second thin film transistor are located in the metalized area;
- the first electrode of the first thin film transistor has a first overlap portion that overlaps the gate of the first thin film transistor, and the first overlap portion and the gate of the first thin film transistor constitute the first capacitor ,
- the first electrode of the first thin film transistor has a sixth overlapping portion overlapping the metalized region, the sixth overlapping portion and the metalized region constitute a sixth capacitor, and the first electrode of the first thin film transistor
- One pole is connected to the active layer of the first thin film transistor through a first via hole, and the first via hole passes through the interlayer insulating layer and the gate insulating layer;
- the second electrode of the second thin film transistor has a fourth overlapping portion overlapping the gate of the second thin film transistor, and the fourth overlapping portion and the gate of the second thin film transistor constitute a fourth capacitor, so
- the second electrode of the second thin film transistor has a fifth overlapping portion overlapping with the metalized area, the fifth overlapping portion and the metalized area constitute a fifth capacitor, and the second electrode of the second thin film transistor
- the second via is connected to the active layer of the second thin film transistor, and the second via passes through the interlayer insulating layer and the gate insulating layer.
- the array substrate includes: a substrate and a semiconductor layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source and drain layer sequentially stacked on the substrate,
- the active layer of the first thin film transistor and the active layer of the second thin film transistor are located on the semiconductor layer, and the active layer of the first thin film transistor and the active layer of the second thin film transistor are integrated Structure, and the one-piece structure has a metallized area, the gate of the first thin film transistor and the gate of the second thin film transistor are located in the gate layer, and the first electrode of the first thin film transistor is The second electrode of the second thin film transistor is located in the source and drain layer, and the second electrode of the first thin film transistor and the first electrode of the second thin film transistor are located in the metalized area;
- the first electrode of the first thin film transistor has a first overlap portion that overlaps the gate of the first thin film transistor, and the first overlap portion and the gate of the first thin film transistor constitute the first capacitor
- a part of the first electrode of the first thin film transistor is located in the fifth via hole, and the fifth via hole is located in the interlayer insulating layer and corresponds to the position of the second electrode of the first thin film transistor.
- the portion of the first electrode of the first thin film transistor located in the fifth via has a sixth overlapping portion overlapping with the metallized region, and the sixth overlapping portion and the metallized region constitute a sixth capacitor, so
- the first electrode of the first thin film transistor is connected to the active layer of the first thin film transistor through a first via hole, and the first via hole passes through the interlayer insulating layer and the gate insulating layer;
- the second electrode of the second thin film transistor has a fourth overlapping portion overlapping the gate of the second thin film transistor, and the fourth overlapping portion and the gate of the second thin film transistor constitute a fourth capacitor, so A part of the second electrode of the second thin film transistor is located in the sixth via hole, the sixth via hole is located in the interlayer insulating layer and corresponds to the position of the first electrode of the second thin film transistor, and the second The portion where the second electrode of the thin film transistor is located in the sixth via has a fifth overlapping portion overlapping with the metallized region, the fifth overlapping portion and the metallized region constitute a fifth capacitor, and the first The second electrodes of the two thin film transistors are connected to the active layer of the second thin film transistor through a second via hole, and the second via hole penetrates the interlayer insulating layer and the gate insulating layer.
- the material of the semiconductor layer is an oxide semiconductor, and the aspect ratio of the channel of the first thin film transistor is less than 1/20 and greater than 1/100.
- the first wire is one of a gate line, a data line, and an electrostatic protection line
- the second wire is one of a gate line, a data line, and an electrostatic protection line
- the array substrate further includes a third wire, a fourth wire, and a second electrostatic protection unit.
- the second electrostatic protection unit is connected between the third wire and the fourth wire.
- the structure of the second electrostatic protection unit is the same as the structure of the first electrostatic protection unit.
- the first wire is a gate wire
- the second wire is a first electrostatic protection wire
- the third wire is a data wire
- the fourth wire is a second electrostatic protection wire.
- the extension direction of the line intersects the extension direction of the gate line
- the extension direction of the first electrostatic protection line is the same as the extension direction of the data line
- the extension direction of the second electrostatic protection line is the same as the extension direction of the gate line. The same direction.
- the first electrostatic protection wire is connected to the second electrostatic protection wire.
- the first electrostatic protection line and the second electrostatic protection line are connected to a reference voltage input terminal.
- the embodiment of the present disclosure also provides a display device, which includes any of the aforementioned array substrates.
- An embodiment of the present disclosure also provides an electrostatic protection unit, including a first thin film transistor and a first capacitor, the gate of the first thin film transistor is suspended, and the gate of the first thin film transistor passes through the first The capacitor is connected to the first pole of the first thin film transistor.
- the electrostatic protection unit further includes a second capacitor, and the gate of the first thin film transistor is connected to the second electrode of the first thin film transistor through the second capacitor.
- the electrostatic protection unit further includes: a second thin film transistor and a third capacitor, the gate of the second thin film transistor is suspended, and the gate of the second thin film transistor is connected through the third capacitor To the first electrode of the second thin film transistor, the first electrode of the second thin film transistor is connected to the second electrode of the first thin film transistor.
- the electrostatic protection unit further includes: a fourth capacitor, and the gate of the second thin film transistor is connected to the second electrode of the second thin film transistor through the fourth capacitor.
- the electrostatic protection unit further includes: a second thin film transistor, a fourth capacitor, a fifth capacitor, and a sixth capacitor, and the first electrode of the first thin film transistor is connected to the second thin film transistor through the sixth capacitor.
- a second electrode of a thin film transistor, the second electrode of the first thin film transistor is connected to the first electrode of the second thin film transistor,
- the gate of the second thin film transistor is suspended, the gate of the second thin film transistor is connected to the second electrode of the second thin film transistor through the fourth capacitor, and the first electrode of the second thin film transistor is The electrode is connected to the second electrode of the second thin film transistor through the fifth capacitor.
- FIG. 1 is a circuit structure diagram of an electrostatic protection unit provided by an embodiment of the disclosure
- FIG. 2 is a circuit structure diagram of another electrostatic protection unit provided by an embodiment of the disclosure.
- FIG. 3 is a circuit structure diagram of another electrostatic protection unit provided by an embodiment of the disclosure.
- FIG. 4 is a circuit structure diagram of another electrostatic protection unit provided by an embodiment of the disclosure.
- FIG. 5 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure.
- FIG. 6 is a schematic diagram of a planar structure of an electrostatic protection unit of an array substrate provided by an embodiment of the disclosure
- FIG. 7 is a schematic cross-sectional structure diagram of the electrostatic protection unit in FIG. 6 along the line AA';
- FIG. 8 is a schematic diagram of a planar structure of an electrostatic protection unit of an array substrate provided by an embodiment of the disclosure.
- FIG. 9 is a schematic cross-sectional structure diagram of the electrostatic protection unit in FIG. 8 along the line AA';
- FIG. 10 is a schematic plan view of another electrostatic protection unit provided by an embodiment of the disclosure.
- Fig. 11 is a cross-sectional view of the electrostatic protection unit in Fig. 10 along the line AA';
- FIG. 12 is a schematic plan view of another electrostatic protection unit provided by an embodiment of the disclosure.
- FIG. 13 is a schematic cross-sectional structure diagram of the electrostatic protection unit in FIG. 12 along the line AA';
- FIG. 14 is a schematic plan view of another electrostatic protection unit provided by an embodiment of the disclosure.
- Fig. 15 is a schematic cross-sectional structure view of the electrostatic protection unit in Fig. 14 along the line AA'.
- the embodiments of the present disclosure provide an electrostatic protection unit, which is mainly applied to an array substrate of a display.
- the structure of the electrostatic protection unit will be described below in conjunction with the connection of the electrostatic protection unit in actual use.
- FIG. 1 is a circuit structure diagram of an electrostatic protection unit provided by an embodiment of the disclosure.
- the electrostatic protection unit includes: a first thin film transistor 100 and a first capacitor C1, and the gate of the first thin film transistor 100 is suspended.
- the gate of the first thin film transistor 100 is connected to the first electrode of the first thin film transistor 100 through the first capacitor C1.
- the first electrode of the first thin film transistor 100 is connected to the first wire 1, and the second electrode of the first thin film transistor 100 is connected to the second wire 2.
- the first conductive line 1 is a data line or a gate line intersecting the data line, and whether the first conductive line 1 is a data line or a gate line is determined according to actual conditions.
- the second wire 2 is a data line or a gate line or an electrostatic protection line intersecting the data line.
- the first electrode is one of the source and the drain
- the second electrode is the other of the source and the drain
- the voltage on the first wire 1 will be coupled to the gate of the first thin film transistor 100 through the first capacitor C1, so that a voltage is generated on the gate, and the voltage on the gate is Under the action of, a conductive path is generated between the first electrode and the second electrode of the first thin film transistor 100, that is, the first thin film transistor 100 is turned on, and the static charge generated on the first wire 1 can be quickly released to the second wire 2.
- the electrostatic protection unit disclosed in this embodiment has a simple structure, is easy to implement, and has a low manufacturing cost.
- the electrostatic protection unit when the electrostatic charge is generated on the first wire of the array substrate, the conduction between the first electrode and the second electrode of the first thin film transistor will be realized through the gate of the first thin film transistor. Through, and then quickly release the static charge, which plays the purpose of protecting the array substrate.
- FIG. 2 is a circuit structure diagram of another electrostatic protection unit provided by an embodiment of the disclosure. As shown in FIG. 2, the electrostatic protection unit in FIG. 2 adds a second capacitor C2 to the electrostatic protection unit in FIG. 1. The gate of the first thin film transistor 100 is connected to the second electrode of the first thin film transistor 100 through the second capacitor C2.
- the voltage on the second wire 2 is coupled to the gate of the first thin film transistor 100 through the second capacitor C2, so that a voltage is generated on the gate, and under the action of the gate voltage A conductive channel is formed between the first electrode and the second electrode of the first thin film transistor 100, and the static charge generated on the second wire 2 can be quickly released to the first wire 1.
- the electrostatic protection unit disclosed in this embodiment has a simple structure, is easy to implement, and has a low manufacturing cost.
- the electrostatic protection unit when the electrostatic charge is generated on the first wire or the second wire of the array substrate, the first electrode and the second electrode of the first thin film transistor will be realized through the gate of the first thin film transistor. The conduction between the two, and then quickly release the static charge, which plays the purpose of protecting the array substrate.
- the second electrode of the first thin film transistor is directly connected to the second wire, while in other embodiments, the second electrode of the first thin film transistor may be connected to the second electrode.
- the two wires are indirectly connected, for example, the second electrode of the first thin film transistor is connected to the second wire through other electronic components (such as the second thin film transistor, etc.).
- the case where the first thin film transistor is connected to the second wire through the second thin film transistor will be exemplarily described.
- the embodiment of the present disclosure also provides another electrostatic protection unit, and the structure of the electrostatic protection unit will be described below in conjunction with the connection of the electrostatic protection unit of this structure in actual use.
- 3 is a schematic diagram of the circuit structure of another electrostatic protection unit provided by an embodiment of the disclosure. As shown in FIG. 3, on the basis of the embodiments shown in FIGS. 1 to 2, the electrostatic protection unit of this embodiment further includes a second The thin film transistor 200, the third capacitor C3 and the fourth capacitor C4.
- the gate of the first thin film transistor 100 is suspended, the gate of the first thin film transistor 100 is connected to the first electrode of the first thin film transistor 100 through a first capacitor C1, and the gate of the first thin film transistor 100 is connected through a second capacitor C2. Connected to the second electrode of the first thin film transistor 100.
- the gate of the second thin film transistor 200 is floating, the gate of the second thin film transistor 200 is connected to the first electrode of the second thin film transistor 200 through a third capacitor C3, and the gate of the second thin film transistor 200 is connected through a fourth capacitor C4. Connected to the second electrode of the second thin film transistor 200.
- the second electrode of the first thin film transistor 100 is connected to the first electrode of the second thin film transistor 200.
- the first electrode of the first thin film transistor 100 is connected to the first wire 1
- the second electrode of the second thin film transistor 200 is connected to the second wire 2, that is, the second electrode of the first thin film transistor 100 passes through the
- the two thin film transistors 200 are connected to the second wire 2.
- the voltage on the first wire 1 is coupled to the gate of the first thin film transistor 100 through the first capacitor C1, so that a voltage is generated on the gate of the first thin film transistor 100.
- a conductive path is generated between the first electrode and the second electrode of the first thin film transistor 100 under the action of the gate voltage. Since the second electrode of the first thin film transistor 100 is connected to the first electrode of the second thin film transistor 200, the electrostatic The charge is coupled to the gate of the second thin film transistor 200 through the third capacitor C3, so that a voltage is generated on the gate of the second thin film transistor 200. Under the action of the gate voltage, the first electrode of the second thin film transistor 200 A conductive path is created between the second pole and the second pole, thereby releasing static charge to the second wire 2.
- the voltage on the second wire 2 will be connected to the gate of the second thin film transistor 200 through the fourth capacitor C4, so that a voltage is generated on the gate of the second thin film transistor 200.
- a conductive path is created between the first electrode and the second electrode of the second thin film transistor 200 under the action of the gate voltage. Since the second electrode of the first thin film transistor 100 is connected to the first electrode of the second thin film transistor 200, the electrostatic The charge is coupled to the gate of the first thin film transistor 100 through the second capacitor C2, so that a voltage is generated on the gate of the first thin film transistor 100. Under the action of the gate voltage, the first electrode of the first thin film transistor 100 is A conductive path is created between the second pole and the second pole, thereby releasing static charge to the first wire 1.
- the second capacitor C2 and the fourth capacitor C4 in FIG. 3 can be removed. After the second capacitor C2 and the fourth capacitor C4 are removed, only the first wire 1 to the first wire can be realized. Electrostatic discharge of the second wire 2.
- a plurality of capacitors can play a role of storing static charges, so that the electrostatic shock during the electrostatic discharge process can be reduced.
- FIG. 4 is a schematic diagram of a circuit structure of another electrostatic protection unit provided by an embodiment of the disclosure.
- the electrostatic protection unit includes: a first thin film transistor 100, a second thin film transistor 200, a first capacitor C1, and a second capacitor.
- the gate of the first thin film transistor 100 is suspended, and the gate of the first thin film transistor 100 is connected to the first electrode of the first thin film transistor 100 through the first capacitor C1.
- the first electrode of the first thin film transistor 100 is connected to the second electrode of the first thin film transistor 100 through the sixth capacitor C6.
- the gate of the second thin film transistor 200 is floating, the gate of the second thin film transistor 200 is connected to the second electrode of the second thin film transistor 200 through the fourth capacitor C4; the first electrode of the second thin film transistor 200 is connected to the fifth capacitor C5 The second electrode of the second thin film transistor 200 is connected.
- the second electrode of the first thin film transistor 100 is connected to the first electrode of the second thin film transistor 200.
- the first electrode of the first thin film transistor 100 is connected to the first wire 1
- the second electrode of the second thin film transistor 200 is connected to the second wire 2.
- the voltage on the first wire 1 is coupled to the gate of the first thin film transistor 100 through the first capacitor C1, so that a voltage is generated on the gate of the first thin film transistor 100, so that A conductive path is formed between the first electrode and the second electrode of the first thin film transistor 100.
- the voltage on the first wire 1 is also coupled to the gate of the second thin film transistor 200 through the sixth capacitor, the fifth capacitor C5, and the fourth capacitor C4, so that the first electrode and the second electrode of the second thin film transistor 200 are There is a conductive path between.
- the static charge is discharged to the second wire 2 through the first electrode and the second electrode of the first thin film transistor 100 and the first electrode and the second electrode of the second thin film transistor 200.
- the electrostatic discharge process when electrostatic charges are generated on the second wire 2 is similar to the electrostatic discharge process when electrostatic charges are generated on the first wire 1, which will not be described in detail here.
- the fifth capacitor C5 and the sixth capacitor C6 can also provide a pure capacitor discharge path to further ensure the effect of electrostatic discharge.
- the embodiments of the present disclosure also provide an array substrate, which includes a first wire, a second wire, and any of the foregoing electrostatic protection units.
- the electrostatic protection unit is connected between the first wire and the second wire.
- the first wire is one of a grid line, a data line, and an electrostatic protection line
- the second wire is one of a grid line, a data line, and an electrostatic protection line.
- the number of electrostatic protection units included in the array substrate and the types of the first wire and the second wire connected to the electrostatic protection unit can be set according to actual needs, which is not limited in the embodiment of the present disclosure.
- the electrostatic protection unit may adopt one or more of the electrostatic protection units shown in FIGS. 1 to 4.
- FIG. 5 is a schematic diagram of a planar structure of an array substrate provided by an embodiment of the disclosure.
- the array substrate includes a plurality of data lines D1 to Dm, a plurality of gate lines G1 to Gn, a first electrostatic protection line P1, a second electrostatic protection line P2, a first electrostatic protection unit E1, and The second electrostatic protection unit E2.
- the array substrate has a display area and a peripheral area surrounding the display area.
- a plurality of data lines D1 to Dm and a plurality of gate lines G1 to Gn intersect to form a plurality of pixel units, and each pixel unit is connected to a corresponding gate line and data line. Multiple pixel units are located in the display area.
- the extension direction of the first electrostatic protection line P1 is the same as the extension direction of the data line
- the extension direction of the second electrostatic protection line P2 is the same as the extension direction of the gate line.
- the first electrostatic protection unit E1 is connected between the first electrostatic protection line P1 and the gate line
- the second electrostatic protection unit E2 is connected between the second electrostatic protection line P2 and the data line.
- the first electrostatic protection line P1, the second electrostatic protection line P2, the first electrostatic protection unit E1, and the second electrostatic protection unit E2 are all located in the peripheral area.
- the first electrode of the first thin film transistor of the first electrostatic protection unit E1 is connected to the gate line, and the second electrode of the first thin film transistor of the first electrostatic protection unit E1 is connected to the first electrostatic protection line P1.
- the first electrode of the first thin film transistor of the second electrostatic protection unit E2 is connected to the data line, and the second electrode of the first thin film transistor of the second electrostatic protection unit E2 is connected to the second electrostatic protection line P2.
- first electrostatic protection wire and the second electrostatic protection wire may be electrically connected, for example, the first electrostatic protection wire P1 and the second electrostatic protection wire P2 are connected on the array substrate.
- a reference voltage can be provided for the first electrostatic protection line P1 and the second electrostatic protection line P2.
- the first electrostatic protection line P1 and the second electrostatic protection line P2 can be connected to the reference voltage input by lead wires.
- the reference voltage input terminal is connected to a flexible circuit board (FPC), and a reference voltage is provided through the flexible circuit board to reduce the leakage current caused by the floating gate of the thin film transistor of the electrostatic protection unit.
- the reference voltage may be the common voltage of the cathode of the AMOLED or the common voltage of the LCD, or may be another voltage different from the common voltage of the cathode of the AMOLED or the common voltage of the LCD.
- circuit structure of the first electrostatic protection unit E1 and the second electrostatic protection unit E2 shown in FIG. 5 is the same as the circuit structure of the electrostatic protection unit shown in FIG. Figure 2 shows the electrostatic protection unit in the embodiment.
- at least one of the first electrostatic protection unit E1 and the second electrostatic protection unit E2 can be replaced with the electrostatic protection unit in the embodiment shown in FIG. 1 or FIG. 3 or FIG. 4 according to requirements.
- the circuit structure of the first electrostatic protection unit E1 and the structure of the second electrostatic protection unit E2 may be the same or different.
- FIG. 6 is a schematic plan view of the electrostatic protection unit on the array substrate shown in FIG. 5.
- Fig. 7 is a schematic cross-sectional structure diagram of the electrostatic protection unit in Fig. 6 along the line AA'.
- the array substrate includes a substrate 10 and a semiconductor layer 20, a gate insulating layer 30, a gate layer 40, an interlayer insulating layer 50, and a source and drain layer 60 which are sequentially disposed on the substrate 10.
- the active layer 104 of the first thin film transistor 100 is located on the semiconductor layer 20, the gate 101 of the first thin film transistor 100 is located on the gate layer 40, and the first electrode 102 and the second electrode 103 of the first thin film transistor 100 are both located at the source and drain. Layer 60.
- the gate 101 of the first thin film transistor 200 is suspended.
- the first electrode 102 of the first thin film transistor 100 is connected to the active layer 104 of the first thin film transistor 100 through a first via 111 passing through the interlayer insulating layer 50 and the gate insulating layer 30.
- the first electrode 102 of the first thin film transistor 100 has a first extension 1021, and the overlapping area between the first extension 1021 and the gate 101 is called the first overlapping portion, and the first overlapping portion and the gate 101 respectively serve as the first overlapping portion.
- the two plates of the capacitor C1 constitute the first capacitor C1, and the interlayer insulating layer 50 in the corresponding area serves as the insulating medium of the first capacitor C1.
- the second electrode 103 of the first thin film transistor 100 is connected to the active layer 104 of the first thin film transistor 100 through the second via hole 121 passing through the interlayer insulating layer 50 and the gate insulating layer 30, and the second electrode 103 of the first thin film transistor 100
- the second pole 103 has a second extension portion 1031.
- the area where the second extension portion 1031 and the gate 101 overlap is called the second overlap portion.
- the second overlap portion and the gate 101 respectively serve as the two poles of the second capacitor C2.
- the board constitutes the second capacitor C2, and the interlayer insulating layer 50 in the corresponding area serves as the insulating medium of the second capacitor C2.
- the first electrode 102 of the first thin film transistor 100 is connected to the first wire 1, and the second electrode 103 of the first thin film transistor 100 passes through The third via 131 of the interlayer insulating layer 50 is connected to the second wire 2.
- the first wire 1 is located in the source and drain layer 60, and the second wire 2 is located in the gate layer 40. That is, the first wire 1 is the data wire in FIG. 5, and the second wire 2 is the second electrostatic protection wire P2.
- FIG. 8 is a schematic plan view of the electrostatic protection unit on the array substrate shown in FIG. 5 after being replaced with the electrostatic protection unit shown in FIG. 1.
- Fig. 9 is a schematic cross-sectional structure diagram of the electrostatic protection unit in Fig. 8 along the line AA'.
- the electrostatic protection unit shown in FIGS. 8 and 9 Compared with the electrostatic protection unit shown in FIGS. 6 and 7, in the electrostatic protection unit shown in FIGS. 8 and 9, there is no gap between the second electrode 103 of the first thin film transistor 100 and the gate 101 of the first thin film transistor 100. There is overlap, so the first electrostatic protection unit does not include the second capacitor C2.
- FIG. 10 is a schematic plan view of the electrostatic protection unit on the array substrate shown in FIG. 5 after the electrostatic protection unit shown in FIG. 3 is replaced.
- FIG. 11 is a schematic cross-sectional structure diagram of the electrostatic protection unit in FIG. 10 along the line AA'.
- the array substrate includes a substrate 10 and a semiconductor layer 20, a gate insulating layer 30, a gate layer 40, an interlayer insulating layer 50, and a source and drain layer 60 which are sequentially disposed on the substrate 10.
- the active layer 104 of the first thin film transistor 100 and the active layer 204 of the second thin film transistor 200 are located on the semiconductor layer 20, and the gate 101 of the first thin film transistor 100 and the gate 201 of the second thin film transistor 200 are both located on the gate layer 40.
- the first electrode 102 and the second electrode 103 of the first thin film transistor 100 and the first electrode 202 and the second electrode 203 of the second thin film transistor 200 are both located in the source and drain layer 60. It should be noted that the active layer 104 of the first thin film transistor 100 and the active layer 204 of the second thin film transistor 200 are an integral structure.
- the gate 101 of the first thin film transistor 200 is suspended.
- the first electrode 102 of the first thin film transistor 100 is connected to the active layer 104 of the first thin film transistor through a first via 111 passing through the interlayer insulating layer 50 and the gate insulating layer 30.
- the first electrode 102 of the first thin film transistor 100 has a first extension 1021.
- the area where the first extension 1021 overlaps with the gate 101 of the first thin film transistor 100 is called the first overlap.
- the gate 101 serves as the two plates of the first capacitor C1 to form the first capacitor C1, and the interlayer insulating layer 50 in the corresponding area serves as the insulating medium of the first capacitor C1.
- the second electrode 103 of the first thin film transistor 100 has a second extension portion 1032.
- the area between the second extension portion 1032 and the gate 101 of the first thin film transistor 100 is called the second overlap portion.
- the pole 101 serves as the two pole plates of the second capacitor C2 to form the second capacitor C2, and the interlayer insulating layer 50 in the corresponding area serves as the insulating medium of the second capacitor C2.
- the gate 201 of the second thin film transistor 200 is floating.
- the first electrode 202 of the second thin film transistor 200 has a third extension 2021, the third extension 2021 and the gate 201 of the second thin film transistor 200 have a third overlap portion, and the third overlap portion and the gate 201 respectively serve as the third
- the two plates of the capacitor C3 constitute the third capacitor C3, and the interlayer insulating layer 50 in the corresponding area serves as the insulating medium of the third capacitor C3.
- the second electrode 203 of the second thin film transistor 200 has a fourth extension portion 2031, the fourth extension portion 2031 and the gate 201 of the second thin film transistor 200 have a fourth overlapping portion, and the fourth overlapping portion and the gate 201 respectively serve as the fourth
- the two plates of the capacitor C4 constitute the fourth capacitor C4, and the interlayer insulating layer 50 in the corresponding area serves as the insulating medium of the fourth capacitor C4.
- the second electrode 203 of the second thin film transistor 200 is connected to the active layer 204 of the second thin film transistor 200 through a second via 121 passing through the interlayer insulating layer 50 and the gate insulating layer 30.
- the first electrode 102 of the first thin film transistor 100 is connected to the first wire 1
- the second electrode 203 of the second thin film transistor 200 is passed through
- the third via 131 of the interlayer insulating layer 50 is connected to the second wire 2.
- the related content of the first wire 1 and the second wire 2 please refer to the relevant parts of the embodiment shown in FIG. 6 and FIG. 7, which will not be repeated here.
- the second thin film transistor 200 is connected in series with the first thin film transistor 100.
- the first electrode 202 of the second thin film transistor 200 is connected to the second electrode 103 of the first thin film transistor 100.
- the first electrode 202 of the second thin film transistor 200 is connected to the first electrode 103 of the first thin film transistor 100.
- the second electrode 103 of the thin film transistor 100 is an integrated structure 70 that is connected to the semiconductor layer 20 through a fourth via 141 passing through the interlayer insulating layer 50 and the gate insulating layer 30.
- the integrated structure 70 uses a T-shaped source and/or drain metal layer, one end of which is the second extension 1032, and the other end is the third extension 2021. In actual use, it can also be selected to achieve the same effect. For metal layers of other shapes, this embodiment is not limited here.
- FIG. 12 is a schematic plan view of the electrostatic protection unit on the array substrate shown in FIG. 5 after the electrostatic protection unit shown in FIG. 4 is replaced.
- Fig. 13 is a schematic cross-sectional structure diagram of the electrostatic protection unit in Fig. 12 along the line AA'.
- the array substrate includes a substrate 10 and a semiconductor layer 20, a gate insulating layer 30, a gate layer 40, an interlayer insulating layer 50, and a source and drain layer 60 which are sequentially disposed on the substrate 10.
- the active layer 104 of the first thin film transistor 100 and the active layer 204 of the second thin film transistor 200 are both located on the semiconductor layer 20.
- the gate 101 of the first thin film transistor 100 and the gate 201 of the second thin film transistor 200 are both located on the gate layer 40.
- the first electrode 102 of the first thin film transistor 100 and the second electrode 203 of the second thin film transistor 200 are located in the source and drain layer 60.
- the active layer 104 of the first thin film transistor 100 and the active layer 204 of the second thin film transistor 200 are an integrated structure, and the integrated structure has a metallized area including the first thin film transistor 100.
- the second electrode 103 and the first electrode 202 of the second thin film transistor 200 The metalized area is to metalize a part of the integrated structure into a conductor.
- the gate 101 of the first thin film transistor 100 is floating.
- the first electrode 102 of the first thin film transistor 100 is connected to the active layer 104 of the first thin film transistor 100 through a first via 111 passing through the interlayer insulating layer 50 and the gate insulating layer 30.
- the first electrode 102 of the first thin film transistor 100 has a first extension 1021.
- the area between the first extension 1021 and the gate 101 of the first thin film transistor 100 is called a first overlap.
- the pole 101 serves as the two pole plates of the first capacitor C1 to form the first capacitor C1, and the interlayer insulating layer 40 in the corresponding area serves as the insulating medium of the first capacitor C1.
- the gate 201 of the second thin film transistor 200 is floating.
- the second electrode 203 of the second thin film transistor 200 is connected to the active layer 204 through the second via hole 121 passing through the interlayer insulating layer 50 and the gate insulating layer 30.
- the second electrode 203 of the second thin film transistor 200 has a fourth extension portion 2031, the fourth extension portion 2031 and the gate 201 of the second thin film transistor 200 have a fourth overlapping portion, and the fourth overlapping portion and the gate 201 respectively serve as the fourth
- the two plates of the capacitor C4 constitute the fourth capacitor C4, and the interlayer insulating layer 50 in the corresponding area serves as the insulating medium of the fourth capacitor C4.
- the fourth extension portion 2031 and the first electrode 202 of the second thin film transistor 200 located on the semiconductor layer 20 have a fifth overlapping portion, and the fifth overlapping portion and the first electrode 202 of the second thin film transistor 200 located on the semiconductor layer 20 constitute a fifth overlapping portion.
- the capacitor C5, the gate insulating layer 30 and the interlayer insulating layer 50 in the corresponding area all serve as the insulating medium of the fifth capacitor C5.
- the first extension portion 1021 and the second electrode 103 of the first thin film transistor 100 located on the semiconductor layer 20 have a sixth overlapping portion, and the sixth overlapping portion and the second electrode 103 of the first thin film transistor 100 located on the semiconductor layer 20 constitute a sixth overlapping portion.
- the capacitor C6, the gate insulating layer 30 and the interlayer insulating layer 50 in the corresponding area all serve as the insulating medium of the sixth capacitor C6.
- the first electrode 102 of the first thin film transistor 100 is connected to the first wire 1
- the second electrode 203 of the second thin film transistor 200 is passed through
- the third via 131 of the interlayer insulating layer 50 is connected to the second wire 2.
- the related content of the first wire 1 and the second wire 2 please refer to the relevant parts of the embodiment shown in FIG. 6 and FIG. 7, which will not be repeated here.
- FIG. 14 is a schematic diagram of another planar structure after the electrostatic protection unit on the array substrate shown in FIG. 5 is replaced with the electrostatic protection unit shown in FIG. 4.
- Fig. 15 is a schematic cross-sectional structure view of the electrostatic protection unit in Fig. 14 along the line AA'.
- the interlayer insulating layer 50 corresponds to the position of the second electrode 103 of the semiconductor layer 20 of the first thin film transistor 100
- a fifth via hole 151 is formed on the upper side.
- a part of the first extension 1021 is located in the fifth via hole 151.
- the sixth overlapping portion is located in the fifth via hole 151.
- the insulating medium of the sixth capacitor C6 is The position of the hole 151 corresponds to the gate insulating layer 30.
- a sixth via hole 161 is opened in the interlayer insulating layer 50 corresponding to the position of the second thin film transistor 200 at the first pole 202 of the semiconductor layer 20, and a part of the fourth extension portion 2031 is located in the sixth via hole 161.
- the fifth overlapping portion is located in the sixth via hole 161
- the insulating medium of the fifth capacitor C5 is the gate insulating layer 30 corresponding to the position of the sixth via hole 161.
- the material of the semiconductor layer 20 may be any one of amorphous silicon, polysilicon, and oxide semiconductor, for example, an oxide semiconductor material, such as indium gallium zinc oxide (IGZO).
- oxide semiconductor material such as indium gallium zinc oxide (IGZO).
- the aspect ratio of the oxide semiconductor channel of the first thin film transistor is less than 1/20 and greater than 1/100; the aspect ratio of the oxide semiconductor channel of the second thin film transistor is less than 1/20 and greater than 1/100.
- all the gates, sources and drains in this embodiment can be made of metal materials such as copper Cu, aluminum Al, molybdenum Mo, titanium Ti, chromium Cr, tungsten W, etc., or can be made of alloys of these materials. It can be a single-layer structure or a multi-layer structure, such as Mo ⁇ Al ⁇ Mo, Ti ⁇ Cu ⁇ Ti, MoTi ⁇ Cu, etc.; both the gate insulating layer and the interlayer insulating layer can be made of silicon nitride or silicon oxide, Both the gate insulating layer and the interlayer insulating layer may have a single-layer structure or a multi-layer structure, such as a composite structure of silicon nitride and silicon oxide.
- the electrostatic protection unit is installed on the array substrate.
- the electrostatic charge When the electrostatic charge is generated on the data line or gate line of the array substrate, the electrostatic charge will be connected to the signal line (ie the gate line and the data line) and the electrostatic protection line.
- the electrostatic protection unit in between enables the electrostatic charge to be quickly released, thereby reducing the damage caused by static electricity to the array substrate, and the structure of the electrostatic protection unit in this embodiment is simple, the manufacturing cost is lower, and it is convenient for realization and mass production.
- the embodiments of the present disclosure also provide a display device, which includes any of the aforementioned array substrates.
- the display device may be an AMOLED display or LCD.
- the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
- a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
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Abstract
Description
Claims (23)
- 一种阵列基板,包括:第一导线(1)、第二导线(2)和第一静电保护单元(E1),所述第一静电保护单元(E1)包括第一薄膜晶体管(100)和第一电容(C1),所述第一薄膜晶体管(100)的栅极(101)是悬浮的,所述第一薄膜晶体管(100)的栅极(101)通过所述第一电容(C1)连接至所述第一薄膜晶体管(100)的第一极(102),所述薄膜晶体管(100)的第一极(102)与所述第一导线(1)连接,所述第一薄膜晶体管(100)的第二极(103)与所述第二导线(2)连接。
- 根据权利要求1所述的阵列基板,其中,所述第一静电保护单元(E1)还包括:第二电容(C2),所述第一薄膜晶体管(100)的栅极(101)通过所述第二电容(C2)连接至所述第一薄膜晶体管(100)的第二极(103)。
- 根据权利要求1或2所述的阵列基板,其中,所述第一静电保护单元(E1)还包括第二薄膜晶体管(200)和第三电容(C3),所述第二薄膜晶体管(200)的栅极(201)是悬浮的,所述第二薄膜晶体管(200)的栅极(201)通过所述第三电容(C3)连接至所述第二薄膜晶体管(200)的第一极(202),所述第二薄膜晶体管(200)的第一极(202)与所述第一薄膜晶体管(100)的第二极(103)连接,所述第二薄膜晶体管(200)的第二极(203)与所述第二导线(2)连接,使得所述第一薄膜晶体管(100)的第二极(103)通过所述第二薄膜晶体管(200)与所述第二导线(2)连接。
- 根据权利要求3所述的阵列基板,其中,所述第一静电保护单元(E1)还包括第四电容(C4),所述第二薄膜晶体管(200)的栅极(201)通过所述第四电容(C4)连接至所述第二薄膜晶体管(200)的第二极(203)。
- 根据权利要求1所述的阵列基板,其中,所述第一静电保护单元(E1)还包括:第二薄膜晶体管(200)、第四电容(C4)、第五电容(C5)和第六电容(C6),所述第一薄膜晶体管(100)的第一极(102)通过所述第六电容(C6)连接至所述第一薄膜晶体管(100)的第二极(103),所述第一薄膜晶体管(100)的第二极(103)与所述第二薄膜晶体管(200)的第一极(202)连接,所述第二薄膜晶体管(200)的栅极(201)是悬浮的,所述第二薄膜晶体管(200)的栅极(201)通过所述第四电容(C4)连接至所 述第二薄膜晶体管(200)的第二极(203),所述第二薄膜晶体管(200)的第一极(202)通过所述第五电容(C5)连接至所述第二薄膜晶体管的第二极。
- 根据权利要求1所述的阵列基板,包括:基板(10)和依次层叠在所述基板(10)上的半导体层(20)、栅极绝缘层(30)、栅极层(40)、层间绝缘层(50)、源漏极层(60),所述第一薄膜晶体管(100)的有源层(104)位于所述半导体层(20),所述第一薄膜晶体管(100)的栅极(101)位于所述栅极层(40),所述第一薄膜晶体管(100)的第一极(102)和第二极(103)位于所述源漏极层(60),所述第一薄膜晶体管(100)的第一极(102)具有与所述第一薄膜晶体管(100)的栅极(101)重叠的第一重叠部分,所述第一重叠部分和所述第一薄膜晶体管(100)的栅极(101)构成所述第一电容(C1),所述第一薄膜晶体管(100)的第一极(102)通过第一过孔(111)与所述第一薄膜晶体管(100)的有源层(104)连接,所述第一薄膜晶体管(100)的第二极(103)通过第二过孔(121)与所述第一薄膜晶体管(100)的有源层(104)连接,所述第一过孔(111)和所述第二过孔(121)穿过所述层间绝缘层(50)和所述栅极绝缘层(30)。
- 根据权利要求6所述的阵列基板,其中,所述第一薄膜晶体管(100)的第二极(103)具有与所述第一薄膜晶体管(100)的栅极(101)重叠的第二重叠部分,所述第二重叠部分和所述第一薄膜晶体管(100)的栅极(101)构成第二电容(C2)。
- 根据权利要求3所述的阵列基板,包括:基板(10)和依次层叠在所述基板(10)上的半导体层(20)、栅极绝缘层(30)、栅极层(40)、层间绝缘层(50)、源漏极层(60),所述第一薄膜晶体管(100)的有源层(104)、所述第二薄膜晶体管(200)的有源层(204)位于所述半导体层(20),所述第一薄膜晶体管(100)的栅极(101)和所述第二薄膜晶体管(200)的栅极(201)位于所述栅极层(40),所述第一薄膜晶体管(100)的第一极(102)和第二极(103)以及所述第二薄膜晶体管(200)的第一极(202)和第二极(203)位于所述源漏极层(60),所述第一薄膜晶体管(100)的第一极(102)具有与所述第一薄膜晶体管(100)的栅极(101)重叠的第一重叠部分,所述第一重叠部分和所述第一薄膜晶体管(100)的栅极(101)构成所述第一电容(C1),所述第一薄膜晶体管(100) 的第一极(102)通过第一过孔(111)与所述第一薄膜晶体管(100)的有源层(104)连接,所述第一薄膜晶体管(100)的第二极(103)通过第四过孔(141)与所述第一薄膜晶体管(100)的有源层(104)连接;所述第二薄膜晶体管(200)的第一极(202)具有与所述第二薄膜晶体管(200)的栅极(201)重叠的第三重叠部分,所述第三重叠部分和所述第二薄膜晶体管(200)的栅极(201)构成所述第三电容(C3),所述第二薄膜晶体管(200)的第一极(202)通过所述第四过孔(141)与所述第二薄膜晶体管(200)的有源层(204)连接,所述第二薄膜晶体管(200)的第二极(203)通过第二过孔(121)与所述第二薄膜晶体管(200)的有源层(204)连接;其中,所述第一过孔(111)、所述第二过孔(121)和所述第四过孔(141)穿过所述层间绝缘层(50)和所述栅极绝缘层(30)。
- 根据权利要求8所述的阵列基板,其中,所述第一薄膜晶体管(100)的第二极(103)具有与所述第一薄膜晶体管(100)的栅极(101)重叠的第二重叠部分,所述第二重叠部分和所述第一薄膜晶体管(100)的栅极(101)构成第二电容(C2);和/或,所述第二薄膜晶体管(200)的第二极(203)具有与所述第二薄膜晶体管(200)的栅极(201)重叠的第四重叠部分,所述第四重叠部分和所述第二薄膜晶体管(200)的栅极(201)构成第四电容(C4)。
- 根据权利要求4所述的阵列基板,包括:基板(10)和依次层叠在所述基板(10)上的半导体层(20)、栅极绝缘层(30)、栅极层(40)、层间绝缘层(50)、源漏极层(60),所述第一薄膜晶体管(100)的有源层(104)和所述第二薄膜晶体管(200)的有源层(204)位于所述半导体层(20),所述第一薄膜晶体管(100)的有源层(104)和所述第二薄膜晶体管(200)的有源层(204)为一体结构,且所述一体结构具有金属化区域,所述第一薄膜晶体管(100)的栅极(101)和所述第二薄膜晶体管(200)的栅极(201)位于所述栅极层(40),所述第一薄膜晶体管(100)的第一极(102)和所述第二薄膜晶体管(200)的第二极(203)位于所述源漏极层(60),所述第一薄膜晶体管(100)的第二极(103)和所述第二薄膜晶体管(200)的第一极(202)位于所述金属化区域;所述第一薄膜晶体管(100)的第一极(102)具有与所述第一薄膜晶体管(100)的栅极(101)重叠的第一重叠部分,所述第一重叠部分和所述第一薄膜晶体管 (100)的栅极(101)构成所述第一电容(C1),所述第一薄膜晶体管(100)的第一极(102)具有与所述金属化区域重叠的第六重叠部分,所述第六重叠部分和所述金属化区域构成第六电容(C6),所述第一薄膜晶体管(100)的第一极(102)通过第一过孔(111)与所述第一薄膜晶体管(100)的有源层(104)连接,所述第一过孔(111)穿过所述层间绝缘层(50)和所述栅极绝缘层(30);所述第二薄膜晶体管(200)的第二极(203)具有与所述第二薄膜晶体管(200)的栅极(201)重叠的第四重叠部分,所述第四重叠部分和所述第二薄膜晶体管(200)的栅极(201)构成第四电容(C4),所述第二薄膜晶体管(200)的第二极(203)具有与所述金属化区域重叠的第五重叠部分,所述第五重叠部分和所述金属化区域构成第五电容(C5),所述第二薄膜晶体管(200)的第二极(203)通过第二过孔(121)与所述第二薄膜晶体管(200)的有源层(204)连接,所述第二过孔(121)穿过所述层间绝缘层(50)和所述栅极绝缘层(30)。
- 根据权利要求4所述的阵列基板,包括:基板(10)和依次层叠在所述基板(10)上的半导体层(20)、栅极绝缘层(30)、栅极层(40)、层间绝缘层(50)、源漏极层(60),所述第一薄膜晶体管(100)的有源层(104)和所述第二薄膜晶体管(200)的有源层(204)位于所述半导体层(20),所述第一薄膜晶体管(100)的有源层(104)和所述第二薄膜晶体管(200)的有源层(204)为一体结构,且所述一体结构具有金属化区域,所述第一薄膜晶体管(100)的栅极(101)和所述第二薄膜晶体管(200)的栅极(201)位于所述栅极层(40),所述第一薄膜晶体管(100)的第一极(102)和所述第二薄膜晶体管(200)的第二极(203)位于所述源漏极层(60),所述第一薄膜晶体管(100)的第二极(103)和所述第二薄膜晶体管(200)的第一极(202)位于所述金属化区域;所述第一薄膜晶体管(100)的第一极(102)具有与所述第一薄膜晶体管(100)的栅极(101)重叠的第一重叠部分,所述第一重叠部分和所述第一薄膜晶体管(100)的栅极(101)构成所述第一电容(C1),所述第一薄膜晶体管(100)的第一极(102)的一部分位于第五过孔(151)中,所述第五过孔(151)位于所述层间绝缘层(50)且对应所述第一薄膜晶体管(100)的第二极(103)的位置,所述第一薄膜晶体管(100)的第一极(102)位于所述第五过孔(151)中的部分具有与所述金属化区域重叠的第六重叠部分,所述第六重叠部分和所 述金属化区域构成第六电容(C6),所述第一薄膜晶体管(100)的第一极(102)通过第一过孔(111)与所述第一薄膜晶体管(100)的有源层(104)连接,所述第一过孔(111)穿过所述层间绝缘层(50)和所述栅极绝缘层(30);所述第二薄膜晶体管(200)的第二极(203)具有与所述第二薄膜晶体管(200)的栅极(201)重叠的第四重叠部分,所述第四重叠部分和所述第二薄膜晶体管(200)的栅极(201)构成第四电容(C4),所述第二薄膜晶体管(200)的第二极(203)的一部分位于第六过孔(161)中,所述第六过孔(161)位于所述层间绝缘层(50)且对应所述第二薄膜晶体管(200)的第一极(202)的位置,所述第二薄膜晶体管(200)的第二极(203)位于所述第六过孔(161)中的部分具有与所述金属化区域重叠的第五重叠部分,所述第五重叠部分和所述金属化区域构成第五电容(C5),所述第二薄膜晶体管(200)的第二极(203)通过第二过孔(121)与所述第二薄膜晶体管(200)的有源层(204)连接,所述第二过孔(121)穿过所述层间绝缘层(50)和所述栅极绝缘层(30)。
- 根据权利要求6至11任一项所述的阵列基板,其中,所述半导体层(20)的材料为氧化物半导体,所述第一薄膜晶体管(100)的沟道的宽长比小于1/20且大于1/100。
- 根据权利要求1至12任一项所述的阵列基板,其中,所述第一导线(1)为栅线、数据线、静电保护线中的一种,所述第二导线(2)为栅线、数据线、静电保护线中的一种。
- 根据权利要求13所述的阵列基板,还包括第三导线、第四导线和第二静电保护单元(E2),所述第二静电保护单元(E2)连接在所述第三导线和所述第四导线之间,所述第二静电保护单元(E2)的结构与所述第一静电保护单元(E1)的结构相同。
- 根据权利要求14所述的阵列基板,其中,所述第一导线(1)为栅线,所述第二导线(2)为第一静电保护线(P1),所述第三导线为数据线,所述第四导线为第二静电保护线(P2),所述数据线与所述栅线相交,所述第一静电保护线(P1)的延伸方向与所述数据线的延伸方向相同,所述第二静电保护线(P2)的延伸方向与所述栅线的延伸方向相同。
- 根据权利要求15所述的阵列基板,其中,所述第一静电保护线(P1)与所述第二静电保护线(P2)连接。
- 根据权利要求16所述的阵列基板,其中,所述第一静电保护线(P1)与所述第二静电保护线(P2)连接至一参考电压输入端(V0)。
- 一种显示装置,包括权利要求1至17任一项所述的阵列基板。
- 一种静电保护单元,包括第一薄膜晶体管和第一电容,所述第一薄膜晶体管的栅极是悬浮的,所述第一薄膜晶体管的栅极通过所述第一电容连接至所述第一薄膜晶体管的第一极。
- 根据权利要求19所述的静电保护单元,还包括:第二电容,所述第一薄膜晶体管的栅极通过所述第二电容连接至所述第一薄膜晶体管的第二极。
- 根据权利要求19或20所述的静电保护单元,还包括:第二薄膜晶体管和第三电容,所述第二薄膜晶体管的栅极是悬浮的,所述第二薄膜晶体管的栅极通过所述第三电容连接至所述第二薄膜晶体管的第一极,所述第二薄膜晶体管的第一极与所述第一薄膜晶体管的第二极连接。
- 根据权利要求21所述的静电保护单元,还包括第四电容,所述第二薄膜晶体管的栅极通过所述第四电容连接至所述第二薄膜晶体管的第二极。
- 根据权利要求19所述的静电保护单元,还包括:第二薄膜晶体管、第四电容、第五电容和第六电容,所述第一薄膜晶体管的第一极通过所述第六电容连接至所述第一薄膜晶体管的第二极,所述第一薄膜晶体管的第二极与所述第二薄膜晶体管的第一极连接,所述第二薄膜晶体管的栅极是悬浮的,所述第二薄膜晶体管的栅极通过所述第四电容连接至所述第二薄膜晶体管的第二极,所述第二薄膜晶体管的第一极通过所述第五电容连接至所述第二薄膜晶体管的第二极。
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US20090174975A1 (en) * | 2008-01-09 | 2009-07-09 | Chunghwa Picture Tubes, Ltd. | Two-way electrostatic discharge protection circuit |
CN106024781A (zh) * | 2016-07-22 | 2016-10-12 | 京东方科技集团股份有限公司 | 静电放电器件、其制造方法及阵列基板、显示面板和装置 |
CN110061062A (zh) * | 2019-04-19 | 2019-07-26 | 深圳市华星光电半导体显示技术有限公司 | Esd防护薄膜晶体管及esd防护结构 |
CN110085584A (zh) * | 2019-04-29 | 2019-08-02 | 深圳市华星光电半导体显示技术有限公司 | Esd防护薄膜晶体管及esd防护结构 |
CN210575951U (zh) * | 2019-11-06 | 2020-05-19 | 北京京东方技术开发有限公司 | 静电保护单元及阵列基板 |
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