WO2014172970A1 - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2014172970A1
WO2014172970A1 PCT/CN2013/077355 CN2013077355W WO2014172970A1 WO 2014172970 A1 WO2014172970 A1 WO 2014172970A1 CN 2013077355 W CN2013077355 W CN 2013077355W WO 2014172970 A1 WO2014172970 A1 WO 2014172970A1
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Prior art keywords
opening
line lead
electrode
common electrode
forming
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PCT/CN2013/077355
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English (en)
French (fr)
Inventor
徐向阳
聂竹华
邓立赟
金玟秀
王凯
Original Assignee
合肥京东方光电科技有限公司
京东方科技集团股份有限公司
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Application filed by 合肥京东方光电科技有限公司, 京东方科技集团股份有限公司 filed Critical 合肥京东方光电科技有限公司
Priority to US14/361,520 priority Critical patent/US9799688B2/en
Publication of WO2014172970A1 publication Critical patent/WO2014172970A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the array substrate, and a display device including the array substrate. Background technique
  • the array substrate is divided into a display area and a peripheral area adjacent to the display area, and the display area is divided into a plurality of pixel units, and each of the pixel units is provided with a thin film transistor and a pixel electrode.
  • a drain of the thin film transistor is electrically connected to the pixel electrode through a via.
  • the metal in the via contacts the pixel electrode, a large contact resistance is generated, resulting in uneven charge distribution between the common electrode and the pixel electrode.
  • One of the objects of the present invention is to provide an array substrate, a method of manufacturing the array substrate, and a display device including the array substrate.
  • the charge distribution between the common electrode and the pixel electrode is uniform.
  • an array substrate including a display area and a peripheral area adjacent to the display area, the display area including a plurality of pixel units, each of the pixels A thin film transistor and a pixel electrode are disposed in the cell, wherein a drain of the thin film transistor is in direct contact with the pixel electrode.
  • the array substrate further includes a common electrode line
  • the pixel unit includes a common electrode
  • the common electrode is in direct contact with the common electrode line.
  • the pixel electrode includes a pixel electrode body and a connection portion protruding from the pixel electrode body, the connection portion being in direct contact with a drain of the thin film transistor.
  • connection portion is located between a drain of the thin film transistor and a gate insulating layer of the thin film transistor. In one example, the connection portion covers a portion of an upper surface of a drain of the thin film transistor.
  • the active layer of the thin film transistor includes a first portion, a second portion, and a third portion, the first portion covering at least a portion of an upper surface of a source of the thin film transistor, and the second portion is covered a portion of an upper surface of a gate insulating layer of the thin film transistor, the third portion covering at least a portion of an upper surface of a drain of the thin film transistor.
  • the peripheral region is provided with a gate line lead, a gate line lead electrode electrically connected to the gate line lead above the gate line lead, a common electrode line lead, and disposed above the common electrode line lead And a common electrode line lead electrode electrically connected to the common electrode lead, a data line lead, and a data line lead electrode disposed above the data line lead and electrically connected to the data line lead, the gate line lead and the display
  • the gate lines in the region are correspondingly electrically connected
  • the common electrode line leads are electrically connected correspondingly to the common electrode lines in the display area, the data line leads and the data lines in the display area— -
  • the gate line lead electrode, the common electrode line lead electrode and the data line lead electrode are both used for electrical connection with an external drive circuit.
  • the gate line lead, the common electrode line lead and the gate line, the common electrode line are in the same film layer; and/or the data line lead and the data line are in the same film layer.
  • the active layer of the thin film transistor is made of an oxide.
  • the oxide is an indium gallium oxide.
  • a display device comprising an array substrate, wherein the array substrate is the above array substrate provided by the present invention.
  • a method of manufacturing an array substrate comprises the following steps:
  • first set of patterns including data lines, sources and drains
  • second set of patterns the second set of patterns comprising pixel electrodes, the pixel electrodes being directly opposite the drain contact.
  • the manufacturing method further includes successive steps:
  • a fourth set of patterns is formed, the fourth set of patterns including a common electrode line that is in direct contact with the common electrode.
  • the forming the third group is performed prior to the step of forming the first set of graphics a step of patterning
  • the fourth group of patterns further includes a gate, a gate line, a gate line lead correspondingly connected to the gate line, and a common electrode line lead correspondingly connected to the common electrode line
  • the graphic also includes data line leads that are correspondingly coupled to the data lines.
  • the manufacturing method further includes the step of forming a gate insulating layer after the step of forming the fourth set of patterns, the gate insulating layer covering the fourth set of patterns.
  • the manufacturing method further includes sequentially performing the step of forming the first set of graphics:
  • the pattern of the active layer including a first portion, a second portion, and a third portion sequentially connected, the first portion covering at least a portion of an upper surface of the source, the second portion Covering a portion of an upper surface of the gate insulating layer, the third portion covering at least a portion of an upper surface of the drain;
  • a passivation layer is formed.
  • the step of forming a second set of patterns is performed after the step of forming a gate insulating layer, and the forming the first set of patterns is performed after the forming the second set of patterning steps step.
  • Forming a first opening, a second opening and a third opening on the passivation layer, wherein the first opening, the second opening and the third opening penetrate the passivation layer The first opening is located above the gate line lead, the second opening is located above the common electrode line lead, and the third opening is located above the data line lead;
  • the gate line lead electrode Electrically connecting to the gate line lead through the first opening
  • the common electrode lead electrode is electrically connected to the common electrode line lead through the second opening
  • the data line lead electrode passes through the third An opening is electrically connected to the data line lead.
  • the step of forming a passivation layer to form an opening portion on the passivation layer, and the step of forming the second group of patterns after the step of forming a passivation layer The pixel electrode covers the opening and is in direct contact with the drain.
  • the second set of patterns further includes a gate line lead electrode, a common electrode line lead electrode, and a data line lead electrode
  • the manufacturing method further includes forming the first opening, the second opening, and the first a third opening, the first opening, the second opening and the third opening are formed on the passivation layer, the first opening, the second opening and the first Each of the three openings is penetrating the passivation layer, and the first opening is located above the gate line lead, the second opening is located above the common electrode line lead, and the third opening is located at the Above the data line lead
  • the step of forming the second set of patterns is performed after the step of forming the first opening, the second opening and the third opening, such that the gate line lead electrode passes the first
  • the opening is electrically connected to the gate line lead
  • the common electrode line lead electrode is electrically connected to the common electrode line lead through the second opening
  • the data line lead electrode passes through the third opening and the The data line leads are electrically connected.
  • the pixel electrode includes a pixel electrode body and a connection portion protruding from the pixel electrode body, the connection portion being in direct contact with a drain of the thin film transistor.
  • the pixel electrode and the thin film transistor are not electrically connected through the via hole, but are directly in contact, so that contact resistance is not generated, and the charge between the common electrode and the pixel electrode can be made. Evenly distributed.
  • FIG. 1 is a plan view of a portion of a pixel unit of a first embodiment of an array substrate provided by the present invention
  • Figure 2 is a cross-sectional view taken along line C-C of Figure 1;
  • Figure 3 is a cross-sectional view taken along line D-D of Figure 1;
  • FIG. 4 is a top plan view of a portion of a peripheral region of a first embodiment of the array substrate provided by the present invention.
  • Figure 5 is a cross-sectional view taken along line A-A of Figure 4.
  • Figure 6 is a plan view showing another portion of the peripheral region of the first embodiment of the array substrate provided by the present invention.
  • Figure 7 is a cross-sectional view taken along line B-B of Figure 6;
  • Figure 8 is a process view for forming the array substrate shown in Figure 1;
  • Figure 10 is a cross-sectional view taken along line E-E of Figure 9;
  • Figure 11 is a cross-sectional view taken along line F-F of Figure 9;
  • an array substrate is provided.
  • the array substrate is divided into a display area and a peripheral area adjacent to the display area, and the display area includes a plurality of pixel units.
  • a thin film transistor and a pixel electrode 20 are disposed in each of the pixel units, and in each of the pixel units, the drain 11 of the thin film transistor is in direct contact with the pixel electrode 20.
  • a plurality of gate lines 15 (only two of which are shown) and a plurality of data lines 17 (only two of which are shown) are interleaved. And dividing the display area into a plurality of pixel units.
  • the common electrode 40 is disposed in the pixel unit, and the common electrode line 50 connects the common electrodes 40 in the same row in series to supply power to the common electrode 40 of the same row.
  • a portion of the gate line 15 serves as the gate of the thin film transistor at the same time.
  • the array substrate in the embodiment of the present invention may also include independent gate lines and gates, and the gate lines are connected to the gates. Since the pixel electrode 20 is in direct contact with the drain 11 of the thin film transistor, contact resistance is not generated between the pixel electrode 20 and the drain 11 of the thin film transistor.
  • the difference between "direct contact” and “via via connection” as described herein is that in the case where the drain 11 is "straight" with the pixel electrode 20, the thickness of the pixel electrode 20 is uniform, and In the case where the drain electrode 11 and the pixel electrode 20 are "connected through a via hole", the pixel electrode 20 is formed with a convex portion which is matched with the via hole, and the "protrusion portion” is generated. The main part of the contact resistance. In the embodiment of the present invention, there is no “protrusion” on the pixel electrode 20, so that no contact resistance is generated. In the case where no contact resistance is generated, the charge distribution on the pixel electrode 20 is relatively uniform.
  • a peripheral circuit is provided in the peripheral region, and the peripheral circuit is used to display the display area
  • the pixel cells within are electrically coupled to an external drive circuit to provide signals to pixel cells within the display region.
  • the array substrate further includes a common electrode 40 that cooperates with the pixel electrode 20.
  • the common electrode 40 directly contacts the common electrode line 50.
  • the common electrode 40 The charge distribution on the top is also relatively uniform.
  • FIGS. 1 As a first embodiment of the present invention, as shown in FIGS.
  • the pixel electrode 20 may include a pixel electrode body 21 and a connection portion 22 protruding from the pixel electrode body 21, and the connection portion 22 is disposed on the thin film transistor
  • the drain 11 is between the gate insulating layer 14 of the thin film transistor.
  • the pixel electrode 20 in this manner can be formed by the processing steps shown in FIG.
  • a method of manufacturing the array substrate according to the first embodiment will be described in detail, and will not be described herein.
  • the pixel electrode 20 includes a pixel electrode body 21 and a connection portion 22 protruding from the pixel electrode body 21, and the connection portion 22 covers the drain electrode 11 of the thin film transistor. Part of the upper surface.
  • the method of manufacturing the array substrate described in the second embodiment will be described in detail hereinafter, and will not be described herein.
  • the peripheral region is provided with a peripheral circuit including a gate line lead 63, above the gate line lead 63 and the gate.
  • a gate line lead electrode 61 electrically connected to the wire lead 63, a common electrode line lead (not shown), a common electrode line lead electrode (not shown) disposed above the common electrode line lead and electrically connected to the common electrode line lead a data line lead 73 and a data line lead electrode 71 disposed above the data line lead 73 and electrically connected to the data line lead 73.
  • the gate line lead 63 is electrically connected correspondingly to the gate line 15 in the display area.
  • the common electrode line lead is electrically connected correspondingly to the common electrode line 50 in the display area, and the data line lead 73 is electrically connected correspondingly to the data line 17 in the display area, the gate line lead electrode 61.
  • the common electrode line lead electrode and the data line lead electrode 71 are both used for electrical connection with an external driving circuit.
  • the gate line lead electrode 61, the common electrode line lead electrode, and the data line lead electrode 71 can be electrically connected to the display area after being electrically connected to the external driving circuit.
  • the electrical connection manner of the gate line lead 63 and the gate line lead electrode 61, the electrical connection manner of the common electrode lead and the common electrode lead electrode, and the electrical connection manner of the data line lead 73 and the data line lead electrode 71 There are no special regulations. For example, vias can be used for electrical connections.
  • the gate line lead 63 can also be directly in contact with the gate line lead electrode 61 to make the public power
  • the pole lead is in direct contact with the common electrode lead electrode, so that the data line lead 73 is in direct contact with the data line lead electrode 71.
  • the method of direct contact will be specifically described below, and will not be described here.
  • Power can be supplied to the pixel units in the display area through the peripheral area.
  • the gate line lead 63 and the common electrode line lead may be located in the same film layer as the gate line 15 and the common electrode line 50.
  • the data line lead 73 can be located on the same film layer as the data line 17.
  • the thin film transistor may be an etch barrier type thin film transistor.
  • the active layer 12 is located under the source 13 and the drain 11, and an etch stop layer is formed over the active layer 12, so that the source 13 and the drain 11 are prevented from being formed.
  • the source layer 12 causes damage.
  • the thin film transistor may also be a back channel etch type thin film transistor, and the active layer 12 is directly under the source 13 and the drain 11.
  • the thin film transistor manufacturing process of this structure is relatively simple.
  • the thin film transistor may be a coplanar thin film transistor.
  • the active layer 12 of the thin film transistor includes a first portion, a second portion, and a third portion, the first portion covering at least a portion of an upper surface of the source 13 of the thin film transistor, Two portions cover a portion of an upper surface of the gate insulating layer 14 of the thin film transistor, and the third portion covers at least a portion of an upper surface of the drain electrode 11 of the thin film transistor.
  • the direction "upper” described herein is described with reference to the up and down direction in Fig. 2. Since the active layer 12 is located above the source 13 and the drain 11, the formation of the source 13 and the drain 11 does not cause damage to the active layer 12. Moreover, the process for fabricating a coplanar thin film transistor is more compact than that of an etch barrier thin film transistor.
  • the active layer 12 of the thin film transistor may be made of an oxide.
  • Thin film transistors made of oxide have higher mobility.
  • the oxide may be made of indium gallium oxide (IGZO).
  • IGZO indium gallium oxide
  • the indium gallium oxide has the advantages of high uniformity, transparency, and a single process, which can better satisfy large-size liquid crystal displays and active organic electroluminescence. Device (OLED) requirements.
  • a display device comprising an array The substrate, wherein the array substrate is the above-mentioned column substrate provided by the present invention.
  • the pixel electrode 20 of the array substrate and the drain of the thin film transistor are the pixel electrode 20 of the array substrate and the drain of the thin film transistor
  • the display device may be a liquid crystal display device.
  • the manufacturing method includes the following steps:
  • first set of patterns Forming a first set of patterns, the first set of patterns comprising a data line 17, a source 13 and a drain 11; and forming a second set of patterns, the second set of patterns comprising a pixel electrode 20, the pixel electrode 20
  • the drain 11 is in direct contact.
  • the array substrate further includes a substrate substrate 30, and the first group of patterns and the second group of patterns are disposed on the substrate substrate 30.
  • the step of performing the step of forming the first group of graphics and the step of forming the second group of graphics there is no particular limitation on the step of performing the step of forming the first group of graphics and the step of forming the second group of graphics, and specifically, which step is needed first. The specific structure of the array substrate to be formed is determined.
  • the display area of the array substrate includes a plurality of pixel units, and each of the pixel units is provided with a thin film transistor and a pixel electrode 20.
  • the source 13 described herein refers to the source of the thin film transistor, and the drain 11 refers to the drain of the thin film transistor.
  • the first set of patterns may be formed by first forming a film layer and then forming the first set of patterns by a patterning process.
  • the film layer may be formed by one of various methods such as deposition, coating, sputtering, etc., and the method of forming the film layer may be selected depending on the specific material of the film layer.
  • the patterning process can generally include steps such as photoresist coating, exposure, development, etching, and photoresist stripping. It will be understood by those skilled in the art that the formation of the first set of patterns is not limited to the above steps, and may be formed by other processes such as transfer.
  • the steps of forming the second set of graphics are similar to the steps of forming the first set of graphics, and are not described here.
  • the common electrode 40 and the pixel electrode 20 are located on the same substrate substrate 30. Therefore, the method for manufacturing the array substrate further includes: Forming a third set of patterns, the third set of patterns including the common electrode 40; and
  • a fourth set of patterns is formed, the fourth set of patterns including a common electrode line 50 that is in direct contact with the common electrode 40.
  • the common electrode 40 is in direct contact with the substrate substrate 30, and therefore, in the manufacture of the array substrate, the step of forming the third group of patterns is first performed.
  • the steps of forming the third set of patterns are not necessary when fabricating the array substrate. Because, in some display devices, the common electrode is located on the array substrate, a step of forming a third set of patterns is required.
  • the display device provided by the embodiment of the present invention belongs to this structure. In some display devices, the common electrode is located on the color filter substrate (opposing substrate), and at this time, the step of forming the third group of patterns is not required when manufacturing the array substrate.
  • the fourth layer pattern further includes a gate, a gate line 15, a gate line lead 63 electrically connected to the gate line 15 , and a common electrode line lead electrically connected to the common electrode line 50
  • the first The group graphics may also include data line leads 73 that are electrically coupled to the data lines 17.
  • a portion of the gate line 15 serves as the gate of the thin film transistor.
  • the array substrate further includes a peripheral region adjacent to the display region, and the gate line leads 63, the common electrode line leads, and the data line leads 73 are part of peripheral circuits in the peripheral region.
  • the roles of the gate line lead 63, the common electrode line lead, and the data line lead 73 have been described above, and will not be described again here.
  • the method of fabricating the array substrate further includes the step of forming a gate insulating layer after the step of forming the fourth group of patterns, the gate insulating layer 14 covering the fourth group of patterns.
  • the thin film transistors in the array substrate disclosed in the first embodiment and the second embodiment of the present invention are all coplanar type thin film transistors. Therefore, the method of manufacturing the array substrate further includes forming the first The steps of the group graphics are followed by:
  • the active layer 12 includes a first portion, a second portion, and a third portion that are sequentially connected, the first portion covering at least a portion of an upper surface of the source electrode 13, and the second portion covering a gate insulating layer a portion of the upper surface of layer 14, the third portion covering at least a portion of the upper surface of drain 11; and forming passivation layer 16.
  • the step of forming a gate insulating layer is performed first, then the step of forming a second group of patterns is performed, and the second group of patterns is formed.
  • Shape The step of forming the first set of graphics is performed after the step (as shown in FIG. 8, but only the order of some of the steps is shown in FIG. 8). Fabricating the array substrate in the above order may cause a portion of the pixel electrode 20 to be disposed between the gate insulating layer 14 and the drain 11.
  • the passivation layer 16 is located above the pixel electrode 20, and therefore, the manufacturing method is further performed after the step of forming the passivation layer:
  • first opening 62, a second opening, and a third opening 72 in the passivation layer 16 are both penetrating the passivation layer 16, and first
  • the opening 62 is located above the gate line lead 63
  • the second opening is located above the common electrode line lead
  • the third opening 72 is located above the data line lead 73;
  • a gate line I line electrode 61, a common electrode line I line electrode, and a data line I line electrode 71 are formed on the passivation layer 16, and the gate line lead electrode 61 is electrically connected to the gate line lead 63 through the first opening 62, the common The electrode lead electrode is electrically connected to the common electrode line lead through the second opening, and the data line lead electrode 71 is electrically connected to the data line lead 73 through the third opening 72.
  • the gate line lead electrode 61, the common electrode lead electrode, and the data line lead electrode 71 are also part of the peripheral circuit, which has been described in detail above and will not be described herein.
  • the first opening 62 formed should reach the gate line lead 63, i.e., the first opening 62 should penetrate the gate insulating layer 14 in addition to the passivation layer 16.
  • the second opening should also reach the common electrode lead. Since the common electrode lead and the gate lead 63 are located in the same film layer, the second opening should also penetrate the gate insulating layer 14.
  • the third opening 72 should reach the data line lead 73. In the embodiment of the present invention, the data line lead 73 is located above the gate insulating layer, and therefore, the third opening 72 penetrates the passivation layer 16.
  • the first opening 62 has a sufficiently large cross-sectional area such that the thickness of the portion of the gate line lead electrode 61 located in the first opening 62 and the portion of the gate line lead electrode 61 located outside the first opening 62 The thickness is consistent. This arrangement can avoid contact resistance between the gate line lead electrode 61 and the gate line lead 63.
  • the second opening should also have a sufficiently large cross-sectional area, such that the thickness of the portion of the common electrode line lead located in the second opening and the common electrode line are located in the second opening
  • the outer portions have the same thickness.
  • the third opening 72 may also have a sufficiently large cross-sectional area such that the thickness of the portion of the data line lead 73 located in the third opening 72 and the portion of the data line lead 73 located outside the third opening 72. The thickness of the points is the same.
  • the steps of the manufacturing method of the first embodiment of the present invention are as follows: a step of providing a village substrate; a step of forming a fourth group of patterns; a step of forming a second group of patterns; a step of forming a first group of patterns; a step of forming a pattern of the active layer; a step of forming a passivation layer; forming a first opening, a second opening a step of forming a hole and a third opening; and forming a gate line lead electrode, a common electrode line lead electrode, and a data line lead electrode.
  • Forming the array substrate according to the first embodiment of the present invention requires a total of seven steps of patterning process steps. According to this manufacturing method, the array substrate shown in Figs. 1 to 7 can be obtained.
  • the step of forming the second group of patterns may be performed after the step of forming the passivation layer.
  • the passivation layer 16 formed in the step of forming the passivation layer should have an opening portion, and the pixel electrode 20 formed in the step of forming the second group pattern is covered by the opening portion Pole 11 is in direct contact.
  • the "opening portion" described herein needs to have a large cross-sectional area to ensure that the thickness of the portion of the pixel electrode 20 covering the opening portion can coincide with the thickness of other portions of the pixel electrode 20.
  • the opening portion has a large cross-sectional area, and therefore, the passivation layer having the opening portion can be directly formed, or the opening portion can be formed on the passivation layer 16 after the passivation layer is formed.
  • the second group of patterns may further include a gate line lead electrode, a common electrode line lead electrode, and a data line lead electrode.
  • the second group of patterns may further include a gate line lead electrode, a common electrode line lead electrode, and a data line lead electrode, that is, may be formed while forming the pixel electrode 20. a gate line lead electrode, a common electrode line lead electrode, and a data line lead electrode.
  • the manufacturing method further includes forming a first opening, a second opening, and a third opening, the first opening, the first The second opening and the third opening are formed on the passivation layer, and the first opening, the second opening and the third opening respectively penetrate the passivation layer, and the a first opening is located above the gate line lead, the second opening is located above the common electrode line lead, and the third opening is located above the data line lead, the forming a second group of graphics
  • the gate line lead electrode is electrically connected to the gate line lead through the first opening
  • the common electrode line lead electrode is electrically connected to the common electrode line lead through the second opening
  • the data line lead electrode is electrically connected to the data line lead through the third opening.
  • the first opening should penetrate the gate insulating layer 14 in addition to the passivation layer 16; the second opening penetrates through the passivation layer. 16th, should also penetrate the gate insulating layer 14; the third opening penetrates through the passivation layer 16.
  • the opening portion may be formed while forming the first opening, the second opening, and the third opening.
  • the steps of the manufacturing method of the second embodiment of the present invention are as follows: a step of providing a substrate substrate; a step of forming a third group of patterns; a fourth set of patterns; a step of forming a gate insulating layer; a step of forming a first set of patterns; a step of forming a pattern of the active layer; a step of forming a passivation layer; forming a first opening, a second opening a step of the hole, the third opening and the opening; forming a step like the second set of figures.
  • Forming the array substrate of the first embodiment of the present invention requires a total of six step patterning process steps. According to this method, the array substrate shown in Figs. 9 to 11 can be obtained.
  • the manufacturing method of the second embodiment eliminates the step of the one-step photolithography process as compared with the first embodiment.
  • the pixel electrode 20 formed in the step of forming the second group of patterns includes the pixel electrode body 21 and the connecting portion 22 protruding from the pixel electrode body 21, and the connecting portion 22 is in direct contact with the drain electrode 11.
  • the process steps are single, and the electric field between the array substrate common electrode 40 and the pixel electrode 20 can be distributed relatively uniformly.

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Abstract

一种阵列基板及其制造方法和显示装置，该阵列基板包括显示区和与所述显示区邻接的周边区，所述显示区包括多个像素单元，每个所述像素单元内都设置有薄膜晶体管和像素电极（20），其中，所述薄膜晶体管的漏极（11）与所述像素电极（20）直接接触。在该阵列基板中，像素电极（20）与薄膜晶体管的漏极（11）之间直接接触，从而不会产生接触电阻，可以使得公共电极（40）和像素电极（20）之间电场均匀分布。

Description

阵列基板及其制造方法和显示装置 技术领域
本发明的实施例涉及一种阵列基板、 该阵列基板的制造方法和包括所述 阵列基板的显示装置。 背景技术
阵列基板分为显示区和与所述显示区邻接的周边区， 所述显示区被划分 为多个像素单元， 每个所述像素单元内都设置有薄膜晶体管和像素电极。 在 每个所述像素单元内， 所述薄膜晶体管的漏极与所述像素电极通过过孔电连 接。 但是， 过孔内的金属与像素电极相接触时会产生较大的接触电阻， 从而 造成公共电极和像素电极之间电荷分布不均匀。
因此， 如何使公共电极和像素电极之间电荷均匀分布成为本领域亟待解 决的技术问题。 发明内容
本发明的目的之一在于提供一种阵列基板、 该阵列基板的制造方法以及 包括所述阵列基板的显示装置。 在所述阵列基板中， 公共电极与像素电极之 间电荷分布均匀。
为了实现上述目的， 作为本发明的一个方面， 提供一种阵列基板， 该阵 列基板包括显示区和与所述显示区邻接的周边区， 所述显示区包括多个像素 单元， 每个所述像素单元内都设置有薄膜晶体管和像素电极， 其中， 所述薄 膜晶体管的漏极与所述像素电极直接接触。
在一个示例中， 所述阵列基板还包括公共电极线， 所述像素单元包括公 共电极， 所述公共电极与所述公共电极线直接接触。
在一个示例中， 所述像素电极包括像素电极本体和从所述像素电极本体 上突出的连接部， 所述连接部与所述薄膜晶体管的漏极直接接触。
在一个示例中， 所述连接部位于所述薄膜晶体管的漏极与所述薄膜晶体 管的栅极绝缘层之间。 在一个示例中， 所述连接部覆盖所述薄膜晶体管的漏极的上表面的一部 分。
在一个示例中， 所述薄膜晶体管的有源层包括第一部分、 第二部分和第 三部分， 所述第一部分覆盖所述薄膜晶体管的源极的上表面的至少一部分， 所述第二部分覆盖所述薄膜晶体管的栅极绝缘层的上表面的一部分， 所述第 三部分覆盖所述薄膜晶体管的漏极的上表面的至少一部分。
在一个示例中， 所述周边区设置有栅线引线、 在所述栅线引线的上方与 该栅线引线电连接的栅线引线电极、 公共电极线引线、 设置在所述公共电极 线引线上方且与该公共电极引线电连接的公共电极线引线电极、 数据线引线 和设置在所述数据线引线上方且与该数据线引线电连接的数据线引线电极， 所述栅线引线与所述显示区内的栅线——对应地电连接， 所述公共电极线引 线与所述显示区内的公共电极线——对应地电连接， 所述数据线引线与所述 显示区内的数据线——对应地电连接， 所述栅线引线电极、 公共电极线引线 电极和数据线引线电极均用于与外部驱动电路电连接。
在一个示例中， 所述栅线引线、 公共电极线引线与所述栅线、 所述公共 电极线在同一膜层； 和 /或所述数据线引线与所述数据线在同一膜层。
在一个示例中， 所述薄膜晶体管的有源层由氧化物制成。
在一个示例中， 所述氧化物为铟镓辞氧化物。
作为本发明的另一个方面， 还提供一种显示装置， 所述显示装置包括阵 列基板， 其中， 所述阵列基板为本发明所提供的上述阵列基板。
作为本发明的再一个方面， 还提供一种阵列基板的制造方法， 其中， 所 述制造方法包括以下步骤：
形成第一组图形， 该第一组图形包括数据线、 源极和漏极； 和 形成第二组图形， 该第二组图形包括像素电极， 该像素电极与所述漏极 直接接触。
在一个示例中， 所述制造方法还包括先后进行的：
形成第三组图形， 该第三组图形包括公共电极； 和
形成第四组图形， 该第四组图形包括公共电极线， 该公共电极线与所述 公共电极直 触。
在一个示例中， 在所述形成第一组图形的步骤之前进行所述形成第三组 图形的步骤， 所述第四组图形还包括栅极、 栅线、 与所述栅线对应连接的栅 线引线和与所述公共电极线对应连接的公共电极线引线， 所述第一组图形还 包括与所述数据线对应连接的数据线引线。
在一个示例中， 所述制造方法还包括在所述形成第四组图形的步骤后进 行的形成栅极绝缘层的步骤， 所述栅极绝缘层覆盖所述第四组图形。
在一个示例中， 所述制造方法还包括在所述形成第一组图形的步骤之后 依次进行的：
形成有源层的图形， 所述有源层的图形包括依次连接的第一部分、 第二 部分和第三部分， 所述第一部分覆盖所述源极的上表面的至少一部分， 所述 第二部分覆盖所述栅极绝缘层的上表面的一部分， 所述第三部分覆盖所述漏 极的上表面的至少一部分； 和
形成钝化层。
在一个示例中， 在所述形成栅极绝缘层的步骤之后进行所述形成第二组 图形的步骤， 并在所述形成第二组图形步骤之后进行所述形成第一组图形的 步骤。 在所述钝化层上形成第一开孔、 第二开孔和第三开孔， 所述第一开孔、 所述第二开孔和所述第三开孔均贯穿所述钝化层， 所述第一开孔位于所述栅 线引线上方， 所述第二开孔位于所述公共电极线引线上方， 所述第三开孔位 于所述数据线引线上方； 和
在形成有所述第一开孔、 所述第二开孔和所述第三开孔的钝化层形成栅 线引线电极、 公共电极线引线电极和数据线引线电极， 所述栅线引线电极通 过所述第一开孔与所述栅线引线电连接， 所述公共电极引线电极通过所述第 二开孔与所述公共电极线引线电连接， 所述数据线引线电极通过所述第三开 孔与所述数据线引线电连接。
在一个示例中， 所述形成钝化层的步骤后在所述钝化层上形成开口部的 步骤， 在所述形成钝化层的步骤之后进行所述形成所述第二组图形的步骤， 所述像素电极覆盖所述开口部与所述漏极直接接触。
在一个示例中， 所述第二组图形还包括栅线引线电极、 公共电极线引线 电极和数据线引线电极， 所述制造方法还包括形成第一开孔、 第二开孔和第 三开孔，所述第一开孔、所述第二开孔和所述第三开孔形成在所述钝化层上， 所述第一开孔、 所述第二开孔和所述第三开孔均贯穿所述钝化层， 且所述第 一开孔位于所述栅线引线上方，所述第二开孔位于所述公共电极线引线上方， 所述第三开孔位于所述数据线引线上方， 所述形成第二组图形的步骤在所述 形成第一开孔、 第二开孔和第三开孔的步骤之后进行， 使得所述栅线引线电 极通过所述第一开孔与所述栅线引线电连接， 所述公共电极线引线电极通过 所述第二开孔与所述公共电极线引线电连接， 所述数据线引线电极通过所述 第三开孔与所述数据线引线电连接。
在一个示例中， 所述像素电极包括像素电极本体和从所述像素电极本体 上突出的连接部， 所述连接部与所述薄膜晶体管的漏极直接接触。
在本发明实施例所提供的阵列基板中， 像素电极与薄膜晶体管之间并未 通过过孔电连接， 而是直接接触， 从而不会产生接触电阻， 可以使得使公共 电极和像素电极之间电荷均匀分布。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1是本发明提供的阵列基板的第一种实施方式的像素单元的一部分的 俯视图；
图 2是图 1的 C-C剖视图；
图 3是图 1的 D-D剖视图；
图 4是本发明提供的阵列基板的第一种实施方式的周边区的一部分的俯 视图；
图 5是图 4的 A-A剖视图；
图 6是本发明提供的阵列基板的第一种实施方式的周边区的另一部分的 俯视图；
图 7是图 6的 B-B剖视图；
图 8是形成图 1中所示的阵列基板的工序图；
图 9是本发明提供的阵列基板的第二种实施方式的像素单元的一部分的 俯视图；
图 10是图 9的 E-E剖视图；
图 11是图 9的 F-F剖视图；
图 12是本发明所提供的阵列基板的制造方法的流程图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
如图 1至图 11中所示，作为本发明的一个方面，提供一种阵列基板， 该 阵列基板分为显示区和与该显示区邻接的周边区， 所述显示区包括多个像素 单元， 每个所述像素单元内都设置有薄膜晶体管和像素电极 20, 其中， 在每 个所述像素单元内， 所述薄膜晶体管的漏极 11与像素电极 20直接接触。
如图 1所示，在所述显示区内，多条栅线 15 (图中仅示出了其中的两条） 和多条数据线 17 (图中仅示出了其中的两条）互相交错， 将所述显示区划分 为多个像素单元。 公共电极 40设置在所述像素单元内， 并且公共电极线 50 将位于同一行的公共电极 40串联， 以向同一行的公共电极 40供电。
本发明实施例中， 栅线 15的一部分同时作为薄膜晶体管的栅极。 当然， 本发明实施例中的阵列基板也可以包括独立的栅线和栅极， 栅线与栅极相连 接。 由于像素电极 20与薄膜晶体管的漏极 11之间直接接触， 所以像素电极 20和薄膜晶体管的漏极 11之间不会产生接触电阻。 应当理解的是， 此处所 述的 "直接接触" 与 "通过过孔连接" 的区别在于， 在漏极 11 与像素电极 20 "直 触" 的情况中， 像素电极 20的厚度均匀一致， 而在漏极 11与像 素电极 20 "通过过孔连接" 的情况中， 像素电极 20上形成有凸出部， 该凸 出部与所述过孔相匹配， 而此 "凸出部" 则是产生接触电阻的主要部分。 在 本发明实施例中， 像素电极 20上并没有 "凸出部" ， 因此也不会产生接触电 阻。 在没有接触电阻产生的情况下， 像素电极 20上的电荷分布较为均匀。
在阵列基板中， 在周边区内设置有周边电路， 该周边电路用于将显示区 内的像素单元与外部驱动电路电连接，从而向显示区内的像素单元提供信号。 阵列基板还包括与像素电极 20相配合的公共电极 40, 在本发明实施例 中，如图 3和图 11中所示，公共电极 40直接与公共电极线 50相接触，同理， 共电极 40上的电荷分布得也比较均匀。 作为本发明的第一种实施方式，如图 1和图 2所示，像素电极 20可以包 括像素电极本体 21和从像素电极本体 21上突出的连接部 22, 连接部 22设 置在所述薄膜晶体管的漏极 11与所述薄膜晶体管的栅极绝缘层 14之间。 可 以通过图 8中所示的加工步骤形成这种方式的像素电极 20。下文中将对第一 种实施方式所述的阵列基板的制造方法进行详细的介绍， 这里先不赘述。
作为本发明的第二种实施方式， 如图 9和图 10所示， 像素电极 20包括 像素电极本体 21和从像素电极本体 21上突出的连接部 22, 连接部 22覆盖 薄膜晶体管的漏极 11的上表面的一部分。 同样地，下文中将对第二种实施方 式所述的阵列基板的制造方法进行详细的介绍， 这里先不赘述。
在本发明实施例所提供的阵列基板中， 如图 4至图 7所示， 所述周边区 设置有周边电路， 该周边电路包括栅线引线 63、 在该栅线引线 63的上方与 该栅线引线 63电连接的栅线引线电极 61、 公共电极线引线（未示出） 、 设 置在该公共电极线引线上方且与该公共电极线引线电连接的公共电极线引线 电极（未示出） 、 数据线引线 73和设置在该数据线引线 73上方且与该数据 线引线 73电连接的数据线引线电极 71 ,栅线引线 63与所述显示区内的栅线 15——对应地电连接，所述公共电极线引线与所述显示区内的公共电极线 50 ——对应地电连接， 数据线引线 73与所述显示区内的数据线 17——对应地 电连接， 栅线引线电极 61、 公共电极线引线电极和数据线引线电极 71均用 于与外部驱动电路电连接。 栅线引线电极 61、公共电极线引线电极和数据线 引线电极 71与外部驱动电路电连接之后， 可以向所述显示区供电。
在本发明实施例中， 对栅线引线 63与栅线引线电极 61的电连接方式、 公共电极引线与公共电极引线电极的电连接方式以及数据线引线 73 与数据 线引线电极 71的电连接方式并没有特殊的规定。例如，可以利用过孔进行电 连接。 当然， 也可以使栅线引线 63与栅线引线电极 61直接接触， 使公共电 极引线与公共电极引线电极直 触， 使数据线引线 73 与数据线引线电极 71直接接触。 下文中将具体介绍直接接触的方法， 这里先不赘述。
本领域技术人员应当理解的是， 此处所述的方向 "上" 是以图 5和图 7 中的上下方向为基准进行描述的。
通过所述周边区可以向所述显示区内的像素单元进行供电。
为了便于制造， 在本发明实施例中， 栅线引线 63、 公共电极线引线可以 与栅线 15以及公共电极线 50位于同一膜层。 同样地，数据线引线 73可以与 数据线 17位于同一膜层。
在本发明实施例中， 对薄膜晶体管的具体结构并没有特殊要求， 例如， 所述薄膜晶体管可以是刻蚀阻挡型薄膜晶体管。 在这种结构的晶体管中， 有 源层 12位于源极 13和漏极 11下方， 在有源层 12上方形成有刻蚀阻挡层， 从而可以避免在形成源极 13和漏极 11是对有源层 12造成损坏。
所述薄膜晶体管还可以是背沟道刻蚀型薄膜晶体管，有源层 12直接位于 源极 13和漏极 11下方。 这种结构的薄膜晶体管制造工艺流程比较筒单。
在一个示例中，所述薄膜晶体管可以为共面型薄膜晶体管。如图 2所示， 所述薄膜晶体管的有源层 12包括第一部分、第二部分和第三部分，所述第一 部分覆盖所述薄膜晶体管的源极 13的上表面的至少一部分,所述第二部分覆 盖所述薄膜晶体管的栅极绝缘层 14的上表面的一部分,所述第三部分覆盖所 述薄膜晶体管的漏极 11的上表面的至少一部分。应当理解的是，此处所述的 方向 "上"是以图 2中的上下方向为基准进行描述的。 由于有源层 12位于源 极 13和漏极 11的上方，因此形成源极 13和漏极 11并不会对有源层 12造成 破坏。 并且， 与刻蚀阻挡型薄膜晶体管相比， 制造共面型薄膜晶体管的工艺 流程更加筒单。
例如，所述薄膜晶体管的有源层 12可以由氧化物制成。利用氧化物制成 的薄膜晶体管具有较高的迁移率。
具体地， 所述氧化物可以包括铟镓辞氧化物（IGZO )制成。 除了可以使 得所述薄膜晶体管具有较高的迁移率，铟镓辞氧化物还具有均匀性高、透明、 制作工艺筒单等优点， 可以更好地满足大尺寸液晶显示器和有源有机电致发 光器件（OLED ) 的需求。
作为本发明的另一个方面， 提供一种显示装置， 该液显示装置包括阵列 基板， 其中， 所述阵列基板为本发明所提供的上述列基板。
在所述显示装置中， 由于阵列基板的像素电极 20 与薄膜晶体管的漏极
11之间直接接触， 从而不会产生接触电阻， 并且公共电极 40直接与公共电 阻。 这使得所述阵列基板的公共电极 40和像素电极 20之间电场分布比较均 匀， 进而使得所述显示装置具有良好的显示效果。 作为本发明的一种实施方 式， 所述显示装置可以是液晶显示装置。
作为本发明的再一个方面， 还提供一种阵列基板的制造方法， 如图 12 所示， 所述制造方法包括以下步骤：
形成第一组图形， 该第一组图形包括数据线 17、 源极 13和漏极 11 ; 和 形成第二组图形， 该第二组图形包括像素电极 20, 该像素电极 20与漏 极 11直接接触。
应当理解的是， 所述阵列基板还包括村底基板 30, 所述第一组图形以及 所述第二组图形都是设置在村底基板 30上的。并且，在本发明实施例中对进 行所述形成所述第一组图形的步骤以及所述形成所述第二组图形的步骤的顺 序并没有特殊的限定， 具体先进行哪一步需要根据待形成的阵列基板的具体 结构进行确定。
本领域技术人员还应理解的是，阵列基板的显示区内包括多个像素单元， 每个像素单元内都设置有薄膜晶体管和像素电极 20。 此处所述的源极 13是 指薄膜晶体管的源极， 漏极 11是指薄膜晶体管的漏极。
作为本发明的一种实施方式， 可以通过以下方式形成所述第一组图形： 首先形成一层膜层，然后通过构图工艺形成所述第一组图形。可以利用沉积、 涂敷、 溅射等多种方式中的一种来形成所述膜层， 可以根据膜层的具体材料 来选择膜层的形成方法。 构图工艺通常可以包括光刻胶涂敷、 曝光、 显影、 刻蚀和光刻胶剥离等步骤。 本领域技术人员应当理解的是， 形成所述第一组 图形并不限于上述步骤， 还可以通过其他工艺例如转印等步骤形成。
形成所述第二组图形的步骤与形成所述第一组图形的步骤相似， 这里不 再赘述。
在本发明所提供的实施方式中， 公共电极 40和像素电极 20位于同一个 村底基板 30上。 因此， 所述阵列基板的制造方法还包括先后进行的： 形成第三组图形， 该第三组图形包括公共电极 40; 和
形成第四组图形， 该第四组图形包括公共电极线 50, 该公共电极线 50 与公共电极 40直接接触。
通常， 公共电极 40与村底基板 30直接接触， 因此， 在制造所述阵列基 板时， 首先进行所述形成第三组图形的步骤。
本领域技术人员应当理解的是， 在制造阵列基板时， 所述形成第三组图 形的步骤并不是必须的。 因为， 在有些显示装置中， 公共电极位于阵列基板 上， 此时需要进行形成第三组图形的步骤。 本发明实施例所提供的显示装置 便属于这种结构。 而在有些显示装置中， 公共电极位于彩膜基板 (相对基板) 上， 此时， 在制造阵列基板时便不需要进行所述形成第三组图形的步骤。
为了便于制造， 所述第四层图形还包括栅极、 栅线 15、 与栅线 15对应 电连接的栅线引线 63以及与公共电极线 50对应电连接的公共电极线引线， 所述第一组图形还可以包括与数据线 17对应电连接的数据线引线 73。 在本 发明所提供的实施方式中，栅线 15的一部分充当了薄膜晶体管的栅极。栅线 15为多条， 数据线 17为多条， 栅线 15和数据线 17相交， 将阵列基板的村 底基板 30划分为多个像素单元。如上文中所述， 阵列基板还包括与显示区邻 接的周边区， 栅线引线 63、 公共电极线引线和数据线引线 73是周边区中的 周边电路的一部分。 上文中已经介绍了栅线引线 63、 公共电极线引线和数据 线引线 73的作用， 这里不再赘述。
通常， 所述阵列基板的制造方法还包括在所述形成第四组图形的步骤后 进行的形成栅极绝缘层的步骤， 所述栅极绝缘层 14覆盖所述第四组图形。
在本发明的第一种实施方式和第二种实施方式中所公开的阵列基板中的 薄膜晶体管均为共面型薄膜晶体管， 因此， 所述阵列基板的制造方法还包括 在形成所述第一组图形的步骤之后依次进行的：
形成有源层的图形，有源层 12包括依次连接的第一部分、第二部分和第 三部分，所述第一部分覆盖源极 13的上表面的至少一部分，所述第二部分覆 盖栅极绝缘层 14的上表面的一部分， 所述第三部分覆盖漏极 11的上表面的 至少一部分； 和形成钝化层 16。
在形成图 1至图 8中所示的阵列基板时， 需要先进行所述形成栅极绝缘 层的步骤， 后进行所述形成第二组图形的步骤， 并且在所述形成第二组图形 的步骤之后再进行所述形成第一组图形的步骤（如图 8中所示， 但图 8中仅 示出了其中部分步骤的先后顺序） 。 按照上述顺序制造阵列基板可以使得像 素电极 20的一部分设置在栅极绝缘层 14和漏极 11之间。
在这种情况下， 钝化层 16位于像素电极 20的上方， 因此， 所述制造方 法还包括在所述形成钝化层的步骤后进行：
在钝化层 16上形成第一开孔 62、第二开孔和第三开孔 72,第一开孔 62、 第二开孔和第三开孔 72均贯穿钝化层 16, 且第一开孔 62位于栅线引线 63 上方，所述第二开孔位于所述公共电极线引线上方，第三开孔 72位于数据线 引线 73上方； 和
在钝化层 16上形成栅线 I线电极 61、 公共电极线 I线电极和数据线 I 线电极 71 , 栅线引线电极 61通过第一开孔 62与栅线引线 63电连接， 所述 公共电极引线电极通过所述第二开孔与所述公共电极线引线电连接， 数据线 引线电极 71通过第三开孔 72与数据线引线 73电连接。 栅线引线电极 61、 公共电极引线电极和数据线引线电极 71也是周边电路的一部分，上文中已经 进行了详细的描述， 这里不再赘述。
应当理解的是， 形成的第一开孔 62应当到达栅线引线 63 , 即， 第一开 孔 62除了贯穿钝化层 16之外， 还应贯穿栅极绝缘层 14。 同样地， 所述第二 开孔也应当到达所述公共电极引线，由于公共电极引线与栅线引线 63位于同 一膜层， 所以， 所述第二开孔也应当贯穿栅极绝缘层 14。 同样地， 第三开孔 72应当到达数据线引线 73。 在本发明的实施方式中， 数据线引线 73位于栅 极绝缘层的上方， 因此， 第三开孔 72贯穿钝化层 16。
在本发明中，第一开孔 62具有足够大的横截面积可以使得栅线引线电极 61位于第一开孔 62中的部分的厚度与栅线引线电极 61位于第一开孔 62外 部的部分的厚度一致。 这样设置可以避免栅线引线电极 61和栅线引线 63之 间产生接触电阻。
同理， 所述第二开孔也应当具有足够大的横截面积， 可以使得公共电极 线引线位于所述第二开孔中的部分的厚度与所述公共电极线位于所述第二开 孔外的部分的厚度一致。
同理， 第三开孔 72也可以具有足够大的横截面积， 使得数据线引线 73 位于第三开孔 72中的部分的厚度与数据线引线 73位于第三开孔 72外部的部 分的厚度一致。
当然， 也可以使用过孔将栅线引线电极 61与栅线引线 63电连接， 使用 线电极 71与数据线引线 73电连接。
综上所述，本发明的第一种实施方式的制造方法的步骤（如图 12中左侧 部分所示） 的顺序为： 提供村底基板的步骤； 形成第四组图形的步骤； 形成 栅极绝缘层的步骤； 形成第二组图形的步骤； 形成第一组图形的步骤； 形成 有源层的图形的步骤； 形成钝化层的步骤； 形成第一开孔、 第二开孔和第三 开孔的步骤； 形成栅线引线电极、 公共电极线引线电极和数据线引线电极的 步骤。形成本发明第一种实施方式所述的阵列基板共需要 7步构图工艺步骤。 按照该制造方法可以获得图 1至图 7中所示的阵列基板。
在形成图 9至图 11中所示的阵列基板时，可以在所述形成钝化层的步骤 之后进行所述形成第二组图形的步骤。 当然， 在所述形成钝化层的步骤中形 成的钝化层 16上应当具有开口部，在所述形成第二组图形的步骤中形成的像 素电极 20通过覆盖所述开口部而与漏极 11直接接触。 需要指出的是， 此处 所述的 "开口部"需要具有较大的横截面积， 以确保像素电极 20覆盖开口部 的部分的厚度可以与像素电极 20的其他部分的厚度一致。如上所述，所述开 口部具有较大的横截面积， 因此， 可以直接形成具有开口部的钝化层， 或者 在形成钝化层后， 再在钝化层 16上开设所述开口部。
同样地，在图 9至图 11中所示的第二种实施方式中，所述第二组图形还 可以包括栅线引线电极、 公共电极线引线电极和数据线引线电极。 为了筒化 制造阵列基板的工艺步骤， 优选地， 所述第二组图形还可以包括栅线引线电 极、 公共电极线引线电极和数据线引线电极， 即， 可以在形成像素电极 20 的同时形成栅线引线电极、 公共电极线引线电极和数据线引线电极。
因此， 在本发明所述的第二种实施方式的制造方法中， 所述制造方法还 包括形成第一开孔、 第二开孔和第三开孔， 所述第一开孔、 所述第二开孔和 所述第三开孔形成在所述钝化层上， 所述第一开孔、 所述第二开孔和所述第 三开孔均贯穿所述钝化层， 且所述第一开孔位于所述栅线引线上方， 所述第 二开孔位于所述公共电极线引线上方， 所述第三开孔位于所述数据线引线上 方， 所述形成第二组图形的步骤在所述形成第一开孔、 第二开孔和第三开孔 的步骤之后进行， 使得所述栅线引线电极通过所述第一开孔与所述栅线引线 电连接， 所述公共电极线引线电极通过所述第二开孔与所述公共电极线引线 电连接， 所述数据线引线电极通过所述第三开孔与所述数据线引线电连接。
与第一种实施方式中相似， 应当理解的是， 所述第一开孔除了贯穿钝化 层 16之夕卜，还应贯穿栅极绝缘层 14;所述第二开孔除了贯穿钝化层 16之夕卜， 也应当贯穿栅极绝缘层 14; 所述第三开孔贯穿钝化层 16。
第一开孔、 第二开孔和第三开孔的设置方式以及横截面积大小均可以与 第一种实施方式中的相同， 这里不再赘述。 在本实施方式中， 可以在形成所 述第一开孔、 所述第二开孔和所述第三开孔的同时形成所述开口部。
综上所述，本发明的第二种实施方式的制造方法的步骤（如图 12中左侧 部分所示） 的顺序为： 提供村底基板的步骤； 形成第三组图形的步骤； 形成 第四组图形的步骤； 形成栅极绝缘层的步骤； 形成第一组图形的步骤； 形成 有源层的图形的步骤； 形成钝化层的步骤； 形成第一开孔、 第二开孔、 第三 开孔和开口部的步骤； 形成像第二组图形的步骤。 形成本发明第一种实施方 式所述的阵列基板共需要 6步构图工艺步骤。 按照这种方法可以获得图 9至 图 11中所示的阵列基板。
由此可知， 与第一种实施方式相比， 第二种实施方式的制造方法省去了 一步光刻工艺的步骤。
应当理解的是,在形成第二组图形的步骤中形成的像素电极 20包括像素 电极本体 21和从该像素电极本体 21上突出的连接部 22, 该连接部 22与漏 极 11直接接触。
本发明实施例所述的阵列基板的制造方法工艺步骤筒单， 且制得的阵列 基板公共电极 40和像素电极 20之间电场可以分布的比较均匀。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种阵列基板，该阵列基板包括显示区和与所述显示区邻接的周边区， 所述显示区包括多个像素单元， 每个所述像素单元内都设置有薄膜晶体管和 像素电极， 其中， 所述薄膜晶体管的漏极与所述像素电极直接接触。
2、根据权利要求 1所述的阵列基板，还包括公共电极线， 所述像素单元 包括公共电极， 所述公共电极与所述公共电极线直接接触。
3、根据权利要求 1或 2所述的阵列基板， 其中， 所述像素电极包括像素 电极本体和从所述像素电极本体上突出的连接部， 所述连接部与所述薄膜晶 体管的漏极直接接触。
4、根据权利要求 3所述的阵列基板， 其中， 所述连接部位于所述薄膜晶 体管的漏极与所述薄膜晶体管的栅极绝缘层之间。
5、根据权利要求 3所述的阵列基板， 其中， 所述连接部覆盖所述薄膜晶 体管的漏极的上表面的一部分。
6、根据权利要求 1至 5中任意一项所述的阵列基板， 其中， 所述薄膜晶 体管的有源层包括第一部分、 第二部分和第三部分， 所述第一部分覆盖所述 薄膜晶体管的源极的上表面的至少一部分， 所述第二部分覆盖所述薄膜晶体 管的栅极绝缘层的上表面的一部分， 所述第三部分覆盖所述薄膜晶体管的漏 极的上表面的至少一部分。
7、根据权利要求 1至 6中任意一项所述的阵列基板， 其中， 所述周边区 设置有栅线引线、 在所述栅线引线的上方与该栅线引线电连接的栅线引线电 极、 公共电极线引线、 设置在所述公共电极线引线上方且与该公共电极引线 电连接的公共电极线引线电极、 数据线引线和设置在所述数据线引线上方且 与该数据线引线电连接的数据线引线电极， 所述栅线引线与所述显示区内的 栅线——对应地电连接， 所述公共电极线引线与所述显示区内的公共电极线 ——对应地电连接， 所述数据线引线与所述显示区内的数据线——对应地电 连接， 所述栅线引线电极、 公共电极线引线电极和数据线引线电极均用于与 外部驱动电路电连接。
8、 根据权利要求 7所述的阵列基板， 其中， 所述栅线引线、公共电极线 引线与所述栅线、 所述公共电极线在同一膜层； 和 /或所述数据线引线与所述 数据线在同一膜层。
9、根据权利要求 1至 8中任意一项所述的阵列基板， 其中， 所述薄膜晶 体管的有源层由氧化物制成。
10、 根据权利要求 9所述的阵列基板， 其中， 所述氧化物为铟镓辞氧化 物。
11、 一种显示装置， 包括阵列基板， 其中， 所述阵列基板为权利要求 1 至 10中任意一项所述的阵列基板。
12、 一种阵列基板的制造方法， 包括以下步骤：
形成第一组图形， 该第一组图形包括数据线、 源极和漏极； 和
形成第二组图形， 该第二组图形包括像素电极， 该像素电极与所述漏极 直接接触。
13、 根据权利要求 12所述的制造方法， 还包括先后进行的：
形成第三组图形， 该第三组图形包括公共电极； 和
形成第四组图形， 该第四组图形包括公共电极线， 该公共电极线与所述 公共电极直接接触。
14、根据权利要求 13所述的制造方法， 其中， 在所述形成第一组图形的 步骤之前进行所述形成第三组图形的步骤， 所述第四组图形还包括栅极、 栅 线、 与所述栅线对应连接的栅线引线和与所述公共电极线对应连接的公共电 极线引线， 所述第一组图形还包括与所述数据线对应连接的数据线引线。
15、根据权利要求 14的制造方法，还包括在所述形成第四组图形的步骤 后进行的形成栅极绝缘层的步骤， 所述栅极绝缘层覆盖所述第四组图形。
16、根据权利要求 15所述的制造方法，还包括在所述形成第一组图形的 步骤之后依次进行的：
形成有源层的图形， 所述有源层的图形包括依次连接的第一部分、 第二 部分和第三部分， 所述第一部分覆盖所述源极的上表面的至少一部分， 所述 第二部分覆盖所述栅极绝缘层的上表面的一部分， 所述第三部分覆盖所述漏 极的上表面的至少一部分； 和
形成钝化层。
17、根据权利要求 16所述的制造方法， 其中， 在所述形成栅极绝缘层的 步骤之后进行所述形成第二组图形的步骤， 并在所述形成第二组图形步骤之 后进行所述形成第一组图形的步骤。
18、根据权利要求 17所述的制造方法，还包括在所述形成钝化层的步骤 后进行：
在所述钝化层上形成第一开孔、 第二开孔和第三开孔， 所述第一开孔、 所述第二开孔和所述第三开孔均贯穿所述钝化层， 所述第一开孔位于所述栅 线引线上方， 所述第二开孔位于所述公共电极线引线上方， 所述第三开孔位 于所述数据线引线上方； 和
在形成有所述第一开孔、 所述第二开孔和所述第三开孔的钝化层形成栅 线引线电极、 公共电极线引线电极和数据线引线电极， 所述栅线引线电极通 过所述第一开孔与所述栅线引线电连接， 所述公共电极引线电极通过所述第 二开孔与所述公共电极线引线电连接， 所述数据线引线电极通过所述第三开 孔与所述数据线引线电连接。
19、根据权利要求 16所述的制造方法， 其中， 所述形成钝化层的步骤后 在所述钝化层上形成开口部的步骤， 在所述形成钝化层的步骤之后进行所述 形成所述第二组图形的步骤， 所述像素电极覆盖所述开口部与所述漏极直接 接触。
20、根据权利要求 19所述的制造方法， 其中， 所述第二组图形还包括栅 线引线电极、 公共电极线引线电极和数据线引线电极， 所述制造方法还包括 形成第一开孔、 第二开孔和第三开孔， 所述第一开孔、 所述第二开孔和所述 第三开孔形成在所述钝化层上， 所述第一开孔、 所述第二开孔和所述第三开 孔均贯穿所述钝化层， 且所述第一开孔位于所述栅线引线上方， 所述第二开 孔位于所述公共电极线引线上方， 所述第三开孔位于所述数据线引线上方， 所述形成第二组图形的步骤在所述形成第一开孔、 第二开孔和第三开孔的步 骤之后进行， 使得所述栅线引线电极通过所述第一开孔与所述栅线引线电连 接， 所述公共电极线引线电极通过所述第二开孔与所述公共电极线引线电连 接， 所述数据线引线电极通过所述第三开孔与所述数据线引线电连接。
21、 根据权利要求 12至 20中任意一项所述的制造方法， 其中， 所述像 素电极包括像素电极本体和从所述像素电极本体上突出的连接部， 所述连接 部与所述薄膜晶体管的漏极直接接触。
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