WO2014166153A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2014166153A1
WO2014166153A1 PCT/CN2013/077177 CN2013077177W WO2014166153A1 WO 2014166153 A1 WO2014166153 A1 WO 2014166153A1 CN 2013077177 W CN2013077177 W CN 2013077177W WO 2014166153 A1 WO2014166153 A1 WO 2014166153A1
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Prior art keywords
conductive pattern
array substrate
conductive
signal line
stv signal
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PCT/CN2013/077177
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English (en)
French (fr)
Inventor
于海峰
封宾
崔晓鹏
林鸿涛
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US14/348,652 priority Critical patent/US9224760B2/en
Publication of WO2014166153A1 publication Critical patent/WO2014166153A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of manufacturing the same, and a display device. Background technique
  • TFT-LCD thin film transistor liquid crystal display
  • manufacturers are adopting new technologies to reduce the cost of products, thereby improving The competitiveness of its products in the market.
  • Array substrate The Gate Driver on Array (GOA) technology is a typical example of these new technologies.
  • the GOA technology integrates a gate switching circuit on an Array substrate, thereby eliminating the gate driver IC (Gate Driver IC) portion, and reducing product cost in terms of material cost and process steps. the goal of.
  • the STV (data carry signal) signal line is only connected to the first row (or the first few rows) of the GOA unit because its trace is generated. Once the static electricity is generated in the STV signal line, the charge cannot be diffused like other traces, such as the accumulated charge. Larger ones broke out at the first GOA unit, causing poor electrical related.
  • the anti-static structure of the conventional STV signal line is to access the capacitor before the STV input point, and to use the breakdown current generated at high voltage to conduct the static electricity.
  • the capacitor is formed by the gate metal layer STV signal lines, source-drain metal layer is formed V ss signal line and the gate insulating layer.
  • Embodiments of the present invention provide an array substrate.
  • the array substrate is formed with a first conductive pattern connecting a low level potential, a second conductive pattern in the same layer as the STV signal line, and an insulating layer between the first conductive pattern and the second conductive pattern.
  • the first conductive pattern, the insulating layer and the second conductive pattern have overlapping regions to form a storage capacitor.
  • the STV signal line is formed with a conductive tip toward the second conductive pattern at a position corresponding to the second conductive pattern.
  • Embodiments of the present invention also provide a display device.
  • the display device includes the above Array substrate.
  • Embodiments of the present invention also provide a method of fabricating an array substrate.
  • the array substrate is formed with a first conductive pattern connecting a low-level potential, a second conductive pattern in the same layer as the STV signal line, and an insulating layer between the first conductive pattern and the second conductive pattern.
  • the first conductive pattern, the insulating layer and the second conductive pattern have overlapping regions to form a storage capacitor.
  • the manufacturing method includes forming a conductive tip toward the second conductive pattern at a position where the STV signal line corresponds to the second conductive pattern.
  • FIG. 1 is a schematic diagram of an electrostatic protection structure of a STV signal line in a conventional GOA circuit
  • FIG. 2 is a schematic diagram of an electrostatic protection structure of a STV signal line in an array substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic view showing another electrostatic protection structure of an STV signal line in an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram showing current states of an array substrate at a normal signal input according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of electrostatic transfer of an array substrate in the presence of static electricity according to an embodiment of the invention.
  • FIG. detailed description is a schematic diagram of electrostatic transfer of an array substrate in the presence of static electricity according to an embodiment of the invention.
  • Embodiments of the present invention provide an array substrate, a method of manufacturing the same, and a display device capable of effectively discharging static electricity accumulated on a STV signal line without affecting a display effect.
  • a first conductive pattern connecting a low-level potential and a second conductive pattern in the same layer as the STV signal line are formed on the array substrate according to an embodiment of the present invention, between the first conductive pattern and the second conductive pattern. Insulation layer. The first conductive pattern, the insulating layer and the second conductive pattern have overlapping regions to form a storage capacitor. The STV signal line corresponds to the second conductive pattern The location is formed with a conductive tip that faces the second conductive pattern.
  • the array substrate according to an embodiment of the present invention may be a top gate type structure or a bottom gate type structure.
  • the first conductive pattern may be formed of a gate metal layer
  • the second conductive pattern and the STV signal line may be formed of a source/drain metal layer
  • the insulating layer may be formed of a gate insulating layer Forming, the first conductive pattern, the insulating layer and the second conductive pattern have overlapping regions to form a storage capacitor, and the source-drain metal layer is used to form the conductive tip.
  • the first conductive pattern may be formed of a source/drain metal layer
  • the second conductive pattern and the STV signal line may be formed of a gate metal layer
  • the insulating layer may be formed of a gate insulating layer Forming, the first conductive pattern, the insulating layer and the second conductive pattern have overlapping regions to form a storage capacitor, and a gate metal layer is used to form the conductive tip.
  • the insulating layer that forms the storage capacitor using the gate insulating layer is not limited, as long as the insulating layer between the first conductive pattern and the second conductive pattern can be used to form the memory.
  • the insulating layer of the capacitor is not limited, as long as the insulating layer between the first conductive pattern and the second conductive pattern can be used to form the memory.
  • the array substrate according to the embodiment of the present invention is not limited to a horizontal electric field type array substrate, and may be a vertical electric field type array substrate as long as it can be connected to the first conductive pattern of the low level potential and the same layer as the STV signal line.
  • a storage capacitor may be formed between the second conductive patterns.
  • the first conductive pattern when the first conductive pattern is formed by the source/drain metal layer, the first conductive pattern and the source electrode and the drain electrode of the array substrate may be simultaneously formed by one patterning process.
  • the second conductive pattern, the conductive tip, and the STV signal line are formed by using a gate metal layer, the second conductive pattern, the conductive tip, the STV signal line, and the array substrate may be simultaneously formed by one patterning process. Gate electrode, gate line. This makes it possible to implement the technical solution according to an embodiment of the present invention without increasing the number of patterning processes.
  • the array substrate according to the embodiment of the present invention is an example of the bottom gate type structure, and the array substrate according to the embodiment of the present invention may include:
  • a second conductive pattern formed on the substrate by a gate metal layer, the conductive tip, the STV signal line, a gate electrode, and a gate line;
  • the first conductive pattern, the source electrode, and the source/drain metal layer formed on the gate insulating layer Leakage electrode are formed on the gate insulating layer Leakage electrode.
  • the embodiment of the invention further provides a method for manufacturing the above array substrate.
  • the array substrate is formed with a first conductive pattern connecting a low-level potential, a second conductive pattern in the same layer as the STV signal line, and an insulating layer between the first conductive pattern and the second conductive pattern.
  • the first conductive pattern, the insulating layer and the second conductive pattern have overlapping regions to form a storage capacitor.
  • the manufacturing method includes forming a conductive tip toward the second conductive pattern at a position where the STV signal line corresponds to the second conductive pattern.
  • the array substrate according to an embodiment of the present invention may be a top gate type structure or a bottom gate type structure.
  • the first conductive pattern may be formed of a gate metal layer
  • the second conductive pattern and the STV signal line may be formed of a source/drain metal layer
  • the insulating layer may be formed of a gate insulating layer Forming, the first conductive pattern, the insulating layer and the second conductive pattern have overlapping regions to form a storage capacitor, and the source-drain metal layer is used to form the conductive tip.
  • the first conductive pattern may be formed of a source/drain metal layer
  • the second conductive pattern and the STV signal line may be formed of a gate metal layer
  • the insulating layer may be formed of a gate insulating layer Forming, the first conductive pattern, the insulating layer, and the second conductive pattern have overlapping regions to form a storage capacitor, and a gate metal layer is used to form the conductive tip.
  • the insulating layer that forms the storage capacitor using the gate insulating layer is not limited, as long as the insulating layer between the first conductive pattern and the second conductive pattern can be used to form the memory.
  • the insulating layer of the capacitor is not limited, as long as the insulating layer between the first conductive pattern and the second conductive pattern can be used to form the memory.
  • the array substrate according to the embodiment of the present invention is not limited to a horizontal electric field type array substrate, and may be a vertical electric field type array substrate as long as it can be connected to the first conductive pattern of the low level potential and the same layer as the STV signal line.
  • a storage capacitor may be formed between the second conductive patterns.
  • the first conductive pattern and the source and drain electrodes of the array substrate may be simultaneously formed by one patterning process.
  • the second conductive pattern, the conductive tip and the STV signal line are formed by using a gate metal layer
  • the second conductive pattern, the conductive tip, the STV signal line and the array substrate may be simultaneously formed by one patterning process Gate electrode, gate line.
  • the array substrate according to the embodiment of the invention is a bottom gate type structure, and the manufacturing method includes:
  • the second conductive pattern composed of a gate metal layer, the conductive tip, the STV signal line, and the gate electrode and the gate line on the substrate;
  • the first conductive pattern, the source electrode and the drain electrode composed of the source/drain metal layer are formed on the substrate subjected to the second patterning process by a third patterning process.
  • a data line is further formed in the third patterning process;
  • the pixel electrodes required for the array substrate can also be fabricated, including:
  • a pixel electrode composed of a transparent conductive layer is formed on the insulating layer by a fifth patterning process, and the pixel electrode is connected to the drain electrode through the pixel electrode via.
  • the first conductive pattern, the insulating layer and the second conductive pattern have overlapping regions to form a storage capacitor, and the position of the STV signal line corresponding to the second conductive pattern is formed toward the second conductive pattern.
  • Conductive tip When the display device is operating normally, the charge on the STV signal line is not input to the storage capacitor and thus does not cause an abnormal display. When a large amount of static electricity accumulates on the STV signal line, static electricity is released to the second conductive pattern through the conductive tip, thereby achieving the purpose of electrostatic discharge. Therefore, the array substrate according to the embodiment of the present invention can effectively discharge the static electricity accumulated on the STV signal line without affecting the display effect.
  • FIG. 2 is a schematic diagram of an electrostatic protection structure of an STV signal line in an array substrate according to an embodiment of the present invention.
  • the V ss signal line 1 connected to the low-level potential is connected to the first conductive pattern 5
  • the second conductive pattern 3 and the first conductive pattern 5 are used to form the storage capacitor
  • the STV signal line 2 and the first GOA are connected.
  • Unit 4 is connected.
  • the STV signal line 2 is not connected to the second conductive pattern 3 through the trace, but the conductive tip 6 is disposed at a position corresponding to the second conductive pattern 3 of the STV signal line 2, and the tip end of the conductive tip 6 faces the second
  • the pattern 3 is conductive and there is a certain distance between the conductive tip 6 and the second conductive pattern 3.
  • a conductive tip may also be disposed at a position corresponding to the STV signal line 2 of the second conductive pattern 3. Connected to the second conductive pattern 3 The tip end of the conductive tip faces the STV signal line 2.
  • the array substrate according to an embodiment of the present invention effectively utilizes the property of the tip discharge to form a conductive tip toward the second conductive pattern at a position where the STV signal line corresponds to the second conductive pattern.
  • the technical solution according to an embodiment of the present invention combines a conductive tip with a storage capacitor, and the arrangement of the conductive tip can enhance the electrostatic discharge effect without generating excessive RC load.
  • the display panel is working normally, the charge on the STV signal line is not input to the storage capacitor, and thus does not cause an abnormal display.
  • static electricity is released to the second conductive pattern through the conductive tip.
  • the storage capacitor stores the charge in the energized state, the charge is slowly released, and the high voltage is used to generate the storage capacitor in the non-energized state.
  • the crash current conducts static electricity to achieve electrostatic discharge.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the display device can be: a product or a component having any display function such as a liquid crystal panel, an electronic paper, an OLED (Organic Light Emitting Diode) panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, or a tablet computer.
  • a display device including the array substrate as described above.
  • the display device can be: a product or a component having any display function such as a liquid crystal panel, an electronic paper, an OLED (Organic Light Emitting Diode) panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, or a tablet computer.
  • OLED Organic Light Emitting Diode

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Abstract

一种阵列基板及其制造方法、显示装置。阵列基板上形成有连接低电平电位的第一导电图形（5）、与STV信号线（2）同层的第二导电图形（3）、位于第一导电图形（5）和第二导电图形（3）之间的绝缘层。第一导电图形（5）、绝缘层与第二导电图形（3）存在有交叠区域以形成存储电容。STV信号线（2）对应第二导电图形（3）的位置形成有朝向第二导电图形（3）的导电尖端（6）。

Description

阵列基板及其制造方法、 显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制造方法、 显示装置。 背景技术
随着薄 H莫晶体管液晶显示器 ( Thin film transistor liquid crystal display, TFT-LCD )产业的发展， TFT-LCD产品的竟争日趋激烈， 各厂家都在通过采 用新技术以降低产品的成本， 从而提高其产品在市场上的竟争力。 阵列基板 行驱动（Gate Driver on Array, GOA )技术就是这些新技术的典型代表。
GOA技术是将栅极（Gate )开关电路集成于阵列 （Array )基板上， 从 而可以省掉栅极驱动集成电路（Gate Driver IC )部分， 从材料成本和工艺步 骤两个方面可以达到降低产品成本的目的。 STV (数据进位信号）信号线由 于其走线仅与第一行（或前几行） GOA单元相连接， 一旦 STV信号线内产 生静电将无法像其它走线一样将电荷扩散， 如聚集电荷较大则易在第一个 GOA单元处爆发， 造成相关电学不良。
传统的 STV信号线的防静电结构是在 STV输入点之前接入电容器， 并 利用高电压下产生的崩溃电流将静电导走。如图 1所示，该电容器由形成 STV 信号线的栅金属层、形成 Vss信号线的源漏金属层以及栅绝缘层组成。 然而， 由于电容器具有存储电荷的特性， 而此特性又会导致在走线正常工作的状况 下产生信号衰减， 最终造成异常显示 （ Abnormal display ) 。 发明内容
本发发明的实施例提供一种阵列基板。 所述阵列基板上形成有连接低电 平电位的第一导电图形、与 STV信号线同层的第二导电图形、位于所述第一 导电图形和所述第二导电图形之间的绝缘层。 所述第一导电图形、 所述绝缘 层与所述第二导电图形存在有交叠区域以形成存储电容。所述 STV信号线对 应所述第二导电图形的位置形成有朝向所述第二导电图形的导电尖端。
本发明的实施例还提供了一种显示装置。 所述显示装置包括如上所述的 阵列基板。
本发明的实施例还提供了一种阵列基板的制造方法。 所述阵列基板上形 成有连接低电平电位的第一导电图形、 与 STV信号线同层的第二导电图形、 位于所述第一导电图形和所述第二导电图形之间的绝缘层。 所述第一导电图 形、 所述绝缘层与所述第二导电图形存在有交叠区域以形成存储电容。 所述 制造方法包括：在所述 STV信号线对应所述第二导电图形的位置形成朝向所 述第二导电图形的导电尖端。 附图说明
图 1为在传统的 GOA电路中 STV信号线的静电保护结构的示意图； 图 2为在根据本发明实施例的阵列基板中 STV信号线的静电保护结构的 示意图；
图 3为在根据本发明实施例的阵列基板中 STV信号线的另一静电保护结 构的示意图；
图 4为根据本发明实施例的阵列基板在正常信号输入时的电流状态示意 图；
图 5为根据本发明实施例的阵列基板在静电发生时的静电传送示意图。 具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图， 对本发明实施例的技术方案进行清楚、 完整地描述。 显然， 所描述的实施例 是本发明的一部分实施例， 而不是全部的实施例。 基于所描述的本发明的实 施例， 本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实 施例， 都属于本发明保护的范围。
本发明的实施例提供一种阵列基板及其制造方法、 显示装置， 能够在不 影响显示效果的情况下， 有效释放 STV信号线上积累的静电。
根据本发明实施例的阵列基板上形成有连接低电平电位的第一导电图 形、与 STV信号线同层的第二导电图形、位于所述第一导电图形和所述第二 导电图形之间的绝缘层。 所述第一导电图形、 所述绝缘层与所述第二导电图 形存在有交叠区域以形成存储电容。所述 STV信号线对应所述第二导电图形 的位置形成有朝向所述第二导电图形的导电尖端。
根据本发明实施例的阵列基板可以为顶栅型结构也可以为底栅型结构。 在根据本发明实施例的阵列基板为顶栅型结构时， 第一导电图形可以由栅金 属层形成， 第二导电图形和 STV信号线可以由源漏金属层形成， 绝缘层可以 由栅绝缘层形成， 第一导电图形、 绝缘层和第二导电图形存在交叠区域以形 成存储电容， 并采用源漏金属层形成导电尖端。 在根据本发明实施例的阵列 基板为底栅型结构时， 第一导电图形可以由源漏金属层形成， 第二导电图形 和 STV信号线可以由栅金属层形成， 绝缘层可以由栅绝缘层形成， 第一导电 图形、 绝缘层和第二导电图形存在交叠区域以形成存储电容， 并采用栅金属 层形成导电尖端。
进一步地， 在根据本发明实施例的阵列基板中并不局限于采用栅绝缘层 形成存储电容的绝缘层， 只要处于第一导电图形和第二导电图形之间的绝缘 层均可以用以形成存储电容的绝缘层。
进一步地， 根据本发明实施例的阵列基板并不局限为水平电场型阵列基 板， 还可以为垂直电场型阵列基板， 只要能够在连接低电平电位的第一导电 图形和与 STV信号线同层的第二导电图形之间形成存储电容即可。
进一步地， 在第一导电图形采用源漏金属层形成时， 可以通过一次构图 工艺同时形成所述第一导电图形和阵列基板的源电极、 漏电极。 在第二导电 图形、所述导电尖端和所述 STV信号线采用栅金属层形成时，可以通过一次 构图工艺同时形成所述第二导电图形、所述导电尖端、所述 STV信号线和阵 列基板的栅电极、 栅线。 这样可以在不增加构图工艺次数的前提下实现根据 本发明实施例的技术方案。
进一步地， 以根据本发明实施例的阵列基板为底栅型结构为例， 根据本 发明实施例的阵列基板可以包括：
基板；
位于所述基板上由栅金属层形成的所述第二导电图形、 所述导电尖端、 所述 STV信号线、 栅电极和栅线；
位于形成有所述第二导电图形、 所述导电尖端、 所述 STV信号线、栅电 极和栅线的基板上的栅绝缘层；
位于所述栅绝缘层上由源漏金属层形成的所述第一导电图形、 源电极和 漏电极。
本发明实施例还提供了一种上述阵列基板的制造方法。 所述阵列基板上 形成有连接低电平电位的第一导电图形、 与 STV信号线同层的第二导电图 形、 位于所述第一导电图形和所述第二导电图形之间的绝缘层。 所述第一导 电图形、 所述绝缘层与所述第二导电图形存在有交叠区域以形成存储电容。 所述制造方法包括：在所述 STV信号线对应所述第二导电图形的位置形成朝 向所述第二导电图形的导电尖端。
根据本发明实施例的阵列基板可以为顶栅型结构也可以为底栅型结构。 在根据本发明实施例的阵列基板为顶栅型结构时， 第一导电图形可以由栅金 属层形成， 第二导电图形和 STV信号线可以由源漏金属层形成， 绝缘层可以 由栅绝缘层形成， 第一导电图形、 绝缘层和第二导电图形存在交叠区域以形 成存储电容， 并采用源漏金属层形成导电尖端。 在根据本发明实施例的阵列 基板为底栅型结构时， 第一导电图形可以由源漏金属层形成， 第二导电图形 和 STV信号线可以由栅金属层形成， 绝缘层可以由栅绝缘层形成， 第一导电 图形、 绝缘层和第二导电图形存在交叠区域以形成存储电容， 并采用栅金属 层形成导电尖端。
进一步地， 在根据本发明实施例的阵列基板中并不局限于采用栅绝缘层 形成存储电容的绝缘层， 只要处于第一导电图形和第二导电图形之间的绝缘 层均可以用以形成存储电容的绝缘层。
进一步地， 根据本发明实施例的阵列基板并不局限为水平电场型阵列基 板， 还可以为垂直电场型阵列基板， 只要能够在连接低电平电位的第一导电 图形和与 STV信号线同层的第二导电图形之间形成存储电容即可。
进一步地， 为了不增加构图工艺的次数， 在第一导电图形采用源漏金属 层形成时， 可以通过一次构图工艺同时形成所述第一导电图形和阵列基板的 源电极、 漏电极。 在第二导电图形、 所述导电尖端和所述 STV信号线采用栅 金属层形成时， 可以通过一次构图工艺同时形成所述第二导电图形、 所述导 电尖端、 所述 STV信号线和阵列基板的栅电极、 栅线。
进一步地， 以根据本发明实施例的阵列基板为底栅型结构为例， 所述制 造方法包括：
提供一基板； 通过第一次构图工艺， 在所述基板上形成由栅金属层组成的所述第二导 电图形、 所述导电尖端、 所述 STV信号线以及栅电极和栅线；
通过第二次构图工艺， 在经过所述第一次构图工艺的基板上形成栅绝缘 层和有源层图形；
通过第三次构图工艺， 在经过所述第二次构图工艺的基板上形成由源漏 金属层组成的所述第一导电图形、 源电极和漏电极。 优选的， 在该第三次构 图工艺中还形成数据线；
进一步的， 形成所需的存储电容和导电尖端之后， 还可以制作阵列基板 所需的像素电极， 包括：
通过第四次构图工艺， 在经过所述第三次构图工艺的基板上形成包括像 素电极过孔的绝缘层；
通过第五次构图工艺， 在所述绝缘层上形成由透明导电层组成的像素电 极， 所述像素电极通过所述像素电极过孔与所述漏电极相连接。
在根据本发明实施例的阵列基板中， 第一导电图形、 绝缘层与第二导电 图形存在有交叠区域以形成存储电容， STV信号线对应第二导电图形的位置 形成有朝向第二导电图形的导电尖端。 当显示装置正常工作时， STV信号线 上的电荷不会输入到存储电容中， 因而也不会造成异常显示。 当 STV信号线 上积累有较大静电时， 静电会通过导电尖端释放到第二导电图形上， 从而达 到静电释放的目的。 因此， 根据本发明实施例的阵列基板能够在不影响显示 效果的情况下， 有效释放 STV信号线上积累的静电。
下面结合附图 2-5对根据本发明实施例的阵列基板进行详细介绍。
图 2为在根据本发明实施例的阵列基板中 STV信号线的静电保护结构的 示意图。 如图 2所示， 连接低电平电位的 Vss信号线 1与第一导电图形 5连 接， 第二导电图形 3与第一导电图形 5用于形成存储电容， STV信号线 2与 第一 GOA单元 4连接。 与传统技术不同， STV信号线 2并不通过走线与第 二导电图形 3连接，而是在 STV信号线 2对应第二导电图形 3的位置设置导 电尖端 6,导电尖端 6的尖端朝向第二导电图形 3,并且在导电尖端 6和第二 导电图形 3之间存在一定距离。
进一步地， 为了优化静电释放的效率， 如图 3所示， 还可以在第二导电 图形 3对应 STV信号线 2的位置也设置导电尖端。与第二导电图形 3连接的 导电尖端的尖端朝向 STV信号线 2。
如图 4所示， 当显示装置正常工作时电荷不会输入到存储电容， STV信 号线 2上的电荷流向第一 GOA单元 4。 当 STV信号线上积累有较大静电的 时候， 如图 5所示， 静电会通过导电尖端 6释放到存储电容的下极板（即第 二导电图形 3 ) ,并通过存储电容使电荷流向连接低电平电位的 Vss信号线 1 , 从而达到静电释放的目的。
根据本发明实施例的阵列基板有效地利用尖端放电的性质，在 STV信号 线对应第二导电图形的位置形成朝向第二导电图形的导电尖端。 根据本发明 实施例的技术方案将导电尖端与存储电容相结合， 导电尖端的设置能够在加 强静电释放效果的同时又不会产生过多的 RC负载。当显示面板正常工作时， STV信号线上的电荷不会输入到存储电容中， 因而也不会造成异常显示。 当 STV信号线上积累有较大静电时， 静电会通过导电尖端释放到第二导电图形 上， 在通电状态下存储电容存储电荷后緩慢释放电荷， 在不通电状态下利用 高压使存储电容内产生崩溃电流将静电导走， 从而达到静电释放的目的。
本发明实施例还提供了一种显示装置， 包括如上所述的阵列基板。 该显 示装置可以为： 液晶面板、 电子纸、 OLED ( Organic Light Emitting Diode, 有机发光二极管） 面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电 脑等具有任何显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1. 一种阵列基板，所述阵列基板上形成有连接低电平电位的第一导电图 形、与 STV信号线同层的第二导电图形、位于所述第一导电图形和所述第二 导电图形之间的绝缘层， 所述第一导电图形、 所述绝缘层与所述第二导电图 形存在有交叠区域以形成存储电容，其中所述 STV信号线对应所述第二导电 图形的位置形成有朝向所述第二导电图形的导电尖端。
2. 根据权利要求 1 所述的阵列基板， 其中所述第二导电图形对应所述 STV信号线的位置形成有朝向所述 STV信号线的导电尖端。
3.根据权利要求 1所述的阵列基板，其中所述第一导电图形采用源漏金 属层形成， 所述第二导电图形、所述导电尖端和所述 STV信号线采用栅金属 层形成。
4.根据权利要求 3所述的阵列基板，其中所述第一导电图形和阵列基板 的源电极、 漏电极通过一次构图工艺同时形成； 所述第二导电图形、 所述导 电尖端、所述 STV信号线和阵列基板的栅电极、栅线通过一次构图工艺同时 形成。
5.根据权利要求 1所述的阵列基板，其中所述第一导电图形采用栅金属 层形成，所述第二导电图形、所述导电尖端和所述 STV信号线采用源漏金属 层形成。
6.根据权利要求 5所述的阵列基板，其中所述第一导电图形和阵列基板 的栅电极、 栅线通过一次构图工艺同时形成； 所述第二导电图形、 所述导电 尖端、所述 STV信号线和阵列基板的源电极、漏电极通过一次构图工艺同时 形成。
7. 一种显示装置， 其该显示装置包括如权利要求 1~6 中任一项所述的 阵列基板。
8. 一种阵列基板的制造方法，所述阵列基板上形成有连接低电平电位的 第一导电图形、与 STV信号线同层的第二导电图形、位于所述第一导电图形 和所述第二导电图形之间的绝缘层， 所述第一导电图形、 所述绝缘层与所述 第二导电图形存在有交叠区域以形成存储电容， 其中所述制造方法包括： 在 所述 STV信号线对应所述第二导电图形的位置形成朝向所述第二导电图形 的导电尖端。
9.根据权利要求 8所述的阵列基板的制造方法，其中所述制造方法还包 括： 在所述第二导电图形对应所述 STV信号线的位置形成朝向所述 STV信 号线的导电尖端。
10. 根据权利要求 8所述的阵列基板的制造方法， 其中所述制造方法包 括：
采用源漏金属层形成所述第一导电图形； 采用栅金属层形成所述第二导 电图形、 所述导电尖端和所述 STV信号线。
11.根据权利要求 10所述的阵列基板的制造方法，其中所述制造方法包 括： 通过一次构图工艺利用源漏金属层同时形成所述第一导电图形和阵列基 板的源电极、 漏电极； 通过一次构图工艺采用栅金属层同时形成所述第二导 电图形、 所述导电尖端、 所述 STV信号线和阵列基板的栅电极、 栅线。
12. 根据权利要求 8所述的阵列基板的制造方法， 其中所述制造方法包 括：
采用栅金属层形成所述第一导电图形， 采用源漏金属层形成所述第二导 电图形、 所述导电尖端和所述 STV信号线。
13.根据权利要求 12所述的阵列基板的制造方法，其中所述制造方法包 括： 通过一次构图工艺采用栅金属层同时形成所述第一导电图形和阵列基板 的栅电极、 栅线； 通过一次构图工艺采用源漏金属层同时形成所述第二导电 图形、 所述导电尖端、 所述 STV信号线和阵列基板的源电极、 漏电极。
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