CN103227173A - 阵列基板及其制造方法、显示装置 - Google Patents
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Abstract
本发明提供一种阵列基板及其制造方法、显示装置,属于显示技术领域。其中,所述阵列基板上形成有连接低电平电位的第一导电图形、与数据进位信号STV信号线同层的第二导电图形、位于所述第一导电图形和所述第二导电图形之间的绝缘层,所述第一导电图形、所述绝缘层与所述第二导电图形存在有交叠区域以形成存储电容,其中,所述STV信号线对应所述第二导电图形的位置形成有朝向所述第二导电图形的导电尖端。本发明的技术方案能够在不影响显示效果的情况下,有效释放STV信号线上积累的静电。
Description
技术领域
本发明涉及显示技术领域,特别是指一种阵列基板及其制造方法、显示装置。
背景技术
随着薄膜晶体管液晶显示器(Thin film transistor liquid crystal display,TFTLCD)产业的发展,TFT LCD产品的竞争日趋激烈,各厂家都在通过采用新技术以降低产品的成本,从而提高其产品在市场上的竞争力,阵列基板行驱动(Gate Driver on Array,GOA)技术就是这些新技术的典型代表。
GOA技术是将栅极(Gate)开关电路集成于阵列(Array)基板上,从而可以省掉栅极驱动集成电路(Gate Driver IC)部分,从材料成本和工艺步骤两个方面可以达到降低产品成本的目的。STV(数据进位信号)信号线由于其走线仅与第一行(或前几行)GOA单元相连接,一旦STV信号线内产生静电将无法像其它走线一样将电荷扩散,如聚集电荷较大则易在第一个GOA单元处爆发,造成相关电学不良。
现有的STV防静电结构是在STV输入点之前接入电容器,在工艺过程中利用高电压下产生的崩溃电流将静电导走,如图1所示,该电容器由形成STV信号线的栅金属层、形成VSS信号线的源漏金属层以及栅绝缘层组成。然而由于电容器存在存储电荷的特性,而此特性又会导致在走线正常工作的状况下产生信号衰减,最终造成异常显示(Abnormal display)。
发明内容
本发明要解决的技术问题是提供一种阵列基板及其制造方法、显示装置,能够在不影响显示效果的情况下,有效释放STV信号线上积累的静电。
为解决上述技术问题,本发明的实施例提供技术方案如下:
一方面,提供一种阵列基板,所述阵列基板上形成有连接低电平电位的第一导电图形、与数据进位信号STV信号线同层的第二导电图形、位于所述第一导电图形和所述第二导电图形之间的绝缘层,所述第一导电图形、所述绝缘层与所述第二导电图形存在有交叠区域以形成存储电容,其中,所述STV信号线对应所述第二导电图形的位置形成有朝向所述第二导电图形的导电尖端。
进一步地,上述阵列基板中,所述第二导电图形对应所述STV信号线的位置形成有朝向所述STV信号线的导电尖端。
进一步地,上述阵列基板中,所述第一导电图形为采用源漏金属层形成,所述第二导电图形、所述导电尖端和所述STV信号线为采用栅金属层形成。
进一步地,上述阵列基板中,所述第一导电图形和阵列基板的源电极、漏电极为通过一次构图工艺同时形成;所述第二导电图形、所述导电尖端、所述STV信号线和阵列基板的栅电极、栅线为通过一次构图工艺同时形成。
本发明实施例还提供了一种显示装置,包括如上所述的阵列基板。
本发明实施例还提供了一种阵列基板的制造方法,所述阵列基板上形成有连接低电平电位的第一导电图形、与数据进位信号STV信号线同层的第二导电图形、位于所述第一导电图形和所述第二导电图形之间的绝缘层,所述第一导电图形、所述绝缘层与所述第二导电图形存在有交叠区域以形成存储电容,其中,所述制造方法包括:在所述STV信号线对应所述第二导电图形的位置形成朝向所述第二导电图形的导电尖端。
进一步地,所述制造方法还包括:在所述第二导电图形对应所述STV信号线的位置形成朝向所述STV信号线的导电尖端。
进一步地,所述制造方法包括:
采用源漏金属层形成所述第一导电图形;采用栅金属层形成所述第二导电图形、所述导电尖端和所述STV信号线。
进一步地,所述制造方法包括:通过一次构图工艺利用源漏金属层同时形成所述第一导电图形和阵列基板的源电极、漏电极;通过一次构图工艺同时形成所述第二导电图形、所述导电尖端、所述STV信号线和阵列基板的栅电极、栅线。
本发明的实施例具有以下有益效果:
上述方案中,第一导电图形、绝缘层与第二导电图形存在有交叠区域以形成存储电容,STV信号线对应第二导电图形的位置形成有朝向第二导电图形的导电尖端,当显示面板正常工作时,STV信号线上的电荷不会输入到存储电容中,因而也不会造成异常显示;而当STV信号线上积累有较大静电时,静电会通过导电尖端释放到第二导电图形上,从而达到静电释放的目的。
附图说明
图1为现有GOA电路中STV信号线静电保护结构的示意图;
图2为本发明实施例阵列基板中STV信号线静电保护结构的示意图;
图3为本发明实施例阵列基板中STV信号线另一静电保护结构的示意图;
图4为本发明实施例阵列基板正常信号输入时的电流状态示意图;
图5为本发明实施例阵列基板静电发生时的静电传送示意图。
附图标记
1 VSS信号线 2 STV信号线 3 第二导电图形4 第一GOA单元 5 第一导电图形 6 导电尖端
具体实施方式
为使本发明的实施例要解决的技术问题、技术方案和优点更加清楚,下面将结合附图及具体实施例进行详细描述。
本发明的实施例针对现有STV防静电结构是在STV输入点之前接入电容器,由于电容器存在存储电荷的特性,而此特性又会导致在走线正常工作的状况下产生信号衰减,最终造成异常显示的问题,提供一种阵列基板及其制造方法、显示装置,能够在不影响显示效果的情况下,有效释放STV信号线上积累的静电。
本发明的阵列基板上形成有连接低电平电位的第一导电图形、与数据进位信号STV信号线同层的第二导电图形、位于所述第一导电图形和所述第二导电图形之间的绝缘层,所述第一导电图形、所述绝缘层与所述第二导电图形存在有交叠区域以形成存储电容,其中,所述STV信号线对应所述第二导电图形的位置形成有朝向所述第二导电图形的导电尖端。
本发明的阵列基板可以为顶栅型结构也可以为底栅型结构,在本发明的阵列基板为顶栅型结构时,第一导电图形可以为由栅金属层形成,第二导电图形和STV信号线可以由源漏金属层形成,第一导电图形、栅绝缘层和第二导电图形存在交叠区域以形成存储电容,并采用源漏金属层形成导电尖端;在本发明的阵列基板为底栅型结构时,第一导电图形可以由源漏金属层形成,第二导电图形和STV信号线可以由栅金属层形成,第一导电图形、栅绝缘层和第二导电图形存在交叠区域以形成存储电容,并采用栅金属层形成导电尖端。
进一步地,本发明阵列基板中并不局限于采用栅绝缘层形成存储电容的绝缘层,只要处于第一导电图形和第二导电图形之间的绝缘层均可以用以形成存储电容的绝缘层。
进一步地,本发明的阵列基板并不局限为水平电场型阵列基板,还可以为垂直电场型阵列基板,只要能够在连接低电平电位的第一导电图形和与STV信号线同层的第二导电图形之间形成存储电容即可。
进一步地,在第一导电图形为采用源漏金属层形成时,可以通过一次构图工艺同时形成所述第一导电图形和阵列基板的源电极、漏电极;在第二导电图形、所述导电尖端和所述STV信号线为采用栅金属层形成时,可以通过一次构图工艺同时形成所述第二导电图形、所述导电尖端、所述STV信号线和阵列基板的栅电极、栅线。这样可以在不增加构图工艺次数的前提下实现本发明的技术方案。
进一步地,以本发明的阵列基板为底栅型结构为例,本发明的阵列基板具体可以包括:
基板;
位于所述基板上由栅金属层形成的所述第二导电图形、所述导电尖端、栅电极和栅线;
位于形成有所述公共电极和栅电极、栅线的基板上的栅绝缘层;
位于所述栅绝缘层上由源漏金属层形成的所述第一导电图形、源电极和漏电极。
本发明实施例还提供了一种上述阵列基板的制造方法,所述阵列基板上形成有连接低电平电位的第一导电图形、与数据进位信号STV信号线同层的第二导电图形、位于所述第一导电图形和所述第二导电图形之间的绝缘层,所述第一导电图形、所述绝缘层与所述第二导电图形存在有交叠区域以形成存储电容,其中,所述制造方法包括:在所述STV信号线对应所述第二导电图形的位置形成朝向所述第二导电图形的导电尖端。
本发明的阵列基板可以为顶栅型结构也可以为底栅型结构,在本发明的阵列基板为顶栅型结构时,第一导电图形可以为由栅金属层形成,第二导电图形和STV信号线可以由源漏金属层形成,第一导电图形、栅绝缘层和第二导电图形存在交叠区域以形成存储电容,并采用源漏金属层形成导电尖端;在本发明的阵列基板为底栅型结构时,第一导电图形可以由源漏金属层形成,第二导电图形和STV信号线可以由栅金属层形成,第一导电图形、栅绝缘层和第二导电图形存在交叠区域以形成存储电容,并采用栅金属层形成导电尖端。
进一步地,本发明阵列基板中并不局限于采用栅绝缘层形成存储电容的绝缘层,只要处于第一导电图形和第二导电图形之间的绝缘层均可以用以形成存储电容的绝缘层。
进一步地,本发明的阵列基板并不局限为水平电场型阵列基板,还可以为垂直电场型阵列基板,只要能够在连接低电平电位的第一导电图形和与STV信号线同层的第二导电图形之间形成存储电容即可。
进一步地,为了不增加构图工艺的次数,在第一导电图形为采用源漏金属层形成时,可以通过一次构图工艺同时形成所述第一导电图形和阵列基板的源电极、漏电极;在第二导电图形、所述导电尖端和所述STV信号线为采用栅金属层形成时,可以通过一次构图工艺同时形成所述第二导电图形、所述导电尖端、所述STV信号线和阵列基板的栅电极、栅线。
进一步地,以本发明的阵列基板为底栅型结构为例,所述制造方法具体包括:
提供一基板;
通过第一次构图工艺,在所述基板上形成由栅金属层组成的所述第二导电图形、所述导电尖端、所述STV信号线和栅电极和栅线;
通过第二次构图工艺,在经过所述第一次构图工艺的基板上形成栅绝缘层和有源层图形;
通过第三次构图工艺,在经过所述第二次构图工艺的基板上形成由源漏金属层组成的所述第一导电图形、源电极和漏电极。优选的,还包括形成数据线的图形;
进一步的,形成所需的存储电容和导电尖端之后,还可以制作阵列基板所需的像素电极,具体包括:
通过第四次构图工艺,在经过所述第三次构图工艺的基板上形成包括有像素电极过孔的绝缘层的图形;
通过第五次构图工艺,在所述绝缘层上形成由透明导电层组成的像素电极的图形,所述像素电极通过所述像素电极过孔与所述漏电极相连接。
本发明的阵列基板中,第一导电图形、绝缘层与第二导电图形存在有交叠区域以形成存储电容,STV信号线对应第二导电图形的位置形成有朝向第二导电图形的导电尖端,当显示面板正常工作时,STV信号线上的电荷不会输入到存储电容中,因而也不会造成异常显示;而当STV信号线上积累有较大静电时,静电会通过导电尖端释放到第二导电图形上,从而达到静电释放的目的。
下面结合附图2-5对本发明的阵列基板进行详细介绍:
图2为本发明阵列基板的结构示意图,如图2所示,连接低电平电位的VSS信号线1与第一导电图形5连接,第二导电图形3与第一导电图形5之间形成存储电容,STV信号线2与第一GOA单元4连接,与现有技术不同,STV信号线2并不通过走线与第二导电图形3连接,而是在STV信号线2对应第二导电图形3的位置设置导电尖端6,导电尖端6的尖端朝向第二导电图形3,并且在导电尖端6和第二导电图形3之间存在一定距离。
进一步地,为了优化静电释放的效率,如图3所示,还可以在第二导电图形3对应STV信号线2的位置也设置导电尖端,其中,与第二导电图形3连接的导电尖端的尖端朝向STV信号线2。
如图4所示,当显示面板正常工作时电荷不会输入到存储电容,STV信号线2上的电荷流向第一GOA单元4。而当STV信号线上积累有较大静电的时候,如图5所示,静电会通过导电尖端6释放到存储电容的下极板(即第二导电图形3),并通过存储电容使电荷流向连接低电平电位的VSS信号线1,从而达到静电释放的目的。
本发明的阵列基板有效地利用尖端放电的性质,在STV信号线对应第二导电图形的位置形成朝向第二导电图形的导电尖端。本发明的技术方案将导电尖端与存储电容相结合,导电尖端的设置能够在加强静电释放效果的同时又不会产生过多的RC负载,当显示面板正常工作时,STV信号线上的电荷不会输入到存储电容中,因而也不会造成异常显示;而当STV信号线上积累有较大静电时,静电会通过导电尖端释放到第二导电图形上,在通电状态下存储电容存储电荷后缓慢释放电荷,在不通电状态下利用高压使存储电容内产生崩溃电流将静电导走,从而达到静电释放的目的。
本发明实施例还提供了一种显示装置,包括如上所述的阵列基板。该显示装置可以为:液晶面板、电子纸、OLED(Organic Light Emitting Diode,有机发光二极管)面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。
以上所述是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明所述原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (9)
1.一种阵列基板,所述阵列基板上形成有连接低电平电位的第一导电图形、与数据进位信号STV信号线同层的第二导电图形、位于所述第一导电图形和所述第二导电图形之间的绝缘层,所述第一导电图形、所述绝缘层与所述第二导电图形存在有交叠区域以形成存储电容,其特征在于,所述STV信号线对应所述第二导电图形的位置形成有朝向所述第二导电图形的导电尖端。
2.根据权利要求1所述的阵列基板,其特征在于,所述第二导电图形对应所述STV信号线的位置形成有朝向所述STV信号线的导电尖端。
3.根据权利要求1所述的阵列基板,其特征在于,所述第一导电图形为采用源漏金属层形成,所述第二导电图形、所述导电尖端和所述STV信号线为采用栅金属层形成。
4.根据权利要求3所述的阵列基板,其特征在于,所述第一导电图形和阵列基板的源电极、漏电极为通过一次构图工艺同时形成;所述第二导电图形、所述导电尖端、所述STV信号线和阵列基板的栅电极、栅线为通过一次构图工艺同时形成。
5.一种显示装置,其特征在于,包括如权利要求1~4中任一项所述的阵列基板。
6.一种阵列基板的制造方法,所述阵列基板上形成有连接低电平电位的第一导电图形、与数据进位信号STV信号线同层的第二导电图形、位于所述第一导电图形和所述第二导电图形之间的绝缘层,所述第一导电图形、所述绝缘层与所述第二导电图形存在有交叠区域以形成存储电容,其特征在于,所述制造方法包括:在所述STV信号线对应所述第二导电图形的位置形成朝向所述第二导电图形的导电尖端。
7.根据权利要求6所述的阵列基板的制造方法,其特征在于,所述制造方法还包括:在所述第二导电图形对应所述STV信号线的位置形成朝向所述STV信号线的导电尖端。
8.根据权利要求6所述的阵列基板的制造方法,其特征在于,所述制造方法包括:
采用源漏金属层形成所述第一导电图形;采用栅金属层形成所述第二导电图形、所述导电尖端和所述STV信号线。
9.根据权利要求8所述的阵列基板的制造方法,其特征在于,所述制造方法包括:通过一次构图工艺利用源漏金属层同时形成所述第一导电图形和阵列基板的源电极、漏电极;通过一次构图工艺同时形成所述第二导电图形、所述导电尖端、所述STV信号线和阵列基板的栅电极、栅线。
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