CN105226055A - 阵列基板及制作方法、显示面板及显示装置 - Google Patents

阵列基板及制作方法、显示面板及显示装置 Download PDF

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CN105226055A
CN105226055A CN201510738246.3A CN201510738246A CN105226055A CN 105226055 A CN105226055 A CN 105226055A CN 201510738246 A CN201510738246 A CN 201510738246A CN 105226055 A CN105226055 A CN 105226055A
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CN105226055B (zh
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裴晓光
刘冲
肖志莲
赵海生
彭志龙
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to PCT/CN2016/104067 priority patent/WO2017076260A1/zh
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Abstract

本发明提供了一种阵列基板及制作方法、显示面板及显示装置，属于显示技术领域。其中，阵列基板的制作方法包括：在衬底基板上形成多个相互独立的、包括有端部的第一金属层图形，所述端部位于所述阵列基板的非显示区域；在所述第一金属层图形上形成绝缘层；沉积第二金属层之前，在所述绝缘层上形成与所述端部对应的半导体图形。本发明的技术方案能够减少尖端放电导致的GOA单元损坏，提高显示产品的良品率。

Description

阵列基板及制作方法、显示面板及显示装置
技术领域
本发明涉及显示技术领域，特别是指一种阵列基板及制作方法、显示面板及显示装置。
背景技术
为提高目前显示产品在模组端的抗静电能力，产品设计开发时将GOA(栅极驱动电路)结构里的驱动信号线由源漏金属层制作改为由栅金属层制作，这种设计导致在沉积源漏金属层之前栅线属于单独的线，如图1和图2所示，栅线1和GOA单元2之间没有连接，此种情况下栅线1由于接触或其他原因引入静电后无法释放，会在栅线1尖端接近GOA单元2的区域进行放电，造成GOA单元损坏，严重影响显示产品的良品率。
发明内容
本发明要解决的技术问题是提供一种阵列基板及制作方法、显示面板及显示装置，能够减少尖端放电导致的GOA单元损坏，提高显示产品的良品率。
为解决上述技术问题，本发明的实施例提供技术方案如下：
一方面，提供一种阵列基板的制作方法，包括：
在衬底基板上形成多个相互独立的、包括有端部的第一金属层图形，所述端部位于所述阵列基板的非显示区域；
在所述第一金属层图形上形成绝缘层；
沉积第二金属层之前，在所述绝缘层上形成与所述端部对应的半导体图形。
进一步地，所述方法还包括：
在沉积第二金属层之前，对形成有所述半导体图形的衬底基板进行加热。
进一步地，所述在衬底基板上形成多个相互独立的、包括有端部的第一金属层图形包括：
形成端部的宽度大于其他部分的宽度的所述第一金属层图形。
进一步地，所述形成端部的宽度大于其他部分的宽度的所述第一金属层图形包括：
在衬底基板上形成多个相互独立的、包括有端部的栅线的图形，其中，所述端部的宽度大于所述栅线其他部分的宽度，所述端部用于与所述阵列基板的栅极驱动电路连接。
进一步地，所述阵列基板上形成有多个薄膜晶体管，所述在所述绝缘层上形成与所述端部对应的半导体图形包括：
在所述绝缘层上通过一次构图工艺同时形成所述薄膜晶体管的有源层的图形和所述半导体图形。
本发明实施例还提供了一种阵列基板，包括：
位于衬底基板上的多个相互独立的、包括有端部的第一金属层图形，所述端部位于所述阵列基板的非显示区域；
位于所述第一金属层图形上的绝缘层；
位于所述绝缘层上与所述端部对应的半导体图形，在预设温度下所述半导体图形与所述端部交叠的区域形成电容。
进一步地，所述端部的宽度大于所述第一金属层图形的其他部分的宽度。
进一步地，所述第一金属层图形为栅线的图形，其中，所述端部的宽度大于所述栅线其他部分的宽度，所述端部用于与所述阵列基板的栅极驱动电路连接。
进一步地，所述阵列基板上形成有多个薄膜晶体管，所述半导体图形与所述薄膜晶体管的有源层的图形为同层同材料设置。
进一步地，所述半导体图形与所述有源层的图形为采用非晶硅。
本发明实施例还提供了一种显示面板，包括如上所述的阵列基板。
本发明实施例还提供了一种显示装置，包括如上所述的阵列基板。
本发明的实施例具有以下有益效果：
上述方案中，在多个独立的第一金属层图形上形成绝缘层，在沉积第二金属层之前，在绝缘层上形成与端部对应的半导体图形，这样在沉积第二金属层前进行预热时，半导体图形的导电性能增加，与端部交叠的区域形成电容，能够通过电容充电的方式来降低第一金属层图形端部积累电荷的电压值，使得第一金属层图形端部积累的电荷很难发生尖端放电，减少由于第一金属层图形端部尖端放电导致的GOA单元损坏，提高显示产品的良品率。
附图说明
图1为现有阵列基板中栅线的布局示意图；
图2为现有阵列基板中栅线和GOA单元之间的位置关系示意图；
图3为现有阵列基板中栅线和GOA单元上累积电荷的示意图；
图4为本发明实施例中栅线和GOA单元之间的位置关系示意图；
图5为本发明实施例中栅线和半导体图形的布局示意图。
附图标记
1栅线2GOA单元3驱动信号线4a-si图形
5栅线的端部6半导体图形
具体实施方式
为使本发明的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
本发明的实施例针对现有技术中在沉积源漏金属层之前栅线属于单独的线，栅线和GOA单元之间没有连接，栅线尖端接近GOA单元的区域容易进行放电，造成GOA单元损坏的问题，提供一种阵列基板及制作方法、显示面板及显示装置，能够减少尖端放电导致的GOA单元损坏，提高显示产品的良品率。
实施例一
本实施例提供了一种阵列基板的制作方法，包括：
在衬底基板上形成多个相互独立的、包括有端部的第一金属层图形，所述端部位于所述阵列基板的非显示区域；
在所述第一金属层图形上形成绝缘层；
沉积第二金属层之前，在所述绝缘层上形成与所述端部对应的半导体图形。
本实施例在多个独立的第一金属层图形上形成绝缘层，在沉积第二金属层之前，在绝缘层上形成与端部对应的半导体图形，这样在沉积第二金属层前进行预热时，半导体图形的导电性能增加，与端部交叠的区域形成电容，能够通过电容充电的方式来降低第一金属层图形端部积累电荷的电压值，使得第一金属层图形端部积累的电荷很难发生尖端放电，减少由于第一金属层图形端部尖端放电导致的GOA单元损坏，提高显示产品的良品率。
进一步地，所述方法还包括：
在沉积第二金属层之前，对形成有所述半导体图形的衬底基板进行加热。
在常温下，半导体图形的导电性能较差，虽然与端部交叠的区域也能够形成电容，但是进行电容充电的效果不大。在沉积第二金属层前进行预热时，半导体图形所处的环境温度从室温上升到170摄氏度左右，半导体图形的导电性能增加，能够有效地进行电容充电，大幅降低第一金属层图形端部积累电荷的电压值。
进一步地，所述在衬底基板上形成多个相互独立的、包括有端部的第一金属层图形包括：
形成端部的宽度大于其他部分的宽度的所述第一金属层图形。本实施例中，端部的宽度大于第一金属层图形其他部分的宽度，这样对应的半导体图形也可以设置的比较宽，由于电容大小是和两个电容基板面积成正比的，这样能够增加第一金属层图形端部与半导体图形之间形成电容的大小，进一步加强电容充电的效果。
具体实施例中，所述形成端部的宽度大于其他部分的宽度的所述第一金属层图形包括：
在衬底基板上形成多个相互独立的、包括有端部的栅线的图形，其中，所述端部的宽度大于所述栅线其他部分的宽度，所述端部用于与所述阵列基板的栅极驱动电路连接。即具体实施例中，第一金属层图形为栅线的图形，栅线端部的宽度大于栅线其他部分的宽度，栅线端部位于阵列基板的非显示区域且用于与阵列基板的栅极驱动电路连接。
这样在沉积源漏金属层进行预热时，栅线端部与半导体图形交叠的区域形成电容，能够通过电容充电的方式来降低栅线端部积累电荷的电压值，使得栅线端部积累的电荷很难发生尖端放电，减少由于栅线端部尖端放电导致的GOA单元损坏，提高显示产品的良品率。
进一步地，所述阵列基板上形成有多个薄膜晶体管，所述在所述绝缘层上形成与所述端部对应的半导体图形包括：
在所述绝缘层上通过一次构图工艺同时形成所述薄膜晶体管的有源层的图形和所述半导体图形，这样能够在不增加构图工艺的前提下形成半导体图形，节省了构图工艺，降低了产品的生产成本。
实施例二
本实施例提供了一种阵列基板，包括：
位于衬底基板上的多个相互独立的、包括有端部的第一金属层图形，所述端部位于所述阵列基板的非显示区域；
位于所述第一金属层图形上的绝缘层；
位于所述绝缘层上与所述端部对应的半导体图形。
本实施例在多个独立的第一金属层图形上形成绝缘层，在沉积第二金属层之前，在绝缘层上形成与端部对应的半导体图形，这样在沉积第二金属层前进行预热时，半导体图形的导电性能增加，与端部交叠的区域形成电容，能够通过电容充电的方式来降低第一金属层图形端部积累电荷的电压值，使得第一金属层图形端部积累的电荷很难发生尖端放电，减少由于第一金属层图形端部尖端放电导致的GOA单元损坏，提高显示产品的良品率。
进一步地，端部的宽度大于第一金属层图形其他部分的宽度，这样对应的半导体图形也可以设置的比较宽，由于电容大小是和两个电容基板面积成正比的，这样能够增加第一金属层图形端部与半导体图形之间形成电容的大小，进一步加强电容充电的效果。
具体实施例中，所述第一金属层图形为栅线的图形，其中，所述端部的宽度大于所述栅线其他部分的宽度，所述端部用于与所述阵列基板的栅极驱动电路连接。这样在沉积源漏金属层进行预热时，栅线端部与半导体图形交叠的区域形成电容，能够通过电容充电的方式来降低栅线端部积累电荷的电压值，使得栅线端部积累的电荷很难发生尖端放电，减少由于栅线端部尖端放电导致的GOA单元损坏，提高显示产品的良品率。
进一步地，所述阵列基板上形成有多个薄膜晶体管，所述半导体图形与所述薄膜晶体管的有源层的图形为同层同材料设置，这样半导体图形与有源层的图形可以通过一次构图工艺同时形成，这样能够在不增加构图工艺的前提下形成半导体图形，节省了构图工艺，降低了产品的生产成本。
具体实施例中，半导体图形为与有源层的图形为采用a-si。
实施例三
本实施例还提供了一种显示面板，包括上述的阵列基板。该显示面板可以为液晶显示面板或OLED显示面板。
实施例四
本实施例还提供了一种显示装置，包括上述的阵列基板。显示装置其他部分的结构可以参考现有技术，对此本文不再详细描述。该显示装置可以为：液晶面板、电子纸、液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。
实施例五
下面结合附图对本发明的阵列基板进行进一步介绍：
如图3所示，现有阵列基板的制作过程中，在沉积源漏金属层之前，阵列基板的非显示区域的栅线1与GOA单元2之间没有连接，此种情况下栅线1由于接触或其他原因引入静电后无法释放会产生电荷累积。在沉积源漏金属层前预热后半导体导电性能增加，与GOA单元2连接的驱动信号线3与上面平行的a-si图形4之间形成电容，驱动信号线3和a-si图形4分别为电容的下基板和上基板，如果栅线1上累积的是正电荷，那么根据电容效应对应的a-si图形4聚集负电荷，此时栅线1的尖端和a-si图形4的尖端分别带不同极性的电荷，当电荷积累到一定程度后两者的尖端放电造成ESD(静电释放)，即阵列基板生产过程中的GOAESD不良，影响了阵列基板的良品率。
为了解决上述问题，本实施例利用半导体在高温时导电性能增加这一特性，如图4和图5所示，阵列基板的非显示区域中，在栅线1上的绝缘层上形成半导体图形6，半导体图形6与栅线朝向GOA单元2的端部5相对应，在常温下，半导体图形6的导电性能较差，虽然与端部5交叠的区域也能够形成电容，但是进行电容充电的效果不大。
在沉积源漏金属层前进行预热时，半导体图形6所处的环境温度从室温上升到170摄氏度左右，半导体图形6的导电性能增加，与栅线端部5交叠的区域形成电容能够有效地进行电容充电，利用静电具有电压值高而电荷较少的特点，根据电压值＝电量值/电容值方式将电压值减小，电压值减小后栅线端部5积累的电荷就很难发生尖端放电，减少由于栅线端部5放电导致的GOA单元损坏，提高阵列基板的良品率。
进一步地，为了加强电容充电的效果，栅线端部5的宽度大于栅线其他部分的宽度，对应的，半导体图形6的宽度也比较大，由于电容大小是和两个电容基板面积成正比的，这样能够有效增加栅线端部5与半导体图形6之间形成电容的大小。优选地，栅线端部5的宽度可以是栅线其他部分的宽度的2-10倍；半导体图形6的大小随栅线端部5的大小改变而改变，优选地，半导体图形6的大小等于栅线端部5的大小。
另外，为了不增加生产阵列基板的构图工艺的次数，半导体图形6可以与阵列基板上薄膜晶体管的有源层同层同材料设置，这样半导体图形6可以与阵列基板上薄膜晶体管的有源层通过一次构图工艺同时形成，降低了阵列基板的生产成本。由于薄膜晶体管的有源层一般采用a-si制成，因此，半导体图形6也可以采用a-si制成。当然，如果薄膜晶体管的有源层采用其他材料制成，相应地，半导体图形6也采用与薄膜晶体管的有源层同样的材料制成。
本实施例以第一金属层图形为栅线举例进行说明，当然，第一金属层图形并不局限为栅线，阵列基板的制作过程中，在形成第一金属层图形之后，沉积第二金属层之前，都可以在非显示区域中第一金属层上的绝缘层上形成与第一金属层图形端部对应的半导体图形，以释放第一金属层图形端部积累的静电。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (12)

1.一种阵列基板的制作方法，其特征在于，包括：
在衬底基板上形成多个相互独立的、包括有端部的第一金属层图形，所述端部位于所述阵列基板的非显示区域；
在所述第一金属层图形上形成绝缘层；
沉积第二金属层之前，在所述绝缘层上形成与所述端部对应的半导体图形。
2.根据权利要求1所述的阵列基板的制作方法，其特征在于，所述方法还包括：
在沉积第二金属层之前，对形成有所述半导体图形的衬底基板进行加热。
3.根据权利要求1所述的阵列基板的制作方法，其特征在于，所述在衬底基板上形成多个相互独立的、包括有端部的第一金属层图形包括：
形成端部的宽度大于其他部分的宽度的所述第一金属层图形。
4.根据权利要求3所述的阵列基板的制作方法，其特征在于，所述形成端部的宽度大于其他部分的宽度的所述第一金属层图形包括：
在衬底基板上形成多个相互独立的、包括有端部的栅线的图形，其中，所述端部的宽度大于所述栅线其他部分的宽度，所述端部用于与所述阵列基板的栅极驱动电路连接。
5.根据权利要求3所述的阵列基板的制作方法，其特征在于，所述阵列基板上形成有多个薄膜晶体管，所述在所述绝缘层上形成与所述端部对应的半导体图形包括：
在所述绝缘层上通过一次构图工艺同时形成所述薄膜晶体管的有源层的图形和所述半导体图形。
6.一种阵列基板，其特征在于，包括：
位于衬底基板上的多个相互独立的、包括有端部的第一金属层图形，所述端部位于所述阵列基板的非显示区域；
位于所述第一金属层图形上的绝缘层；
位于所述绝缘层上与所述端部对应的半导体图形。
7.根据权利要求6所述的阵列基板，其特征在于，所述端部的宽度大于所述第一金属层图形的其他部分的宽度。
8.根据权利要求7所述的阵列基板，其特征在于，所述第一金属层图形为栅线的图形，其中，所述端部的宽度大于所述栅线其他部分的宽度，所述端部用于与所述阵列基板的栅极驱动电路连接。
9.根据权利要求7所述的阵列基板，其特征在于，所述阵列基板上形成有多个薄膜晶体管，所述半导体图形与所述薄膜晶体管的有源层的图形为同层同材料设置。
10.根据权利要求9所述的阵列基板，其特征在于，所述半导体图形与所述有源层的图形为采用非晶硅。
11.一种显示面板，其特征在于，包括如权利要求6-10中任一项所述的阵列基板。
12.一种显示装置，其特征在于，包括如权利要求6-10中任一项所述的阵列基板。
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CN107065339A (zh) * 2016-10-27 2017-08-18 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN107367876A (zh) * 2017-08-01 2017-11-21 深圳市华星光电技术有限公司 防静电电路及液晶显示面板
CN107425144A (zh) * 2017-08-21 2017-12-01 江苏集萃有机光电技术研究所有限公司 Oled蒸发源、蒸镀设备及oled面板像素阵列的制备方法
CN107425144B (zh) * 2017-08-21 2020-06-05 江苏集萃有机光电技术研究所有限公司 Oled蒸发源、蒸镀设备及oled面板像素阵列的制备方法

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