WO2014205858A1 - 阵列基板及其制作方法、平板显示装置 - Google Patents

阵列基板及其制作方法、平板显示装置 Download PDF

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Publication number
WO2014205858A1
WO2014205858A1 PCT/CN2013/078559 CN2013078559W WO2014205858A1 WO 2014205858 A1 WO2014205858 A1 WO 2014205858A1 CN 2013078559 W CN2013078559 W CN 2013078559W WO 2014205858 A1 WO2014205858 A1 WO 2014205858A1
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Prior art keywords
metal strip
fan
metal
length
strip portions
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PCT/CN2013/078559
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English (en)
French (fr)
Inventor
柴立
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to JP2016520231A priority Critical patent/JP6127209B2/ja
Priority to RU2016101413A priority patent/RU2619814C1/ru
Priority to US13/985,285 priority patent/US9210797B2/en
Priority to GB1522340.7A priority patent/GB2530211B/en
Priority to KR1020167000647A priority patent/KR101847307B1/ko
Publication of WO2014205858A1 publication Critical patent/WO2014205858A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0242—Structural details of individual signal conductors, e.g. related to the skin effect
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0248—Skew reduction or using delay lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details
    • H05K2201/0776—Resistance and impedance
    • H05K2201/0784—Uniform resistance, i.e. equalizing the resistance of a number of conductors

Definitions

  • the present invention relates to the field of flat panel display technologies, and in particular, to an array substrate, a method for fabricating an array substrate, and a flat panel display device.
  • the fan-out leads 12 are obtained by an array process on the first metal layer 121, the insulating layer 122, the second metal layer 123, and the passivation layer 124 which are sequentially stacked. Since the first metal layer 121 and the second metal layer 123 are insulated from each other, the first metal layer 121 and the second metal layer 123 are equivalent to two parallel resistors when inputting a signal.
  • the fan-out lead 11 and the fan-out lead 13 have the same internal structure as the fan-out lead 12.
  • the fan-out leads have the same structure and the same length, the fan-out leads 11, the fan-out leads 12, and the fan-out leads 13 have the same impedance.
  • the winding portion of the fan-out lead 12 is relatively evacuated, resulting in an increase in the height of the fan-out lead 12, and an area occupied by the non-effective display area is increased, thereby being disadvantageous for the display panel.
  • the narrow bezel design reduces the utilization of the array substrate.
  • a primary object of the present invention is to provide an array substrate, a method of fabricating the same, and a flat panel display device capable of maintaining uniform impedance of each of the fan-out leads when the lengths are not equal.
  • any of the fan-out leads further includes a passivation layer, and the passivation layer covers the second metal strip.
  • another technical solution adopted by the present invention is to provide a method for fabricating an array substrate, comprising: forming a first metal layer on a glass substrate, and forming the first metal layer into a fan-shaped distribution. a plurality of first metal wires, wherein each of the first metal wires includes a predetermined number of first metal strip portions, each of the first metal strip portions is spaced apart, and the first metal strip portions of the plurality of first metal wires are spaced apart
  • the length of the fan increases in the direction of the edge toward the edge and the predetermined number decreases in the direction;
  • the insulating layer is formed on the plurality of metal lines, and the first via hole and the first layer are formed at positions where the insulating layer covers each of the first metal strip portions a second via hole; a second metal layer is formed on the insulating layer, and the second metal layer is formed into a plurality of second metal strip portions, wherein each of the second metal strip portions passes through the first via hole and the second via hole Contacting the first metal strip
  • the manufacturing method further comprises: forming a passivation layer on the plurality of second metal strip portions.
  • each of the first metal strips is equally spaced apart.
  • a flat panel display device including an array substrate, the array substrate including an effective display area and an ineffective display area surrounding the effective display area, and the display is not effective.
  • the fan has a plurality of fan-out leads distributed in a fan shape, each fan lead has a predetermined length, and a predetermined length of the plurality of fan-out leads gradually increases along a center-to-edge direction of the fan shape, and any of the fan-out leads includes: a predetermined number a first metal strip portion on the glass substrate, a predetermined number of first metal strip portions are spaced apart along a direction in which the fan-out leads extend, and a length of each of the first metal strip portions is less than or equal to a predetermined length; a layer covering each of the first metal strips, and a first via and a second via being disposed at a position where the insulating layer covers each of the first metal strips; and a second metal strip on the insulating layer And contacting each of the fan
  • each of the first metal strip portions has the same length.
  • each of the first metal strips is equally spaced apart.
  • the array substrate of the present invention, the manufacturing method thereof, and the flat panel display device are provided with a first via hole and a second via hole at a position where the insulating layer covers each of the first metal strip portions, so that the second metal strip portion
  • the first via hole and the second via hole are in contact with each of the first metal strip portions, and the length of each of the fan-out leads is unequal in length by adjusting the length of the first metal strip portion of each of the fan-out leads.
  • the height of the fan-out leads can be reduced, the utilization of the array substrate can be increased, and the narrow bezel design of the display panel is facilitated.
  • FIG 3 is a schematic structural view of an embodiment of a fan-out lead in an ineffective display area on an array substrate of the present invention.
  • the three fan-out leads 21, 22, and 23 each have a predetermined length, and the predetermined length L of the fan-out leads 22 is smaller than a predetermined length of the fan-out leads 21, 23.
  • the fan-out lead 22 includes a first metal strip portion 221, an insulating layer 222, and a second metal strip portion 223.
  • the insulating layer 222 covers each of the first metal strips 221, and the first vias 2221 and the second vias 2222 are disposed at positions of the insulating layer 222 covering each of the first metal strips 221 . Between the two first metal strips 221, the insulating layer 222 also covers the glass substrate.
  • the equivalent circuit of the fan-out lead 22 is compared with the equivalent circuit of the fan-out lead 12 of FIG. 2, assuming that the impedances of the two layers of the upper and lower insulation of the fan-out lead 12 in the prior art are R1' and R2', respectively.
  • the equivalent circuit is R1' and R2' in parallel, and it can be known that R1' is larger than R1.
  • the first metal layer can be formed by a process such as deposition. After the first metal layer is formed, the first metal layer may be formed into a plurality of first metal lines distributed in a fan shape by a wet etching process. Since each of the metal lines includes a predetermined number of first metal strips spaced apart, the first metal lines are not continuous. The predetermined number of first metal strips of each of the first metal wires is different, and the longer the length of the first metal strips, the smaller the predetermined number.
  • Step S33 forming a second metal layer on the insulating layer, and forming the second metal layer into a plurality of second metal strip portions, wherein each of the second metal strip portions passes through the first via hole and the second via hole The first metal strip portion of each of the first metal wires is in contact, and the length of the second metal strip portion is greater than or equal to the first metal strip portion.
  • the manufacturing method may further include: forming a passivation layer on the plurality of second metal strip portions.
  • the passivation layer can protect the second metal strip.

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Abstract

提供一种阵列基板及其制作方法、平板显示装置。阵列基板的任一扇出引线包括：预定数目的第一金属条状部（221），位于玻璃基板上，沿扇出引线的延伸方向间隔设置；绝缘层（222），覆盖每一第一金属条状部（221），设有第一过孔（2221）和第二过孔（2222）；第二金属条状部（223），位于绝缘层（222）上，通过第一过孔（2221）和第二过孔（2222）与每一第一金属条状部（221）接触；多条扇出引线的第一金属条状部（221）的长度沿扇形的中心向边缘的方向逐渐递增以使各扇出引线的阻抗保持一致。

Description

阵列基板及其制作方法、平板显示装置
【技术领域】
本发明涉及平板显示技术领域，特别是涉及一种阵列基板，还涉及一种阵列基板的制作方法，另外涉及一种平板显示装置。
【背景技术】
人们对显示设备的需求日益增长，平板显示得以广泛普及，因此也带动了LCD（Liquid Crystal Display，液晶显示）、OLED（Organic Light-Emitting Diode，有机发光二极管）等行业的快速发展。
阵列基板是显示面板的重要组成部分，其具有有效显示区（简称AA 区，Active Area）以及环绕有效显示区的非有效显示区，有效显示区内具有信号线：扫描线和数据线，非有效显示区具有呈扇形分布的扇出引线，信号线与扇出引线对应连接，并通过扇出引线与外围的芯片连接。由于各扇出引线的长度并不相等，那么在扇出引线线宽相等的情况下，位于扇形中部的扇出引线的阻抗小于位于扇形边缘的扇出引线的阻抗，造成芯片输出的信号在到达信号线时不能保持同步，会造成显示不均匀现象。
请结合参见图1和图2，图1是现有技术一种扇形引线的结构示意图。图1中仅示意了三条扇出引线。扇出引线11、扇出引线12和扇出引线13呈扇形分布，扇出引线12位于扇形中心，扇出引线11和扇出引线13位于扇形边缘。扇形引线11和扇出引线13的长度相等。扇出引线12采用弯曲绕线的方式，增加了有效长度，与扇形引线11和扇出引线13的长度保持一致。图2是图1所示的扇出引线12的A-A'方向的剖视示意图。扇出引线12在依次层叠的第一金属层121、绝缘层122、第二金属层123和钝化层124上采用阵列制程得到。由于第一金属层121和第二金属层123相互绝缘，在输入信号时，第一金属层121和第二金属层123等效于两个并联的电阻。扇出引线11和扇出引线13与扇出引线12的内部结构相同。
由于各扇出引线的结构相同，长度也保持一致，因此扇出引线11、扇出引线12和扇出引线13的阻抗相等。但是，由于现有技术的工艺与制程的限制，扇出引线12的绕线部分会比较疏散，导致扇出引线12的高度增加，非有效显示区占用的面积将增大，因此不利于显示面板的窄边框设计，降低了阵列基板的利用率。
【发明内容】
本发明的主要目的是提供一种阵列基板及其制作方法、平板显示装置，能够使各扇出引线在长度不等的情况下阻抗保持一致。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包含有效显示区和环绕有效显示区的非有效显示区，非有效显示区内具有呈扇形分布的多条扇出引线，每一扇出引线具有预定长度，多条扇出引线的预定长度沿扇形的中心向边缘的方向逐渐递增，任一扇出引线包括：预定数目的第一金属条状部，位于玻璃基板上，预定数目的第一金属条状部沿扇出引线的延伸方向间隔设置，且每一第一金属条状部的长度小于或等于预定长度；绝缘层，覆盖每一第一金属条状部，且绝缘层覆盖每一第一金属条状部的位置设有第一过孔和第二过孔；第二金属条状部，位于绝缘层上，并通过第一过孔和第二过孔与每一第一金属条状部接触，第二金属条状部的长度等于预定长度；其中，多条扇出引线的第一金属条状部的长度沿扇形的中心向边缘的方向逐渐递增且预定数目沿该方向逐渐递减，以使各扇出引线的阻抗保持一致。
其中，任一扇出引线还包括钝化层，钝化层覆盖第二金属条状部。
其中，每一第一金属条状部的长度相等。
其中，每一第一金属条状部间隔的距离相等。
其中，每一扇出引线的线宽相等。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板的制作方法，制作方法包括：在玻璃基板上形成第一金属层，将第一金属层制成呈扇形分布的多条第一金属线，其中，每一第一金属线包括预定数目的第一金属条状部，每一第一金属条状部间隔设置，多条第一金属线的第一金属条状部的长度沿扇形的中心向边缘的方向递增且预定数目沿该方向递减；在多条金属线上形成绝缘层，在绝缘层覆盖每一第一金属条状部的位置形成第一过孔和第二过孔；在绝缘层上形成第二金属层，将第二金属层制成多条第二金属条状部，其中，每一第二金属条状部通过第一过孔和第二过孔与每一第一金属线的第一金属条状部接触，并且第二金属条状部的长度大于或等于第一金属条状部。
其中，制作方法还包括：在多条第二金属条状部上形成钝化层。
其中，每一第一金属线的各第一金属条状部的长度相等。
其中，每一第一金属条状部间隔的距离相等。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种平板显示装置，平板显示装置包括阵列基板，阵列基板包含有效显示区和环绕有效显示区的非有效显示区，非有效显示区内具有呈扇形分布的多条扇出引线，每一扇出引线具有预定长度，多条扇出引线的预定长度沿扇形的中心向边缘的方向逐渐递增，任一扇出引线包括：预定数目的第一金属条状部，位于玻璃基板上，预定数目的第一金属条状部沿扇出引线的延伸方向间隔设置，且每一第一金属条状部的长度小于或等于预定长度；绝缘层，覆盖每一第一金属条状部，且绝缘层覆盖每一第一金属条状部的位置设有第一过孔和第二过孔；第二金属条状部，位于绝缘层上，并通过第一过孔和第二过孔与每一第一金属条状部接触，第二金属条状部的长度等于预定长度；其中，多条扇出引线的第一金属条状部的长度沿扇形的中心向边缘的方向逐渐递增且预定数目沿该方向逐渐递减，以使各扇出引线的阻抗保持一致。
其中，任一扇出引线还包括钝化层，钝化层覆盖第二金属条状部。
其中，每一第一金属条状部的长度相等。
其中，每一第一金属条状部间隔的距离相等。
其中，每一扇出引线的线宽相等。
综上所述，本发明的阵列基板及其制作方法、平板显示装置在绝缘层覆盖每一第一金属条状部的位置设置第一过孔和第二过孔，使得第二金属条状部通过第一过孔和第二过孔与每一第一金属条状部接触，通过调整各扇出引线的第一金属条状部的长度，达到各扇出引线在长度不等的情况下阻抗保持一致的目的，能够降低扇出引线的高度，增加阵列基板的利用率，有利于显示面板的窄边框设计。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
【附图说明】
图1是现有技术一种扇形引线的结构示意图；
图2是图1所示的扇出引线12的A-A'方向的剖视示意图；
图3是本发明阵列基板上非有效显示区内的扇出引线一实施例的结构示意图；
图4是图3所示的B-B'方向的剖视示意图；
图5是图4所示的扇出引线的等效电路示意图；
图6是本发明阵列基板的制作方法的流程示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，均属于本发明保护的范围。
请参见图3，是本发明阵列基板上非有效显示区内的扇出引线一实施例的结构示意图。
阵列基板包含有效显示区和非有效显示区。非有效显示区环绕有效显示区，有效显示区内具有信号线，非有效显示区内具有呈扇形分布的多条扇出引线。信号线与扇出引线对应连接以接收外部输入的信号。每一扇出引线具有预定长度，多条扇出引线的预定长度沿扇形的中心向边缘的方向逐渐递增。在本实施例中，每一扇出引线的线宽相等。应当理解，图中仅示意了三条扇出引线21、22和23，但并不限定扇出引线的数目。扇出引线22位于扇形中心，扇出引线21、23位于扇形边缘。
三条扇出引线21、22和23均具有预定长度，扇出引线22的预定长度L小于扇出引线21、23的预定长度。请结合参见图4，是图3所示的B-B'方向的剖视示意图。扇出引线22包括第一金属条状部221、绝缘层222和第二金属条状部223。
第一金属条状部221为预定数目个，位于玻璃基板（图未示）上，预定数目的第一金属条状部221沿扇出引线22的延伸方向间隔设置，且每一第一金属条状部221的长度d小于或等于预定长度L。由于受到扇出引线22的预定长度L的限制，第一金属条状部221的长度d越接近预定长度L，预定数目就越小。可以理解，如果第一金属条状部221的长度d等于预定长度L，那么第一金属条状部221的预定数目为1。在本实施例中，每一第一金属条状部221的长度d相等。进一步，每一第一金属条状部221间隔的距离相等。
绝缘层222覆盖每一第一金属条状部221，且绝缘层222覆盖每一第一金属条状部221的位置设有第一过孔2221和第二过孔2222。在两个第一金属条状部221之间，绝缘层222还覆盖玻璃基板。
第二金属条状部223位于绝缘层222上，并通过第一过孔2221和第二过孔2222与每一第一金属条状部221接触，第二金属条状部223的长度等于预定长度L。
扇出引线21和扇出引线23的内部结构与扇出引线22的内部结构相同，不同之处在于，扇出引线21和扇出引线23的第一金属条状部的长度大于扇出引线22的第一金属条状部221的长度d，且扇出引线21和扇出引线23同扇出引线22共用绝缘层222。对于三条及以上的多条扇出引线而言，多条扇出引线的第一金属条状部的长度沿扇形的中心向边缘的方向逐渐递增且预定数目沿该方向逐渐递减，以使各扇出引线的阻抗保持一致。
在更多实施例中，扇出引线22还包括钝化层224，钝化层224覆盖于第二金属条状部223上，可增强第二金属条状部223的耐磨和耐腐蚀能力。
请再结合参见图2和图5，图5是图4所示的扇出引线的等效电路示意图。图4中具有两个第一金属条状部221，其对应图5中的两个阻抗R1，并且每一第一金属条状部221通过第一过孔2221和第二过孔2222与第二金属条状部223接触，相当于第一金属条状部221与第二金属条状部223的部分并联，其对应图5中的阻抗R1与阻抗R21及R23并联。由于第二金属条状部223并不是每个部分都与第一金属条状部221接触，没有接触的部分等效于图5中的阻抗R22。也就是说，阻抗R21、阻抗R22、阻抗R23的和为第二金属条状部223的阻抗。
这里将扇出引线22的等效电路与图2中扇出引线12的等效电路作比较，假设现有技术中扇出引线12的上下绝缘的两层金属的阻抗分别为R1'和R2'，其等效电路为R1'和R2'并联，可以知道R1'大于R1。
由于图4中扇出引线22的第二金属条状部223的长度等于预定长度L，则R2与R2'很接近，可认为R2=R2'=R21+R22+R23。
图2中扇出引线12的等效阻抗为：
Ro '=(R1'*R2')/(R1'+R2')=R2'/(1+R2'/R1')
在同等长度条件下，第二金属层123的厚度一般小于第一金属层121的厚度，因此根据电阻的公式R=ρl/S，R2'≥R1'，则Ro '≤R2/2
图5中扇出引线22的等效阻抗为：
Ro =(R1*R21)/(R1+R21)+R22+(R1*R23)/(R1+R23)=R21/(1+R21/R1)+R22+R23/(1+R23/R1)
如果调整第一金属条状部221的长度d小于一定值，R22就可以超过R2的一半，则Ro 就可以大于R2/2，那么Ro ≥Ro '。
因此，在同等长度的条件下，经过合理调整第一金属条状部221的长度d，可使得扇出引线22的阻抗与扇出引线12的阻抗保持一致。
此外，若扇出引线22的第一金属条状部221的长度d增加，则第二金属条状部223与第一金属条状部221没有接触的部分长度将减小，导致阻抗R22减小，进而Ro 减小。这表明扇出引线21、23的预定长度虽然大于扇出引线22的预定长度L，但是可以通过增加扇出引线21、23的第一金属条状部的长度，使得扇出引线21或23的阻抗减小，从而与扇出引线22的阻抗保持一致。
本发明实施例的阵列基板通过调整各扇出引线的第一金属条状部的长度，能够使各扇出引线在长度不等的情况下阻抗保持一致，不必对扇出引线进行绕线处理，能够降低扇出引线的高度，增加阵列基板的利用率，有利于显示面板的窄边框设计。
本发明还提供一种平板显示装置，该平板显示装置包括上述实施例的阵列基板。平板显示装置的其他部分请参照现有技术，此处不详述。
请参见图6，是本发明阵列基板的制作方法的流程示意图。制作方法包括以下步骤：
步骤S31：在玻璃基板上形成第一金属层，将第一金属层制成呈扇形分布的多条第一金属线，其中，每一第一金属线包括预定数目的第一金属条状部，每一第一金属条状部间隔设置，多条第一金属线的第一金属条状部的长度沿扇形的中心向边缘的方向递增且预定数目沿该方向递减。
其中，第一金属层可以通过沉积等工艺形成。第一金属层形成后，可通过湿法蚀刻工艺将第一金属层制作成呈扇形分布的多条第一金属线。由于每一金属线包括间隔设置的预定数目的第一金属条状部，则第一金属线不是连续的。每条第一金属线的第一金属条状部的预定数目是不同的，第一金属条状部的长度越长，预定数目越小。
在本实施例中，每一第一金属线的各第一金属条状部的长度相等，每一第一金属条状部间隔的距离相等。
步骤S32：在多条金属线上形成绝缘层，在绝缘层覆盖每一第一金属条状部的位置形成第一过孔和第二过孔。
其中，绝缘层可通过涂覆等工艺形成，绝缘层形成后，可通过干法蚀刻工艺在绝缘层上设置第一过孔和第二过孔。。
步骤S33：在绝缘层上形成第二金属层，将第二金属层制成多条第二金属条状部，其中，每一第二金属条状部通过第一过孔和第二过孔与每一第一金属线的第一金属条状部接触，并且第二金属条状部的长度大于或等于第一金属条状部。
其中，第二金属层也可通过沉积等工艺形成，第二金属层形成后，可通过湿法蚀刻工艺将第二金属层制作成多条第二金属条状部，第二金属条状部的线宽与绝缘条状部的线宽相等。第二金属条状部的长度即是扇出引线的长度，第一金属条状部的长度可以等于第二金属条状部的长度，此时第一金属条状部的预定数目为1，相应的，此时第一过孔和第二过孔也各为一个，这种情况等效于，第一金属条状部与第二金属条状部并联。
在步骤S33后，制作方法还可包括：在多条第二金属条状部上形成钝化层。钝化层可对第二金属条状部起到保护作用。
通过上述方式，本发明的阵列基板及其制作方法、平板显示装置在绝缘层覆盖每一第一金属条状部的位置设置第一过孔和第二过孔，使得第二金属条状部通过第一过孔和第二过孔与每一第一金属条状部接触，通过调整各扇出引线的第一金属条状部的长度，达到各扇出引线在长度不等的情况下阻抗保持一致的目的，能够降低扇出引线的高度，增加阵列基板的利用率，有利于显示面板的窄边框设计。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (14)

  1. 一种阵列基板，包含有效显示区和环绕所述有效显示区的非有效显示区，所述非有效显示区内具有呈扇形分布的多条扇出引线，其特征在于，每一所述扇出引线具有预定长度，多条所述扇出引线的预定长度沿所述扇形的中心向边缘的方向逐渐递增，任一所述扇出引线包括：
    预定数目的第一金属条状部，位于玻璃基板上，所述预定数目的第一金属条状部沿所述扇出引线的延伸方向间隔设置，且每一所述第一金属条状部的长度小于或等于所述预定长度；
    绝缘层，覆盖每一所述第一金属条状部，且所述绝缘层覆盖每一所述第一金属条状部的位置设有第一过孔和第二过孔；
    第二金属条状部，位于所述绝缘层上，并通过所述第一过孔和所述第二过孔与每一所述第一金属条状部接触，所述第二金属条状部的长度等于所述预定长度；
    其中，多条所述扇出引线的第一金属条状部的长度沿所述扇形的中心向边缘的方向逐渐递增且预定数目沿所述方向逐渐递减，以使各所述扇出引线的阻抗保持一致。
  2. 根据权利要求1所述的阵列基板，其特征在于，任一所述扇出引线还包括钝化层，所述钝化层覆盖所述第二金属条状部。
  3. 根据权利要求1所述的阵列基板，其特征在于，每一所述第一金属条状部的长度相等。
  4. 根据权利要求3所述的阵列基板，其特征在于，每一所述第一金属条状部间隔的距离相等。
  5. 根据权利要求1所述的阵列基板，其特征在于，每一所述扇出引线的线宽相等。
  6. 一种阵列基板的制作方法，其特征在于，所述制作方法包括：
    在玻璃基板上形成第一金属层，将所述第一金属层制成呈扇形分布的多条第一金属线，其中，每一所述第一金属线包括预定数目的第一金属条状部，每一所述第一金属条状部间隔设置，多条所述第一金属线的第一金属条状部的长度沿所述扇形的中心向边缘的方向递增且预定数目沿所述方向递减；
    在所述多条金属线上形成绝缘层，在所述绝缘层覆盖每一所述第一金属条状部的位置形成第一过孔和第二过孔；
    在所述绝缘层上形成第二金属层，将所述第二金属层制成多条第二金属条状部，其中，每一所述第二金属条状部通过所述第一过孔和所述第二过孔与每一所述第一金属线的第一金属条状部接触，并且所述第二金属条状部的长度大于或等于所述第一金属条状部。
  7. 根据权利要求1所述的制作方法，其特征在于，所述制作方法还包括：在所述多条第二金属条状部上形成钝化层。
  8. 根据权利要求7所述的制作方法，其特征在于，每一所述第一金属线的各所述第一金属条状部的长度相等。
  9. 根据权利要求8所述的制作方法，其特征在于，每一所述第一金属条状部间隔的距离相等。
  10. 一种平板显示装置，其特征在于，所述平板显示装置包括阵列基板，所述阵列基板包含有效显示区和环绕所述有效显示区的非有效显示区，所述非有效显示区内具有呈扇形分布的多条扇出引线，每一所述扇出引线具有预定长度，多条所述扇出引线的预定长度沿所述扇形的中心向边缘的方向逐渐递增，任一所述扇出引线包括：
    预定数目的第一金属条状部，位于玻璃基板上，所述预定数目的第一金属条状部沿所述扇出引线的延伸方向间隔设置，且每一所述第一金属条状部的长度小于或等于所述预定长度；
    绝缘层，覆盖每一所述第一金属条状部，且所述绝缘层覆盖每一所述第一金属条状部的位置设有第一过孔和第二过孔；
    第二金属条状部，位于所述绝缘层上，并通过所述第一过孔和所述第二过孔与每一所述第一金属条状部接触，所述第二金属条状部的长度等于所述预定长度；
    其中，多条所述扇出引线的第一金属条状部的长度沿所述扇形的中心向边缘的方向逐渐递增且预定数目沿所述方向逐渐递减，以使各所述扇出引线的阻抗保持一致。
  11. 根据权利要求10所述的平板显示装置，其特征在于，任一所述扇出引线还包括钝化层，所述钝化层覆盖所述第二金属条状部。
  12. 根据权利要求10所述的平板显示装置，其特征在于，每一所述第一金属条状部的长度相等。
  13. 根据权利要求12所述的平板显示装置，其特征在于，每一所述第一金属条状部间隔的距离相等。
  14. 根据权利要求10所述的平板显示装置，其特征在于，每一所述扇出引线的线宽相等。
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