TWI327671B - Electrical connector and method thereof and electronic module - Google Patents
Electrical connector and method thereof and electronic module Download PDFInfo
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- TWI327671B TWI327671B TW95126033A TW95126033A TWI327671B TW I327671 B TWI327671 B TW I327671B TW 95126033 A TW95126033 A TW 95126033A TW 95126033 A TW95126033 A TW 95126033A TW I327671 B TWI327671 B TW I327671B
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- 238000000034 method Methods 0.000 title claims description 11
- 239000011532 electronic conductor Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 3
- 125000006850 spacer group Chemical group 0.000 claims 2
- 241000239226 Scorpiones Species 0.000 claims 1
- 235000013405 beer Nutrition 0.000 claims 1
- 238000005452 bending Methods 0.000 claims 1
- 230000005250 beta ray Effects 0.000 claims 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims 1
- 238000005192 partition Methods 0.000 claims 1
- 238000004804 winding Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 21
- 229910052736 halogen Inorganic materials 0.000 description 5
- 125000005843 halogen group Chemical group 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910052500 inorganic mineral Inorganic materials 0.000 description 2
- 239000011707 mineral Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
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Description
1.327671 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一組介於兩電子元件間的電子連接 ', 器(connector) ’特別是有關於一組介於一個驅動1C以及 , 一個顯示面板的晝素區間的電子連接器。 【先前技術】 顯示面板通常包括有一個晝素區以及連接到晝素區 的複數條資料線DL與閘極線GL,例如液晶顯示(liquid ® crystal display,LCD)面板。如第1圖所示,這些資料線與 閘極線係被連接到複數個積體電路驅動器或驅動晶片 (driver 1C)如資料驅動晶片10或閘極驅動晶片20上。所 有驅動晶片皆包括有具有複數個電性導線墊(未顯示)的 一個焊接墊區(bond pad area) 210,以將複數條電子導線 (electrical conductor)連接到在晝素區的連接器區220上, 如第2圖所不。由於在晶片端相鄰導線間的間隔SI係运 小於在晝素區端相鄰導線間的間隔SP,一個展開(fan-out, φ FS)樣本(pattern)係用來使導線從晶片端展開到晝素區。此 展開樣本中,樣本邊界的導線總是遠比中間部分的導線 長。舉例來說,導線A係短於導線B,導線B係短於導 線C,以此類推。如果導線是由相同的材質所構成且具有 . 相同的厚度及寬度,則較長導線的電阻值會大於較短導線 的電阻值。 ' 如第3圖所示,為了減少一個展開樣本的導線間的電 阻值差異,不同的鑛齒形路徑(zigzag path)樣本被用在中 間部分的導線上。特別地,Na等(美國專利第6, 104, 4651.327671 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a set of electronic connections between two electronic components, 'the connector' is particularly related to a group of one drive 1C and one The electronic connector of the display panel's pixel section. [Prior Art] The display panel usually includes a pixel region and a plurality of data lines DL and gate lines GL connected to the pixel regions, such as a liquid crystal display (LCD) panel. As shown in Fig. 1, these data lines and gate lines are connected to a plurality of integrated circuit drivers or driver 1C such as data drive wafer 10 or gate drive wafer 20. All of the driver wafers include a bond pad area 210 having a plurality of electrical conductor pads (not shown) for connecting a plurality of electrical conductors to the connector region 220 in the pixel region. On, as shown in Figure 2. Since the spacing SI between adjacent wires at the wafer end is smaller than the spacing SP between adjacent wires at the end of the pixel region, a fan-out (φ FS) pattern is used to unwind the wire from the wafer end. To the Susie District. In this expanded sample, the wire at the sample boundary is always much longer than the wire in the middle portion. For example, wire A is shorter than wire B, wire B is shorter than wire C, and so on. If the wires are made of the same material and have the same thickness and width, the resistance of the longer wires will be greater than the resistance of the shorter wires. As shown in Figure 3, in order to reduce the difference in resistance between the wires of a developed sample, different zigzag path samples were used on the middle portion of the wire. In particular, Na et al. (US Patent No. 6, 104, 465)
Client's Docket No,:AU0503080 TT’s Docket No:0632-A50666-TW/Final/Jasonkung 5 連接器樣本’其具有-直線區域以及 同:Λ線區域以及彎曲區域中的導 ^ ^ ^^ ^ £成中的泠線可包括數種不同 4曲$狀例如波浪形狀以及脊狀線形狀。Client's Docket No,: AU0503080 TT's Docket No:0632-A50666-TW/Final/Jasonkung 5 Connector sample 'It has a - straight line area and the same: the Λ line area and the bend in the bend area ^ ^ ^ ^ ^ £ The rifling line may include several different ridges such as a wave shape and a ridge line shape.
Kim專(美國專利第$ iqi 本,其中每一條導後右一個ϋ1就)揭露了一個展開樣 JtR八- ’、、'〃有個乍導線部分連接到一個寬墓線 4刀。错由調整寬導線部分的長产, ’、 以減少導線間的電阻值差異。X 增加電阻值 樣本,美國專利第I Μ7,450幻揭露了一個展開 以ί -個I: I有一個窄導線部分、-個寬導線部分 間的中f H二於窄導線部分寬度與寬導線部分寬度之 門的中間免度的傾斜導線部分。 ι 口用改叇導線覓度或利用調整寬導後邱八f声类 開樣本的導線間的電阻值差異。= ===利用不同銘齒形路徑來降低其電阻值差異。如 ΐ产Γ:吉:個蘇齒形路徑以可允許-條導線的路徑 有見度(swath Wldth)。舉例來說,導線A因具 c而具有鑛齒寬度^,導線6具有銀齒 ^又B,導線C、D及E則分別具有鑛齒寬度|、1以 i寬^:^言…個㈣形路徑的轉長度會隨著銀 二= 。因此,為了降低導線間的電阻值差昱, 本中,中間導線的蘇齒形鑛齒寬度會大於兩 =線的鑛齒形錯齒寬度。如第3圖所示,Wa大於Wc,Kim specializes (US Patent No. $ iqi, each of which leads to the right one ϋ1) reveals an unfolding JtR eight- ’, '〃 has a 乍 wire part connected to a wide tomb line 4 knives. The error is to adjust the long-term production of the wide wire portion, to reduce the difference in resistance between the wires. X increases the resistance value sample, U.S. Patent No. I, 7,450 reveals an unfolding to ί - I: I has a narrow wire portion, - a wide wire portion between the middle f H two narrow wire portion width and a wide wire The portion of the width of the door that is free of the inclined portion of the wire. Use the 觅 port to change the wire width or use the adjustment width to guide the difference between the wires of the sample. = === Use different indentation paths to reduce the difference in resistance values. Such as ΐ Γ Γ: Kyrgyzstan: a suture-shaped path with allowable - wire path visibility (swath Wldth). For example, the wire A has a mineral tooth width ^ with a c, the wire 6 has a silver tooth and a B, and the wires C, D, and E respectively have a tooth width |, 1 with an i width ^: ^... (4) The length of the shape of the path will follow the silver two =. Therefore, in order to reduce the difference in resistance between the wires, the width of the S-toothed tooth of the intermediate wire is greater than the width of the tooth-shaped tooth of the two-line. As shown in Figure 3, Wa is greater than Wc,
Wc貝丨大於Wd以及We。因此,導線中的路徑長度差異可Wc Bellow is larger than Wd and We. Therefore, the path length difference in the wire can be
Client's Docket N〇.:AU0503080 TT s Docket N〇:〇632-A50666-TW/FinaVJasonkung 6 1327671 饭降低氧大致消除„恐昍由次、 器晝素區的導線數目漸增,在二個d f動晶片到顯示 展開樣本(如第3圖所示的樣本)的。段的 效降低導線間的電阻值差異。 形路仫可舵無法有 因此,需要提供一個 ㈣路徑長度的範S。叫展_本,明加一個鋸 【發明内容】Client's Docket N〇.: AU0503080 TT s Docket N〇: 〇 632-A50666-TW/FinaVJasonkung 6 1327671 The reduction of oxygen in the rice is roughly eliminated „ 昍 昍 、 、 、 、 、 、 、 、 、 、 、 、 、 、 To display the unfolded sample (such as the sample shown in Figure 3), the effect of the segment reduces the difference in resistance between the wires. The shape of the rudder cannot be rudder. Therefore, it is necessary to provide a (S) path length of the S. , Mingjia a saw [invention content]
有鑑於此,本發明提供一種具有兩個以上 展開樣本,用以降低哎洁除厍門婵士 士 a 1 ί-段的 *低Μ除展開樣本中的電子導線間的路 = 在驅動晶片以及顯示面板間的導線可 ,、有兩個以上的鋸齒形鋸齒寬度。 士、上於上述目的,一種具有兩個以上展閧區段的展開樣 ,應用在-驅動晶片(IC)以及—顯示面板間,用以降低 ,消除展開樣本中的電子導線間的路徑長度差異。因此, 部分在驅動晶片以及顯示面板間的導線具有兩個以上的 鑛齒形蘇齿寬度。 …在一個具有兩個展開區段的展開樣本中,舉例來說, 一第一展開區段擴大晶片端兩相鄰導線間的間隔&到一 個中間間Fwj SM,並且一第二展開區段更進一步擴大此中 ,間隔SM到間隔sp在晝素區端。利用此兩個展開區段, 第一次鋸齒形擴展係應用在晶片端以及第一展開區段之 間的部分導線上,且第二次鋸齒形擴展係應用在第一展開 區段以及第二展開區段之間的部分導線上。一般而言,第 一次鑛齒形擴展部分的鋸齒形鋸齒寬度會大於第一次鋸 齒形擴展部分的鋸齒形鋸齒寬度。In view of the above, the present invention provides a method for reducing the path between the electronic wires in the unfolded sample of the Μ 厍 婵 a = = = = = = = = = = = = = The wires between the display panels can have more than two zigzag zigzag widths. For the above purpose, a deployment sample having two or more spread sections is applied between the -drive wafer (IC) and the display panel to reduce and eliminate the difference in path length between the electronic leads in the unfolded sample. . Therefore, the wire partially driven between the wafer and the display panel has more than two orthodontic tooth widths. ...in a deployed sample having two expanded sections, for example, a first expanded section enlarges the spacing between two adjacent wires at the wafer end & to an intermediate space Fwj SM, and a second expanded section Further expanding this, the interval SM to the interval sp is at the end of the pixel region. With the two expansion sections, the first zigzag extension is applied to a portion of the wire between the wafer end and the first deployment section, and the second zigzag extension is applied to the first deployment section and the second Expand on some of the wires between the segments. In general, the zigzag serration width of the first tooth profile extension will be greater than the zigzag serration width of the first zigzag extension.
Chengs Docket No.:AU0503080 π s Docket N〇:0632-A50666-TW/Fmayjasonkung 1327671 開區擴展’使得展開樣本可具有介於第二展 00又 旦素區之間的一個或以上的展開區段。 【實施方式】 :讓二發明之上述和其他目的、特徵、和優點能更明 ,.'、 文特舉出較佳實施例,並配合所附圖式,作詳 細說明如下。 ν 17 ^ 本發明係利用設置於_個展開#本中的複數倏電子 一個積體電路(驅動晶片)以及-個顯示面板 mil ° ^ ^:^ 或以上的展開區段以兩次或兩次以上 擴大相鄰導線間的寬度。如第4A_4B圖所示 區段观擴大晶片端兩相鄰導線_間 1 區段FS2更進-步擴大此二 &sM到間feSp在晝素區端。利用此兩次 鑛齒形路徑可應用在至少兩個區段。如第5圖所示^一 ==段现係大約位於晶片端與第一展開區段 曰 1且弟—鋸齒形路徑區段ZS2係大 =现與第二展開區段FS2之間。一般而言弟同f 2二鑛Γ路徑區段ZS1的鑛齒形鑛齒寬度係小 :弟亡形路徑區段ZS2的鋸齒形鋸齒寬度。舉例來 鑛齒形路徑區段观的鑛齒形㈣寬度 A1 h小於其在弟—鑛齒形路;^阿_|π· 7 q。卜 办峪仫的鋸齒形鋸齒寬 :Α”α此’舉例來說,當欲降低導線八與導線f間的 ::力值?’同時使用鑛齒寬度WA1以及鑛齒寬度^ 采曰加導線A的路徑長度係比單獨利用—個鑛齒寬度—Chengs Docket No.: AU0503080 π s Docket N〇: 0632-A50666-TW/Fmayjasonkung 1327671 Open area expansion ' allows the unfolded sample to have one or more expanded sections between the second 00 and the dans. The above and other objects, features, and advantages of the invention will be apparent from the description of the appended claims. ν 17 ^ The present invention utilizes a plurality of integrated circuits (drive wafers) and a display panel mil ° ^ ^: ^ or more of the expansion sections set in the _ expansions to be used twice or twice. The above expands the width between adjacent wires. As shown in Fig. 4A_4B, the segment view expands the wafer end two adjacent wires _ between the 1 segment FS2 and further expands the two &sM to the interfeSp at the end of the pixel region. This two-toothed toothed path can be applied to at least two sections. As shown in Fig. 5, the ^== segment is now located approximately at the wafer end and the first unfolding segment 曰 1 and the sigmoid-shaped path segment ZS2 is large = now between the second unfolding segment FS2. Generally speaking, the width of the ore-shaped ore tooth of the path segment ZS1 of the f 2 second ore zone is small: the zigzag serration width of the zone segment ZS2. For example, the ore shape of the ore-shaped path section (4) width A1 h is smaller than its —-mine tooth-shaped road; ^A_|π· 7 q. The zigzag serrated width of the 峪仫 峪仫 Α Α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α α The path length of A is more than the width of the single tooth.
Client’s Docket No.:AU0503080 TT5s Docket No:0632-A50666-TW/Final/Ja: tsonkung 1327671 更有效。 根據在晶月端的導線間隔&以及在畫素區端 間隔sP,以及根據晶片與晝素區之間的距離,可呈右j 個以上的展開區段,使得兩個以上的鑛齒 可ΐ實作在其上。舉例純,可具有 二人擴大導線間隔,如第6圖所示。如圖所示,第一 區段FS1擴大在晶片端的導線間隔&到—個第 = 隔s=,並且第二展開區段FS2擴大此第一中間間严Β曰 到一第二中間間隔〜2。第三展開區段FS3接著用:= ^端=二中間間隔Sm2在畫素區端擴大到間隔“ 段。擴大方式,儲形路徑可應用在至少三個區 曰又月端Μ所不’弟一鑛齒形路徑區段ZS1係大約位於 】曰片=展開區段FS1之間,第二鑛齒形 Γ二日t 第—展開區段fsi與第二展開區段FS2 段is2二:鑛:形路徑區段ZS3係大約位於第二展開區 I、弟二展開區段FS3之間。一般而言,同— 形路徑區段ZS1的鋸齒形鑛齒寬度係小於第 开,路徑區段ZS2的鋸齒形鋸齒寬度,而且盆在第= ==彳㈣段ZS2㈣㈣鑛齒寬度係小於其: 鑛回,路徑區段ZS3的鑛齒形銘齒寬度。 弟- 综上所述,在一依據本發明之顯示面板中 辛ί二接至晝素區。用來電性連接驅動晶片到書 設置於一或多個展開樣本中。其中至ί 圖:2有至少兩個展開區段。舉例來說,如第7 來電性連接每個驅動晶片如資料驅動晶>5 710 或閘極驅動W 72G到畫素㈣某—區段的電子導線= 一一 9 LSZ/t/l = 開區?的展開樣本中。因此,兩個 示。 又可應用在母個展開樣本中,如第5圖所 用來^第5:所示的刪路徑樣本只是 擴展線在i直線“邊Ϊ 隨著增加:度。因此,導線的電阻值也可 ί曲I?線可以是如第8B圖所示的波浪形樣二 ϊ;也r是不規則的。此外,其中部分導他 二.'乂 1例^’靠近畫素區端的導線F或導線e的一段 i^ #近晶片端的同—導線寬,以降低導線的電阻值。 (addlt在―或多個展開區段中湘—個外加雜齒形 圖所_^,^)樣本以增加導線的路徑長度。如第9 ,斤不,可在弟—展開區段㈣,實作一 細。同理,也可在第二展開區段上力2 = 乍個第一外加鑛#形路徑區段azS2。 徑長用種降:設置於一展開樣本的導線間路 長度差異方法,用以電性連接一驅動晶片到至 =板的畫素區的一區段上。任何熟悉此項技藝者亦可輕易 :用本發明在設置於-展開樣本的電子導線間,用以電性 連接兩個電子模組或元件。Client’s Docket No.: AU0503080 TT5s Docket No:0632-A50666-TW/Final/Ja: tsonkung 1327671 More effective. According to the wire spacing & at the end of the crystal moon and the spacing sP at the pixel end, and according to the distance between the wafer and the halogen region, there may be more than j expansion segments on the right side, so that more than two mineral teeth may be The implementation is on it. For example, it can have two people to expand the wire spacing, as shown in Figure 6. As shown, the first segment FS1 expands the wire spacing at the wafer end & to the first = s =, and the second expanded segment FS2 expands the first intermediate to the second intermediate interval. 2. The third expansion section FS3 then uses: = ^ end = two intermediate intervals Sm2 to expand to the interval "section" at the pixel end. The expansion mode, the storage path can be applied in at least three areas, and the end of the month is not the same. The first tooth profile path section ZS1 is located approximately between the 曰 = = expansion section FS1, the second ore profile Γ 2nd t first-expansion section fsi and the second expansion section FS2 section is2 2: mine: The shape path section ZS3 is located between the second deployment area I and the second expansion section FS3. In general, the zigzag tooth width of the same-shaped path section ZS1 is smaller than the first opening, and the path section ZS2 Zigzag serrated width, and the basin is in the ===彳(4) segment ZS2(4)(4) The ore tooth width is smaller than: the mine back, the path segment ZS3 has the ore tooth shape width. Brother - In summary, in accordance with the present invention The display panel is connected to the halogen region, and is used to electrically connect the driving chip to the book and set in one or more unfolded samples. wherein to 2: there are at least two expanded segments. For example, The seventh caller is connected to each driver chip such as data drive crystal > 5 710 or gate drive W 72G to pixel (4) - The electronic conductor of the segment = one 9 LSZ / t / l = open region of the unfolded sample. Therefore, two shows. Can also be applied to the parent expansion sample, as shown in Figure 5 ^ 5: The cut-off path sample shown is just the extension line in the i-line "edge" with increasing: degree. Therefore, the resistance value of the wire can also be I. The wire can be a wave-like shape as shown in Fig. 8B; also r is irregular. In addition, some of them lead to the second. '乂1 case^' is close to the wire F of the pixel end or a section of the wire e of the same wire width of the near-wafer end to reduce the resistance value of the wire. (addlt is in the "or" or "extended" section - plus a dentate pattern _^, ^) sample to increase the path length of the wire. If the ninth, Jin is not, can be in the younger - expand the section (four), the implementation of a fine. Similarly, it is also possible to force 2 = one first additional ore-shaped path section azS2 on the second unfolding section. Path length drop: A method of difference in length between wires of an unfolded sample for electrically connecting a drive wafer to a section of the pixel region of the plate. Anyone skilled in the art can also easily use the present invention to electrically connect two electronic modules or components between electronic leads disposed in the unfolded sample.
、因此,雖然本發明已以較佳實施例揭露如上,然豆 並非用以限^本發明,任何熟悉此項技藝者,在不脫ϋ 發明之精神和範圍内’當可做些許更動與_,因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。XTherefore, although the present invention has been disclosed above in the preferred embodiments, the present invention is not intended to limit the invention, and any person skilled in the art will be able to make some changes and _ without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. X
Clients Docket N〇.:AU0503080 TT's Docket No.O632-.450666-TW/Final/Jasonkung 10 1327671 【圖式簡單說明】 第1圖為一示意圖,係顯示在一習知顯示面板的晝素 區中複數資料驅動晶片以及閘極驅動晶片係電性連接至 - 資料線及閘極線。 . 第2圖為一示意圖,係顯示一習知展開樣本,用於利 ' 用電子導線連接一驅動晶片的焊接墊區以及至少晝素區 的一段。 第3圖為一示意圖,係顯示在一習知展開樣本的一個 典型鋸齒形路徑長度擴展。 • 第4A-4B圖為一示意圖,係顯示一依據本發明實施例 的展開樣本,用於利用電子導線連接一驅動晶片的焊接墊 區以及至少晝素區的一段。 第5圖為一示意圖,係顯示一依據本發明實施例的一 展開樣本的鋸齒形路徑長度擴展。 第6圖為一示意圖,係顯示一依據本發明另一實施例 的展開樣本。 第7圖為一示意圖,係顯示一顯示面板具有複數驅動 φ 晶片利用依據本發明之設置於一展開樣本中的複數電子 導線電性連接至一晝素區。 第8A圖為一示意圖,係顯示一鋸齒形樣本。 第8B圖為一示意圖,係顯示另一鋸齒形樣本。 第9圖為一示意圖,係顯示在展開區段中一個或以上 ' 的外加鋸齒形樣本。 【主要元件符號說明】 10〜貢料驅動晶片,Clients Docket N〇.:AU0503080 TT's Docket No.O632-.450666-TW/Final/Jasonkung 10 1327671 [Simplified Schematic] Figure 1 is a schematic diagram showing the plural in a pixel area of a conventional display panel The data driving chip and the gate driving chip are electrically connected to the - data line and the gate line. Fig. 2 is a schematic view showing a conventional unfolded sample for connecting a solder pad region of a driving wafer and at least a segment of a halogen region by an electronic wire. Figure 3 is a schematic diagram showing a typical zigzag path length extension of a conventionally developed sample. • 4A-4B is a schematic view showing an unfolded sample for connecting a solder pad region of a driving wafer and at least a segment of a halogen region using an electronic wire in accordance with an embodiment of the present invention. Figure 5 is a schematic diagram showing the zigzag path length extension of an unfolded sample in accordance with an embodiment of the present invention. Fig. 6 is a schematic view showing an unfolded sample according to another embodiment of the present invention. Fig. 7 is a schematic view showing a display panel having a complex drive φ wafer electrically connected to a halogen region by a plurality of electronic wires disposed in a developed sample according to the present invention. Figure 8A is a schematic view showing a zigzag sample. Figure 8B is a schematic view showing another zigzag sample. Figure 9 is a schematic diagram showing an applied zigzag sample of one or more ' in the unfolded section. [Main component symbol description] 10~ tribute drive wafer,
Client’s Docket No.:AU0503080 TT's Docket No:0632-A50666-TW/Final/Jasonkung 11 1327671 20〜間極驅動晶片, DL〜資料線; GL〜閘極線; - 210〜焊接墊區; . 220〜連接器區; S】、Sm、Sp、SmI、Sjy[2〜導線間隔, ZS〜雜齒形路控區段, A-F〜導線, WA、WA1、WA2、WB、wc' WD、WE〜鋸齒寬度; # FS1〜第一展開區段; FS2〜第二展開區段; FS3〜第三展開區段; ZS1〜第一鋸齒形路徑區段; ZS2〜第二鋸齒形路徑區段; ZS3〜第三鋸齒形路徑區段; 710〜貢料驅劫晶片, 720〜閘極驅動晶片; φ AZS1〜第一外加鋸齒形路徑區段; AZS2〜第二外加鋸齒形路徑區段。Client's Docket No.: AU0503080 TT's Docket No: 0632-A50666-TW/Final/Jasonkung 11 1327671 20~Interpolar drive chip, DL~ data line; GL~gate line; - 210~ solder pad area; . 220~ connection S], Sm, Sp, SmI, Sjy [2 ~ wire spacing, ZS ~ miscellaneous road section, AF ~ wire, WA, WA1, WA2, WB, wc' WD, WE ~ sawtooth width; #FS1~1nd expansion section; FS2~2nd expansion section; FS3~3rd expansion section; ZS1~1nd zigzag path section; ZS2~2nd zigzag path section; ZS3~3rd sawtooth Shape path section; 710 ~ tribute robbing wafer, 720 ~ gate drive wafer; φ AZS1 ~ first applied zigzag path section; AZS2 ~ second plus zigzag path section.
Client's Docket N〇.:AU0503080 TT5s Docket No:0632-A50666-TW/Final/JasonkungClient's Docket N〇.:AU0503080 TT5s Docket No:0632-A50666-TW/Final/Jasonkung
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US20090262292A1 (en) * | 2008-04-16 | 2009-10-22 | Au Optronics Corporation | Electrical connectors between electronic devices |
US8325309B2 (en) * | 2008-09-23 | 2012-12-04 | Apple Inc. | Display having a plurality of driver integrated circuits |
TWI391730B (en) * | 2009-02-11 | 2013-04-01 | Au Optronics Corp | Flat panel display |
CN101510383B (en) * | 2009-03-26 | 2011-12-07 | 友达光电股份有限公司 | Flat display panel |
KR101627245B1 (en) * | 2009-05-11 | 2016-06-07 | 삼성디스플레이 주식회사 | Display Device Having Fanout Wiring |
TWI411835B (en) * | 2009-06-29 | 2013-10-11 | Au Optronics Corp | Display panel and display device |
TWI395007B (en) * | 2009-09-30 | 2013-05-01 | Au Optronics Corp | Fan-out circuit and display panel |
TWI418906B (en) * | 2009-10-06 | 2013-12-11 | Au Optronics Corp | Display panel with optimum pad layout of the gate driver |
CN104714696B (en) * | 2010-07-08 | 2017-11-24 | 友达光电股份有限公司 | touch display substrate |
CN101893962A (en) * | 2010-07-08 | 2010-11-24 | 友达光电股份有限公司 | Touch display and touch display substrate thereof |
SG11201404670QA (en) * | 2012-03-21 | 2014-11-27 | Sharp Kk | Active matrix substrate and display panel including the same |
CN105359073B (en) * | 2013-05-10 | 2019-03-19 | 诺基亚技术有限公司 | Sinuous interconnection in deformable substrate |
CN103337501B (en) * | 2013-06-24 | 2015-11-25 | 深圳市华星光电技术有限公司 | Array base palte and preparation method thereof, panel display apparatus |
CN106297623B (en) * | 2015-06-10 | 2019-11-01 | 群创光电股份有限公司 | Fan-out circuit and the display device for applying it |
CN206020893U (en) | 2016-08-31 | 2017-03-15 | 京东方科技集团股份有限公司 | Array base palte and display device |
KR102529828B1 (en) | 2016-10-31 | 2023-05-08 | 엘지디스플레이 주식회사 | Display device and multiple display device |
KR20200143558A (en) * | 2019-06-13 | 2020-12-24 | 삼성디스플레이 주식회사 | Display apparatus |
KR20210085388A (en) * | 2019-12-30 | 2021-07-08 | 엘지디스플레이 주식회사 | Touch display device |
WO2023155140A1 (en) * | 2022-02-18 | 2023-08-24 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
CN114779967A (en) * | 2022-05-27 | 2022-07-22 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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JP2771661B2 (en) * | 1990-02-16 | 1998-07-02 | 三洋電機株式会社 | Liquid crystal display |
KR200162435Y1 (en) * | 1993-06-21 | 1999-12-15 | 손욱 | Stn-lcd |
KR100237679B1 (en) * | 1995-12-30 | 2000-01-15 | 윤종용 | Liquid crystal display panel |
JPH10153791A (en) * | 1996-11-25 | 1998-06-09 | Hitachi Ltd | Liquid crystal display device with bent wiring electrode |
JPH1195244A (en) * | 1997-09-22 | 1999-04-09 | Toshiba Corp | Circuit board and liquid crystal display device having this circuit board |
JP3296299B2 (en) * | 1998-08-03 | 2002-06-24 | 日本電気株式会社 | Layout method of lead wiring and display device having high-density wiring |
JP3964546B2 (en) * | 1998-08-04 | 2007-08-22 | シャープ株式会社 | Display device |
JP2003140181A (en) * | 2001-11-02 | 2003-05-14 | Nec Corp | Liquid crystal display device |
US6842200B1 (en) * | 2003-06-18 | 2005-01-11 | Hannstar Display Corporation | Liquid crystal panel having compensation capacitors for balancing RC delay effect |
TW594177B (en) * | 2003-07-23 | 2004-06-21 | Hannstar Display Corp | Liquid crystal display panel for eliminating flicker |
JP2005250062A (en) * | 2004-03-03 | 2005-09-15 | Toshiba Matsushita Display Technology Co Ltd | Liquid crystal display device |
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