JP2005250062A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device wherein a resistance value of an inclined wiring part is easily optimized. <P>SOLUTION: An inclined angle of a first inclined wiring part 51 is adjusted so that the resistance value of the inclined wiring part 41 positioned in the outermost side of inclined wiring parts 41 connected to an OLB (Outer Lead Bonding) pad 43 is minimized. The resistance value of the inclined wiring part 41 positioned in the outermost side is lessened to the minimum to be optimized while the distance of a first inclined wiring part 51 from the OLB pad 43 is kept constant and the resistance values of the inclined wiring parts 41 can be easily optimized. The inclined angles of the inclined wiring parts 41 are easily optimized about the inclined angles corresponding to the sheet resistance values of the inclined wiring parts 41. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a liquid crystal display device in which liquid crystal is interposed between an array substrate and a counter substrate.

  Conventionally, in this type of liquid crystal display device, liquid crystal is interposed between an array substrate and a counter substrate. On the glass substrate of the array substrate, a plurality of scanning lines and signal lines are arranged so as to intersect with each other. The first electrode pattern or the second electrode pattern is electrically connected to the end portions of the plurality of scanning lines and signal lines. Each of the first electrode pattern and the second electrode pattern includes a plurality of oblique wiring electrode portions disposed to be inclined with respect to any of the plurality of scanning lines and signal lines. One end of each of the oblique wiring electrode portions is electrically connected to one end of a plurality of scanning lines and signal lines.

  In addition, one end of each of the linear wiring electrode portions arranged in parallel to any of the plurality of scanning lines and signal lines is electrically connected to the other end of each of the oblique wiring electrode portions. . Each of these linear wiring electrode portions is disposed outside the counter substrate. That is, each of these linear wiring electrodes is disposed on the array substrate in a state exposed to the atmosphere. Further, these linear wiring electrode portions are formed to have a larger line width than the respective oblique wiring electrode portions. Therefore, each of these linear wiring electrode portions is configured such that the resistance value per unit length is smaller than that of the oblique wiring electrode portion.

In each of the first electrode pattern and the second electrode pattern, the combined resistance of the oblique wiring electrode portion and the straight wiring electrode portion electrically connected to each of the plurality of scanning lines and signal lines is equal. In addition, a configuration is known in which the lengths of the diagonal wiring electrode portions and the straight wiring electrode portions are adjusted (see, for example, Patent Document 1).
JP-A-6-67191 (page 2-4, FIG. 1)

  However, in the above-described liquid crystal display device, the oblique wiring electrode portions of the first electrode pattern and the second electrode pattern are arranged to be inclined with respect to any of the plurality of scanning lines and signal lines. The linear wiring electrode portions of each of the first electrode pattern and the second electrode pattern are arranged in parallel to any of the plurality of scanning lines and signal lines.

  Therefore, in order to make the combined resistances of the straight wiring electrode part and the diagonal wiring electrode part equal, when the lengths of the linear wiring electrode part and the diagonal electrode wiring part are adjusted, Since the distances from the ends of the plurality of scanning lines and signal lines are not uniform, there is a problem that it is not easy to optimize the combined resistance of the straight wiring electrode part and the oblique electrode wiring part.

  The present invention has been made in view of such a point, and an object thereof is to provide a liquid crystal display device capable of easily optimizing the resistance value of the wiring portion.

  The present invention provides an array substrate provided with a switching element, a counter substrate disposed to face the array substrate, a liquid crystal interposed between the counter substrate and the array substrate, and one of the array substrates. A drive circuit that is disposed along the side and drives the switching element; and a plurality of wiring portions that are electrically connected to the drive circuit. A pad portion disposed along the side portion, a first wiring portion disposed from the pad portion to a position through a predetermined gap, and the first wiring portion and the drive circuit are electrically connected. A second wiring portion having a resistance different from that of the first wiring portion, and the pad portion so that a resistance value of the wiring portion located on the outermost side among the plurality of wiring portions is minimized. The inclination angle of the first wiring part with respect to Are those adjusted respectively disposed.

  Then, the first wiring portion disposed from the pad portion disposed along one side portion of the array substrate to a position through a predetermined gap, and the first wiring portion and the drive circuit are electrically connected. Of the plurality of wiring parts having a second wiring part having a resistance different from that of the first wiring part, the first wiring with respect to the pad part so that the resistance value of the outermost wiring part is minimized. The inclination angle of the part is adjusted and arranged. As a result, the resistance value of the wiring part located on the outermost side can be minimized while keeping the distance from one side of the array substrate in each of the first wiring parts constant. Easy to optimize.

  According to the present invention, by arranging and arranging the inclination angle of the first wiring portion with respect to the pad portion so that the resistance value of the outermost wiring portion among the plurality of wiring portions is minimized. Since the resistance value of the wiring part located on the outermost side can be minimized while keeping the distance from one side of the array substrate in each first wiring part constant, the resistance value of these wiring parts can be easily optimized. it can.

  The configuration of the first embodiment of the liquid crystal display device of the present invention will be described below with reference to FIGS.

  1 to 4, reference numeral 1 denotes a liquid crystal display device 1 as a flat display device. The liquid crystal display device 1 is an active matrix type liquid crystal display panel having a substantially rectangular flat plate shape as a circuit board. The liquid crystal display device 1 includes a rectangular plate array substrate 2. A rectangular pixel area 3 as an image display area is provided at the center of the array substrate 2. The pixel area 3 is a central portion in the width direction of the array substrate 2 and is provided in the central portion in the longitudinal direction of the array substrate 2.

  The array substrate 2 is provided with a counter substrate 4 facing the array substrate 2. The counter substrate 4 is formed in a rectangular flat plate shape substantially equal to the array substrate 2. Further, between the counter substrate 4 and the array substrate 2, between the array substrate 2 and the counter substrate 4, along the peripheral edges of the array substrate 2 and the counter substrate 4, as shown in FIG. A sealing material 5 is attached for sealing and liquid-tight connection. A liquid crystal 6 is interposed between the pixel area 3 and the counter substrate 4 of the array substrate 2 sealed with the sealing material 5 so as to be sealed.

  Also, as shown in FIG. 4, elongated rectangular Y driver circuits 7 and 8 as drive circuits are attached to both edges in the longitudinal direction of the pixel area 3 of the array substrate 2, respectively. Each of these Y driver circuits 7 and 8 has a length dimension slightly longer than the width dimension of the pixel area 3, and the longitudinal direction of these Y driver circuits 7 and 8 is aligned with the width direction of the pixel area 3. In a state, that is, attached in parallel to one side of the pixel area 3. These Y driver circuits 7 and 8 are provided between the array substrate 2 and the counter substrate 4 inside the sealing material 5.

  Further, an elongated rectangular X driver circuit 9 as a drive circuit is attached to one side edge in the width direction of the pixel area 3 of the array substrate 2. The X driver circuit 9 has a longitudinal dimension equal to the longitudinal dimension of the pixel area 3. Further, the X driver circuit 9 is mounted in a state in which the longitudinal direction of the X driver circuit 9 is aligned with the longitudinal direction of the pixel area 3, that is, parallel to one side of the pixel area 3. Yes. The X driver circuit 9 is provided between the array substrate 2 and the counter substrate 4 inside the sealing material 5. Here, the X driver circuit 9 supplies a video signal, which is an image signal input from the outside via an OLB pad 43 described later, to a signal line in the pixel area 3.

  On the other hand, the array substrate 2 has a glass substrate 11 as a translucent substrate, which is a substantially transparent rectangular flat plate-like insulating substrate, as shown in FIG. An undercoat layer 12 is laminated on the entire surface of the glass substrate 11 as a main surface. On the undercoat layer 12, thin film transistors (TFTs) 13 as pixel transistors, which are switching elements for pixel circuits, are laminated in a matrix. Each of these thin film transistors 13 constitutes a part of a circuit built on the glass substrate 11 of the array substrate 2. Further, these thin film transistors 13 have an elongated substantially rectangular active layer 14 as a semiconductor layer formed on the undercoat layer 12. The active layer 14 is composed of a polysilicon thin film as a polycrystalline semiconductor thin film.

Further, the active layer 14 has a channel region 15 provided in the central portion of the active layer 14. On both sides of the channel region 15, a source region 16 and a drain region 17 are provided as electrode portions that are n ⁺ regions. Further, between these source region 16 and drain region 17 and the channel region 15, LDD (Lightly Doped Drain) regions 18 and 19 which are n ⁻ regions as low impurity concentration regions are formed. These LDD regions 18 and 19 are provided on both sides of the channel region 15 of each thin film transistor 13, and a source region 16 and a drain region 17 are provided on both sides of the LDD regions 18 and 19.

On the other hand, a gate insulating film 21 having a thickness of about 100 nm is laminated on the entire surface of the undercoat layer 12 including the channel region 15, the source region 16, the drain region 17, and the LDD regions 18 and 19 of each active layer 14. The film is formed. The gate insulating film 21 is formed of a silicon oxide film (SiO _x ), and is a gate insulating layer as a first insulating film that is a silicon oxide film having an insulating property.

  On the gate insulating film 21 facing each channel region 15, a gate electrode 22 formed by etching the gate wiring material is laminated and formed. The gate electrode 22 is made of molybdenum (Mo), tungsten (W), aluminum (Al), or an alloy thereof. The gate electrodes 22 face the channel regions 15 of the thin film transistors 13 through the gate insulating film 21 and have a width dimension substantially equal to the width dimension of the channel regions 15. Further, these gate electrodes 22 are formed in an elongated strip shape that is an elongated rectangular shape, and have a longitudinal direction orthogonal to the longitudinal direction of the active layer 14.

  Here, each of these gate electrodes 22 is electrically connected to a scanning line (not shown). These scanning lines are stacked on the gate insulating film 21, and are arranged along the longitudinal direction of the array substrate 2 at a regular interval in the width direction of the array substrate 2. Has been. Further, these scanning lines drive the thin film transistors 13 by supplying the scanning signals supplied from the Y driver circuits 7 and 8 to the thin film transistors 13 through the gate electrodes 22. Further, an auxiliary capacitance wiring (not shown) is provided between these scanning lines. These auxiliary capacitance lines are wired in parallel to the scanning lines adjacent to each other.

  Further, on the gate insulating film 21 including the gate electrode 22 of each thin film transistor 13, an interlayer insulating film 23 as a second insulating layer which is a silicon oxide film having an insulating property is laminated and formed. The interlayer insulating film 23 and the gate insulating film 21 are provided with a plurality of contact holes 24 and 25 which are contact portions as conductive portions penetrating through the interlayer insulating film 23 and the gate insulating film 21, respectively. It has been.

  Here, each of the contact holes 24 and 25 is provided on the source region 16 and the drain region 17 of the thin film transistor 13 on both sides of the gate electrode 22 of the thin film transistor 13. The contact hole 24 is opened to communicate with the source region 16 of the thin film transistor 13. The contact hole 25 communicates with the drain region 17 of the thin film transistor 13 and opens.

  Further, a source electrode 26 that is a signal line is laminated and provided in the contact hole 24 that communicates with the source region 16 of each thin film transistor 13. These source electrodes 26 are electrically connected to the source region 16 of the thin film transistor 13 through the contact hole 24 to be conductive. In addition, a drain electrode 27 that is a signal line is provided in a stacked manner in the contact hole 25 that communicates with the drain region 17 of each thin film transistor 13. These drain electrodes 27 are electrically connected to the drain region 17 of the thin film transistor 13 through the contact hole 25 to be conductive. Each of the source electrode 26 and the drain electrode 27 is formed by patterning a signal line material.

  Here, a signal line (not shown) is integrally formed and electrically connected to each drain electrode 27. These signal lines are laminated on the interlayer insulating film 23, and are arranged in parallel along the width direction of the array substrate 2 at equal intervals in the longitudinal direction of the array substrate 2. It is installed. As a result, these signal lines are arranged so as to be insulated from each other and crossed, that is, orthogonal to each scanning line. Therefore, each thin film transistor 13 is arranged corresponding to an intersection that is an intersection of each signal line and scanning line.

  Then, on the interlayer insulating film 23 including each of the source electrode 26 and the drain electrode 27 of each thin film transistor 13, a passivation film as a protective film configured by a silicon nitride (SiN) film so as to cover the thin film transistor 13. 28 are laminated to form a film. The passivation film 28 is provided with a contact hole 29 serving as a conduction portion that penetrates the passivation film 28. The contact hole 29 is opened to communicate with the drain electrode 25 of the thin film transistor 13.

  Further, a pixel electrode 31 controlled by the thin film transistor 13 is laminated and formed on the passivation film 28 including the contact hole 29. The pixel electrode 31 is electrically connected to the drain electrode 27 of the thin film transistor 13 through the contact hole 29 to be conductive. The pixel electrode 31 is disposed corresponding to each thin film transistor 13 so as to overlap with the signal line. Further, an alignment film 32 is laminated and formed on the passivation film 28 including the pixel electrode 31.

  On the other hand, the counter substrate 4 includes a glass substrate 35 which is a substantially transparent rectangular flat plate-like insulating substrate. On one main surface of the glass substrate 35 on the side facing the array substrate 2, a counter electrode 36 as a common electrode is laminated and formed. On the counter electrode 36, an alignment film 37 is laminated and formed. A liquid crystal 6 is interposed between the alignment film 37 and the alignment film 32 of the array substrate 2.

  Furthermore, one end of each of the plurality of diagonal wiring portions 41 is electrically connected to one side edge of the array substrate 2 in the width direction of the X driver circuit 9. In each of the oblique wiring portions 41, the adjacent oblique wiring portions 41 are arranged with a certain gap, that is, with a certain distance. Furthermore, these diagonal wiring portions 41 are connected by being wired while maintaining a certain line width. The diagonal wiring portions 41 are provided between the array substrate 2 and the counter substrate 4, and one end portion is provided at one side edge of the X driver circuit 9 located on the opposite side of the pixel area 3 of the array substrate 2. Are electrically connected. That is, these diagonal wiring portions 41 electrically connect the X driver circuit 9 to a plurality of scanning lines. Here, these oblique wiring portions 41 are formed by laminating a first wiring layer 42 as a first wiring portion that is laminated and formed on the gate insulating film 21 of the array substrate 2. The first wiring layer 42 is wired from the inner edge of the sealing material 5 on the array substrate 2 to one end edge in the width direction of the array substrate 2.

  On the outer side of the seal material 5 on each of the first wiring layers 42, for example, four OLB (Outer Lead Bonding) pads 43 are stacked and provided as pad portions. These OLB pads 43 electrically connect the liquid crystal display device 1 to a signal source (not shown). These OLB pads 43 are attached to one side edge in the width direction of the glass substrate 11 of the array substrate 2. Further, these OLB pads 43 are attached in a state of being separated by a distance P that is a pitch at equal intervals along the longitudinal direction of the X driver circuit 9. In addition, the OLB pads 43 are electrically connected to the other end portions of the first wiring layers 42 of the respective diagonal wiring portions 41 only in the OLB pads 43 arranged at the closest positions of the OLB pads 43. It is connected.

Here, each of these OLB pads 43 includes a second wiring layer 44 which is a second wiring film formed by being laminated on the first wiring layer 42. The second wiring layer 44 is laminated on the first wiring layer 42 outside the sealing material 5. Then, the second wiring layer 44 has a different sheet resistance sigma ₂ is the sheet resistance sigma ₁ of the first wiring layer 42. Specifically, the second wiring layer 44 is configured such that the sheet resistance is set larger than the sheet resistance of the first wiring layer 42 (σ ₂ > σ ₁ ). In other words, the second wiring layer 44 is set to have a resistance value per unit length of the first wiring layer 42, that is, a resistivity larger than the resistivity. Further, a pixel electrode layer 45 is laminated on the second wiring layer 44 and formed. The pixel electrode layer 45 is formed of the same material as each pixel electrode layer 45 in the same process. Further, on the pixel electrode layer 45, a flexible substrate 46 having flexibility is laminated and pressure-bonded.

  Further, an interlayer insulating film 23 is laminated and formed on the gate insulating film 21 including the first wiring layer 42 inside each OLB pad 43. The interlayer insulating film 23 is provided with a contact hole 47 communicating with one end in the longitudinal direction of the first wiring layer 42. The contact hole 47 is provided between the sealing material 5 and the first wiring layer 42. On the interlayer insulating film 23 including the contact hole 47, a second wiring layer 48 as a second wiring portion is laminated and formed. The second wiring layer 48 forms an oblique wiring portion 41 with the first wiring layer 42 and is formed in the same material and in the same process as the second wiring layer 44 of each OLB pad 43.

  The second wiring layer 48 is wired from the central portion in the width direction of the sealing material 5 to the X driver circuit 9. That is, one end portion of the second wiring layer 48 is located between the sealing material 5 and the interlayer insulating film 23, and is electrically connected to one end portion of the first wiring layer 42 through the contact hole 47. It is connected. Further, the other end portion of the second wiring layer 48 in the longitudinal direction is located between the interlayer insulating film 23 and the liquid crystal 6 and is electrically connected to the X driver circuit 9.

Here, as shown in FIG. 1, each portion of the first wiring layer 42 between the OLB pad 43 and the contact hole 47 is a first inclined wiring portion 51 as a first wiring portion. ing. These first inclined wire portion 51 is provided to be disposed from each OLB pads 43 to the dividing position 50 is a position through a predetermined distance l _1. Here, the division position 50 is provided in parallel to one side of each OLB pad 43 via a predetermined distance l _{1 and} to one side of the X driver circuit 9 in the width direction. It is provided in parallel with a predetermined gap l ₂ Te.

Further, the first inclined wiring portion 51 is wired in a state where the longitudinal direction is inclined by an angle θ _{1 with} respect to the longitudinal direction of the OLB pad 43. These first inclined wiring portions 51 have a width dimension _WL1 that is a constant line width, and are arranged while maintaining this width dimension. Further, these first inclined wiring portions 51 are wired from one end portion of these OLB pads 43 to a divided position 50 that is a position of a distance l ₁ along the longitudinal direction of each OLB pad 43. In other words, these first inclined wiring portions 51 are arranged via a distance ₁₁ that is a constant gap. Furthermore, each of the first inclined wire portion 51 is wired are equally spaced with a gap W _S1.

And these 1st inclination wiring parts 51 are this OLB so that the sheet resistance value of the diagonal wiring part 41 located in the outermost side among the diagonal wiring parts 41 connected to arbitrary OLB pads 43 may become the smallest. the inclination angle theta ₁ is arranged are adjusted respectively with the pads 43. In other words, these first inclined wiring portions 51 are wirings having the largest inclination angle among one oblique wiring portion 41 connecting from the end of an arbitrary OLB pad 43 to the end of the X driver circuit 9. The resistance value is set to be minimum. That is, among these first inclined wiring portions 51, the first inclined wiring portion 51 located on the outermost side of each OLB pad 43 is an oblique wiring having the largest angle. Each of the first inclined wiring portions 51 having a small angle located inside the first inclined wiring portion 51 located on the outermost side is gradually loosened and made smaller toward the inside. Are wired in stages.

Further, each portion of the second wiring layer 48 between the contact hole 47 and the X driver circuit 9 serves as a second inclined wiring portion 52 as a second wiring portion. These second inclined wiring portions 52 electrically connect the first inclined wiring portion 51 and the X driver circuit 9. These second inclined wiring portions 52 are wired in a state where the longitudinal direction is inclined by an angle θ _{2 with} respect to the longitudinal direction of the OLB pad 43. The second inclined wiring portions 52 have a width dimension _WL2 which is a line width, and an X driver is connected from the other end of the first inclined wiring portion 51 along the longitudinal direction of each OLB pad 43. Wired for a distance l ₂ between the circuit 9. That is, these second inclined wiring portions 52 are wired from the one side edge in the width direction of the X driver circuit 9 to the division position 50 which is a position of the distance l ₂ . Further, each of the second inclined wiring portions 52 is wired with being spaced at equal intervals through the gap _WS2 .

The other end portion of the second inclined wiring portion 52 is electrically connected to one of a plurality of terminal portions 53 electrically connected to the X driver circuit 9. These terminal portions 53 are attached in a state of being spaced apart by a distance P that is a wiring pitch at equal intervals along the longitudinal direction of the X driver circuit 9. Furthermore, these terminal portions 53 are located at _a distance La from the other end of the OLB pad 43 connected to these terminal portions 53 via the second inclined wiring portion 52 and the first inclined wiring portion 51. Is provided. These terminal portions 53 are provided at a distance L _b as horizontally spaced position relative to the longitudinal direction of the OLB pads 43 connected to the terminals 53.

  Next, a method for designing the oblique wiring portion of the liquid crystal display device according to the first embodiment will be described.

  First, among the diagonal wiring portions 41 connected to each OLB pad 43, the diagonal wiring portion 41 located on the outermost side is the diagonal wiring with the tightest angle.

  Then, the resistance of the oblique wiring that makes the largest inclination angle between the OLB pad 41 and the X driver circuit 9 in the oblique wiring portion 41 is calculated.

At this time, since the resistance of one diagonal wiring portion 41 is considered, the distance P of the OLB pad 43 and the pitch P of the X driver circuit 9 are set to be the same for convenience as shown in FIG. In addition, the gaps W _S1 and W _S2 of the first inclined wiring portion 51 and the second inclined wiring portion 52 of each diagonal wiring portion 41 are different from those of the first inclined wiring portion 51 and the second inclined wiring portion 52, respectively. Even if the wiring angles θ ₁ and θ ₂ change, it is constant.

Further, the distance l ₁ from the OLB pad 43 of the first inclined wiring portion 51, the distance l ₂ from the other end of the first inclined wiring portion 51 to the X driver circuit 9, and the distance from the OLB pad 43 to the X driver circuit 9. , A linear distance L _a that is a distance along the width direction of the X driver circuit, and a horizontal distance that is a distance along the longitudinal direction of the X driver circuit 9 from the OLB pad 43 to the terminal portion 53 of the X driver circuit 9 Each of L _b is also constant.

In this state, assuming that the sheet resistances of the first wiring layer 42 and the second wiring layer 48 are σ ₁ and σ ₂ , the resistance value (R ₁ ) of the first inclined wiring portion 51 is R ₁ = W _L1 × l ₁ / cos (θ ₁ ) = (P × cos (θ ₁ ) −W _S1 ) × l ₁ / cos (θ ₁ ). At this time, the resistance value (R ₂ ) of the second inclined wiring portion 52 is R ₂ = W _L2 × l ₂ / cos (θ ₂ ) = [P × l ₂ / √ {(L _b −l ₁ × tan (θ ₁ )) ² + l ₂ ² } −W _S2 ] × √ {(L _b −l ₁ × tan (θ ₁ ) ² + l ₂ ²

Accordingly, the resistance value (R) of one diagonal wiring portion 41 located on the outermost side is R [θ ₁ ] = R ₁ [θ ₁ ] + R ₂ [θ ₁ ].

Therefore, for example, the wiring pitch P = 30 μm, L _a = 100 μm, L _b = 500 μm, l ₁ = 200 μm, l ₂ = 300 μm, and the sheet resistance σ _{1 of} the first wiring layer 42 = 1.0Ω / μm ² , the sheet resistance σ _{2 of} the second wiring layer 48 = 0.1Ω / μm ² , the wiring interval W _{S1 of} the first inclined wiring part 51 = 10.0 μm, and the second inclined wiring part 52 calculating the wiring interval _{W S2} as 10.0 [mu] m.

As a result, as shown in FIGS. 5 and 6, it is found that the optimum wiring angle is obtained when the inclination angle θ ₁ = 18 ° of the first inclined wiring portion 51 located on the outermost side.

  As described above, according to the first embodiment, since the second wiring layer 48 of each oblique wiring portion 41 has a sheet resistance smaller than that of the first wiring layer 42, the OL driver pad 43 can be used as an X driver circuit. Although it is conceivable to wire up to 9 with the second wiring layer 48, the second wiring layer 48 is disposed outside the sealing material 5 and may be exposed to the atmosphere and corroded. Outside the sealing material 5, it is connected to the first wiring layer 42 through a contact hole 47.

It is also conceivable to move the position of the sealing material 5 further outward to shorten the linear distance l ₁ of the first inclined wiring part 51 and increase the linear distance l ₂ of the second inclined wiring part 52. However, the first inclined wiring portion 51 and the second inclined wiring portion 52 may interfere with the OLB pad 43. Therefore, the linear distances l ₁ and l ₂ of the first inclined wiring part 51 and the second inclined wiring part 52 cannot be changed, and the position of the sealing material 5 cannot be moved.

  Therefore, in the conventional liquid crystal display device, the OLB pad and the X driver circuit are connected in a straight line at an oblique wiring portion. However, in connection with two kinds of wiring layers having different sheet resistances by the first inclined wiring part 51 and the second inclined wiring part 52 of the oblique wiring part 41, the wiring resistance from the OLB pad 43 to the X driver circuit 9 is related. It's not the best way.

  Therefore, the inclination angle of the first inclined wiring part 51 is adjusted so that the resistance value of the oblique wiring part 41 located on the outermost side among the oblique wiring parts 41 connected to each OLB pad 43 is minimized. To do.

  As a result, while keeping the distance of the first inclined wiring part 51 from the OLB pad 43 constant, the resistance value of the oblique wiring part 41 located on the outermost side and having the largest resistance value can be minimized and optimized. The resistance value of these diagonal wiring portions 41 can be easily optimized. Therefore, according to the sheet resistance value of each of the oblique wiring portions 41, the inclination angle of the oblique wiring portion 41 that electrically connects the OLB pad 43 and the X driver circuit 9 can be easily optimized with respect to the resistance.

In the above-described first embodiment, the case of not fixing the respective line width W _L2 of the line width W _L1 and the second inclined wire portion 52 of the first inclined wire portion 51 of the oblique line portion 41 described but was, as in the second embodiment shown in FIGS. 7 and 8 were fixed to each of the line width W _L2 of the first line width W _L1 and the second inclined wire portion 52 of the inclined wire portion 51 In this case, when the optimum wiring angle of the resistance R [θ ₁ ] = R ₁ [θ ₁ ] + R ₂ [θ ₁ ] for one diagonal wiring portion 41 located on the outermost side is calculated, R ₁ [θ ₁ ] = W _L1 × l ₁ / cos (θ ₁ ), and R ₂ [θ ₂ ] = W _L2 × √ {(L _b −l ₁ × tan (θ ₁ )) ² + l ₂ ² }.

Thus, each of the line width W _L2 of the first line width W _L1 and the second inclined wire portion 52 of the inclined wire portion 51 and 15.0 .mu.m, the other conditions were the same as the first embodiment In this case, as shown in FIGS. 7 and 8, since the wiring resistance is minimized when the inclination angle θ ₁ = 5 ° of the first inclined wiring portion 51 located on the outermost side, this angle is the optimum wiring. It becomes an angle.

FIG. 2 is an explanatory plan view showing a part of the liquid crystal display device according to the first embodiment of the present invention. It is explanatory sectional drawing which shows a liquid crystal display device same as the above. It is a description exploded perspective view of a liquid crystal display device same as the above. It is a description top view of a liquid crystal display device same as the above. This is data when the inclination angle of the first wiring layer of the liquid crystal display device is changed. It is a graph at the time of changing the inclination-angle of the 1st wiring layer of a liquid crystal display device same as the above. This is data when the inclination angle of the first wiring layer in the second embodiment of the liquid crystal display device of the present invention is changed. It is a graph at the time of changing the inclination-angle of the 1st wiring layer of a liquid crystal display device same as the above.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Array substrate 4 Opposite substrate 6 Liquid crystal 9 X driver circuit as a drive circuit
13 Thin-film transistors as switching elements
41 Diagonal wiring section as wiring section
43 OLB pad as pad
51 First inclined wiring section as a first wiring section
52 Second inclined wiring section as second wiring section

Claims (4)

An array substrate with switching elements;
A counter substrate disposed to face the array substrate;
A liquid crystal interposed between the counter substrate and the array substrate;
A drive circuit disposed along one side of the array substrate and driving the switching element;
A plurality of wiring portions electrically connected to the drive circuit;
The plurality of wiring portions include a pad portion disposed along one side portion of the array substrate, a first wiring portion disposed from the pad portion to a position through a predetermined gap, and the first wiring portion. A wiring portion electrically connected to the driving circuit and having a second wiring portion having a resistance different from that of the first wiring portion, and the wiring portion located on the outermost side among the plurality of wiring portions The liquid crystal display device is characterized in that the inclination angle of the first wiring part with respect to the pad part is respectively adjusted so as to minimize the resistance value of the liquid crystal display device. The liquid crystal display device according to claim 1, wherein the second wiring portion has a larger resistance than the first wiring portion. 3. The liquid crystal display device according to claim 1, wherein each of the plurality of wiring portions is disposed at a constant interval. The liquid crystal display device according to any one of claims 1 to 3, wherein each of the plurality of wiring portions is arranged with a constant line width.

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