CN1928676A - Electronic connectors and connection method thereof, and electronic modules - Google Patents
Electronic connectors and connection method thereof, and electronic modules Download PDFInfo
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- CN1928676A CN1928676A CN 200610121678 CN200610121678A CN1928676A CN 1928676 A CN1928676 A CN 1928676A CN 200610121678 CN200610121678 CN 200610121678 CN 200610121678 A CN200610121678 A CN 200610121678A CN 1928676 A CN1928676 A CN 1928676A
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Abstract
A fan-out pattern having two or more fan-out sections is implemented between a driver IC and a display for reducing or eliminating the pathlength differences among the electrical conductors in the fan-out pattern. As such, some of the conductors between the driver IC and the display can have two or more zigzag swath widths. In a fan-out pattern having two fan-out sections, a first fan-out section widens the spacing, SI, between two adjacent conductors at the IC side to an intermediate spacing, SM, and a second fan-out section further widens the intermediate spacing SM to the spacing, SP, at the display side. With two fan-out sections, the first zigzag extension is implemented in some conductors between the IC side and the first fan-out section, and the second zigzag extension is implemented in some conductors between the first fan-out section and the second fan-out section.
Description
Technical field
The present invention relates to one group of electric power connector (connector) between between two electronic packages, particularly relate to one group of electric power connector between the pixel range of a drive IC and a display panel.
Background technology
Many data line DL and gate lines G L that display panel generally includes a pixel region and is connected to pixel region, for example liquid crystal display (liquid crystal display, LCD) panel.As shown in Figure 1, these data lines and gate line are connected to a plurality of driver ics or chip for driving (driverIC) as on data chip for driving 10 or the gate-drive chip 20.All chip for driving all include the welded gasket district (bond pad area) 210 with a plurality of electric lead pad (not shown)s, so that many electronic wires (electrical conductor) are connected on the connector area 220 of pixel region, as shown in Figure 2.Because the interval S between the die terminals adjacent wires
IMuch smaller than the interval S between pixel region end adjacent wires
P, (fan-out, FS) sample (pattern) is used for making lead to be deployed into pixel region from die terminals in an expansion.This launches in the sample, and the lead on sample border is always long more than the lead of center section.For instance, lead A is shorter than lead B, and lead B is shorter than lead C, by that analogy.If lead is constituted and is had identical thickness and width by identical material, then can be greater than the resistance value than short lead than the resistance value of long lead.
As shown in Figure 3, for the resistance value difference between the lead that reduces by an expansion sample, different serrate path (zigzag path) sample is used on the lead of center section.Especially, Na etc. (United States Patent (USP) the 6th, 104, No. 465) have disclosed an expansion connector sample, and it has a straight line zone and a bending area, and wherein, the lead in linearity region and the bending area is made of unlike material.In addition, the lead in the bending area can comprise several different curved shapes for example wave-like and carinate wire shaped.
Kim etc. (United States Patent (USP) the 5th, 499, No. 131) have disclosed one and have launched sample, and wherein each bar lead has a narrow conductor part to be connected to a wide conductor part.By the length of adjusting wide conductor part, can reduce or increase resistance value to reduce the resistance value difference between lead.
(United States Patent (USP) the 5th such as Fujii, 757, No. 450) disclosed an expansion sample, wherein each lead has a narrow conductor part, a wide conductor part and the inclination conductor part with the intermediate width between narrow conductor part width and wide conductor part width.
When a chip for driving need promote lot of data line/gate line, be not suitable for utilizing changing conductor width or utilizing and adjust wide conductor part width and reduce the resistance value difference between the lead that launches sample.Can launch to utilize different serrate path to reduce its resistance value difference in the sample this moment at one.As shown in Figure 3, a serrate path ZS can allow the path of a lead to expand simultaneously on the both sides of straight line.This expansion area can be expressed as the tooth width (swath width) among Fig. 3.For instance, lead A has tooth width W because of having the expansion of serrate path
A, lead B has tooth width W
B, lead C, D and E then have tooth width W respectively
C, W
DAnd W
EGenerally speaking, the path in a serrate path can increase together along with tooth width.Therefore, in order to reduce the resistance value difference between lead, launch in the sample at one, the serrate tooth width of central conductor can be greater than the serrate tooth width of both sides lead.As shown in Figure 3, W
AGreater than W
C, W
CThen greater than W
DAnd W
ETherefore, the path length difference in the lead can be lowered or roughly eliminate.Yet,, only have a serrate path of launching the expansion sample (sample as shown in Figure 3) of section at one and possibly can't effectively reduce resistance value difference between lead because it is cumulative to the lead number in display picture element district to connect a chip for driving.
Therefore, need provide a different expansion sample, to increase the scope of a serrate path.
Summary of the invention
In view of this, the invention provides a kind of expansion sample that launches section more than two that has, in order to the path length difference between the electronic wire in reduction or the elimination expansion sample.Therefore, the lead between chip for driving and display panel can have plural serrate tooth width.
Based on above-mentioned purpose, a kind of expansion sample with expansion section more than two is used between a chip for driving (IC) and a display panel, in order to the path length difference between the electronic wire in reduction or the elimination expansion sample.Therefore, the lead of part between chip for driving and display panel has plural serrate tooth width.
Have in two expansion samples that launch sections at one, for instance, one first launches section enlarges interval S between die terminals two adjacent leads
ITo a midfeather S
M, and one second expansion section further enlarges this midfeather S
MTo interval S
PAt the pixel region end.Utilize these two to launch sections, the serrate expanded application is on the die terminals and the first part lead that launches between the section for the first time, and the serrate expanded application is launched on the section and the second part lead that launches between the section first for the second time.Generally speaking, the serrate tooth width of serrate expansion can be greater than the serrate tooth width of the serrate expansion first time for the second time.
The present invention also can be expanded, and makes that launching sample can have or the above expansion section that launches between section and the pixel region between second.
Description of drawings
Fig. 1 is a synoptic diagram, is to be presented in the pixel region of an existing display panel a plurality of data driving chip to be electrically connected to data line and gate line with the gate-drive chip.
Fig. 2 is a synoptic diagram, is to show an existing sample that launches, and is used to utilize electronic wire to connect the welded gasket district of a chip for driving and a section of pixel region at least.
Fig. 3 is a synoptic diagram, is to be presented at an existing typical serrate path expansion that launches sample.
Fig. 4 A-4B is a synoptic diagram, is to show an expansion sample according to the embodiment of the invention, is used to utilize electronic wire to connect the welded gasket district of a chip for driving and a section of pixel region at least.
Fig. 5 is a synoptic diagram, is demonstration one launches sample according to one of the embodiment of the invention serrate path expansion.
Fig. 6 is a synoptic diagram, is to show an expansion sample according to another embodiment of the present invention.
Fig. 7 is a synoptic diagram, is to show that a display panel has a plurality of chip for driving utilizations and is electrically connected to a pixel region according to a plurality of electronic wires that launch in the sample that are arranged on of the present invention.
Fig. 8 A is a synoptic diagram, is to show a serrate sample.
Fig. 8 B is a synoptic diagram, is to show another serrate sample.
Fig. 9 is a synoptic diagram, is to be presented to launch in the section one or the above serrate sample that adds.
The reference numeral explanation
The 10-data driving chip;
The 20-grid drive chip;
The DL-data line;
The GL-gate line;
210-welded gasket district;
The 220-connector area;
S
I, S
M, S
P, S
M1, S
M2-conductor spacing;
ZS-serrate path-segments;
The F-lead;
W
A, W
A1, W
A2, W
B, W
C, W
D, W
E-tooth width;
FS1-first launches section;
FS2-second launches section;
FS3-the 3rd launches section;
The ZS1-first serrate path-segments;
The ZS2-second serrate path-segments;
ZS3-the 3rd serrate path-segments;
The 710-data driving chip;
The 720-grid drive chip;
AZS1-first adds the serrate path-segments;
AZS2-second adds the serrate path-segments.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below.
Utilization of the present invention is arranged on many electronic wires that launch in the sample and connects with the electronics of pixel range that an integrated circuit (chip for driving) and a display panel are provided.Especially, according to the expansion sample of the embodiment of the invention, it has two or more expansion sections with twice or twice above width that enlarges between adjacent wires.Shown in Fig. 4 A-4B, first launches the interval S between section FS1 expansion die terminals two adjacent leads
ITo a midfeather S
M, and the second expansion section FS2 further enlarges this midfeather S
MTo interval S
PAt the pixel region end.Utilize this two minor tick to enlarge mode, the serrate path can be applicable at least two sections.As shown in Figure 5, the first serrate path-segments ZS1 approximately launches between the section FS1 in die terminals and first, and the second serrate path-segments ZS2 approximately launches between the section FS1 and the second expansion section FS2 first.Generally speaking, same lead is in the serrate tooth width of the first serrate path-segments ZS1 serrate tooth width less than the second serrate path-segments ZS2.For instance, lead A is at the serrate tooth width W of the first serrate path-segments ZS1
A1Less than its serrate tooth width W at the second serrate path-segments ZS2
A2Therefore, for instance, when the resistance value difference between desire reduction lead A and lead F, use tooth width W simultaneously
A1And tooth width W
A2The path that increases lead A is than utilizing a tooth width W separately
A1More effective.
According at the conductor spacing of die terminals S
IAnd at the conductor spacing of pixel region end S
P, and, can have plural expansion section according to the distance between chip and the pixel region, make plural serrate path-segments ZS to be implemented on it.For instance, can have three expansion section FS and come to enlarge the conductor spacing three times, as shown in Figure 6.As shown in the figure, first launch section FS1 expansion at the conductor spacing of die terminals S
ITo one first midfeather S
M1, and the second expansion section FS2 enlarges this first midfeather S
M1To one second midfeather S
M2The 3rd launches section FS3 then is used at the pixel region end the second midfeather S
M2Expand S at interval at the pixel region end
PUtilize this three minor tick to enlarge mode, the serrate path can be applicable at least three sections.As shown in Figure 6, the first serrate path-segments ZS1 approximately launches between the section FS1 in die terminals and first, the second serrate path-segments ZS2 approximately launches section FS1 and second first and launches between the section FS2, and the 3rd serrate path-segments ZS3 approximately launches between section FS2 and the 3rd expansion section FS3 second.Generally speaking, same lead is in the serrate tooth width of the first serrate path-segments ZS1 serrate tooth width less than the second serrate path-segments ZS2, and its in the serrate tooth width of the second serrate path-segments ZS2 less than its serrate tooth width at the 3rd serrate path-segments ZS3.
In sum, in foundation display panel of the present invention, a plurality of chip for driving are electrically connected to pixel region.Being used for electrically connecting chip for driving is arranged on one or more to the electronic wire of pixel region and launches in sample.Wherein at least one expansion sample has at least two expansion sections.For instance, as shown in Figure 7, be used for electrically connecting each chip for driving such as data chip for driving 710 or gate-drive chip 720 and can be arranged on one to the electronic wire of a certain section of pixel region and have in two expansion samples that launch sections.Therefore, two serrate path-segments also can be applicable in each expansion sample, as shown in Figure 5.
It should be noted that serrate path sample as shown in Figure 5 just is used for explaining notion of the present invention.Generally speaking, a serrate path sample can allow a lead along with a slalom course is expanded on the both sides of straight line, to increase the path of lead.Therefore, the resistance value of lead also can be along with increase.Slalom course can comprise the connection linear section shown in Fig. 8 A.Slalom course can be the waveform sample shown in Fig. 8 B.Wherein, slalom course can be the repeated sample shown in Fig. 8 A and Fig. 8 B, but it also can be irregular.In addition, wherein the part lead can be wider than other lead.For instance, one section of the lead F of close pixel region end or lead E can be wideer than the same lead of close die terminals, to reduce the resistance value of lead.In addition, also can launch to utilize in the section one to add serrate (addition zigzag, AZ) sample is to increase the path of lead at one or more.As shown in Figure 9, can launch to do one first in fact among the section FS1 first and add serrate path-segments AZS1.In like manner, also can launch to do one second in fact among the section FS2 and add serrate path-segments AZS2 second.
The present invention discloses a kind of reduction and is arranged on one and launches path length difference method between the lead of sample, in order to electrically connect a chip for driving to a section of the pixel region of at least one display panel.Any those who are familiar with this art also can use the present invention easily between the electronic wire that is arranged on an expansion sample, in order to electrically connect two electronic modules or assembly.
Therefore; though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those who are familiar with this art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the present patent application claim person of defining.
Claims (22)
1. electronics method of attachment, be used between one first electronic package and one second electronic package, this first electronic package comprises a plurality of first electronics links, have one first between the adjacent link of the described first electronics link at interval, this second electronic package comprises a plurality of second electronics links, one second interval greater than this first interval is arranged between the adjacent link of the described second electronics link, wherein, this electronics connects and comprises many electronic wires that are provided with a connection sample, with so that each this electronic wire can be connected to 1 of the described first electronics link the second electronics link of a correspondence, this connection sample has one first end near this first electronic package, one second end near this second electronic package, two borderline regions between between this first end and this second end and the zone line between between described borderline region, this electronics method of attachment comprises the following steps:
Be arranged near first of this first end of this connections sample one and launch in the section described electronic wire to be launched outwardly, so that the interval between the adjacent wires increases to one greater than this first at interval the 3rd interval;
Send out in this first centre portion at this connection sample, described electronic wire is expanded towards this second end; And
Launch in the section one second, to launch outwardly from the described electronic wire in this first centre portion, connect this second end of sample towards this, further to make the interval between the adjacent wires increase to the 4th interval greater than the 3rd interval, wherein, be provided between this first one first crooked sample that launches between section and this second expansion section, to increase the length of described portions of electronics lead at least partially in the electronic wire in this zone line of this connection sample.
2. electronics method of attachment as claimed in claim 1, wherein, the 4th equates with this second interval at interval substantially.
3. electronics method of attachment as claimed in claim 1 wherein, is provided one second crooked sample at least partially in the electronic wire that this connection sample is sent out in this zone line and close this connection sample is sent out this first end.
4. electronics method of attachment as claimed in claim 3 wherein, is arranged on this to this second crooked sample of small part and second launches in section.
5. electronics method of attachment as claimed in claim 1 wherein, is arranged on this to this first crooked sample of small part and first launches in section.
6. electronics method of attachment as claimed in claim 1 more comprises the following steps:
With this second described electronic wire that launches in section, connect in another centre portion of sample further towards this second end expansion at this, wherein this another centre portion second launches section and should connect between this second end of sample between this; And
Launch to launch outwardly from the described electronic wire in other centre portion in the section one the 3rd, connect this second end of sample, increase to the 5th interval greater than the 4th interval further to make the interval between the adjacent wires towards this.
7. electronics method of attachment as claimed in claim 6 more comprises the following steps:
Electronic wire in this zone line that connects sample at least partially in this provides one second crooked sample, launches between section, with the length of the described portions of electronics lead of further increase between this second expansion section and the 3rd at least.
8. electronics method of attachment as claimed in claim 7, wherein, the 5th equates with this second interval at interval substantially.
9. electronics method of attachment as claimed in claim 1 wherein, also is provided one second crooked sample in this first expansion section at least partially in the electronic wire in this zone line of this connection sample.
10. electronics method of attachment as claimed in claim 1 wherein also is provided one second crooked sample in this second expansion section at least partially in the electronic wire in this zone line of this connection sample.
11. electric power connector, in order to provide the electronics between one first electronic package and one second electronic package to connect, this first electronic package comprises a plurality of first electronics links, have one first between the adjacent link of the described first electronics link at interval, this second electronic package comprises a plurality of second electronics links, one second interval greater than this first interval is arranged between the adjacent link of the described second electronics link, and this electric power connector comprises:
Many electronic wires, be to connect the sample setting with one, with so that each this electronic wire can be connected to 1 of the described first electronics link the second electronics link of a correspondence, wherein, this connection sample has one first end near this first electronic package, one second end, two borderline regions between between this first end and this second end and the zone line between between described borderline region of close this second electronic package, wherein, this connection sample comprises:
One first expansion section is arranged near this first end, and wherein, described electronic wire is to launch outwardly in this first expansion section, so that the interval between the adjacent wires increases to the 3rd interval greater than this first interval;
One first centre portion between between this first expansion section and this second end, wherein, is towards this second end expansion at this first described electronic wire that launches in section; And
One second launches section, between between this first centre portion and this second end, wherein, described electronic wire is to launch outwardly, further to make the interval between the adjacent wires increase to the 4th interval greater than the 3rd interval, wherein, be provided at least between this first one first crooked sample that launches between section and this second expansion section, to increase the length of described portions of electronics lead at least partially in the electronic wire in this first centre portion of this connection sample.
12. electric power connector as claimed in claim 11, wherein, the 4th equates with this second interval at interval substantially.
13. electric power connector as claimed in claim 11, wherein, at least partially in being provided one second crooked sample in this zone line of this connection sample and near the electronic wire of this first end of this connection sample.
14. electric power connector as claimed in claim 13 wherein, is arranged on this to this second crooked sample of small part and second launches in section.
15. electric power connector as claimed in claim 11 wherein is arranged on this to this first crooked sample of small part and first launches in section.
16. electric power connector as claimed in claim 11 more comprises:
One second centre portion between between this second expansion section and this second end, is towards this second end expansion at this second described electronic wire that launches in section wherein; And
One the 3rd launches section, between between this second centre portion and this second end, wherein said electronic wire is to launch outwardly, further to make the interval between the adjacent wires increase to the 5th interval greater than the 4th interval, wherein be provided one the 3rd crooked sample at least partially in the electronic wire in this zone line of this connection sample, launch between section, at this second expansion section and the 3rd with the length of the described portions of electronics lead of further increase.
17. electric power connector as claimed in claim 16, wherein, the 5th equates with this second interval at interval substantially.
18. an electronic module comprises:
One substrate;
One first electronic package, it has a plurality of first electronics links that are arranged on this substrate, has one first between the adjacent link of the described first electronics link at interval;
One second electronic package, it has a plurality of second electronics links that are arranged on this substrate, and second interval greater than this first interval is arranged between the adjacent link of the described second electronics link;
One electric power connector connects in order to the electronics between this first electronic package and this second electronic package to be provided, and this electric power connector comprises:
Many electronic wires, connect the sample setting with one, with so that each this electronic wire can be connected to 1 of the described first electronics link the second electronics link of a correspondence, this connection sample has one first end near this first electronic package, one second end, two borderline regions between between this first end and this second end and the zone line between between described borderline region of close this second electronic package, and wherein this connection sample comprises:
One first launches section, is arranged near this first end, and wherein, described electronic wire is to launch outwardly in this first expansion section, so that the interval between the adjacent wires increases to the 3rd interval greater than this first interval;
One first centre portion between between this first expansion section and this second end, wherein, is towards this second end expansion at this first described electronic wire that launches in section; And
One second launches section, between between this first centre portion and this second end, wherein, described electronic wire is to launch outwardly, further to make the interval between the adjacent wires increase to the 4th interval greater than the 3rd interval, wherein, be provided one first crooked sample at least partially in the electronic wire in this zone line of this connection sample, between between this first expansion section and this second expansion section, to increase the length of described portions of electronics lead.
19. electronic module as claimed in claim 18, wherein, the 4th equates with this second interval at interval substantially.
20. electronic module as claimed in claim 18, wherein, at least partially in being provided one second crooked sample in this zone line of this connection sample and near the electronic wire of this first end of this connection sample.
21. electronic module as claimed in claim 18 wherein, is arranged on this to this first crooked sample of small part and first launches section.
22. electronic module as claimed in claim 20 wherein, is arranged on this to this second crooked sample of small part and second launches section.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/274,834 | 2005-11-14 | ||
| US11/274,834 US7267555B2 (en) | 2005-10-18 | 2005-11-14 | Electrical connectors between electronic devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1928676A true CN1928676A (en) | 2007-03-14 |
| CN100399166C CN100399166C (en) | 2008-07-02 |
Family
ID=37858697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101216780A Active CN100399166C (en) | 2005-11-14 | 2006-08-28 | Electronic connectors and connection method thereof, and electronic modules |
Country Status (3)
| Country | Link |
|---|---|
| JP (2) | JP4538439B2 (en) |
| CN (1) | CN100399166C (en) |
| TW (1) | TWI327671B (en) |
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| CN104714696A (en) * | 2010-07-08 | 2015-06-17 | 友达光电股份有限公司 | Touch display substrate |
| CN106297623A (en) * | 2015-06-10 | 2017-01-04 | 群创光电股份有限公司 | Fan-out circuit and apply its display device |
| WO2018040584A1 (en) * | 2016-08-31 | 2018-03-08 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN112086063A (en) * | 2019-06-13 | 2020-12-15 | 三星显示有限公司 | Display device |
| WO2023155140A1 (en) * | 2022-02-18 | 2023-08-24 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
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| CN104714696B (en) * | 2010-07-08 | 2017-11-24 | 友达光电股份有限公司 | touch display substrate |
| CN106297623A (en) * | 2015-06-10 | 2017-01-04 | 群创光电股份有限公司 | Fan-out circuit and apply its display device |
| CN106297623B (en) * | 2015-06-10 | 2019-11-01 | 群创光电股份有限公司 | Fan-out circuit and the display device for applying it |
| WO2018040584A1 (en) * | 2016-08-31 | 2018-03-08 | 京东方科技集团股份有限公司 | Array substrate and display device |
| US10403647B2 (en) | 2016-08-31 | 2019-09-03 | Boe Technology Group Co., Ltd. | Array substrate and display device |
| CN112086063A (en) * | 2019-06-13 | 2020-12-15 | 三星显示有限公司 | Display device |
| WO2023155140A1 (en) * | 2022-02-18 | 2023-08-24 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
| WO2023226137A1 (en) * | 2022-05-27 | 2023-11-30 | 武汉华星光电半导体显示技术有限公司 | Display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007142387A (en) | 2007-06-07 |
| TWI327671B (en) | 2010-07-21 |
| JP4538439B2 (en) | 2010-09-08 |
| CN100399166C (en) | 2008-07-02 |
| TW200719021A (en) | 2007-05-16 |
| JP2010016400A (en) | 2010-01-21 |
| JP5080541B2 (en) | 2012-11-21 |
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