WO2014171014A1 - 半導体装置の製造方法、及び、半導体装置 - Google Patents

半導体装置の製造方法、及び、半導体装置 Download PDF

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WO2014171014A1
WO2014171014A1 PCT/JP2013/061653 JP2013061653W WO2014171014A1 WO 2014171014 A1 WO2014171014 A1 WO 2014171014A1 JP 2013061653 W JP2013061653 W JP 2013061653W WO 2014171014 A1 WO2014171014 A1 WO 2014171014A1
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semiconductor layer
columnar
layer
film
type diffusion
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PCT/JP2013/061653
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English (en)
French (fr)
Inventor
舛岡　富士雄
原田　望
広記 中村
イーソ リ，
アシット ラマチャンドラ カマス，
ツィシャン ツェン，
テン スン プア，
キンペン ワン，
パトリック グオチャン ロー，
Original Assignee
ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
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Priority to JP2014520854A priority Critical patent/JP5692886B1/ja
Priority to PCT/JP2013/061653 priority patent/WO2014171014A1/ja
Priority to SG11201504337QA priority patent/SG11201504337QA/en
Publication of WO2014171014A1 publication Critical patent/WO2014171014A1/ja
Priority to US14/744,890 priority patent/US9490362B2/en
Priority to US15/263,535 priority patent/US9666688B2/en

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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Definitions

  • the present invention relates to a semiconductor device manufacturing method and a semiconductor device.
  • SGT Surrounding Gate Transistor
  • a silicon pillar with a nitride film hard mask formed in a columnar shape is formed, a diffusion layer is formed under the silicon pillar, and then a gate material is deposited. Thereafter, the gate material is planarized and etched back to form insulating film sidewalls on the sidewalls of the silicon pillars and nitride hard mask. Thereafter, a resist pattern for gate wiring is formed, the gate material is etched, the nitride film hard mask is removed, and a diffusion layer is formed on top of the silicon pillar (for example, Patent Document 4). See).
  • a gate oxide film is formed after forming the silicon pillar. Then, after depositing thin polysilicon, a resist for forming a gate wiring is formed so as to cover the upper part of the silicon pillar. Further, the gate wiring is etched, and then a thick oxide film is deposited to expose the upper part of the silicon pillar, and the thin polysilicon on the upper part of the silicon pillar is removed. Finally, a technique for removing a thick oxide film by wet etching is disclosed (for example, see Non-Patent Document 1).
  • JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2009-182317 A
  • the present invention provides a method for manufacturing a semiconductor device having an SGT structure in which a gate electrode made of a metal material is formed by a self-alignment process by using a thin gate material, and an SGT obtained thereby.
  • the purpose is to provide a structure.
  • a method for manufacturing a semiconductor device includes: Forming a planar semiconductor layer on a semiconductor substrate, and forming a first columnar semiconductor layer and a second columnar semiconductor layer on the planar semiconductor layer; After the first step, Forming a gate insulating film around the first columnar semiconductor layer and the second columnar semiconductor layer; A metal film and a polysilicon film are formed around the gate insulating film, The thickness of the polysilicon film is made thinner than half the distance between the first columnar semiconductor layer and the second columnar semiconductor layer; A third resist is deposited, the polysilicon film on the upper sidewalls of the first columnar semiconductor layer and the second columnar semiconductor layer is exposed, the exposed polysilicon film is removed by etching, and the first columnar semiconductor layer is removed by etching.
  • a second step of removing the resist 3 and removing the metal film by etching After the second step, Forming a fourth resist for forming a gate wiring and performing anisotropic etching to form a gate wiring, a first gate electrode, and a second gate electrode; Having It is characterized by that.
  • the method further includes four steps.
  • Silicide is formed on the first n-type diffusion layer, the second n-type diffusion layer, the first p-type diffusion layer, the second p-type diffusion layer, and the gate wiring. It is preferable that the method further includes a sixth step.
  • a semiconductor device provides: A planar semiconductor layer formed on a semiconductor substrate; First and second columnar semiconductor layers formed on the planar semiconductor layer; A first gate insulating film formed around the first columnar semiconductor layer; A first gate electrode having a laminated structure of a metal film and a polysilicon film formed around the first gate insulating film; A second gate insulating film formed around the second columnar semiconductor layer; A second gate electrode having a laminated structure of a metal film and a polysilicon film formed around the second gate insulating film; A gate wiring connected to the first and second gate electrodes; An oxide film thicker than the gate insulating film formed between the gate wiring and the planar semiconductor layer; A first n-type diffusion layer formed on the first columnar semiconductor layer; A second n-type diffusion layer formed in a lower portion of the first columnar semiconductor layer and an upper portion of the planar semiconductor layer; A first p-type diffusion layer formed on the second columnar semiconductor layer; A second p-type diffusion layer formed on a lower portion
  • the gate wiring has a laminated structure of the metal film and silicide.
  • the center line of the gate wiring is offset by a predetermined amount with respect to a line connecting the center point of the first columnar semiconductor layer and the center point of the second columnar semiconductor layer.
  • a method for manufacturing a semiconductor device having an SGT structure in which a gate electrode made of a metal material is formed by a self-alignment process by using a thin gate material, and an SGT obtained thereby Structure can be provided.
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment, (B) is sectional drawing in the XX 'line of (A), (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • (A) is a top view which shows the manufacturing method of the semiconductor device concerning this embodiment,
  • (B) is sectional drawing in the XX 'line of (A),
  • (C) is Y of (A).
  • FIG. 6 is a cross-sectional view taken along line ⁇ Y ′.
  • a semiconductor device having an SGT structure manufactured by the method for manufacturing a semiconductor device according to an embodiment of the present invention has the following structure.
  • the semiconductor device having the SGT structure includes a planar silicon layer 107 formed on a silicon substrate 101, and first and second planar layers formed on the planar silicon layer 107.
  • a gate insulating film 114, a second gate electrode 119a having a laminated structure of a metal film 115 and a polysilicon film 116 formed around the gate insulating film 114, and polysilicon A film 116 is formed.
  • the thickness of each of the gate insulating film 114, the second gate electrode 119a having a stacked structure of the metal film 115 and the polysilicon film 116 formed around the gate insulating film 114, and the polysilicon film 116 is set to The height of the upper surface of the metal film 115 is smaller than half the distance between the columnar silicon layer 104 and the second columnar silicon layer 105 and the height of the upper surface of the polysilicon film 116 is higher. It is in.
  • the height of the upper surface of the gate wiring 119c connected to the first and second gate electrodes 119b and 119a is lower than the height of the upper surface of the first and second gate electrodes 119b and 119a.
  • the second oxide film is thicker than the gate insulating films 113 and 114 formed between the gate wiring 119c and the planar silicon layer 107.
  • a first n-type diffusion layer 121 formed on the first columnar silicon layer 104 a second n-type diffusion layer 121 formed on the lower portion of the first columnar silicon layer 104 and the upper portion of the planar silicon layer 107.
  • the n-type diffusion layer 122, the first p-type diffusion layer 124 formed on the second columnar silicon layer 105, the lower portion of the second columnar silicon layer 105 and the upper portion of the planar silicon layer 107 are formed.
  • a second p-type diffusion layer 125 is formed.
  • planar silicon layer 107 (planar semiconductor layer) is formed on a silicon substrate 101 (semiconductor substrate), and a first columnar silicon layer 104 (first columnar semiconductor layer) is formed on the planar silicon layer 107. ) And the second columnar silicon layer 105 (second columnar semiconductor layer) will be described in detail.
  • first resists 102 and 103 for forming a first columnar silicon layer 104 and a second columnar silicon layer 105 are first formed on a silicon substrate 101.
  • the silicon substrate 101 is used as a substrate for creating a semiconductor device, but other substrates can be used as long as they are used for creating a semiconductor device.
  • a first columnar silicon layer 104 and a second columnar silicon layer 105 are formed below the first resists 102 and 103.
  • the columnar silicon layer is formed using a hard mask such as an oxide film or a nitride film.
  • the first resists 102 and 103 are stripped and removed.
  • a second resist 106 for forming the planar silicon layer 107 is formed.
  • the planar silicon layer 107 is formed below the second resist 106 by etching the silicon substrate 101.
  • the second resist 106 is stripped and removed.
  • an element isolation film 108 is formed around the planar silicon layer 107.
  • a first oxide film 109 is deposited so as to cover the first columnar silicon layer 104, the second columnar silicon layer 105, and the planar silicon layer 107.
  • CVD chemical vapor deposition
  • the first pillar-shaped silicon layer 104, the second pillar-shaped silicon layer 105, and the planar silicon layer 107 are thickly formed on the first pillar-shaped silicon layer 104.
  • a thin first oxide film 109 is deposited on the sidewalls of the oxide film 109, the columnar silicon layer 104, and the second columnar silicon layer 105.
  • the thickness of the first oxide film 109 deposited on the first columnar silicon layer 104 and the second columnar silicon layer 105 is deposited on the planar silicon layer 107. The thickness of the first oxide film 109 becomes thicker.
  • the first oxide film 109 is removed by using isotropic etching, whereby an oxide film hard layer is formed on the first columnar silicon layer 104 and the second columnar silicon layer 105.
  • Masks 111 and 112 are formed.
  • a second oxide film 110 having a thickness greater than that of the gate insulating films 113 and 114 (see FIG. 11) is formed on the planar silicon layer 107.
  • planar silicon layer 107 (planar semiconductor layer) is formed on the silicon substrate 101 (semiconductor substrate), and the first columnar silicon layer 104 (first columnar semiconductor layer) is formed on the planar silicon layer 107. ) And the second columnar silicon layer 105 (second columnar semiconductor layer) are shown.
  • gate insulating films 113 and 114 are formed around the first columnar silicon layer 104 (first columnar semiconductor layer) and the second columnar silicon layer 105 (second columnar semiconductor layer). Then, a metal film 115 and a thin polysilicon film 116 are formed around the gate insulating films 113 and 114.
  • the thickness of the polysilicon film 116 is half the distance between the first columnar silicon layer 104 (first columnar semiconductor layer) and the second columnar silicon layer 105 (second columnar semiconductor layer). Try to be thinner than the length.
  • a third resist 117 is deposited on the polysilicon film 116, and the first columnar silicon layer 104 (first columnar semiconductor layer) and the second columnar silicon layer 105 (second layer) are deposited from the third resist 117.
  • the polysilicon film 116 on the upper side wall of the columnar semiconductor layer) is exposed.
  • the second step of removing the polysilicon film 116 exposed from the third resist 117 by etching, removing the third resist 117, and removing the metal film 115 by etching will be described in detail.
  • gate insulating films 113 and 114 are formed around the first columnar silicon layer 104 and the second columnar silicon layer 105, and a metal film 115 is formed around the gate insulating films 113 and 114. Then, a thin polysilicon film 116 is formed. Since thin polysilicon is used, generation of voids in the polysilicon film 116 is prevented.
  • titanium nitride is used as the material of the metal film 115.
  • any metal that can be used in the semiconductor manufacturing process and can set the threshold voltage of the transistor is used as the material of the metal film 115. it can.
  • As the gate insulating films 113 and 114 for example, an oxide film, an oxynitride film, a high dielectric film, or the like that is used in a semiconductor process can be used.
  • a third resist 117 is deposited, and the polysilicon film 116 on the upper sidewalls of the first columnar silicon layer 104 and the second columnar silicon layer 105 is exposed from the third resist 117.
  • resist etch back it is preferable to use resist etch back in order to expose the polysilicon film 116 on the upper side wall.
  • the polysilicon film 116 on the upper sidewall may be exposed using a coating film such as spin-on-glass.
  • the polysilicon film 116 exposed from the third resist 117 is removed by etching.
  • the third resist 117 is removed.
  • the metal film 115 is removed by etching.
  • wet etching is used between the polysilicon film 116 and the columnar silicon layers 104 and 105.
  • a certain metal film 115 is etched, and a void may be generated between the polysilicon film 116 and the columnar silicon layers 104 and 105.
  • the gate insulating films 113 and 114 are formed around the first columnar silicon layer 104 (first columnar semiconductor layer) and the second columnar silicon layer 105 (second columnar semiconductor layer), and the gate insulating film A metal film 115 and a thin polysilicon film 116 are formed around 113 and 114.
  • the thickness of the polysilicon film 116 is half the distance between the first columnar silicon layer 104 (first columnar semiconductor layer) and the second columnar silicon layer 105 (second columnar semiconductor layer). Try to be thinner than the length.
  • a third resist 117 is deposited on the polysilicon film 116, and the first columnar silicon layer 104 (first columnar semiconductor layer) and the second columnar silicon layer 105 (second layer) are deposited from the third resist 117.
  • the polysilicon film 116 on the upper side wall of the columnar semiconductor layer) is exposed.
  • a second step was shown in which the polysilicon film 116 exposed from the third resist 117 was removed by etching, the third resist 117 was removed, and the metal film 115 was removed by etching.
  • a fourth resist 118 for forming the gate wiring 119c is formed, and anisotropic etching is performed to form the gate wiring 119c, the first gate electrode 119b, and the second gate electrode 119a.
  • anisotropic etching is performed to form the gate wiring 119c, the first gate electrode 119b, and the second gate electrode 119a. The third step will be described in detail.
  • a fourth resist 118 for forming the gate wiring 119c (see FIG. 17) is formed.
  • the height of the upper surface of the fourth resist 118 is preferably lower than the height of the upper surface of the polysilicon film 116 after the second step.
  • the gate wiring 119c if anisotropic etching is used, the polysilicon film 116 above the first and second gate electrodes 119b and 119a (see FIG. 17) is removed.
  • the height of the upper surface can be made higher than the height of the upper surface of the polysilicon film 116.
  • the center line of the fourth resist 118 for the gate wiring 119c connects the center point of the first columnar silicon layer 104 and the center point of the second columnar silicon layer 105.
  • the third resist 117 is preferably formed so as to be offset by a predetermined amount (see FIG. 17). By offsetting by a predetermined amount in this way, it becomes easy to form a silicide 135 (see FIG. 28) that connects the second n-type diffusion layer 122 and the second p-type diffusion layer 125.
  • the polysilicon film 116 and the metal film 115 are etched to form the first and second gate electrodes 119b and 119a and the gate wiring 119c.
  • the fourth resist 118 for forming the gate wiring 119c may be brought into contact with the gate electrodes 119a and 119b formed around the silicon pillar.
  • the alignment margin of the gate wiring 119c is increased, so that a self-alignment process is realized.
  • the upper portions of the first columnar silicon layer 104 and the second columnar silicon layer 105 are protected by the oxide film hard masks 111 and 112.
  • the height of the upper surface of the metal film 115 is set to the upper surface of the polysilicon film 116.
  • the height can be higher.
  • the second oxide film 110 is removed by etching.
  • the fourth resist 118 is stripped and removed.
  • the fourth resist 118 for forming the gate wiring 119c is formed, and anisotropic etching is performed to form the gate wiring 119c, the first gate electrode 119b, and the second gate electrode 119a.
  • a third step was shown.
  • a first n-type diffusion layer 121 is formed on the upper portion of the first columnar silicon layer 104 (first columnar semiconductor layer), and the lower portion of the first columnar silicon layer 104 and the planar silicon layer 107 (planar surface).
  • a second n-type diffusion layer 122 is formed on the upper portion of the semiconductor layer.
  • a first p-type diffusion layer 124 is formed on the second columnar silicon layer 105 (second columnar semiconductor layer), and on the lower portion of the second columnar silicon layer 105 and the upper portion of the planar silicon layer 107.
  • the fourth step for forming the second p-type diffusion layer 125 will be described in detail.
  • a fifth resist 120 is formed in order to form the first n-type diffusion layer 121 and the second n-type diffusion layer 122.
  • a thin oxide film may be deposited on the upper surface of the planar silicon layer 107 or the like before the fifth resist 120 is formed.
  • arsenic (As) is implanted into the upper and lower portions of the first columnar silicon layer 104, respectively, so that the first n-type diffusion layer 121 and the second n-type diffusion layer are injected. 122 is formed.
  • the fifth resist 120 is stripped and removed.
  • a sixth resist 123 for forming the first p-type diffusion layer 124 and the second p-type diffusion layer 125 is formed.
  • boron or fluorine fluoride is implanted into the upper and lower portions of the second columnar silicon layer 105, respectively, so that the first p-type diffusion layer 124 and the second p-type diffusion layer are implanted.
  • Layer 125 is formed.
  • the sixth resist 123 is stripped and removed.
  • an oxide film 126 and a nitride film 127 are deposited in a layered and uniform manner, followed by heat treatment.
  • the first n-type diffusion layer 121 is formed on the upper portion of the first columnar silicon layer 104 (first columnar semiconductor layer), and the lower portion of the first columnar silicon layer 104 and the planar silicon layer 107 (planar surface).
  • a second n-type diffusion layer 122 is formed on the upper portion of the semiconductor layer.
  • a first p-type diffusion layer 124 is formed on the second columnar silicon layer 105 (second columnar semiconductor layer), and on the lower portion of the second columnar silicon layer 105 and the upper portion of the planar silicon layer 107.
  • a fourth step of forming the second p-type diffusion layer 125 is shown.
  • the silicide 131, the first n-type diffusion layer 121, the second n-type diffusion layer 122, the first p-type diffusion layer 124, the second p-type diffusion layer 125, and the gate wiring 119 c are formed on the silicide 131,
  • the fifth step of forming 135, 132, 134, 130, 133 will be described in detail.
  • insulating film sidewalls 128a, 128b, 129a, 129b, and 129c are formed.
  • a metal material is deposited, heat treatment is performed, and unreacted metal material is removed, whereby the second n-type diffusion layer 122 is formed on the first n-type diffusion layer 121.
  • Silicides 131, 135, 132, 134, 130, 133 are formed on the first p-type diffusion layer 124, the second p-type diffusion layer 125, and the gate wiring 119c, respectively.
  • the insulating film sidewall can be a nitride film sidewall.
  • the second n-type diffusion layer 122 is connected to the second p-type diffusion layer 125 via the silicide 135.
  • the center line of the gate wiring 119c is offset by a predetermined amount with respect to the line connecting the center point of the first columnar silicon layer 104 and the center point of the second columnar silicon layer 105. Therefore, it becomes easy to form the silicide 135. Thereby, high integration of the semiconductor device is realized.
  • the gate wiring 119 c is easily formed from a laminated structure including the metal film 115 and the silicide 130.
  • the silicide 130 and the metal film 115 are in direct contact, the resistance of the gate wiring 119c can be reduced.
  • silicide is formed on the first n-type diffusion layer 121, the second n-type diffusion layer 122, the first p-type diffusion layer 124, the second p-type diffusion layer 125, and the gate wiring 119c.
  • a fifth step of forming 131, 135, 132, 134, 130, 133 was shown.
  • a contact stopper 136 such as a nitride film is formed in layers so as to cover the entire structure, and an interlayer insulating film 137 is formed.
  • a seventh resist 138 for forming contact holes 139 and 140 is formed.
  • the interlayer insulating film 137 is etched to form contact holes 139 and 140 in the opening of the seventh resist 138.
  • the seventh resist 138 is removed and removed.
  • an eighth resist 141 for forming contact holes 142 and 143 is formed.
  • the interlayer insulating film 137 is etched to form contact holes 142 and 143 in the openings of the eighth resist 141.
  • the eighth resist 141 is stripped and removed.
  • the contact stopper 136 is etched to remove the contact stopper 136 under the contact holes 139 and 140 and the contact holes 142 and 143.
  • a metal material is deposited to form a metal layer 148, thereby forming contacts 144, 145, 146, and 147 connected to the lower conductor layer.
  • ninth resists 149, 150, 151, 152 for forming metal wirings 153, 154, 155, 156 are formed.
  • the metal layer 148 is etched to form metal wirings 153, 154, 155, and 156.
  • the ninth resists 149, 150, 151, and 152 are stripped and removed.
  • a method for manufacturing a semiconductor device having an SGT structure in which a gate electrode made of a metal material is formed by a self-alignment process using a thin gate material (polysilicon) has been shown.
  • the height of the upper surface of the metal film 115 is higher than the height of the upper surface of the polysilicon film 116, a void may be generated between the polysilicon film 116 and the first and second columnar silicon layers 104 and 105.
  • a decrease in capacitance between the gate electrodes 119a and 119b and the first and second columnar silicon layers 104 and 105 can be prevented.
  • the semiconductor device having SGT manufactured according to the present embodiment includes the second oxide film 110 having a thickness greater than that of the gate insulating films 113 and 114 formed between the gate wiring 119c and the planar silicon layer 107. Have. Therefore, the capacity between the gate wiring 119c and the silicon substrate 101 can be reduced, and insulation between the gate wiring 119c and the silicon substrate 101 is ensured.
  • the gate wiring 119c is formed from a laminated structure including the metal film 115 and the silicide 130.
  • the silicide 130 and the metal film 115 are in direct contact with each other, so that the resistance of the gate wiring 119c is reduced.
  • the center line of the gate wiring 119c is offset by a predetermined amount with respect to the line connecting the center point of the first columnar silicon layer 104 and the center point of the second columnar silicon layer 105 ( FIG. 17). Therefore, the silicide 135 that connects the second n-type diffusion layer 122 and the second p-type diffusion layer 125 can be easily formed. As a result, high integration of semiconductor devices on a mass production basis is realized.
  • gate insulation is provided around the first columnar silicon layer 104 (first columnar semiconductor layer) and the second columnar silicon layer 105 (second columnar semiconductor layer).
  • Films 113 and 114 are formed.
  • a metal film 115 and a thin polysilicon film 116 are formed around the gate insulating films 113 and 114.
  • the film thickness of the polysilicon film 116 is set to be thinner than half the distance between the first columnar silicon layer 104 and the second columnar silicon layer 105.
  • a third resist 117 is deposited to expose the polysilicon film 116 on the upper sidewalls of the first and second columnar silicon layers 104 and 105.
  • the exposed polysilicon film 116 is removed by etching, the third resist 117 is stripped, and the metal film 115 is removed by etching.
  • a fourth resist 118 for forming the gate wiring 119c is formed, anisotropic etching is performed, and the gate wiring 119c, the first gate electrode 119b, and the second gate electrode 119a are formed.
  • a self-alignment process is realized by the third step to be formed. According to this embodiment, since the semiconductor device is manufactured by the self-alignment process as described above, it is not necessary to use a mask made of another member, and high integration of the semiconductor device is realized.
  • the wet etching is used to remove the polysilicon film 116 and the first and second columnar silicon layers 104 and 105.
  • the metal film 115 between them is etched.
  • voids may occur between the polysilicon film 116 and the first and second columnar silicon layers 104 and 105.
  • the capacitance between the electrodes 119a and 119b and the first and second columnar silicon layers 104 and 105 is reduced.
  • the gate wiring 119c is formed by anisotropic etching.
  • the height of the upper surface of the metal film 115 is set to the height of the upper surface of the polysilicon film 116. Can be higher than the height. This prevents a void from being generated between the polysilicon film 116 and the first and second columnar silicon layers 104 and 105.
  • the present invention is capable of various embodiments and modifications without departing from the broad spirit and scope of the present invention. Further, the above-described embodiment is for describing an example of the present invention, and does not limit the scope of the present invention. The said Example and modification can be combined arbitrarily. Further, even if a part of the configuration of the above embodiment is removed as necessary, it is within the scope of the technical idea of the present invention.
  • a highly integrated semiconductor device having SGT can be manufactured.
  • Nitride film 128a Insulating film sidewall 128b. Insulating film side wall 129a. Insulating film sidewall 129b. Insulating film sidewall 129c. Insulating film sidewall 130. Silicide 131. Silicide 132. Silicide 133. Silicide 134. Silicide 135. Silicide 136. Contact stopper 137. Interlayer insulating film 138. Seventh resist 139. Contact hole 140. Contact hole 141. Eighth resist 142. Contact hole 143. Contact hole 144. Contact 145. Contact 146. Contact 147. Contact 148. Metal layer 149. Ninth resist 150. Ninth resist 151. Ninth resist 152. Ninth resist 153. Metal wiring 154. Metal wiring 155. Metal wiring 156. Metal wiring

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Abstract

　半導体装置の製造方法は、シリコン基板（101）上に平面状シリコン層（107）を形成し、平面状シリコン層上に第１及び第２の柱状シリコン層（104,105）とを形成する第１の工程と、第１及び第２の柱状シリコン層の周囲にゲート絶縁膜（113）を形成し、ゲート絶縁膜の周囲に金属膜（115）及びポリシリコン膜（116）を成膜し、ポリシリコン膜の膜厚を第１及び第２の柱状シリコン層との間の間隔の半分の長さよりも薄くし、第３のレジスト（117）を堆積し、第１及び第２の柱状半導体層の上部側壁のポリシリコン膜を露出させ、露出したポリシリコン膜をエッチングにより除去し、第３のレジストを剥離し、金属膜をエッチングにより除去する第２の工程と、ゲート配線（119c）を形成するための第４のレジスト（118）を形成し、異方性エッチングを行い、ゲート配線、第１のゲート電極、及び第２のゲート電極を形成する第３の工程と、を有する。

Description

半導体装置の製造方法、及び、半導体装置
　本発明は半導体装置の製造方法、及び、半導体装置に関する。
　半導体集積回路、特にＭＯＳトランジスタを用いた集積回路は、高集積化の一途を辿っている。この高集積化に伴って、その中で用いられているＭＯＳトランジスタはナノ領域まで微細化が進んでいる。このようにＭＯＳトランジスタの微細化が進むと、リーク電流の抑制が困難となり、必要な電流量を確保する必要があるために回路の占有面積を小さくすることが難しい、といった問題がある。このような問題を解決するために、基板に対してソース、ゲート、ドレインが垂直方向に配置され、ゲート電極が柱状半導体層を取り囲む構造である、Surrounding Gate Transistor（以下、「ＳＧＴ」という。）が提案されている（例えば、特許文献１、特許文献２、特許文献３を参照）。
　従来のＳＧＴの製造方法では、窒化膜ハードマスクが柱状に形成されたシリコン柱を形成し、シリコン柱の下部に拡散層を形成した後、ゲート材料を堆積する。その後、ゲート材料を平坦化、エッチバックすることで、シリコン柱及び窒化膜ハードマスクの側壁に絶縁膜サイドウォールを形成する。その後、ゲート配線のためのレジストパターンを形成し、ゲート材料をエッチングした後、窒化膜ハードマスクを除去し、シリコン柱の上部に拡散層を形成する方法により製造されている（例えば、特許文献４を参照）。
　このような方法では、隣接するシリコン柱の間隔が狭くなったときに、厚さの厚いゲート材料をシリコン柱の間に堆積することが必要となり、シリコン柱の間にボイドと呼ばれる微小な孔が形成されることがある。このようにボイドが形成されると、エッチバック後にゲート材料に孔が形成される。その後、絶縁膜サイドウォールを形成するためにシリコン柱の間に絶縁膜を堆積すると、このボイド内にこの絶縁膜が堆積する。このため、シリコン柱の間に存在するゲート材料の加工が難しくなる。
　そこで、シリコン柱を形成した後、ゲート酸化膜を形成する。そして、厚さの薄いポリシリコンを堆積した後、シリコン柱の上部を覆うようにゲート配線を形成するためのレジストを形成する。さらにゲート配線をエッチングし、その後、酸化膜を厚く堆積し、シリコン柱の上部を露出させ、シリコン柱の上部の厚さの薄いポリシリコンを除去する。最後に、厚さの厚い酸化膜をウエットエッチングにて除去する技術が開示されている（例えば、非特許文献１を参照）。
　しかしながら、このような従来技術では、ゲート電極に金属を用いる技術は示されていない。また、シリコン柱の上部を覆うゲート配線を形成するためにレジストを形成することが必要となり、そのレジストがシリコン柱の上部を覆うことになり、結果的に自己整合プロセスとはならない。
特開平２－７１５５６号公報 特開平２－１８８９６６号公報 特開平３－１４５７６１号公報 特開２００９－１８２３１７号公報
B.Yang, K.D.Buddharaju, S.H.G.Teo, N.Singh, G.D.Lo,and D.L.Kwong, "Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET", IEEE Electron Device Letters, VOL.29, No.7, July 2008, pp791-794.
　そこで、本発明は、厚さの薄いゲート材料を用いることで、自己整合プロセスによって、金属材料からなるゲート電極が形成される、ＳＧＴの構造を有する半導体装置の製造方法と、それにより得られるＳＧＴの構造を提供することを目的とする。
　本発明の第１の観点に係る半導体装置の製造方法は、
　半導体基板上に平面状半導体層を形成し、前記平面状半導体層上に第１の柱状半導体層と第２の柱状半導体層とを形成する第１の工程と、
　前記第１工程の後、
　前記第１の柱状半導体層及び前記第２の柱状半導体層の周囲にゲート絶縁膜を形成し、
　前記ゲート絶縁膜の周囲に金属膜及びポリシリコン膜を成膜し、
　前記ポリシリコン膜の膜厚を前記第１の柱状半導体層及び前記第２の柱状半導体層の間の間隔の半分の長さよりも薄くし、
　第３のレジストを堆積し、前記第１の柱状半導体層及び前記第２の柱状半導体層の上部側壁の前記ポリシリコン膜を露出させ、この露出した前記ポリシリコン膜をエッチングによって除去し、前記第３のレジストを剥離し、前記金属膜をエッチングにより除去する第２の工程と、
　前記第２の工程の後、
　ゲート配線を形成するための第４のレジストを形成し、異方性エッチングを行うことにより、ゲート配線と、第１のゲート電極と、第２のゲート電極と、を形成する第３の工程と、を有する、
　ことを特徴とする。
　前記第１の工程の後、
　前記第１の柱状シリコン層及び前記第２の柱状シリコン層の上に酸化膜ハードマスクを形成し、前記平面状シリコン層上にゲート絶縁膜よりも厚さの厚い酸化膜を形成する工程をさらに含む、ことが好ましい。
　前記第４のレジストの上面の高さは、前記第２工程を経た後のポリシリコン膜の上面の高さよりも低い、ことが好ましい。
　前記第１の柱状半導体層の上部に第１のｎ型拡散層を形成し、前記第１の柱状半導体層の下部及び前記平面状半導体層の上部に第２のｎ型拡散層を形成し、前記第２の柱状半導体層の上部に第１のｐ型拡散層を形成し、前記第２の柱状半導体層の下部及び前記平面状半導体層の上部に第２のｐ型拡散層を形成する第４の工程をさらに含む、ことが好ましい。
　前記第１のｎ型拡散層上、前記第２のｎ型拡散層上、前記第１のｐ型拡散層上、前記第２のｐ型拡散層上、及び前記ゲート配線上にシリサイドを形成する第６の工程をさらに含む、ことが好ましい。
　本発明の第２の観点に係る半導体装置は、
　半導体基板上に形成された平面状半導体層と、
　前記平面状半導体層上に形成された第１及び第２の柱状半導体層と、
　前記第１の柱状半導体層の周囲に形成された第１のゲート絶縁膜と、
　前記第１のゲート絶縁膜の周囲に形成された金属膜及びポリシリコン膜の積層構造からなる第１のゲート電極と、
　前記第２の柱状半導体層の周囲に形成された第２のゲート絶縁膜と、
　前記第２のゲート絶縁膜の周囲に形成された金属膜及びポリシリコン膜の積層構造からなる第２のゲート電極と、
　前記第１及び前記第２のゲート電極に接続されたゲート配線と、
　前記ゲート配線と前記平面状半導体層との間に形成された前記ゲート絶縁膜よりも厚さが厚い酸化膜と、
　前記第１の柱状半導体層の上部に形成された第１のｎ型拡散層と、
　前記第１の柱状半導体層の下部と前記平面状半導体層の上部とに形成された第２のｎ型拡散層と、
　前記第２の柱状半導体層の上部に形成された第１のｐ型拡散層と、
　前記第２の柱状半導体層の下部及び前記平面状半導体層の上部に形成された第２のｐ型拡散層と、を備え、
　前記ポリシリコン膜の膜厚は前記第１の柱状半導体層と前記第２の柱状半導体層との間の間隔の半分の長さよりも薄く形成されており、
　前記金属膜の上面の高さは、前記ポリシリコン膜の上面の高さよりも高くされており、
　前記ゲート配線の上面の高さは、前記第１及び第２のゲート電極の上面の高さよりも低くされている、ことが好ましい。
　前記ゲート配線は、前記金属膜及びシリサイドの積層構造からなる、ことが好ましい。
　前記ゲート配線の中心線が、前記第１の柱状半導体層の中心点と前記第２の柱状半導体層の中心点とを結ぶ線に対して所定量オフセットしている、ことが好ましい。
　前記第１及び前記第２のｎ型拡散層上と、前記第１及び前記第２のｐ型拡散層上とに形成されたシリサイドをさらに備える、ことが好ましい。
　本発明によれば、厚さが薄いゲート材料を用いることで、自己整合プロセスによって金属材料からなるゲート電極が形成される、ＳＧＴの構造を有する半導体装置の製造方法と、それにより得られるＳＧＴの構造を提供することができる。
（Ａ）は本発明の実施形態に係る半導体装置の平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。 （Ａ）は本実施形態に係る半導体装置の製造方法を示す平面図であり、（Ｂ）は（Ａ）のＸ－Ｘ’線での断面図であり、（Ｃ）は（Ａ）のＹ－Ｙ’線での断面図である。
　本発明の実施形態に係る半導体装置の製造方法により製造される、ＳＧＴの構造を有する半導体装置は、以下の構造を有する。
　図１に示すように、本実施形態に係る、ＳＧＴの構造を有する半導体装置は、シリコン基板１０１上に形成された平面状シリコン層１０７と、平面状シリコン層１０７上に形成された第１及び第２の柱状シリコン層１０４、１０５と、第１の柱状シリコン層１０４の周囲に形成されたゲート絶縁膜１１３と、ゲート絶縁膜１１３の周囲に形成された金属膜１１５及びポリシリコン膜１１６の積層構造からなる第１のゲート電極１１９ｂとを備えている。
　第２の柱状シリコン層１０５の周囲に、ゲート絶縁膜１１４と、ゲート絶縁膜１１４の周囲に形成された金属膜１１５及びポリシリコン膜１１６の積層構造からなる第２のゲート電極１１９ａと、ポリシリコン膜１１６が形成されている。
　ゲート絶縁膜１１４と、ゲート絶縁膜１１４の周囲に形成された金属膜１１５及びポリシリコン膜１１６の積層構造からなる第２のゲート電極１１９ａと、ポリシリコン膜１１６のそれぞれの厚さは、第１の柱状シリコン層１０４と第２の柱状シリコン層１０５との間の間隔の半分の長さよりも薄く、かつ、金属膜１１５の上面の高さは、ポリシリコン膜１１６の上面の高さよりも高い位置にある。
　第１及び第２のゲート電極１１９ｂ、１１９ａに接続されたゲート配線１１９ｃの上面の高さは、第１及び第２のゲート電極１１９ｂ、１１９ａの上面の高さよりも低い位置にある。
　本実施形態に係る、ＳＧＴの構造を有する半導体装置は、さらに、ゲート配線１１９ｃと平面状シリコン層１０７との間に形成されたゲート絶縁膜１１３、１１４よりも厚さが厚い第２の酸化膜１１０と、第１の柱状シリコン層１０４の上部に形成された第１のｎ型拡散層１２１と、第１の柱状シリコン層１０４の下部及び平面状シリコン層１０７の上部に形成された第２のｎ型拡散層１２２と、第２の柱状シリコン層１０５の上部に形成された第１のｐ型拡散層１２４と、第２の柱状シリコン層１０５の下部及び平面状シリコン層１０７の上部に形成された第２のｐ型拡散層１２５と、を有する。
　以下、本発明の実施形態に係る、ＳＧＴの構造を有する半導体装置の製造方法について、図２～図４０を参照しながら説明する。
　以下に、シリコン基板１０１（半導体基板）上に平面状シリコン層１０７（平面状半導体層）を形成し、この平面状シリコン層１０７上に、第１の柱状シリコン層１０４（第１の柱状半導体層）と、第２の柱状シリコン層１０５（第２の柱状半導体層）と、を形成する第１の工程を詳細に説明する。
　図２に示すように、まず、シリコン基板１０１上に、第１の柱状シリコン層１０４と第２の柱状シリコン層１０５とを形成するための第１のレジスト１０２、１０３を形成する。本実施形態において、半導体装置作成用の基板としてシリコン基板１０１を用いるが、半導体装置作成用に使用される基板であればその他の基板であっても使用できる。
　次に、図３に示すように、シリコン基板１０１をエッチングすることで、第１のレジスト１０２、１０３の下方に、第１の柱状シリコン層１０４と第２の柱状シリコン層１０５とを形成する。ここでは、酸化膜、窒化膜といったハードマスクを用いて柱状シリコン層を形成する。
　続いて、図４に示すように、第１のレジスト１０２、１０３を剥離、除去する。
　続いて、図５に示すように、平面状シリコン層１０７を形成するための第２のレジスト１０６を形成する。
　続いて、図６に示すように、シリコン基板１０１をエッチングすることで、第２のレジスト１０６の下方に、平面状シリコン層１０７を形成する。
　続いて、図７に示すように、第２のレジスト１０６を剥離、除去する。
　続いて、図８に示すように、平面状シリコン層１０７の周囲に、素子分離膜１０８を形成する。
　続いて、図９に示すように、第１の柱状シリコン層１０４と第２の柱状シリコン層１０５と平面状シリコン層１０７とを覆うように、第１の酸化膜１０９を堆積する。ここでは、第１の酸化膜１０９を常圧ＣＶＤ（化学気相堆積）を用いて堆積することが好ましい。このように、常圧ＣＶＤによって第１の酸化膜１０９を堆積すると、第１の柱状シリコン層１０４と第２の柱状シリコン層１０５及び平面状シリコン層１０７の上には、厚さの厚い第１の酸化膜１０９、柱状シリコン層１０４及び第２の柱状シリコン層１０５の側壁には、厚さの薄い第１の酸化膜１０９がそれぞれ堆積される。さらに、常圧ＣＶＤによれば、第１の柱状シリコン層１０４及び第２の柱状シリコン層１０５の上に堆積される第１の酸化膜１０９の厚さが、平面状シリコン層１０７上に堆積される第１の酸化膜１０９の厚さよりも厚くなる。
　続いて、図１０に示すように、第１の酸化膜１０９を等方性エッチングを用いて除去することによって、第１の柱状シリコン層１０４及び第２の柱状シリコン層１０５の上に酸化膜ハードマスク１１１、１１２を形成する。さらに、平面状シリコン層１０７上にゲート絶縁膜１１３、１１４（図１１参照）よりも厚さの厚い第２の酸化膜１１０を形成する。
　以上により、シリコン基板１０１（半導体基板）上に平面状シリコン層１０７（平面状半導体層）を形成し、この平面状シリコン層１０７上に、第１の柱状シリコン層１０４（第１の柱状半導体層）と、第２の柱状シリコン層１０５（第２の柱状半導体層）と、を形成する第１の工程が示された。
　次に、第１の柱状シリコン層１０４（第１の柱状半導体層）と第２の柱状シリコン層１０５（第２の柱状半導体層）の周囲にゲート絶縁膜１１３、１１４（図１１参照）を形成し、ゲート絶縁膜１１３、１１４の周囲に金属膜１１５及び厚さの薄いポリシリコン膜１１６を成膜する。ここで、ポリシリコン膜１１６の膜厚が第１の柱状シリコン層１０４（第１の柱状半導体層）と第２の柱状シリコン層１０５（第２の柱状半導体層）との間の間隔の半分の長さよりも薄くなるようにする。その後、ポリシリコン膜１１６上から第３のレジスト１１７を堆積し、第３のレジスト１１７から第１の柱状シリコン層１０４（第１の柱状半導体層）及び第２の柱状シリコン層１０５（第２の柱状半導体層）の上部側壁のポリシリコン膜１１６を露出させる。その後、第３のレジスト１１７から露出したポリシリコン膜１１６をエッチングにより除去し、第３のレジスト１１７を剥離し、金属膜１１５をエッチングにより除去する第２の工程を詳細に説明する。
　図１１に示すように、まず、第１の柱状シリコン層１０４と第２の柱状シリコン層１０５の周囲にゲート絶縁膜１１３、１１４を形成し、さらにゲート絶縁膜１１３、１１４の周囲に金属膜１１５及び厚さの薄いポリシリコン膜１１６を成膜する。薄いポリシリコンを使用するため、ポリシリコン膜１１６中にボイドが生じることが防止される。ここでは、金属膜１１５の材料に窒化チタンを使用するが、窒化チタンと同様に、半導体製造工程に用いられ、トランジスタのしきい値電圧を設定し得る金属であれば金属膜１１５の材料として使用できる。ゲート絶縁膜１１３、１１４は、例えば酸化膜、酸窒化膜、高誘電体膜などの、半導体工程に用いられるものが使用できる。
　続いて、図１２に示すように、第３のレジスト１１７を堆積し、第３のレジスト１１７から第１の柱状シリコン層１０４及び第２の柱状シリコン層１０５の上部側壁のポリシリコン膜１１６を露出させる。ここで、上部側壁のポリシリコン膜１１６を露出させるために、レジストエッチバックを用いることが好ましい。また、スピンオングラスといった塗布膜を用いて上部側壁のポリシリコン膜１１６を露出させてもよい。
　続いて、図１３に示すように、第３のレジスト１１７から露出したポリシリコン膜１１６をエッチングにより除去する。ここでは、等方性ドライエッチングを用いてポリシリコン膜１１６の除去することが好ましい。
　続いて、図１４に示すように、第３のレジスト１１７を除去する。
　続いて、図１５に示すように、金属膜１１５をエッチングにより除去する。ここで、第１及び第２の柱状シリコン層１０４、１０５の上方にある金属膜１１５をエッチングにより除去する際、ウエットエッチングを用いると、ポリシリコン膜１１６と柱状シリコン層１０４、１０５との間にある金属膜１１５がエッチングされてしまい、ポリシリコン膜１１６と柱状シリコン層１０４、１０５との間にボイドが生じることがある。
　以上により、第１の柱状シリコン層１０４（第１の柱状半導体層）と第２の柱状シリコン層１０５（第２の柱状半導体層）の周囲にゲート絶縁膜１１３、１１４を形成し、ゲート絶縁膜１１３、１１４の周囲に金属膜１１５及び厚さの薄いポリシリコン膜１１６を成膜する。ここで、ポリシリコン膜１１６の膜厚が第１の柱状シリコン層１０４（第１の柱状半導体層）と第２の柱状シリコン層１０５（第２の柱状半導体層）との間の間隔の半分の長さよりも薄くなるようにする。その後、ポリシリコン膜１１６上から第３のレジスト１１７を堆積し、第３のレジスト１１７から第１の柱状シリコン層１０４（第１の柱状半導体層）及び第２の柱状シリコン層１０５（第２の柱状半導体層）の上部側壁のポリシリコン膜１１６を露出させる。その後、第３のレジスト１１７から露出したポリシリコン膜１１６をエッチングにより除去し、第３のレジスト１１７を剥離し、金属膜１１５をエッチングにより除去する第２の工程が示された。
　次に、ゲート配線１１９ｃを形成するための第４のレジスト１１８を形成し、異方性エッチングを行うことにより、ゲート配線１１９ｃ、第１のゲート電極１１９ｂ、及び第２のゲート電極１１９ａを形成する第３の工程を詳細に説明する。
　続いて、図１６に示すように、まず、ゲート配線１１９ｃ（図１７参照）を形成するための第４のレジスト１１８を形成する。第４のレジスト１１８の上面の高さは、第２工程を終えた後のポリシリコン膜１１６の上面の高さよりも低くすることが好ましい。ゲート配線１１９ｃを形成する際、異方性エッチングを用いると、第１及び第２のゲート電極１１９ｂ、１１９ａ（図１７参照）の上方にあるポリシリコン膜１１６が除去されるため、金属膜１１５の上面の高さを、ポリシリコン膜１１６の上面の高さより高くすることができる。
　また、図１６に示す工程において、ゲート配線１１９ｃのための第４のレジスト１１８の中心線が、第１の柱状シリコン層１０４の中心点と第２の柱状シリコン層１０５の中心点とを結ぶ線に対して所定量オフセット（図１７参照）するように、第３のレジスト１１７を形成することが好ましい。このように所定量オフセットさせることで、第２のｎ型拡散層１２２と第２のｐ型拡散層１２５とを接続するシリサイド１３５（図２８参照）を形成することが容易になる。
　続いて、図１７に示すように、ポリシリコン膜１１６と金属膜１１５とをエッチングすることで、第１及び第２のゲート電極１１９ｂ、１１９ａ、ゲート配線１１９ｃが形成される。これにより、自己整合プロセスが実現される。本実施形態では、シリコン柱の周囲に形成されたゲート電極１１９ａ、１１９ｂに、ゲート配線１１９ｃの形成のための第４のレジスト１１８を接触させればよい。これによりゲート配線１１９ｃの位置合わせマージンが大きくなるので、自己整合プロセスが実現される。このとき、酸化膜ハードマスク１１１、１１２によって、第１の柱状シリコン層１０４、第２の柱状シリコン層１０５の上部が保護される。また、第１のゲート電極１１９ｂ及び第２のゲート電極１１９ａの上方にあるポリシリコン膜１１６が異方性エッチングにより除去されるため、金属膜１１５の上面の高さを、ポリシリコン膜１１６の上面の高さよりも高くすることができる。
　続いて、図１８に示すように、第２の酸化膜１１０をエッチングにより除去する。
　続いて、図１９に示すように、第４のレジスト１１８を剥離し、除去する。
　以上により、ゲート配線１１９ｃを形成するための第４のレジスト１１８を形成し、異方性エッチングを行うことにより、ゲート配線１１９ｃ、第１のゲート電極１１９ｂ、及び第２のゲート電極１１９ａを形成する第３の工程が示された。
　次に、第１の柱状シリコン層１０４（第１の柱状半導体層）の上部に第１のｎ型拡散層１２１を形成し、第１の柱状シリコン層１０４の下部及び平面状シリコン層１０７（平面状半導体層）の上部に第２のｎ型拡散層１２２を形成する。その後、第２の柱状シリコン層１０５（第２の柱状半導体層）の上部に第１のｐ型拡散層１２４を形成し、第２の柱状シリコン層１０５の下部及び平面状シリコン層１０７の上部に第２のｐ型拡散層１２５を形成する第４の工程を詳細に説明する。
　図２０に示すように、まず、第１のｎ型拡散層１２１及び第２のｎ型拡散層１２２を形成するために、第５のレジスト１２０を形成する。なお、第５のレジスト１２０を形成する前に、平面状シリコン層１０７の上表面などに、厚さの薄い酸化膜を堆積してもよい。
　続いて、図２１に示すように、第１の柱状シリコン層１０４の上部及び下部に、それぞれ砒素（Ａｓ）を注入することで、第１のｎ型拡散層１２１と第２のｎ型拡散層１２２を形成する。
　続いて、図２２に示すように、第５のレジスト１２０を剥離、除去する。
　続いて、図２３に示すように、第１のｐ型拡散層１２４と第２のｐ型拡散層１２５（図２４参照）とを形成するための第６のレジスト１２３を形成する。
　続いて、図２４に示すように、第２の柱状シリコン層１０５の上部及び下部に、それぞれボロンまたは弗化ボロンを注入することで、第１のｐ型拡散層１２４と第２のｐ型拡散層１２５とを形成する。
　続いて、図２５に示すように、第６のレジスト１２３を剥離、除去する。
　続いて、図２６に示すように、酸化膜１２６と窒化膜１２７とを層状かつ均一に堆積し、引き続き、熱処理を行う。
　以上により、第１の柱状シリコン層１０４（第１の柱状半導体層）の上部に第１のｎ型拡散層１２１を形成し、第１の柱状シリコン層１０４の下部及び平面状シリコン層１０７（平面状半導体層）の上部に第２のｎ型拡散層１２２を形成する。その後、第２の柱状シリコン層１０５（第２の柱状半導体層）の上部に第１のｐ型拡散層１２４を形成し、第２の柱状シリコン層１０５の下部及び平面状シリコン層１０７の上部に第２のｐ型拡散層１２５を形成する第４の工程が示された。
　次に、第１のｎ型拡散層１２１上、第２のｎ型拡散層１２２上、第１のｐ型拡散層１２４、第２のｐ型拡散層１２５上、及びゲート配線１１９ｃにシリサイド１３１、１３５、１３２、１３４、１３０、１３３を形成する第５の工程を詳細に説明する。
　図２７に示すように、まず、酸化膜１２６、窒化膜１２７をエッチングによってその一部を除去することで、絶縁膜サイドウォール１２８ａ、１２８ｂ、１２９ａ、１２９ｂ、１２９ｃを形成する。
　続いて、図２８に示すように、金属材料を堆積し、さらに熱処理を行い、未反応の金属材料を除去することで、第１のｎ型拡散層１２１上、第２のｎ型拡散層１２２上、第１のｐ型拡散層１２４上、第２のｐ型拡散層１２５上、及びゲート配線１１９ｃ上に、それぞれシリサイド１３１、１３５、１３２、１３４、１３０、１３３を形成する。ここで、絶縁膜サイドウォールは、窒化膜サイドウォールとすることができる。
　以上により、第２のｎ型拡散層１２２が、第２のｐ型拡散層１２５に、シリサイド１３５を介して接続される。また、図１７に示すように、ゲート配線１１９ｃの中心線が、第１の柱状シリコン層１０４の中心点と第２の柱状シリコン層１０５の中心点とを結ぶ線に対して所定量オフセットしているので、シリサイド１３５を形成することが容易になる。これにより、半導体装置の高集積化が実現される。
　また、この構造では、ポリシリコン膜１１６の厚さが薄いため、ゲート配線１１９ｃが、金属膜１１５及びシリサイド１３０からなる積層構造から容易に形成される。このゲート配線１１９ｃでは、シリサイド１３０と金属膜１１５とが直接接触するため、ゲート配線１１９ｃの低抵抗化が実現される。
　以上により、第１のｎ型拡散層１２１上、第２のｎ型拡散層１２２上、第１のｐ型拡散層１２４上、第２のｐ型拡散層１２５上、及びゲート配線１１９ｃ上にシリサイド１３１、１３５、１３２、１３４、１３０、１３３を形成する第５の工程が示された。
　第５の工程に続いて、図２９に示すように、窒化膜などのコンタクトストッパー１３６を、構造体の全体を覆うように層状に成膜し、層間絶縁膜１３７を形成する。
　続いて、図３０に示すように、コンタクト孔１３９、１４０（図３１参照）を形成するための第７のレジスト１３８を形成する。
　続いて、図３１に示すように、層間絶縁膜１３７をエッチングすることで、第７のレジスト１３８の開口部にコンタクト孔１３９、１４０を形成する。
　続いて、図３２に示すように、第７のレジスト１３８を剥離、除去する。
　続いて、図３３に示すように、コンタクト孔１４２、１４３（図３４参照）を形成するための第８のレジスト１４１を形成する。
　続いて、図３４に示すように、層間絶縁膜１３７をエッチングすることで、第８のレジスト１４１の開口部に、コンタクト孔１４２、１４３を形成する。
　続いて、図３５に示すように、第８のレジスト１４１を剥離、除去する。
　続いて、図３６に示すように、コンタクトストッパー１３６をエッチングすることで、コンタクト孔１３９、１４０、コンタクト孔１４２、１４３下のコンタクトストッパー１３６を除去する。
　続いて、図３７に示すように、金属材料を堆積して金属層１４８を形成することで、下層の導体層と接続するコンタクト１４４、１４５、１４６、１４７とする。
　続いて、図３８に示すように、金属配線１５３、１５４、１５５、１５６（図３９参照）を形成するための第９のレジスト１４９、１５０、１５１、１５２を形成する。
　続いて、図３９に示すように、金属層１４８をエッチングすることで、金属配線１５３、１５４、１５５、１５６を形成する。
　次に、図４０に示すように、第９のレジスト１４９、１５０、１５１、１５２を剥離、除去する。
　以上により、厚さの薄いゲート材料（ポリシリコン）を用いることで、自己整合プロセスによって、金属材料からなるゲート電極が形成されるＳＧＴの構造を有する半導体装置の製造方法が示された。
　金属膜１１５の上面の高さが、ポリシリコン膜１１６の上面の高さよりも高いため、ポリシリコン膜１１６と、第１及び第２の柱状シリコン層１０４、１０５との間にボイドが生じることがなく、ゲート電極１１９ａ、１１９ｂと、第１及び第２の柱状シリコン層１０４、１０５との間の容量の減少を防ぐことができる。
　本実施形態により製造される、ＳＧＴを有する半導体装置が、ゲート配線１１９ｃと平面状シリコン層１０７との間に形成されたゲート絶縁膜１１３、１１４よりも厚さが厚い第２の酸化膜１１０を有する。このため、ゲート配線１１９ｃとシリコン基板１０１との間の容量を低減することができ、ゲート配線１１９ｃとシリコン基板１０１間の絶縁性が確保される。
　本実施形態によれば、ゲート配線１１９ｃが、金属膜１１５及びシリサイド１３０からなる積層構造から形成される。このように、ゲート配線１１９ｃでは、シリサイド１３０と金属膜１１５とが直接接触するため、ゲート配線１１９ｃの低抵抗化が実現される。
　本実施形態によれば、ゲート配線１１９ｃの中心線が、第１の柱状シリコン層１０４の中心点と第２の柱状シリコン層１０５の中心点とを結ぶ線に対して所定量オフセットしている（図１７参照）。このため、第２のｎ型拡散層１２２と、第２のｐ型拡散層１２５とを接続するシリサイド１３５を容易に形成できる。これにより、量産ベースでの半導体装置の高集積化が実現される。
　上述した実施形態によれば、第１工程の後、第１の柱状シリコン層１０４（第１の柱状半導体層）と第２の柱状シリコン層１０５（第２の柱状半導体層）の周囲にゲート絶縁膜１１３、１１４を形成する。その後、ゲート絶縁膜１１３、１１４の周囲に金属膜１１５及び厚さの薄いポリシリコン膜１１６を成膜する。ポリシリコン膜１１６の膜厚は第１の柱状シリコン層１０４と第２の柱状シリコン層１０５との間の間隔の半分の長さよりも薄くする。その後、第３のレジスト１１７を堆積し、第１及び第２の柱状シリコン層１０４、１０５の上部側壁のポリシリコン膜１１６を露出させる。その後、露出したポリシリコン膜１１６をエッチングにより除去し、第３のレジスト１１７を剥離し、金属膜１１５をエッチングにより除去する第２の工程を備える。第２の工程の後、ゲート配線１１９ｃを形成するための第４のレジスト１１８を形成し、異方性エッチングを行い、ゲート配線１１９ｃ、第１のゲート電極１１９ｂ、及び第２のゲート電極１１９ａを形成する第３の工程により、自己整合プロセスが実現される。本実施形態によれば、このように自己整合プロセスによって半導体装置が製造されるため、別部材からなるマスクを使用する必要がなく、半導体装置の高集積化が実現される。
　第１及び第２の柱状シリコン層１０４、１０５の上方にある金属膜１１５をエッチングにより除去する際、ウエットエッチングを用いると、ポリシリコン膜１１６と第１及び第２の柱状シリコン層１０４、１０５との間にある金属膜１１５がエッチングされる。これにより、ポリシリコン膜１１６と、第１及び第２の柱状シリコン層１０４、１０５との間にボイドが生じることがある。このようにボイドが生じると、ボイドが生じた部分の比誘電率（媒質の誘電率と真空の誘電率の比ε/ε0=εr）が空気と同様の約１（1.00059）となるため、ゲート電極１１９ａ、１１９ｂと、第１及び第２の柱状シリコン層１０４、１０５との間の容量が減少してしまう。これに対して、本実施形態では、第１及び第２の柱状シリコン層１０４、１０５の上方にある金属膜１１５をエッチングにより除去した後、ゲート配線１１９ｃを異方性エッチングにより形成する。この際、第１及び第２のゲート電極１１９ｂ、１１９ａの上方にあるポリシリコン膜１１６が異方性エッチングにより除去されるため、金属膜１１５の上面の高さを、ポリシリコン膜１１６の上面の高さよりも高くすることができる。これにより、ポリシリコン膜１１６と、第１及び第２の柱状シリコン層１０４、１０５との間にボイドが生じることが防止される。
　なお、本発明は、本発明の広義の精神と範囲を逸脱することなく、様々な実施形態及び変形が可能とされるものである。また、上述した実施形態は、本発明の一実施例を説明するためのものであり、本発明の範囲を限定するものではない。上記実施例及び変形例は任意に組み合わせることができる。さらに、必要に応じて上記実施形態の構成の一部を除いても本発明の技術的思想の範囲内となる。
　例えば、上記実施例において、ｐ型（ｐ＋型を含む。）とｎ型（ｎ＋型を含む。）とをそれぞれ反対の導電型とした半導体装置の製造方法、及び、それにより得られる半導体装置も当然に本発明の技術的範囲に含まれる。
　本発明に係る半導体装置の製造方法によれば、ＳＧＴを有する、高集積度な半導体装置を製造することができる。
１０１．シリコン基板
１０２．第１のレジスト
１０３．第１のレジスト
１０４．第１の柱状シリコン層
１０５．第２の柱状シリコン層
１０６．第２のレジスト
１０７．平面状シリコン層
１０８．素子分離膜
１０９．第１の酸化膜
１１０．第２の酸化膜
１１１．酸化膜ハードマスク
１１２．酸化膜ハードマスク
１１３．ゲート絶縁膜
１１４．ゲート絶縁膜
１１５．金属膜
１１６．ポリシリコン膜
１１７．第３のレジスト
１１８．第４のレジスト
１１９ａ．第２のゲート電極
１１９ｂ．第１のゲート電極
１１９ｃ．ゲート配線
１２０．第５のレジスト
１２１．第１のｎ型拡散層
１２２．第２のｎ型拡散層
１２３．第６のレジスト
１２４．第１のｐ型拡散層
１２５．第２のｐ型拡散層
１２６．酸化膜
１２７．窒化膜
１２８ａ．絶縁膜サイドウォール
１２８ｂ．絶縁膜サイドウォール
１２９ａ．絶縁膜サイドウォール
１２９ｂ．絶縁膜サイドウォール
１２９ｃ．絶縁膜サイドウォール
１３０．シリサイド
１３１．シリサイド
１３２．シリサイド
１３３．シリサイド
１３４．シリサイド
１３５．シリサイド
１３６．コンタクトストッパー
１３７．層間絶縁膜
１３８．第７のレジスト
１３９．コンタクト孔
１４０．コンタクト孔
１４１．第８のレジスト
１４２．コンタクト孔
１４３．コンタクト孔
１４４．コンタクト
１４５．コンタクト
１４６．コンタクト
１４７．コンタクト
１４８．金属層
１４９．第９のレジスト
１５０．第９のレジスト
１５１．第９のレジスト
１５２．第９のレジスト
１５３．金属配線
１５４．金属配線
１５５．金属配線
１５６．金属配線

Claims (9)

  1. 　半導体基板上に平面状半導体層を形成し、前記平面状半導体層上に第１の柱状半導体層と第２の柱状半導体層とを形成する第１の工程と、
    　前記第１工程の後、
    　前記第１の柱状半導体層及び前記第２の柱状半導体層の周囲にゲート絶縁膜を形成し、
    　前記ゲート絶縁膜の周囲に金属膜及びポリシリコン膜を成膜し、
    　前記ポリシリコン膜の膜厚を前記第１の柱状半導体層及び前記第２の柱状半導体層の間の間隔の半分の長さよりも薄くし、
    　第３のレジストを堆積し、前記第１の柱状半導体層及び前記第２の柱状半導体層の上部側壁の前記ポリシリコン膜を露出させ、この露出した前記ポリシリコン膜をエッチングによって除去し、前記第３のレジストを剥離し、前記金属膜をエッチングにより除去する第２の工程と、
    　前記第２の工程の後、
    　ゲート配線を形成するための第４のレジストを形成し、異方性エッチングを行うことにより、ゲート配線と、第１のゲート電極と、第２のゲート電極と、を形成する第３の工程と、を有する、
    　ことを特徴とする半導体装置の製造方法。
  2. 　前記第１の工程の後、
    　前記第１の柱状シリコン層及び前記第２の柱状シリコン層の上に酸化膜ハードマスクを形成し、前記平面状シリコン層上にゲート絶縁膜よりも厚さの厚い酸化膜を形成する工程をさらに含む、ことを特徴とする請求項１に記載の半導体装置の製造方法。
  3. 　前記第４のレジストの上面の高さは、前記第２工程を経た後のポリシリコン膜の上面の高さよりも低い、ことを特徴とする請求項１に記載の半導体装置の製造方法。
  4. 　前記第１の柱状半導体層の上部に第１のｎ型拡散層を形成し、前記第１の柱状半導体層の下部及び前記平面状半導体層の上部に第２のｎ型拡散層を形成し、前記第２の柱状半導体層の上部に第１のｐ型拡散層を形成し、前記第２の柱状半導体層の下部及び前記平面状半導体層の上部に第２のｐ型拡散層を形成する第４の工程をさらに含む、ことを特徴とする請求項１に記載の半導体装置の製造方法。
  5. 　前記第１のｎ型拡散層上、前記第２のｎ型拡散層上、前記第１のｐ型拡散層上、前記第２のｐ型拡散層上、及び前記ゲート配線上にシリサイドを形成する第６の工程をさらに含む、ことを特徴とする請求項４に記載の半導体装置の製造方法。
  6. 　半導体基板上に形成された平面状半導体層と、
    　前記平面状半導体層上に形成された第１及び第２の柱状半導体層と、
    　前記第１の柱状半導体層の周囲に形成された第１のゲート絶縁膜と、
    　前記第１のゲート絶縁膜の周囲に形成された金属膜及びポリシリコン膜の積層構造からなる第１のゲート電極と、
    　前記第２の柱状半導体層の周囲に形成された第２のゲート絶縁膜と、
    　前記第２のゲート絶縁膜の周囲に形成された金属膜及びポリシリコン膜の積層構造からなる第２のゲート電極と、
    　前記第１及び前記第２のゲート電極に接続されたゲート配線と、
    　前記ゲート配線と前記平面状半導体層との間に形成された前記ゲート絶縁膜よりも厚さが厚い酸化膜と、
    　前記第１の柱状半導体層の上部に形成された第１のｎ型拡散層と、
    　前記第１の柱状半導体層の下部と前記平面状半導体層の上部とに形成された第２のｎ型拡散層と、
    　前記第２の柱状半導体層の上部に形成された第１のｐ型拡散層と、
    　前記第２の柱状半導体層の下部及び前記平面状半導体層の上部に形成された第２のｐ型拡散層と、を備え、
    　前記ポリシリコン膜の膜厚は前記第１の柱状半導体層と前記第２の柱状半導体層との間の間隔の半分の長さよりも薄く形成されており、
    　前記金属膜の上面の高さは、前記ポリシリコン膜の上面の高さよりも高くされており、
    　前記ゲート配線の上面の高さは前記第１及び第２のゲート電極の上面の高さよりも低くされている、ことを特徴とする半導体装置。
  7. 　前記ゲート配線は、前記金属膜及びシリサイドの積層構造からなる、ことを特徴とする請求項６に記載の半導体装置。
  8. 　前記ゲート配線の中心線が、前記第１の柱状半導体層の中心点と前記第２の柱状半導体層の中心点とを結ぶ線に対して所定量オフセットしている、ことを特徴とする請求項７に記載の半導体装置。
  9. 　前記第１及び前記第２のｎ型拡散層上と、前記第１及び前記第２のｐ型拡散層上とに形成されたシリサイドをさらに備える、ことを特徴とする請求項８に記載の半導体装置。
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