JP5685344B2 - 半導体装置の製造方法、及び、半導体装置 - Google Patents
半導体装置の製造方法、及び、半導体装置 Download PDFInfo
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- JP5685344B2 JP5685344B2 JP2014516126A JP2014516126A JP5685344B2 JP 5685344 B2 JP5685344 B2 JP 5685344B2 JP 2014516126 A JP2014516126 A JP 2014516126A JP 2014516126 A JP2014516126 A JP 2014516126A JP 5685344 B2 JP5685344 B2 JP 5685344B2
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- 239000004065 semiconductor Substances 0.000 title claims description 64
- 238000004519 manufacturing process Methods 0.000 title claims description 57
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 210
- 229910052710 silicon Inorganic materials 0.000 claims description 210
- 239000010703 silicon Substances 0.000 claims description 210
- 238000009792 diffusion process Methods 0.000 claims description 69
- 229910052751 metal Inorganic materials 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 40
- 229920005591 polysilicon Polymers 0.000 claims description 40
- 229910021332 silicide Inorganic materials 0.000 claims description 26
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 16
- 239000010410 layer Substances 0.000 description 218
- 150000004767 nitrides Chemical class 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 230000010354 integration Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Description
以上により、シリコン基板101上に平面状シリコン層107と、平面状シリコン層107上に、第1の柱状シリコン層104と第2の柱状シリコン層105と、を形成する第1の工程が示された。
102.第1のレジスト
103.第1のレジスト
104.第1の柱状シリコン層
105.第1の柱状シリコン層
106.第2のレジスト
107.平面状シリコン層
108.素子分離膜
109.酸化膜
110.第2の酸化膜
111.酸化膜ハードマスク
112.酸化膜ハードマスク
113.ゲート絶縁膜
114.ゲート絶縁膜
115.金属膜
116.ポリシリコン膜
117.第3のレジスト
118a.ゲート電極
118b.ゲート電極
118c.ゲート配線
119.第4のレジスト
120.第6のレジスト
121.第1のn型拡散層
122.第2のn型拡散層
123.第7のレジスト
124.第1のp型拡散層
125.第2のp型拡散層
126.窒化膜
127.シリサイド
128.シリサイド
129.シリサイド
130.シリサイド
131.シリサイド
132.シリサイド
133.シリサイド
134.シリサイド
137.コンタクトストッパー
138.層間絶縁膜
139.第8のレジスト
140.コンタクト孔
141.コンタクト孔
142.第9のレジスト
143.コンタクト孔
144.コンタクト孔
145.コンタクト
146.コンタクト
147.コンタクト
148.コンタクト
149.金属
150.第10のレジスト
151.第10のレジスト
152.第10のレジスト
153.第10のレジスト
154.金属配線
155.金属配線
156.金属配線
157.金属配線
160.酸化膜
161.第5のレジスト
Claims (4)
- シリコン基板に対してソース、ゲート、ドレインが垂直方向に柱状に配置され、ゲート電極が柱状半導体層を取り囲む構造の半導体装置の製造方法であって、
前記シリコン基板上に平面状シリコン層を形成し、前記平面状シリコン層上に第1の柱状シリコン層と第2の柱状シリコン層とを形成する第1の工程と、
前記第1の工程の後、前記第1の柱状シリコン層と前記第2の柱状シリコン層上に酸化膜ハードマスクを形成し、前記平面状シリコン層上にゲート絶縁膜より厚い第2の酸化膜を形成する第2の工程と、
前記第2工程の後、前記第1の柱状シリコン層と前記第2の柱状シリコン層の周囲にゲート絶縁膜を形成し、前記ゲート絶縁膜の周囲に金属膜及びポリシリコン膜を成膜し、ゲート配線を形成するための第3のレジストを形成し、異方性エッチングを行うことにより前記ゲート配線を形成する第3の工程と、ここで、前記ポリシリコン膜の膜厚は前記第1の柱状シリコン層と前記第2の柱状シリコン層との間の間隔の半分より薄く、
前記第3の工程の後、
第4のレジストを堆積し、前記第1の柱状シリコン層と前記第2の柱状シリコン層上部側壁の前記ポリシリコン膜を露出し、露出した前記ポリシリコン膜をエッチングにより除去し、前記第4のレジストを剥離し、前記金属膜をエッチングにより除去し、前記ゲート配線に接続する第1のゲート電極と第2のゲート電極を形成する第4の工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記第1の柱状シリコン層と前記第2の柱状シリコン層と前記平面状シリコン層上に厚い酸化膜を、前記柱状シリコン層と前記第2の柱状シリコン層の側壁に薄い酸化膜を堆積し、酸化膜を等方性エッチングにより除去することにより、前記第1の柱状シリコン層と前記第2の柱状シリコン層上に酸化膜ハードマスクを形成し、前記平面状シリコン層上にゲート絶縁膜より厚い第2の酸化膜を形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1の柱状シリコン層の上部に第1のn型拡散層を形成し、
前記第1の柱状シリコン層の下部と前記平面状シリコン層の上部に第2のn型拡散層を形成し、
前記第2の柱状シリコン層の上部に第1のp型拡散層を形成し、
前記第2の柱状シリコン層の下部と前記平面状シリコン層の上部に第2のp型拡散層を形成する第5の工程をさらに含むことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第1のn型拡散層上と前記第2のn型拡散層上と前記第1のp型拡散層と前記第2のp型拡散層上と前記ゲート配線にシリサイドを形成する第6の工程とをさらに含むことを特徴とする請求項3に記載の半導体装置の製造方法。
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PCT/JP2012/075072 WO2014049827A1 (ja) | 2012-09-28 | 2012-09-28 | 半導体装置の製造方法、及び、半導体装置 |
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JP2014249789A Division JP5928566B2 (ja) | 2014-12-10 | 2014-12-10 | 半導体装置の製造方法、及び、半導体装置 |
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JP5685344B2 true JP5685344B2 (ja) | 2015-03-18 |
JPWO2014049827A1 JPWO2014049827A1 (ja) | 2016-08-22 |
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JP (1) | JP5685344B2 (ja) |
SG (1) | SG11201500829PA (ja) |
TW (1) | TW201413873A (ja) |
WO (1) | WO2014049827A1 (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2009096002A1 (ja) * | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | 半導体装置の製造方法 |
JP2009182318A (ja) * | 2008-01-29 | 2009-08-13 | Unisantis Electronics Japan Ltd | 半導体装置およびその製造方法 |
JP2012004244A (ja) * | 2010-06-15 | 2012-01-05 | Unisantis Electronics Singapore Pte Ltd | 半導体装置及びその製造方法 |
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- 2012-09-28 SG SG11201500829PA patent/SG11201500829PA/en unknown
- 2012-09-28 WO PCT/JP2012/075072 patent/WO2014049827A1/ja active Application Filing
- 2012-09-28 JP JP2014516126A patent/JP5685344B2/ja active Active
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- 2013-09-25 TW TW102134419A patent/TW201413873A/zh unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2009096002A1 (ja) * | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | 半導体装置の製造方法 |
JP2009182318A (ja) * | 2008-01-29 | 2009-08-13 | Unisantis Electronics Japan Ltd | 半導体装置およびその製造方法 |
JP2012004244A (ja) * | 2010-06-15 | 2012-01-05 | Unisantis Electronics Singapore Pte Ltd | 半導体装置及びその製造方法 |
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Publication number | Publication date |
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TW201413873A (zh) | 2014-04-01 |
JPWO2014049827A1 (ja) | 2016-08-22 |
WO2014049827A1 (ja) | 2014-04-03 |
SG11201500829PA (en) | 2015-03-30 |
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