WO2014138317A1 - Monolithic three dimensional integration of semiconductor integrated circuits - Google Patents

Monolithic three dimensional integration of semiconductor integrated circuits Download PDF

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Publication number
WO2014138317A1
WO2014138317A1 PCT/US2014/020941 US2014020941W WO2014138317A1 WO 2014138317 A1 WO2014138317 A1 WO 2014138317A1 US 2014020941 W US2014020941 W US 2014020941W WO 2014138317 A1 WO2014138317 A1 WO 2014138317A1
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Prior art keywords
transistors
nanowire
semiconductor wafer
tier
transistor
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PCT/US2014/020941
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English (en)
French (fr)
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Yang Du
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Qualcomm Inc
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Qualcomm Inc
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Priority to CN201480011822.8A priority Critical patent/CN105027284B/zh
Priority to EP14715477.7A priority patent/EP2965359A1/en
Priority to JP2015561629A priority patent/JP6306063B2/ja
Priority to KR1020157027338A priority patent/KR20150130350A/ko
Publication of WO2014138317A1 publication Critical patent/WO2014138317A1/en
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    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
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    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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    • H10D88/00—Three-dimensional [3D] integrated devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y99/00—Subject matter not provided for in other groups of this subclass
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less

Definitions

  • the invention relates to microelectronic fabrication, and in particular relates to monolithic three-dimensional integration of semiconductor devices.
  • Embodiments of the invention are directed to systems and methods for three- dimensional integration of semiconductor integrated circuits.
  • a method includes implanting ions into a first semiconductor wafer to facilitate thermal cleavage, and oxide bonding the first semiconductor wafer to a second semiconductor wafer.
  • the first semiconductor wafer is heated to a temperature equal to or less than 450°C to cause thermal cleavage so as to leave a portion of the first semiconductor wafer oxide bonded to the second semiconductor wafer.
  • Sources and drains for a plurality of nanowire transistors in the portion of the first semiconductor wafer oxide bonded to the second semiconductor wafer are formed by doping in-situ during epitaxial growth at temperatures equal to or less than 450°C.
  • an apparatus in another embodiment, includes a silicon substrate; and a top tier oxide bonded to the silicon substrate, the top tier comprising a plurality of nanowire transistors, wherein each nanowire transistor in the plurality of nanowire transistors comprises a source, a drain, and a channel having a doping concentration less than that of the source and the drain.
  • an apparatus in another embodiment, includes a silicon substrate; a bottom tier formed on the silicon substrate, the bottom tier comprising a plurality of transistors; a top tier oxide bonded to the bottom tier, the top tier comprising a plurality of nanowire transistors, wherein each nanowire transistor in the plurality of nanowire transistors comprises a source, a drain, and a channel having a doping concentration less than that of the source and the drain; and a means for connecting, the means for connecting to connect at least one transistor in the plurality of transistors in the bottom tier to at least one nanowire transistor in the plurality of nanowire transistors in the top tier.
  • a method in another embodiment, includes a means for implanting ions, the means for implanting ions to facilitate a thermal cleavage in a first semiconductor wafer; a means for bonding, the means for bonding to oxide bond the first semiconductor wafer to a second semiconductor wafer, the second semiconductor wafer comprising a bottom tier of transistors; a means for heating, the means for heating to heat the first semiconductor wafer to a temperature equal to or less than 450°C to cause thermal cleavage so as to leave a portion of the first semiconductor wafer oxide bonded to the bottom tier; and a means for doping, the means for doping to dope in-situ during epitaxial growth at temperatures equal to or less than 450°C to form sources and drains for a plurality of nanowire transistors in the portion of the first semiconductor wafer oxide bonded to the bottom tier.
  • Figure 1 illustrates various types of nanowire transistors according to an embodiment.
  • Figures 2 A and 2B illustrate various structures and steps in a process flow according to an embodiment.
  • Figure 3 illustrates various steps in a process flow according to an embodiment.
  • Figure 4 illustrates a wireless communication system in which embodiments may find application.
  • Embodiments comprise one or more top active layers of nanowire transistors formed adjacent to a bottom layer of active CMOS (Complimentary Metal Oxide Semiconductor) devices.
  • a top layer may be referred to as a top tier
  • the bottom layer may be referred to as a bottom tier.
  • the bottom layer or tier is adjacent to the wafer substrate upon which it is formed, and is closest to the wafer substrate in relation to the top layers or tiers.
  • a nanowire transistor is a junction- less transistor.
  • a simplified perspective 100 is illustrated comprising a source-channel-drain region 102, a gate 104, and a dielectric 106 disposed between the gate 104 and the source-channel-drain region 102.
  • the dielectric 106 may be a High-K dielectric.
  • the structure is shown integrated on a dielectric film 108.
  • various types of nanowire transistors may be realized: a p-channel field pinched nanowire transistor 110, an n-channel field pinched nanowire transistor 112, an n-type inversion channel nanowire transistor 114, and a p-type inversion channel nanowire transistor 116.
  • the semiconductor material for each of these nanowire transistors may be Silicon (Si), and the gates may be metal or polysilicon.
  • the view indicated by the nanowire transistors 110, 112, 114, and 116 is a simplified cross-sectional view of the nanowire transistor 100.
  • the relationship among these views is indicated by noting that the coordinate system 118 refers to the orientation of the nanowire transistor 100, and the coordinate system 120 refers to the orientation of the nanowire transistors 110, 112, 114, and 116, so that the view of the latter nanowire transistors represents a slice in the y-z plane of the nanowire transistor 100.
  • the nanowire transistors 110 and 112 operate in the accumulation mode, and the nanowire transistors 114 and 116 operate in the inversion mode.
  • the channel 122 of the nanowire transistor 110 is a lightly doped (p+) p-type semiconductor, where a typical doping concentration may be about 10 18 cm ⁇ 3 . Other embodiments may have different doping concentrations, for example, doping concentrations that are less than 10 18 cm ⁇ 3 .
  • the source and drain regions 124 and 126 are highly doped (p++) p-type, where a typical doping concentration may be about 10 20 cm ⁇ 3 . Other embodiments may have different doping concentrations, for example, doping concentrations that are greater than 10 20 cm ⁇ 3 .
  • the channel 128 of the nanowire transistor 112 is lightly doped (n+) n-type, where a typical doping concentration may be about 10 18 cm ⁇ 3 . Other embodiments may have different doping concentrations, for example, doping concentrations that are less than 10 18 cm ⁇ 3 .
  • the source and drain regions 130 and 132 are highly doped (n++) n- type, where a typical doping concentration may be about 10 20 cm ⁇ 3 . Other embodiments may have different doping concentrations, for example, doping concentrations that are greater than 10 20 cm ⁇ 3 .
  • the channel 134 of nanowire transistor 114 is undoped (neutral, or zero donor concentration); and the source and drain regions 136 and 138 are highly doped (n++) n- type, where a typical doping concentration may be about 10 20 cm ⁇ 3 . Other embodiments may have different doping concentrations, for example, doping concentrations that are greater than 10 20 cm ⁇ 3 .
  • the channel 140 of nanowire transistor 116 is undoped; and the source and drain regions 142 and 144 are highly doped (p++) p- type, where a typical doping concentration may be about 10 20 cm ⁇ 3 . Other embodiments may have different doping concentrations, for example, doping concentrations that are greater than 10 20 cm ⁇ 3 .
  • FIGS 2A and 2B represent a process flow according to an embodiment.
  • a silicon wafer 202 is doped by the method of masked ion-implantation to form an active layer (top tier) comprising various n-type and p-type regions.
  • active layer top tier
  • Dielectric deposition or oxidation forms a thin oxide layer 208 above the active layer.
  • a high-temperature, thermal activation anneal is performed at about 1000°C.
  • the active layer comprising the n-type region 204 and the p-type region 206 will form part of the top tier 264 (see Figure 2B) in the final 3D integrated circuit. More precisely, a portion of the active layer comprising the regions 204 and 206 will form part of the top tier 264, as will be described later.
  • the n-type region 204 and p-type region 206 are lightly doped, for example at a donor concentration of about 10 18 cm ⁇ 3 . These regions will form the channels for the nanowire transistors in the top tier 264, as well as part of the sources and drains for these nanowire transistors.
  • step 210 ion implantation is performed to define a cleavage interface 212.
  • the interface 212 is within the active region comprising the regions 204 and 208.
  • the ions may be Hydrogen ions.
  • step 214 the wafer 202 is flipped and oxide bonded to the wafer 216.
  • the oxide bonding is performed at a relatively low temperature, for example at a temperature equal to or less than 400°C.
  • Step 214 does not actually show the wafer 202 bonded to the wafer 216, but in the bonding procedure, the oxide layer 208 in the wafer 202 is bonded to an oxide layer 218 in the wafer 216.
  • the wafer 216 serves as the substrate for the final 3D integrated circuit, and therefore will be referred to as the substrate 216.
  • CMOS active layer comprising pMOSFET (Metal-Oxide- Semiconductor-Field-Effect-Transistor) and nMOSFET devices, with a metal layer and vias making various electrical connections to the sources, drains, and gates of these CMOS devices.
  • CMOS devices 221 comprises source and drain regions 220 and 222, a channel 224, a gate 228, and a dielectric 226 disposed between the gate 228 and the channel 224.
  • CMOS integrated circuit formed on the substrate 216 are one or metal layers, for example the metal layer 230, and vias connecting the device terminals to the one or metal layers, for example the via 232.
  • the CMOS active layer on the substrate 216 is the bottom tier 233 in the final 3D integrated circuit.
  • the bonded wafers are heated to a relatively low temperature, for example equal to or less than 300°C, so that the wafers may be separated at the cleavage interface 212.
  • a thin film (the "portion" referred to previously) of the active layer comprising regions 204 and 206 that was formed on the wafer 202 now remains bonded to the oxide 208 on the substrate 216.
  • oxide isolation trenches are formed in the top tier active layer.
  • the four oxide isolation trenches 238, 240, 242, and 244 are illustrated in step 236.
  • the portion of the p-type region 206 remaining on the substrate 216 after thermal cleavage has been isolated into the p-type region 246 and the p-type region 248; and the portion of the remaining n-type region 204 has been isolated into the n-type region 250.
  • the portion of the active region originally formed on the wafer 202 and bonded to the oxide layer 208 is very thin, it is substantially transparent, and therefore it is practical to use optical alignment when aligning various masks used to form the oxide trenches illustrated in step 236, as well as the features formed in the remaining steps in the fabrication of the top tier.
  • step 252 gate dielectric and electrode deposition is performed, followed by gate definition and spacer formation. In-situ doping during epitaxial growth is performed for selective source and drain formation, at a temperature equal to or less than 450°C.
  • step 252 the p- channel field pinched nanowire transistor 110 is shown, with the source and drain regions 124 and 126, the gate 104, and the gate dielectric 106.
  • Step 252 includes various fabrication steps to finish the 3D integration, such as forming inter-tier vias, for example the inter-tier via 254; forming vias to the sources, drains, and gates of the nanowire transistors, for example the via 256; and one or more metal layers to form interconnects, for example the metal layers 258 and 260. Also formed is the oxide layer 262 encapsulating the metal layers and the nanowire transistors. The oxide layer 262 may also serve as a bonding surface for additional top tier layers, where the previously described steps are repeated.
  • step 200 is modified where the active layer in the wafer 202 that is to be part of the top tier in the final integrated circuit is undoped, or comprises various undoped regions.
  • Figure 3 outlines the process flow described above. Masked n-type and p-type ion implantation is performed on a first wafer to form n-type and p-type regions as part of the active layer in the top tier (302).
  • the n-type and p-type regions are lightly doped, and will be used to form sources, drains, and channels for the nanowire transistors. For some embodiments, there is no doping so that step 302 is not performed, or for some embodiments, some regions are undoped and other regions are lightly doped.
  • a dielectric or oxidation layer is formed over the active region (304), and a thermal activation and anneal (306) is performed at a high temperature to repair crystal damage due to the ion implantation. Hydrogen ion implantation is performed to define a cleavage interface (308), and the first wafer is oxide bonded to a second wafer at a low temperature.
  • the second wafer already has formed thereon an integrated CMOS circuit, where the CMOS active layer will be the bottom tier 233 of the 3D integrated circuit.
  • the second wafer serves as a substrate for the 3D integrated circuit.
  • the cleavage interface is thermally activated so that most of the first wafer material can be removed from the second wafer (312), leaving behind on the bottom tier 233 a thin active layer comprising a portion of the previously formed n-type and p-type regions that will make up the sources, drains, and channels of the nanowire transistors in the top tier.
  • Gate dielectrics and electrodes for the top tier nanowire transistors are fabricated (314).
  • Low temperature in-situ doping during epitaxial growth (316) is used to form the sources and drains for the top tier nanowire transistors.
  • the contacts, intra-tier vias, inter-tier vias, and various metal layers in the top tier are completed and are encapsulated by an oxide layer (318).
  • Figure 4 illustrates a wireless communication system in which embodiments may find application.
  • Figure 4 illustrates a wireless communication network 402 comprising base stations 404A, 404B, and 404C.
  • Figure 4 shows a communication device, labeled 406, which may be a mobile cellular communication device such as a so-called smart phone, a tablet, or some other kind of communication device suitable for a cellular phone network.
  • the communication device 406 need not be mobile.
  • the communication device 406 is located within the cell associated with the base station 404C.
  • Arrows 408 and 410 pictorially represent the uplink channel and the downlink channel, respectively, by which the communication device 406 communicates with the base station 404C.
  • Embodiments may be used in data processing systems associated with the communication device 406, or with the base station 404C, or both, for example.
  • Figure 4 illustrates only one application among many in which the embodiments described herein may be employed.
  • Structures made according to the described embodiments are expected to provide for 1) packing and connecting transistors in three dimension circuits without TSV (Through Silicon Via) area penalty or increased interconnect signal delay; 2) reducing average metal interconnect layers for each transistor tier, thereby reducing total interconnect RC delay (which is difficult to achieve with conventional TSV methods); 3) mitigating problems with wafer (die) bonding alignment, thereby allowing very accurate, high density via connections through the various tiers (semiconductor layers); 4) enabling many core distributed memory architectures that utilize thousands or even millions of vias (which cannot readily be achieved by conventional TSV wide I/O approaches); 5) three dimensional ICs and architectures with high performance elementary devices in each layer; and 6) reducing transistor integration cost by cutting down on metal layer usage, lowering defect density, increasing yield, and lowering testing cost.
  • the bottom tier layer comprises CMOS devices.
  • embodiments are not limited to a top tier of nanowire transistors formed over a bottom tier of CMOS devices.
  • the bottom tier may comprise other types of transistors, such as for example bipolar devices.
  • the nanowire transistors may be oxide bonded to a substrate, where the oxide used for bonding serves as an insulator.
  • a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
  • an embodiment of the invention can include a computer readable media embodying a method for sequential integration of transistors and IC components layer by layer over a single substrate within state of the art microfabrication environment. Accordingly, the invention is not limited to illustrated examples and any means for performing the functionality described herein are included in embodiments of the invention.

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CN105027284A (zh) 2015-11-04
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US20140252306A1 (en) 2014-09-11
TWI543336B (zh) 2016-07-21
EP2965359A1 (en) 2016-01-13
JP6306063B2 (ja) 2018-04-04
KR20150130350A (ko) 2015-11-23
CN105027284B (zh) 2017-12-05
JP2016517625A (ja) 2016-06-16

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