WO2014069559A1 - プラズマ処理方法及びプラズマ処理装置 - Google Patents
プラズマ処理方法及びプラズマ処理装置 Download PDFInfo
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- WO2014069559A1 WO2014069559A1 PCT/JP2013/079520 JP2013079520W WO2014069559A1 WO 2014069559 A1 WO2014069559 A1 WO 2014069559A1 JP 2013079520 W JP2013079520 W JP 2013079520W WO 2014069559 A1 WO2014069559 A1 WO 2014069559A1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
- H01J37/32568—Relative arrangement or disposition of electrodes; moving means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Definitions
- the present invention relates to a plasma processing method and a plasma processing apparatus for etching a multilayer film formed on a substrate to be processed using plasma.
- a three-dimensional stacked semiconductor memory such as a 3D-NAND flash memory includes a stacked film in which a number of different types of layers are alternately stacked (see, for example, Patent Document 1 below).
- a deep recess hole or trench
- plasma etching is used to form this deep recess.
- a plasma treatment for etching a multilayer film if etching is performed for each of the different types of layers constituting the multilayer film, the larger the number of layers, the greater the number of etchings and the lower the throughput. For this reason, a plasma film is etched using a processing gas containing all of the gases necessary for etching different types of layers, thereby forming recesses that penetrate through different types of layers in a single plasma etching. can do.
- a mask layer is formed on the laminated film, in which openings for forming recesses are patterned, and the laminated film is plasma-etched using the mask layer as a mask.
- the oxygen gas flow rate ratio is made smaller than other gases to increase the amount of CF polymer deposited (attached amount) and overetching. Then, the flow rate ratio of oxygen gas may be made larger than that of other gases to reduce the amount of CF polymer deposited.
- the bottom end (bottom) shape of the deep hole can be adjusted so as not to be tapered, but the underlying silicon layer is etched greatly. Loss occurs.
- the main etching time with a large amount of CF polymer deposited is lengthened, the bottom end (bottom) shape of the deep hole cannot be adjusted sufficiently even if the etching to the underlying silicon layer (underlying loss) can be suppressed. End up.
- the present invention has been made in view of such problems, and the object of the present invention is to reduce the substrate loss while enlarging the bottom (bottom) shape of the recess when plasma etching the multilayer film.
- An object of the present invention is to provide a plasma processing method that can be suppressed.
- a substrate to be processed is arranged in a processing chamber, and plasma of a processing gas is generated to pattern a multilayer film formed on the substrate to be processed.
- a plasma processing method in which plasma etching is performed using a mask layer formed as a mask, wherein the multilayer film is formed by alternately stacking first and second films having different relative dielectric constants formed on an underlying silicon film.
- First over-etching is performed by increasing the flow rate ratio of the oxygen gas to the carbon-based gas more than that of the main etching, and is performed by decreasing the flow rate ratio of the oxygen gas to the fluorocarbon-based gas than that of the first over-etching.
- a plasma processing method characterized by repeating 2 over-etching twice or more.
- the first over-etching with a small amount of CF-based polymer deposited and the second over-etching with a large amount of CF-based polymer deposited Can be performed twice or more times, so that the CF-based polymer functions as a protective film for the underlying silicon film and suppresses etching of the underlying silicon film while expanding the bottom end shape of the recess. it can. Thereby, a base
- the progress of the etching is suppressed when the underlying silicon film is exposed while the etching of the multilayer film remaining in the main etching is progressed. Can be suppressed.
- a plasma of a processing gas is generated in the processing chamber, whereby a multilayer film formed on a substrate to be processed is masked with a patterned mask layer.
- a plasma processing apparatus for performing plasma etching as follows: an upper electrode provided in the processing chamber; a first film having a relative dielectric constant different from that formed on the underlying silicon film; A lower electrode on which the substrate to be processed on which the multilayer film having a multilayer film in which second films are alternately stacked is disposed; a first high-frequency power source that applies high-frequency power for generating plasma to the lower electrode; A second high frequency power source for applying a bias high frequency power to the lower electrode, and a processing gas containing a fluorocarbon-based gas and an oxygen gas are introduced into the processing chamber to generate plasma; A control unit that performs a main etching step of forming a recess to a predetermined depth in the laminated film by performing a plasma etching, and
- the processing gas includes a hydrofluorocarbon-based gas
- the flow ratio of the hydrofluorocarbon-based gas in the processing gas is set to zero or less than that of the first over-etching. It may be.
- the processing gas may include one or both of the CF 4 gas and NF 3 gas.
- the number of repetitions of the first overetching and the second overetching is preferably 6 or more.
- the processing conditions for the second over-etching may be the same as the processing conditions for the main etching process.
- One of the first film and the second film constituting the laminated film is, for example, a silicon oxide film, and the other is, for example, a silicon nitride film.
- a multilayer film formed on the substrate to be processed is formed by arranging a substrate to be processed in a processing chamber and generating plasma of a processing gas.
- a plasma processing method in which plasma etching is performed using a patterned mask layer as a mask, wherein the multilayer film is a stacked film in which first films and second films having different relative dielectric constants formed on a base film are alternately stacked.
- Main etching for forming a recess in the laminated film to a predetermined depth by introducing a processing gas containing a first gas and a second gas into the processing chamber to generate plasma and performing plasma etching.
- a subsequent overetching step of forming a recess until the base film is exposed wherein the overetching step includes the step of the second gas with respect to the first gas.
- First over-etching performed by increasing a flow rate ratio relative to the main etching, and second over-etching performed by decreasing a flow rate ratio of the second gas to the first gas compared to the first over-etching.
- a plasma processing method which is repeated twice or more.
- the flow rate ratio of the first gas in the processing gas may be set to zero or may be reduced as compared with the first over-etching.
- a third gas may be included in the processing gas.
- the number of repetitions of the first overetching and the second overetching is preferably 6 or more.
- the processing conditions for the second over-etching may be the same as the processing conditions for the main etching process.
- the bottom loss (bottom part) of the concave portion can be enlarged and the substrate loss can be suppressed, and the variation thereof can also be suppressed.
- FIG. 2 is a cross-sectional view taken along the line AA shown in FIG.
- FIG. 2 is a cross-sectional view taken along line BB shown in FIG.
- FIG. 6 is a cross-sectional view conceptually showing a case where the overetching of the deposition process is performed only once on the multilayer film after the main etching shown in FIG. 5.
- FIG. 6 is a cross-sectional view conceptually showing the case where the first overetching of the deposition process and the second overetching of the deposition process are performed once for the multilayer film after the main etching shown in FIG. 5.
- FIG. 6 is a cross-sectional view conceptually showing a case where the first overetching of the deposition process and the second overetching of the deposition process are alternately repeated a plurality of times on the multilayer film after the main etching shown in FIG. 5. It is a flowchart which shows the outline of the etching process in the embodiment.
- 1 mTorr is (10 ⁇ 3 ⁇ 101325/760) Pa.
- FIG. 1 is a perspective view conceptually showing the structure of a 3D-NAND flash memory.
- FIG. 2A is a cross-sectional view taken along the line AA of the 3D-NAND flash memory shown in FIG. 2B is a cross-sectional view taken along the line BB of the 3D-NAND flash memory shown in FIG.
- the NAND flash memory shown in FIG. 1 is composed of, for example, a plurality of blocks each serving as a unit of erasure.
- FIG. 1 illustrates two blocks BK1 and BK2.
- the source diffusion layer DL is formed in the semiconductor substrate, and is provided in common for all blocks, for example.
- Source diffusion layer DL is connected to source line SL through contact plug PS.
- On the source diffusion layer DL for example, a multilayer film having a laminated film in which first films and second films having different relative dielectric constants are alternately laminated is formed.
- the multilayer film has a six-layer structure for the convenience of illustration, but may be a multilayer film exceeding several tens to hundred layers such as 36 layers and 128 layers, and more. Also good.
- the remaining five films excluding the uppermost layer are each formed in a plate shape in each of the blocks BK1 and BK2, and the end portions in the X direction are stepped to contact each film. Formed.
- the multilayer film has a substantially pyramid shape.
- the lowermost layer is the source line side select gate line SGS, and the remaining four films excluding the lowermost layer and the uppermost layer are the four word lines WL.
- the uppermost layer is composed of a plurality of linear conductive lines extending in the X direction. For example, six conductive lines are arranged in one block BK1. For example, six conductive lines in the uppermost layer become six bit line side select gate lines SGD.
- the plurality of active layers AC for constituting the NAND cell unit are formed in a columnar shape in the Z direction (perpendicular to the surface of the semiconductor substrate) so as to penetrate the plurality of films and reach the source diffusion layer DL.
- the upper ends of the plurality of active layers AC are connected to a plurality of bit lines BL extending in the Y direction.
- the source line side select gate line SGS is connected to a lead line SGS1 extending in the X direction via a contact plug PSG, and the word lines WL are respectively connected to lead lines W1 to W extending in the X direction via contact plugs PW1 to PW4. Connected to W4.
- bit line side select gate line SGD is connected to a lead line SGD1 extending in the X direction via a contact plug PSD.
- the plurality of bit lines BL and lead lines SGS1, lead lines W1 to W4 are made of, for example, metal.
- the source line side select gate line SGS and the word lines WL1 to WL4 are illustrated from the lead line SGS1 and lead lines W1 to W4 extending in the X direction via the contact plug PSG and the contact plugs PW1 to PW4. Not connected to the transistor constituting the driver.
- the plurality of active layers AC pass through the plurality of films SGD, WL4, WL3, WL2, WL1, and SGS to reach the source diffusion layer DL (with respect to the surface of the semiconductor substrate). In the vertical direction).
- the deep hole is formed by forming a patterned mask layer on the laminated film and performing plasma etching using the patterned mask layer as a mask.
- the processing conditions gas type, gas flow ratio, high-frequency power, etc.
- the etching shape can be improved.
- FIG. 3 is a longitudinal sectional view showing a schematic configuration of the plasma processing apparatus 100 according to the present embodiment.
- the plasma processing apparatus 100 has a cylindrical processing chamber (chamber) 110 made of, for example, aluminum whose surface is anodized (anodized).
- the housing of the processing chamber 110 is grounded.
- a mounting table 112 for mounting a semiconductor wafer (hereinafter referred to as “wafer”) W as a substrate to be processed is provided.
- the mounting table 112 is made of aluminum, for example, and is supported by a cylindrical support portion 116 that extends vertically upward from the bottom of the processing chamber 110 via an insulating cylindrical holding portion 114.
- a focus ring 118 made of, for example, silicon is disposed on the upper surface of the mounting table 112 and on the peripheral edge of the electrostatic chuck 140 in order to improve the in-plane uniformity of etching.
- An exhaust passage 120 is formed between the sidewall of the processing chamber 110 and the cylindrical support portion 116.
- An annular baffle plate 122 is attached to the exhaust path 120.
- An exhaust port 124 is provided at the bottom of the exhaust path 120, and the exhaust port 124 is connected to the exhaust unit 128 via an exhaust pipe 126.
- the exhaust unit 128 has a vacuum pump (not shown), and depressurizes the processing space in the processing chamber 110 to a predetermined degree of vacuum.
- a transfer gate valve 130 for opening and closing the loading / unloading port for the wafer W is attached to the side wall of the processing chamber 110.
- a first high-frequency power source 131 for plasma generation and a second high-frequency power source 132 for ion attraction (bias) in plasma are electrically connected to the mounting table 112 via a matching unit 133 and a matching unit 134, respectively. Yes.
- the first high frequency power supply 131 applies a frequency suitable for generating plasma in the processing chamber 110, for example, a first high frequency power of 40 MHz to the mounting table 112.
- the second high frequency power supply 132 applies a low frequency suitable for drawing ions in the plasma to the wafer W on the mounting table 112, for example, a second high frequency power of 3.2 MHz as a bias to the mounting table 112.
- the mounting table 112 also functions as a lower electrode.
- a shower head 138 which will be described later, is provided on the ceiling of the processing chamber 110 as an upper electrode having a ground potential. As a result, high frequency power from the first high frequency power supply 131 is capacitively applied between the mounting table 112 and the shower head 138.
- an electrostatic chuck 140 for holding the wafer W with electrostatic attraction is provided on the upper surface of the mounting table 112.
- the electrostatic chuck 140 is obtained by sandwiching an electrode 140a made of a conductive film between a pair of films.
- a DC voltage source 142 is electrically connected to the electrode 140a via a switch 143.
- the electrostatic chuck 140 attracts and holds the wafer W on the electrostatic chuck with a Coulomb force by the voltage from the DC voltage source 142.
- a heat transfer gas such as He gas is supplied by a heat transfer gas supply unit 152 via a gas supply line 154.
- the shower head 138 on the ceiling of the processing chamber 110 includes an electrode plate 156 having a large number of gas ventilation holes 156a and an electrode support 158 that supports the electrode plate 156 in a detachable manner.
- a buffer chamber 160 is provided inside the electrode support 158, and a processing gas supply unit 162 is connected to a gas inlet 160 a of the buffer chamber 160 via a gas supply pipe 164.
- the processing gas from the processing gas supply unit 162 is introduced into the buffer chamber 160 from the gas inlet 160a via the gas supply pipe 164 and diffused, and is jetted into the processing chamber 110 from the numerous gas vent holes 156a.
- a cooling mechanism is provided inside the mounting table 112. This cooling mechanism is configured to circulate and supply a refrigerant (for example, cooling water) at a predetermined temperature from the chiller unit 184 to the refrigerant pipe 182 provided in the mounting table 112 via pipes 186 and 188, for example.
- a heater 190 is provided below the electrostatic chuck 140.
- a desired AC voltage is applied to the heater 190 from an AC power source 192. With this configuration, the wafer W can be adjusted to a desired temperature by cooling by the chiller unit 184 and heating by the heater 190. These temperature controls are performed based on commands from the control unit 200.
- the control unit 200 includes various units provided in the plasma processing apparatus 100 such as the exhaust unit 128, the AC power supply 144, the DC voltage source 142, the electrostatic chuck switch 143, the first high frequency power supply 131, and the second high frequency power supply 132. , Matching units 133 and 134, heat transfer gas supply unit 152, process gas supply unit 162, chiller unit 184, and the like.
- the control unit 200 is connected to a host computer (not shown).
- the control unit 200 is connected to an operation unit 210 including a keyboard for performing command input operations and the like for management by the operator, and a display for visualizing and displaying the operation status.
- the control unit 200 is connected to a storage unit 220 in which a program for executing an etching process for the wafer W and processing conditions (recipe) necessary for executing the program are stored.
- This processing condition is a summary of multiple parameter values such as control parameters and setting parameters for controlling each part.
- the processing conditions include parameter values such as a processing gas flow rate ratio, processing chamber pressure, and high-frequency power.
- control unit 200 may be realized by operating using software, may be realized by operating using hardware, and further using both software and hardware. May be realized.
- the gate valve 130 is first opened and the wafer W held on the transfer arm is loaded into the processing chamber 110.
- the wafer W is held by lift pins (lifter pins) (not shown), and is placed on the electrostatic chuck 140 when the lift pins are lowered.
- the gate valve 130 is closed, a processing gas is introduced from the processing gas supply unit 162 into the processing chamber 110 at a predetermined flow rate and flow rate ratio, and the pressure in the processing chamber 110 is set to a set value by the exhaust unit 128. Depressurize to.
- high-frequency power with a predetermined power for plasma generation is supplied from the first high-frequency power source 131 to the mounting table 112, and high-frequency power with a predetermined power for bias is superimposed on the mounting table 112 from the second high-frequency power source 132.
- a voltage is applied from the DC voltage source 142 to the electrode 140a of the electrostatic chuck 140 to fix the wafer W on the electrostatic chuck 140, and from the heat transfer gas supply unit 152 to the upper surface of the electrostatic chuck 140 and the wafer W. He gas is supplied as a heat transfer gas between the back surface.
- the processing gas when the processing gas is introduced from the shower head 138, the processing gas is turned into plasma by supplying high frequency power from the first high frequency power supply 131 to the shower head 138.
- plasma is generated in the plasma generation space between the upper electrode (shower head 138) and the lower electrode (mounting table 112), and the multilayer film formed on the surface of the wafer W is etched by the plasma.
- ions in the plasma can be drawn toward the wafer W.
- the wafer W is lifted by lift pins (not shown), is detached from the mounting table 112, and the gate valve 130 is opened.
- the wafer W held by the lift pins is unloaded by a transfer arm (not shown) inserted from the gate valve 130.
- the next wafer W is carried into the processing chamber 110 by the transfer arm, and the wafer W is etched. By repeating such processing, a plurality of wafers W are successively processed.
- FIG. 4 is a cross-sectional view showing a film structure of a multilayer film as an etching target film.
- the film structure shown in FIG. 4 has a multilayer film 320 formed on the underlying silicon film 310 and a mask layer 330 formed on the multilayer film.
- the multilayer film 320 includes a stacked film 340 in which a large number of two different types of films (first film 342 and second film 344) are alternately stacked, and an etching stop film 350 therebelow.
- the etching stop film 350 is, for example, a silicon oxide film (SiO 2 film).
- the number of laminated films 340 is 36, for example. Note that the number of stacked layers 340 is not limited to this, and may be several tens of layers or more than one hundred layers 340.
- the first film 342 and the second film 344 constituting the laminated film 340 are films having different relative dielectric constants. As films having different relative dielectric constants, in this embodiment, the first film 342 is a silicon oxide film (SiO 2 film) and the second film 344 is a silicon nitride film (SiN film).
- membrane 344 is not restricted to this.
- the films constituting the first film 342 and the second film 344 may be reversed. That is, the second film 344 may be a silicon oxide film, and the first film 342 may be a silicon nitride film.
- the combination of the types of the films constituting the first film 342 and the second film 344 is not limited to the combination of the silicon oxide film and the silicon nitride film, and other types of films may be combined.
- a combination of a silicon oxide film (SiO 2 film) and a polysilicon film may be used.
- the polysilicon film may be doped with impurities or may not be doped.
- the relative permittivity of the polysilicon film can be made different depending on the presence or absence of such impurity doping. Therefore, the combination of the first film 342 and the second film 344 is changed to a polysilicon film (no doping) and a polysilicon ( (Impurity doping) may be combined. Examples of the impurity doped into the polysilicon film include boron.
- the mask layer 330 is composed of an amorphous carbon film in which a plurality of openings for forming a plurality of recesses in the multilayer film 320 are patterned.
- the amorphous carbon film used as the mask layer 330 may be of a type containing boron or a type containing no boron.
- the material of the mask layer 330 is not limited to the amorphous carbon film, but may be other organic films.
- the mask layer 330 may be a polysilicon film or the like.
- a fluorocarbon gas such as C 4 F 8 gas and C 4 F 6 gas is used as the first gas.
- Plasma etching is performed using a processing gas containing oxygen gas (O 2 gas) as the second gas.
- O 2 gas oxygen gas
- plasma etching is performed while adjusting the amount of CF-based polymer deposited in the recesses, divided into a main etching process ME for etching partway through the etching stop film 350 and an overetching process OE for etching the underlying silicon film. Etching is performed.
- etching is performed while increasing the amount of CF polymer deposited, so that the recesses are mainly dug in the depth direction while suppressing the opening width from being greatly widened.
- etching is performed while reducing the amount of CF polymer deposited, thereby widening the opening width (bottom CD value) at the bottom and adjusting the etching shape.
- the amount of CF polymer deposited can be adjusted by adjusting the flow rate of oxygen gas relative to the flow rate of fluorocarbon gas, for example. That is, if the flow rate of the oxygen gas with respect to the flow rate of the fluorocarbon-based gas is decreased, the amount of CF-based polymer deposited increases, and if the flow rate of the oxygen gas with respect to the flow rate of the fluorocarbon-based gas is increased, the deposited amount of CF-based polymer decreases. Therefore, in the over-etching process OE, the opening width (bottom CD value) at the bottom is reduced by increasing the flow rate of oxygen gas relative to the flow rate of the fluorocarbon-based gas and suppressing the amount of CF-based polymer deposition in the over-etching process ME. Can be spread.
- the amount of CF-based polymer deposited is small, so that the longer the etching time of the over-etching process OE, the more the base silicon film 310 is etched and the base loss increases. There is.
- the adjustment of the bottom CD value and the suppression of the base loss are a trade-off, and the base loss is reduced while the bottom CD value is sufficiently adjusted only by adjusting the time of the main etching process ME and the over etching process OE. There are limits to suppression.
- the present inventors conducted various experiments, and in the overetching process OE, plasma etching (depotless process) with a small amount of CF polymer deposition and plasma etching (deposition) with a large amount of CF polymer deposition were performed. It has been found that the substrate loss can be suppressed while sufficiently adjusting the bottom CD value.
- the CF polymer deposition amount can be adjusted, for example, by changing the oxygen gas flow rate ratio relative to the CF gas flow rate. Specifically, plasma etching (depot process) with a small CF polymer deposition amount increases the oxygen gas flow rate ratio relative to the CF gas flow rate, and plasma etching (depot process) with a large CF polymer deposition amount is , Reduce the ratio of the oxygen gas flow rate to the CF gas flow rate.
- FIG. 5 is a cross-sectional view conceptually showing the case where the main etching step ME is performed by plasma etching the multilayer film 320 shown in FIG. 4 to a predetermined depth (here, the etching stop film 350).
- FIGS. 6A to 6C are cross-sectional views conceptually showing a case where another over-etching process OE is performed after the main etching process shown in FIG.
- FIG. 6A shows a case where plasma etching (depotless process) with an increased oxygen gas flow ratio is performed only once as overetching OE.
- FIG. 6B shows a case where plasma etching (depotless process) with an increased oxygen gas flow ratio and plasma etching (depot process) with a reduced oxygen gas flow ratio are performed one by one as overetching OE.
- FIG. 6C is a cross-sectional view conceptually showing the case where these plasma etchings are alternately repeated twice or more.
- the bottom CD value is sufficiently adjusted as in the case of performing only the deposition process (FIG. 6A). It was found that the base loss can be reduced as compared with the case where only the less process is performed (FIG. 6A).
- the etching of the etching stop film (here, the silicon oxide film) 350 can proceed in both the deposition process and the deposition process, whereas the etching of the underlying silicon film 310 can be suppressed in the deposition process. it is conceivable that.
- the etching of the etching stop film (silicon oxide film) 350 proceeds while the bottom CD value (hole diameter and groove width) is increased by the deposition process.
- the underlying silicon film 310 is exposed, etching does not proceed in the deposition process. Accordingly, by performing the deposition process after the deposition process, it is possible to suppress the substrate loss while sufficiently adjusting the bottom CD value as shown in FIG. 6B.
- the etching of the etching stop film (silicon oxide film) 350 proceeds, whereas the etching is performed when the underlying silicon film 310 is exposed.
- the progress of is suppressed.
- the variation in the depth of the recess is gradually reduced by alternately repeating the deposition process and the deposition process as the overetching process OE. Therefore, as shown in FIG. 6C, variations in the base loss can be suppressed.
- the bottom loss is suppressed while sufficiently adjusting the bottom CD value. Variations can also be suppressed.
- FIG. 7 is a flowchart showing an outline of the plasma etching process executed by the control unit.
- a plasma etching process for forming a deep hole penetrating the multilayer film is taken as an example.
- a plasma etching process is performed on the wafer W on which the multilayer film 320 as shown in FIG. 8A is formed.
- a first film 342 and a second film 344 are alternately stacked on an underlying silicon film 310 through an etching stop film (here, a silicon oxide film) 350.
- etching stop film here, a silicon oxide film
- a laminated film 340 and a mask layer 330 formed on the laminated film 340 and patterned with openings are formed.
- a main etching step ME is performed in which a hole is dug to a predetermined depth (here, in the middle of the etching stop film 350) while suppressing the expansion of the hole diameter in step S110.
- a predetermined depth here, in the middle of the etching stop film 350
- an over-etching step OE is performed in which the bottom CD value at the bottom of the hole is increased and the shape of the bottom is adjusted while suppressing etching of the underlying silicon film.
- FIGS. 8B to 8D conceptually show cross-sectional views of the respective steps concerning the plasma etching process of the multilayer film according to the present embodiment.
- FIG. 8B shows a state after the main etching step ME.
- FIG. 8C shows a state in the middle of the overetching process OE, and
- FIG. 8D shows a state after the overetching process OE.
- the main etching is performed up to a predetermined depth of the multilayer film 320 shown in FIG. 8A using the mask layer 330 as an etching mask, here, halfway through the etching stop film 350 as shown in FIG. 8B. I do.
- the ratio of the oxygen gas flow rate to the CF gas flow rate is preferably 0.2 to 0.5.
- C 4 F 8 gas and C 4 F 6 gas as the CF-based gas for etching the first film 342 and the second film 344, oxygen gas (O 2 gas), Plasma etching is performed using a processing gas containing.
- the processing gas may contain Ar gas, for example, may contain hydrofluoro-based carbon gas (CHF-based gas) such as CH 2 F 2 gas.
- C 4 F 8 gas and C 4 F 6 gas are used as the CF-based gas for etching the first film (silicon oxide film) 342 and the second film (silicon nitride film) 344
- CF gas fluorocarbon gas
- the multilayer film 320 is etched to a predetermined depth by one main etching is described as an example, but the present invention is not limited to this, and the main film is changed twice or more by changing the gas type and gas flow rate.
- the multilayer film 320 may be etched to a predetermined depth by executing etching. In this case, the number of times of the main etching may be increased as the depth of the hole formed in the laminated film is deeper.
- C 4 F 8 gas, C 4 F 6 gas, and oxygen gas (CF gas) as CF-based gases for etching the first film 342 and the second film 344 are used.
- Plasma etching is performed using a processing gas including O 2 gas.
- the processing gas may include Ar gas, or may include CHF-based gas (for example, CH 2 F 2 gas).
- the amount of CF polymer deposited in the first over-etching, can be reduced by increasing the oxygen gas flow rate relative to the CF-based gas flow rate compared to the main etching, and in the second over-etching, the oxygen gas flow rate relative to the CF-based gas flow rate.
- the amount of CF polymer deposited can be increased by reducing the amount of the first overetching.
- the oxygen gas flow rate ratio relative to the CF gas flow rate in the first overetching is preferably 0.6 to 0.9
- the oxygen gas flow rate ratio relative to the CF gas flow rate in the second overetching is 0.00. It is preferably 2 to 0.5.
- step S140 After executing the first overetching in step S120 and the second overetching in step S130, it is determined in step S140 whether the predetermined number of repetitions has been reached. At this time, if the predetermined number of repetitions has not yet been reached, the process returns to step S120, and the first overetching in step S120 and the second overetching in step S130 are alternately repeated until the predetermined number of repetitions is reached.
- the process returns to step S120, and the first overetching in step S120 and the second overetching in step S130 are alternately repeated until the predetermined number of repetitions is reached.
- the hole depth is uniformly adjusted, and the variation in the base loss is corrected.
- a series of plasma etching processes are terminated. This completes the etching for all holes as shown in FIG. 8D.
- the bottom CD value is increased.
- Substrate loss can be suppressed and variations thereof can also be suppressed.
- the effect of suppressing the base loss can be further increased by reducing or reducing the flow rate of the CHF gas in the second over-etching.
- the base silicon film 310 is easily etched when hydrogen atoms (H) are contained in the processing gas, but the etching suppression effect of the base silicon film 310 can be enhanced by reducing the hydrogen atoms (H). It is.
- CF 4 gas or NF 3 gas may be added as a third gas to the processing gas. Since CF 4 gas and NF 3 gas are easily etched in the lateral direction, the effect of increasing the bottom CD value can be enhanced. Further, since oxygen atoms (O) can be reduced by adding CF 4 gas or NF 3 gas to the processing gas, the deposition of CF polymer is similar to the case of further reducing oxygen gas (O 2 gas). There is an effect to increase the amount. For this reason, the suppression effect of a base
- the 1st, 2nd overetching at least 2 times or more, and it is more preferable to repeat 6 times or more.
- the number of repetitions can also be determined by variations in hole depth after main etching. For example, as the variation in the hole depth after the main etching increases, the variation in the base loss can be suppressed by increasing the number of repetitions of the first and second over-etching.
- the overetching process OE in the overetching process OE, the case where the first overetching and the second overetching are alternately repeated a predetermined number of times in the order after the main etching process ME has been described as an example. It is not limited. For example, after the main etching process ME, the first overetching may be performed, and then the second overetching and the first overetching may be alternately repeated a predetermined number of times. Further, the processing conditions for the second over-etching may be the same as the processing conditions for the deposition process of the main etching process ME.
- the second high frequency power for bias may be pulse-modulated and applied in a pulse shape.
- the bottom CD value can be further increased.
- the positive charge charged at the bottom of the hole during the application of the second high-frequency power is It is discharged from the bottom of the hole while high frequency power is not applied.
- positive charges accumulated at the bottom of the hole can be reduced by applying high frequency power in a pulsed manner.
- repulsion between positive charges and ions is suppressed, so that positive ions can be easily implanted into the bottom of the hole.
- the etching of the hole bottom is promoted, and the effect of widening the bottom CD value can be enhanced.
- FIG. 9A and 9B are scanning electron microscopes each showing a bottom section of a recess (here, a hole) formed by performing an etching process according to the first experiment on the laminated film 340 as shown in FIG. 8A.
- FIG. 2 is a diagram illustrating a trace of a scanning electron microscope (SEM) photograph.
- SEM scanning electron microscope
- FIG. 9A shows the experimental results of a comparative example in which plasma etching of the deposition process is performed only once as the overetching process OE after the main etching process ME.
- FIG. 9B shows the experimental results of this embodiment in which the first over-etching of the deposition process and the second over-etching of the deposition process were repeated a plurality of times as the over-etching process after the same main etching process ME.
- one over etching is performed as the over etching process OE.
- the first main etching is performed to about 90% of the laminated film 340 under the following processing conditions 1-1, and then the second main etching is performed for 215 seconds under the following processing conditions 1-2.
- the overetching step OE the first overetching was performed only once for 200 seconds under the following processing conditions 1-3.
- FIG. 9B after performing the main etching twice as the main etching step ME in the same manner as FIG. 9A, the first over-etching of the deposition process and the second over-etching of the deposition process are performed as the over-etching step OE. This was repeated six times within the same time as the etching step OE.
- the first main etching is performed to about 90% of the laminated film 340 under the following processing conditions 1-1, and then the second main etching is performed under the following processing conditions 1-2. Is performed for 215 seconds, and as a subsequent over-etching process OE, the first over-etching is performed under the following processing conditions 1-3 of the depositionless process, and the following processing conditions 1-4 in which the deposition process is performed by reducing the oxygen gas flow rate.
- the second over-etching performed was repeated 6 times alternately.
- the oxygen gas flow rate is reduced, and C 4 F 8 gas is further deposited on the CF polymer.
- the amount of CF polymer deposited can be increased by adding NF 3 gas instead of easy CF 4 gas.
- the time for one time of the first and second over-etching is set to 23 seconds and 10 seconds, respectively, so that the total time of the over-etching process OE is approximately 200 seconds as in the case of FIG. 9A.
- Second main etching Processing chamber pressure 15 to 30 mTorr
- First high frequency power frequency / power 40 MHz / 700-1500 W
- Frequency / power of second high frequency power 3.2 MHz / 5000 to 7000 W
- the depth of the hole in the underlying silicon film 310 is smaller in the case according to the present embodiment (FIG. 9B) than in the case according to the comparative example (FIG. 9A).
- the depth of each hole is almost the same, and variation in the base loss is suppressed.
- the etching amount of the underlying silicon film 310 was measured, the first overetching was alternately performed while the first overetching was alternately performed while the first overetching was 120 nm in the comparative example (FIG. 9A).
- FIG. 9B In the case of this embodiment repeated several times (FIG. 9B), it is 47 nm, and it can be seen that the base loss is also greatly reduced.
- the hole diameter of the bottom is increased in substantially the same manner.
- 10A and 10B are scanning electron microscopes each showing a bottom section of a recess (here, a hole) formed by performing an etching process according to the first experiment on the laminated film 340 as shown in FIG. 8A. The trace of a SEM photograph is illustrated.
- FIG. 10A shows an experimental result of a comparative example in which plasma etching of a deposition process is performed only once as an overetching process OE after the main etching process ME.
- FIG. 10B shows the experimental results of the present embodiment in which the first overetching of the deposition process and the second overetching of the deposition process were repeated a plurality of times as the overetching process after the same main etching process ME.
- one main etching was performed as the main etching process ME, and then one over etching was performed as the over etching process OE.
- the main etching process ME after the main etching is performed until the etching stop film 350 is reached under the following processing condition 2-1, in the subsequent overetching process OE, the first overetching is performed under the following processing condition 2-2. Only 180 seconds.
- FIG. 10B after the main etching is performed once as the main etching step ME in the same manner as in FIG. 10A, the first overetching of the deposition process and the second overetching of the deposition process are performed as the overetching step OE. This was repeated nine times within the same time as the etching step OE.
- the first main etching is performed until the etching stop film 350 is reached under the following processing conditions 2-1, and the following processing conditions of the deposition process are performed as the subsequent overetching step OE.
- the second over-etching process condition 2-3 has a lower oxygen gas flow rate and zero CHF gas (CH 2 F 2 / CHF 3 ) than the first over-etching process condition 2-2.
- CH 2 F 2 / CHF 3 ratio is preferably 0 to 10, more preferably 0 to 7.
- the time for one time of the first and second over-etching is set to 10 seconds so that the total time of the over-etching process OE becomes 180 seconds as in the case of FIG. 10A.
- Processing chamber pressure 35 to 70 mTorr Frequency / power of first high frequency power: 40 MHz / 600 to 1400 W Frequency / power of second high frequency power: 3.2 MHz / 5000 to 7000 W
- Processing chamber pressure 35 to 70 mTorr Frequency / power of first high frequency power: 40 MHz / 600 to 1400 W Frequency / power of second high frequency power: 3.2 MHz / 5000 to 7000 W
- the depth of the hole in the underlying silicon film 310 is shallower in the case according to the present embodiment (FIG. 10B) than in the case according to the comparative example (FIG. 10A). At the same time, it can be seen that the depth of each hole is almost the same, and variation in the base loss is suppressed.
- the etching amount of the underlying silicon film 310 is measured, the first overetching is performed in an alternating manner in comparison with the case of the first overetching only one time (FIG. 10A), which is 124 nm.
- FIG. 10B In the case of the present embodiment repeated repeatedly (FIG. 10B), it is found that the thickness is 36 nm, and the base loss is greatly reduced. In both cases of FIGS. 10A and 10B, the hole diameter of the bottom increases almost similarly.
- the base CD loss is greatly suppressed while the bottom CD value is increased. It was found that the variation can be suppressed.
- the base loss can be suppressed and the variation can be suppressed while the bottom CD value is enlarged.
- a hole is formed as a recess in the laminated film.
- the plasma processing method according to the present invention can be applied to a trench ( The present invention can also be applied when forming a groove.
- the substrate to be processed in the present invention is not limited to a semiconductor wafer, and is, for example, a large substrate for a flat panel display (FPD), a substrate for an EL element, or a solar cell. Also good.
- FPD flat panel display
- EL element a substrate for an EL element
- solar cell a solar cell.
- ICP Inductively Coupled Plasma
- RLSA plasma a plasma processing apparatus
- magnetron plasma magnetron plasma.
- the present invention is applicable to a plasma processing method and a plasma processing apparatus for etching a multilayer film on a substrate to be processed using plasma.
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Abstract
Description
先ず,本発明の一実施形態に係るプラズマ処理方法による工程を経て製造可能な三次元積層半導体メモリの具体的構成例について,図面を参照しながら説明する。ここでは三次元積層半導体メモリの一例として3D-NANDフラッシュメモリを挙げる。図1は,3D-NANDフラッシュメモリの構造を概念的に示した斜視図である。図2Aは,図1に示す3D-NANDフラッシュメモリのA-A断面図である。図2Bは,図1に示す3D-NANDフラッシュメモリのB-B断面図である。
次に,本実施形態にかかるプラズマ処理方法を実施可能なプラズマ処理装置の構成例について図面を参照しながら説明する。ここでは,互いに対向して平行に配置される上部電極と下部電極を備えた平行平板型(容量結合型)のプラズマエッチング装置として構成したプラズマ処理装置を例に挙げる。図3は,本実施形態にかかるプラズマ処理装置100の概略構成を示す縦断面図である。
次に,このような構成のプラズマ処理装置100の動作について説明する。プラズマ処理装置100において,ウエハWに対してプラズマエッチング処理を行なう際には,先ずゲートバルブ130を開口して搬送アーム上に保持されたウエハWを処理室110内に搬入する。ウエハWは,図示しないリフトピン(リフタピン)により保持され,リフトピンが降下することにより静電チャック140上に載置される。ウエハWを搬入後,ゲートバルブ130が閉じられ,処理ガス供給部162から処理ガスを所定の流量および流量比で処理室110内に導入し,排気部128により処理室110内の圧力を設定値に減圧する。
次に,本実施形態にかかるプラズマ処理によりエッチングを行う被エッチング膜の膜構造について図面を参照しながら説明する。ここでは,被エッチング膜として,ウエハWの表面に形成された多層膜を例に挙げる。この多層膜をプラズマ処理によってエッチングすることで,多層膜に複数の深い凹部(ホール又はトレンチ)を形成する。図4は被エッチング膜としての多層膜の膜構造を示す断面図である。
次に,このような本実施形態にかかる多層膜のプラズマエッチング処理について図面を参照しながらより詳細に説明する。プラズマエッチング処理は,予め設定された処理条件に基づいて制御部200により実行される。図7は制御部にて実行されるプラズマエッチング処理の概略を示すフローチャートである。ここでは,図1に示す多層膜に複数の活性層ACを形成するために,多層膜を貫通する深穴を形成するプラズマエッチング処理を例に挙げる。
図7のステップS110に示すメインエッチング工程MEでは,マスク層330をエッチングマスクとして図8Aに示す多層膜320を所定の深さ,ここでは図8Bに示すようにエッチングストップ膜350の途中までメインエッチングを行う。なお,CF系ガス流量に対する酸素ガス流量比は,好ましくは0.2~0.5である。
次に,図7のステップS120~S140に示すオーバーエッチング工程OEでは,CFポリマの堆積量が少ないデポレスプロセスである第1オーバーエッチングと,CFポリマの堆積量が多いデポプロセスである第2オーバーエッチングを所定回数交互に繰り返し行う。
次に,本実施形態にかかるエッチング処理の効果を確認するために行った第1の実験の結果について説明する。図9A,図9Bはそれぞれ,図8Aに示すような積層膜340に対して第1の実験にかかるエッチング処理を行って形成した凹部(ここではホール(穴))のボトム断面の走査型電子顕微鏡SEM(Scanning Electron Microscope)写真のトレースを図示したものである。
処理室内圧力:15~30mTorr
第1高周波電力の周波数/パワー:40MHz/700~1500W
第2高周波電力の周波数/パワー:3.2MHz/5000~7000W
処理ガス流量比:C4F8/C4F6/CH2F2/Ar/O2=100/80/100/80/135
処理室内圧力:15~30mTorr
第1高周波電力の周波数/パワー:40MHz/700~1500W
第2高周波電力の周波数/パワー:3.2MHz/5000~7000W
処理ガス流量比:C4F8/C4F6/CH2F2/NF3/Ar/O2=45/46/34/10/100/43
処理室内圧力:35~70mTorr
第1高周波電力の周波数/パワー:40MHz/600~1400W
第2高周波電力の周波数/パワー:3.2MHz/5000~7000W
処理ガス流量比:C4F8/C4F6/CH2F2/CHF3/Ar/O2=20/70/50/20/400/110
処理室内圧力:35~70mTorr
第1高周波電力の周波数/パワー:40MHz/600~1400W
第2高周波電力の周波数/パワー:3.2MHz/5000~7000W
処理ガス流量比:CF4/C4F6/CH2F2/NF3/Ar/O2=45/46/34/100/100/43
次に,上記第1の実験結果とは別の処理条件によって本実施形態にかかるエッチング処理の効果を確認するために行った第2の実験の結果について説明する。図10A,図10Bはそれぞれ,図8Aに示すような積層膜340に対して第1の実験にかかるエッチング処理を行って形成した凹部(ここではホール(穴))のボトム断面の走査型電子顕微鏡SEM写真のトレースを図示したものである。
処理室内圧力:20~40mTorr
第1高周波電力の周波数/パワー:40MHz/500~1300W
第2高周波電力の周波数/パワー:3.2MHz/5000~7000W
処理ガス流量比:C4F8/C4F6/CH2F2/Ar/O2=50~60/90~100/95/100/145
処理室内圧力:35~70mTorr
第1高周波電力の周波数/パワー:40MHz/600~1400W
第2高周波電力の周波数/パワー:3.2MHz/5000~7000W
処理ガス流量比:C4F8/C4F6/CH2F2/CHF3/Ar/O2=20~25/65~70/35~50/20/400/110
処理室内圧力:35~70mTorr
第1高周波電力の周波数/パワー:40MHz/600~1400W
第2高周波電力の周波数/パワー:3.2MHz/5000~7000W
処理ガス流量比:C4F8/C4F6/CH2F2/CHF3/Ar/O2=20~25/65~75/0/0/1200/80
110 処理室
112 載置台
114 筒状保持部
116 筒状支持部
118 フォーカスリング
120 排気路
122 バッフル板
124 排気口
126 排気管
128 排気部
130 ゲートバルブ
133,134 整合器
138 シャワーヘッド
140 静電チャック
140a 電極
142 直流電圧源
143 スイッチ
152 伝熱ガス供給部
154 ガス供給ライン
156 電極板
156a ガス通気孔
158 電極支持体
160 バッファ室
160a ガス導入口
162 処理ガス供給部
164 ガス供給配管
180 同様の
182 冷媒管
184 チラーユニット
186,188 配管
190 ヒータ
192 交流電源
200 制御部
210 操作部
220 記憶部
310 下地シリコン膜
320 多層膜
330 マスク層
340 積層膜
350 エッチングストップ膜
AC 活性層
W ウエハ
Claims (12)
- 処理室内に被処理基板を配置し,処理ガスのプラズマを生成することによって,前記被処理基板に形成された多層膜を,パターニングされたマスク層をマスクとしてプラズマエッチングするプラズマ処理方法であって,
前記多層膜は,下地のシリコン膜上に形成された比誘電率の異なる第1膜及び第2膜が交互に積層された積層膜を有し,
フルオロカーボン系ガスと酸素ガスを含む処理ガスを前記処理室内に導入してプラズマを生成し,プラズマエッチングを行うことによって,前記積層膜に所定深さまで凹部を形成するメインエッチング工程と,その後に下地シリコン膜が露出するまで凹部を形成するオーバーエッチング工程とを行い,
前記オーバーエッチング工程は,前記フルオロカーボン系ガスに対する前記酸素ガスの流量比を前記メインエッチングよりも増加させて行う第1オーバーエッチングと,前記フルオロカーボン系ガスに対する前記酸素ガスの流量比を前記第1オーバーエッチングよりも減少させて行う第2オーバーエッチングとを2回以上繰り返すことを特徴とするプラズマ処理方法。 - 前記処理ガスは,ハイドロフルオロカーボン系ガスを含み,
前記第2オーバーエッチングでは,前記処理ガス中の前記ハイドロフルオロカーボン系ガスの流量比をゼロにするか又は前記第1オーバーエッチングよりも減少させることを特徴とする請求項1に記載のプラズマ処理方法。 - 前記第2オーバーエッチングでは,前記処理ガスにCF4ガスとNF3ガスのいずれか又は両方を含めることを特徴とする請求項1又は2に記載のプラズマ処理方法。
- 前記第1オーバーエッチングと前記第2オーバーエッチングの繰り返し回数は6回以上であることを特徴とする請求項1~3のいずれかに記載のプラズマ処理方法。
- 前記第2オーバーエッチングの処理条件は,前記メインエッチング工程の処理条件と同様であることを特徴とする請求項1~4のいずれかに記載のプラズマ処理方法。
- 前記積層膜を構成する第1膜と第2膜のうち,一方はシリコン酸化膜であり,他方はシリコン窒化膜であることを特徴とする請求項1~5のいずれかに記載のプラズマ処理方法。
- 前記処理室内に処理ガスのプラズマを生成することによって,被処理基板に形成された多層膜を,パターニングされたマスク層をマスクとしてプラズマエッチングするプラズマ処理装置であって,
前記処理室内に設けられた上部電極と,
前記上部電極に対向して設けられ,下地のシリコン膜上に形成された比誘電率の異なる第1膜及び第2膜が交互に積層された積層膜を有する前記多層膜が形成された前記被処理基板を配置する下部電極と,
前記下部電極にプラズマ生成用高周波電力を印加する第1高周波電源と,
前記下部電極にバイアス用高周波電力を印加する第2高周波電源と,
フルオロカーボン系ガスと酸素ガスを含む処理ガスを前記処理室内に導入してプラズマを生成し,プラズマエッチングを行うことによって,前記積層膜に所定深さまで凹部を形成するメインエッチング工程と,その後に下地シリコン膜が露出するまで凹部を形成するオーバーエッチング工程とを行う制御部と,を備え,
前記制御部は,前記オーバーエッチング工程にて前記フルオロカーボン系ガスに対する前記酸素ガスの流量比を前記メインエッチングよりも増加させて行う第1オーバーエッチングと,前記フルオロカーボン系ガスに対する前記酸素ガスの流量比を前記第1オーバーエッチングよりも減少させて行う第2オーバーエッチングとを2回以上繰り返すことを特徴とするプラズマ処理装置。 - 処理室内に被処理基板を配置し,処理ガスのプラズマを生成することによって,前記被処理基板に形成された多層膜を,パターニングされたマスク層をマスクとしてプラズマエッチングするプラズマ処理方法であって,
前記多層膜は,下地膜上に形成された比誘電率の異なる第1膜及び第2膜が交互に積層された積層膜を有し,
第1のガスと第2のガスを含む処理ガスを前記処理室内に導入してプラズマを生成し,プラズマエッチングを行うことによって,前記積層膜に所定深さまで凹部を形成するメインエッチング工程と,その後に下地膜が露出するまで凹部を形成するオーバーエッチング工程とを行い,
前記オーバーエッチング工程は,前記第1のガスに対する前記第2のガスの流量比を前記メインエッチングよりも増加させて行う第1オーバーエッチングと,前記第1のガスに対する前記第2のガスの流量比を前記第1オーバーエッチングよりも減少させて行う第2オーバーエッチングとを2回以上繰り返すことを特徴とするプラズマ処理方法。 - 前記第2オーバーエッチングでは,前記処理ガス中の前記第1のガスの流量比をゼロにするか又は前記第1オーバーエッチングよりも減少させることを特徴とする請求項8に記載のプラズマ処理方法。
- 前記第2オーバーエッチングでは,前記処理ガスに第3のガスを含めることを特徴とする請求項8又は9に記載のプラズマ処理方法。
- 前記第1オーバーエッチングと前記第2オーバーエッチングの繰り返し回数は6回以上であることを特徴とする請求項8~10のいずれかに記載のプラズマ処理方法。
- 前記第2オーバーエッチングの処理条件は,前記メインエッチング工程の処理条件と同様であることを特徴とする請求項8~11のいずれかに記載のプラズマ処理方法。
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KR20150077400A (ko) | 2015-07-07 |
KR102149718B1 (ko) | 2020-08-31 |
JP6154820B2 (ja) | 2017-06-28 |
US20150243521A1 (en) | 2015-08-27 |
US9396960B2 (en) | 2016-07-19 |
JPWO2014069559A1 (ja) | 2016-09-08 |
CN104704612A (zh) | 2015-06-10 |
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