WO2013150889A1 - 炭化珪素半導体装置の製造方法 - Google Patents
炭化珪素半導体装置の製造方法 Download PDFInfo
- Publication number
- WO2013150889A1 WO2013150889A1 PCT/JP2013/057741 JP2013057741W WO2013150889A1 WO 2013150889 A1 WO2013150889 A1 WO 2013150889A1 JP 2013057741 W JP2013057741 W JP 2013057741W WO 2013150889 A1 WO2013150889 A1 WO 2013150889A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- silicon carbide
- nickel
- semiconductor device
- manufacturing
- carbide semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
- H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
- H10D64/0115—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors to silicon carbide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/01—Manufacture or treatment
- H10D8/051—Manufacture or treatment of Schottky diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/60—Schottky-barrier diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3408—Silicon carbide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
- H10P14/44—Physical vapour deposition [PVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
Definitions
- the present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a method for manufacturing an ohmic electrode of a silicon carbide semiconductor device.
- silicon power devices Conventionally, for the purpose of controlling high frequency and high power, the performance of power devices using silicon (Si) substrates (hereinafter referred to as silicon power devices) has been improved. However, since silicon power devices cannot be used at high temperatures, application of new semiconductor materials is being studied in response to the demand for higher performance power devices.
- Silicon carbide has a wide band gap of about 3 times that of silicon, so it has excellent controllability of electrical conductivity at high temperatures, and has a breakdown voltage that is about an order of magnitude higher than that of silicon. It can be applied as a substrate material. Furthermore, since silicon carbide has an electron saturation drift velocity about twice that of silicon, it can be applied to a high-frequency and high-power control element.
- the present invention relates to a technology for forming a back electrode of a power device using a silicon carbide substrate, by reacting silicon in a silicon carbide substrate with nickel in a nickel (Ni) film to form a reaction layer made of nickel silicide.
- a method for obtaining ohmic characteristics between a silicon substrate and a nickel film is known.
- the free carbon (C) segregated on the surface of the ohmic electrode reduces the adhesion with the wiring metal layer formed on the ohmic electrode, and the wiring metal layer is easily peeled off. There was a problem. In order to solve this problem, the following methods have been proposed.
- the first surface of a silicon carbide substrate is made of any one of titanium (Ti), tantalum (Ta), and tungsten (W) on a first metal film made of nickel or a nickel alloy.
- a method of forming a second metal film and performing a heat treatment is disclosed. According to this method, carbon liberated by the formation of nickel silicide reacts with the second metal film to generate carbides, so that segregation of carbon components on the metal film surface can be prevented, and ohmic electrodes and wirings can be prevented. It describes that peeling from the metal layer can be prevented.
- the present invention provides a method for manufacturing a silicon carbide semiconductor device capable of improving the usage efficiency of a target with a uniform film thickness and no peeling when forming an ohmic electrode.
- the purpose is to provide.
- a method for manufacturing a silicon carbide semiconductor device has the following characteristics.
- An ohmic metal film is formed on a silicon carbide substrate by sputtering a target made of a mixture or alloy in which nickel and a metal that reduces the magnetic permeability of nickel and generates a carbide are adjusted to a predetermined composition ratio To do. Then, the ohmic metal film is heat treated and fired.
- a method for manufacturing a silicon carbide semiconductor device has the following characteristics.
- An epitaxial layer is grown on the first main surface of the silicon carbide substrate.
- the second main surface of the silicon carbide substrate is sputtered with a target made of a mixture or alloy in which nickel and a metal that reduces the magnetic permeability of nickel and generates carbides are adjusted to a predetermined composition ratio.
- a target made of a mixture or alloy in which nickel and a metal that reduces the magnetic permeability of nickel and generates carbides are adjusted to a predetermined composition ratio.
- an ohmic metal film is formed on the silicon carbide substrate. Further, the ohmic metal film is subjected to heat treatment and fired.
- the method for manufacturing a silicon carbide semiconductor device according to the present invention is the above-described invention, wherein the metal that reduces the magnetic permeability of nickel and generates carbides is molybdenum, tungsten, tantalum, vanadium, zirconium, titanium, chromium, and aluminum. It is characterized by being one or more selected metals.
- the metal that reduces the magnetic permeability of nickel and generates carbide is titanium, and the titanium ratio in the target is 8 at% or more and 50 at% or less. It is characterized by being.
- the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, a temperature for performing the heat treatment is 1050 ° C. or more.
- an ohmic electrode having a uniform film thickness and no peeling can be formed on a silicon carbide substrate. Moreover, the usage efficiency of the target can be improved. Furthermore, according to the present invention described above, the nickel: titanium composition ratio of the ohmic electrode material is accurately controlled to suppress the deposition of carbon on the ohmic electrode layer surface, which causes electrode peeling, and at the same time, increase in contact resistance. Excessive residual titanium can be suppressed.
- the method for manufacturing a silicon carbide semiconductor device when forming an ohmic electrode, there is an effect that the film thickness is uniform, there is no peeling, and the use efficiency of the target can be improved.
- FIG. 1 is a schematic cross-sectional view for illustrating a manufacturing process of a silicon carbide Schottky barrier diode according to an embodiment of the present invention.
- FIG. 2 is a schematic cross-sectional view for illustrating a manufacturing process of the silicon carbide Schottky barrier diode according to the embodiment of the present invention.
- FIG. 3 is a schematic cross-sectional view for illustrating the manufacturing process of the silicon carbide Schottky barrier diode according to the embodiment of the present invention.
- FIG. 4 is a schematic cross-sectional view for illustrating the manufacturing process of the silicon carbide Schottky barrier diode according to the embodiment of the present invention.
- FIG. 1 is a schematic cross-sectional view for illustrating a manufacturing process of a silicon carbide Schottky barrier diode according to an embodiment of the present invention.
- FIG. 2 is a schematic cross-sectional view for illustrating a manufacturing process of the silicon carbide Schottky barrier diode according to the embodiment of the present
- FIG. 5 is a schematic cross-sectional view for illustrating the manufacturing process of the silicon carbide Schottky barrier diode according to the embodiment of the present invention.
- FIG. 6 is a schematic cross-sectional view for illustrating a manufacturing step of the silicon carbide Schottky barrier diode according to the embodiment of the present invention.
- FIG. 7 is a diagram showing the relationship between the ratio of the nickel to titanium ratio in the ohmic electrode and the adhesion of the electrode film, according to an example of the present invention.
- FIG. 8 is a graph showing the relationship between the ratio of the nickel to titanium ratio in the ohmic electrode and the contact resistance according to the embodiment of the present invention.
- FIG. 1 to 6 are schematic cross-sectional views for illustrating a manufacturing process of a silicon carbide Schottky barrier diode according to an embodiment of the present invention.
- a high-concentration n-type silicon carbide substrate 1 having a (0001) plane with a thickness of 350 ⁇ m, for example, doped with nitrogen of 1 ⁇ 10 18 cm ⁇ 3 is prepared.
- nitrogen of 1.8 ⁇ 10 16 cm ⁇ 3 is doped, and the low-concentration n-type silicon carbide drift layer having a thickness of 6 ⁇ m. 2 is deposited.
- phosphorus (P) is implanted into the low concentration n-type silicon carbide drift layer 2 by an ion implantation method in order to form the n-type region 3 for the channel stopper.
- phosphorus (P) is implanted into the low concentration n-type silicon carbide drift layer 2 by an ion implantation method in order to form the n-type region 3 for the channel stopper.
- FIG. 3 in order to form the p-type region 4 for the termination structure and the p-type region 5 for the FLR (field limited ring) structure, for example, aluminum (Al) is implanted by an ion implantation method. .
- phosphorus implanted to form the n-type region 3 for the channel stopper and aluminum implanted to form the p-type region 4 for the termination structure and the p-type region 5 for the FLR structure In order to activate, an activation process is performed in an argon (Ar) atmosphere for 240 seconds at a temperature of 1650 ° C., for example.
- the temperature is increased at a temperature increase rate of, for example, 1 ° C./second, and held for 2 minutes after reaching a temperature of 1050 ° C. or higher, for example, 1100 ° C.
- RTA rapid thermal treatment
- the first metal layer is baked and reacted with silicon in the high-concentration n-type silicon carbide substrate 1 to be silicided, and the second main surface of the high-concentration n-type silicon carbide substrate 1 has a low resistance.
- An ohmic electrode 6 is formed.
- an interlayer insulating film 7 is formed on the first main surface of the high-concentration n-type silicon carbide substrate 1, and the interlayer insulating film 7 is patterned to form a contact hole in which a portion where the Schottky electrode 8 is to be formed is opened. To do. Next, after forming a second metal layer by evaporating, for example, titanium on a portion where the Schottky electrode 8 is to be formed, the temperature is raised at a temperature rising time of, for example, 8 ° C./second, and after reaching 500 ° C., 5 Holding for a minute, the Schottky electrode 8 is formed.
- the terminal portion of the Schottky electrode 8 is formed to extend on the p-type region 4 in order to operate the Schottky barrier diode as a high breakdown voltage element, and the end of the Schottky electrode 8 and the p-type region 4 are connected to each other. Make sure they overlap.
- an electrode pad 9 made of, for example, aluminum-silicon is formed on the Schottky electrode 8 as a bonding electrode pad with a thickness of, for example, 5 ⁇ m, and extends from the interlayer insulating film 7 to the electrode pad 9.
- a passivation film 10 made of polyimide is formed.
- contaminants such as resist residue adhere to the surface of the ohmic electrode 6 through the many steps so far.
- contaminants can be removed by treating the back surface by a reverse sputtering method in which ionized argon is collided to remove impurities.
- a gold (Au) film is formed on the ohmic electrode 6 with a thickness of, for example, 200 nm.
- the external electrode 11 is formed for connection to an external device with little resistance and no peeling.
- the silicon carbide shot manufactured by changing the titanium ratio relative to nickel in the ohmic electrode 6 in the range of 0 to 60 at% was used.
- FIG. 7 is a diagram showing the relationship between the ratio of the nickel to titanium ratio in the ohmic electrode and the adhesion of the electrode film, according to an example of the present invention.
- the silicon carbide Schottky barrier diode having a titanium ratio of 8 to 50 at% in the ohmic electrode 6 no peeling of the external electrode 11 occurred.
- FIG. 8 shows the result of the contact resistance measurement performed on the barrier diode.
- FIG. 8 is a graph showing the relationship between the ratio of the nickel to titanium ratio in the ohmic electrode and the contact resistance according to the embodiment of the present invention. As can be seen from FIG. 8, the contact resistance increased when the ratio of titanium to nickel in the ohmic electrode 6 exceeded 50 at%.
- the nickel: titanium composition ratio of the ohmic electrode material can be accurately controlled by using a target adjusted to a predetermined nickel: titanium composition ratio, carbon on the ohmic electrode layer surface that causes electrode peeling Precipitation can be suppressed. In addition, an increase in contact resistance due to excessive titanium remaining on the surface of the ohmic electrode layer can be suppressed.
- FIGS. 1 to 6 The manufacturing process of the silicon carbide Schottky barrier diode disclosed in FIGS. 1 to 6 is illustrated for the purpose of understanding the present invention, and it goes without saying that the manufacturing conditions disclosed herein can be appropriately changed.
- the (0001) plane is described as an example of the main surface of the high-concentration n-type silicon carbide substrate, but the (000-1) plane may be used as the main surface of the high-concentration n-type silicon carbide substrate. Good.
- MOS gate insulating gate made of metal-oxide film-semiconductor
- the silicon carbide Schottky barrier diode is exemplified as an embodiment and an example, and the manufacturing method thereof has been described in detail, but the present invention is not limited to the embodiment and the example, Various design changes can be made without departing from the spirit of the present invention.
- the sputtering target is exemplified by adding nickel to the ferromagnetic material nickel to reduce the magnetic permeability, but other molybdenum (Mo), tungsten, and tantalum are added to the ferromagnetic material nickel.
- Magnetic permeability may be reduced by adding materials such as vanadium (V), zirconium (Zr), chromium (Cr), and aluminum. These materials may be added in combination of two or more.
- nickel which is a ferromagnetic material
- titanium, molybdenum, tungsten, tantalum, vanadium, zirconium, chromium, and aluminum are added to reduce the magnetic permeability.
- the uneven erosion of the target can be reduced, the uniformity of the ohmic electrode layer can be improved, and at the same time the use efficiency of the target can be improved.
- the method for manufacturing a silicon carbide semiconductor device according to the present invention is useful for a power semiconductor device for high-frequency and high-power control that is used at high temperatures.
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
本発明の実施の形態に係る炭化珪素半導体装置の製造方法を、炭化珪素ショットキーバリアダイオードの製造方法を例示して、以下詳細に説明する。
2 低濃度n型炭化珪素ドリフト層
3 n型領域
4 p型領域(終端)
5 p型領域(FLR)
6 オーミック電極
7 層間絶縁膜
8 ショットキー電極
9 電極パッド
10 パッシベーション膜
11 外部電極
Claims (5)
- ニッケルと、ニッケルの透磁率を低減させるとともに炭化物を生成する金属とが、所定の組成比に調整された混合体あるいは合金からなるターゲットをスパッタすることにより、炭化珪素基板上にオーミック金属膜を形成する工程と、
前記オーミック金属膜に熱処理を施し焼成する工程と、
を含むことを特徴とする炭化珪素半導体装置の製造方法。 - 炭化珪素基板の第一の主面にエピタキシャル層を成長させる工程と、
前記炭化珪素基板の第二の主面にニッケルと、ニッケルの透磁率を低減させるとともに炭化物を生成する金属とが、所定の組成比に調整された混合体あるいは合金からなるターゲットをスパッタすることにより、前記炭化珪素基板上にオーミック金属膜を形成する工程と、
前記オーミック金属膜に熱処理を施し焼成する工程と、
を含むことを特徴とする炭化珪素半導体装置の製造方法。 - 前記ニッケルの透磁率を低減させるとともに炭化物を生成する金属は、モリブデン、タングステン、タンタル、バナジウム、ジルコニウム、チタン、クロム、アルミニウムから選定された1種又は2種以上の金属であることを特徴とする請求項1又は2に記載の炭化珪素半導体装置の製造方法。
- 前記ニッケルの透磁率を低減させるとともに炭化物を生成する金属がチタンであり、前記ターゲット中のチタン比率が8at%以上50at%以下であることを特徴とする請求項1又は2に記載の炭化珪素半導体装置の製造方法。
- 前記熱処理を施す温度が1050℃以上であることを特徴とする請求項1又は2に記載の炭化珪素半導体装置の製造方法。
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201380018024.3A CN104303269B (zh) | 2012-04-06 | 2013-03-18 | 碳化硅半导体装置的制造方法 |
| DE112013001927.2T DE112013001927T5 (de) | 2012-04-06 | 2013-03-18 | Herstellungsverfahren für eine Siliziumcarbid-Halbleitervorrichtung |
| US14/390,715 US9281194B2 (en) | 2012-04-06 | 2013-03-18 | Fabrication method of silicon carbide semiconductor apparatus |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012-087726 | 2012-04-06 | ||
| JP2012087726A JP2013219150A (ja) | 2012-04-06 | 2012-04-06 | 炭化珪素半導体装置のオーミック電極の製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2013150889A1 true WO2013150889A1 (ja) | 2013-10-10 |
Family
ID=49300383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2013/057741 Ceased WO2013150889A1 (ja) | 2012-04-06 | 2013-03-18 | 炭化珪素半導体装置の製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9281194B2 (ja) |
| JP (1) | JP2013219150A (ja) |
| CN (1) | CN104303269B (ja) |
| DE (1) | DE112013001927T5 (ja) |
| WO (1) | WO2013150889A1 (ja) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9552993B2 (en) * | 2014-02-27 | 2017-01-24 | Semiconductor Components Industries, Llc | Semiconductor device and manufacturing method thereof |
| JP2016015424A (ja) * | 2014-07-02 | 2016-01-28 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP6057032B2 (ja) | 2014-07-24 | 2017-01-11 | 富士電機株式会社 | 炭化珪素半導体装置の製造方法 |
| WO2017046868A1 (ja) * | 2015-09-15 | 2017-03-23 | 株式会社日立製作所 | 半導体装置およびその製造方法、電力変換装置、3相モータシステム、自動車並びに鉄道車両 |
| KR102315807B1 (ko) | 2015-09-25 | 2021-10-22 | 마테리온 코포레이션 | 솔더 부착을 갖는 인광체 요소를 사용하는 높은 광출력 광 변환 장치 |
| US9960247B2 (en) * | 2016-01-19 | 2018-05-01 | Ruigang Li | Schottky barrier structure for silicon carbide (SiC) power devices |
| JP6801200B2 (ja) | 2016-03-16 | 2020-12-16 | 富士電機株式会社 | 炭化珪素半導体素子の製造方法 |
| JP6808952B2 (ja) * | 2016-03-16 | 2021-01-06 | 富士電機株式会社 | 炭化珪素半導体装置の製造方法 |
| SE541291C2 (en) * | 2017-09-15 | 2019-06-11 | Ascatron Ab | Feeder design with high current capability |
| DE212020000212U1 (de) | 2019-04-19 | 2020-10-20 | Rohm Co. Ltd. | SiC-Halbleiterbauteil |
| CN110729361A (zh) * | 2019-10-09 | 2020-01-24 | 杭州电子科技大学 | 一种具有MoC合金的肖特基势垒二极管 |
| CN113140656B (zh) * | 2021-04-26 | 2023-04-04 | 晶澳(扬州)太阳能科技有限公司 | 一种太阳能电池和硅薄膜的制备方法 |
| JP7687078B2 (ja) * | 2021-06-21 | 2025-06-03 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000208438A (ja) * | 1999-01-11 | 2000-07-28 | Fuji Electric Co Ltd | SiC半導体デバイス |
| JP2011119585A (ja) * | 2009-12-07 | 2011-06-16 | Toyota Motor Corp | 半導体装置の製造方法 |
| JP2011165880A (ja) * | 2010-02-09 | 2011-08-25 | Showa Denko Kk | 半導体装置および半導体装置の製造方法 |
| JP2011171551A (ja) * | 2010-02-19 | 2011-09-01 | Toyota Motor Corp | 半導体装置の製造方法 |
| WO2011115259A1 (ja) * | 2010-03-19 | 2011-09-22 | Jx日鉱日石金属株式会社 | ニッケル合金スパッタリングターゲット、Ni合金薄膜及びニッケルシリサイド膜 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3381473B2 (ja) * | 1994-08-25 | 2003-02-24 | セイコーエプソン株式会社 | 液体噴射ヘッド |
| JP2003213405A (ja) * | 2002-01-18 | 2003-07-30 | Nikko Materials Co Ltd | 高純度ニッケル又はニッケル合金ターゲット及びその製造方法 |
| JP4610207B2 (ja) * | 2004-02-24 | 2011-01-12 | 三洋電機株式会社 | 半導体装置およびその製造方法 |
| JP4902210B2 (ja) | 2005-02-01 | 2012-03-21 | 国立大学法人東北大学 | 垂直磁気記録媒体及びその製造方法並びに垂直磁気記録再生装置 |
| WO2006087873A1 (ja) * | 2005-02-17 | 2006-08-24 | Nippon Mining & Metals Co., Ltd. | フレキシブル銅基板用バリア膜及びバリア膜形成用スパッタリングターゲット |
| JP4699812B2 (ja) * | 2005-06-07 | 2011-06-15 | 株式会社デンソー | 半導体装置およびその製造方法 |
| JP4836769B2 (ja) * | 2006-12-18 | 2011-12-14 | スタンレー電気株式会社 | 半導体発光装置およびその製造方法 |
| JP2011149034A (ja) * | 2009-12-22 | 2011-08-04 | Toshiba Corp | Ni合金スパッタリングターゲットおよびその製造方法並びに半導体素子の製造方法 |
-
2012
- 2012-04-06 JP JP2012087726A patent/JP2013219150A/ja active Pending
-
2013
- 2013-03-18 CN CN201380018024.3A patent/CN104303269B/zh not_active Expired - Fee Related
- 2013-03-18 US US14/390,715 patent/US9281194B2/en not_active Expired - Fee Related
- 2013-03-18 DE DE112013001927.2T patent/DE112013001927T5/de not_active Withdrawn
- 2013-03-18 WO PCT/JP2013/057741 patent/WO2013150889A1/ja not_active Ceased
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000208438A (ja) * | 1999-01-11 | 2000-07-28 | Fuji Electric Co Ltd | SiC半導体デバイス |
| JP2011119585A (ja) * | 2009-12-07 | 2011-06-16 | Toyota Motor Corp | 半導体装置の製造方法 |
| JP2011165880A (ja) * | 2010-02-09 | 2011-08-25 | Showa Denko Kk | 半導体装置および半導体装置の製造方法 |
| JP2011171551A (ja) * | 2010-02-19 | 2011-09-01 | Toyota Motor Corp | 半導体装置の製造方法 |
| WO2011115259A1 (ja) * | 2010-03-19 | 2011-09-22 | Jx日鉱日石金属株式会社 | ニッケル合金スパッタリングターゲット、Ni合金薄膜及びニッケルシリサイド膜 |
Also Published As
| Publication number | Publication date |
|---|---|
| DE112013001927T5 (de) | 2015-02-26 |
| US20150194313A1 (en) | 2015-07-09 |
| JP2013219150A (ja) | 2013-10-24 |
| CN104303269B (zh) | 2017-05-03 |
| US9281194B2 (en) | 2016-03-08 |
| CN104303269A (zh) | 2015-01-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2013150889A1 (ja) | 炭化珪素半導体装置の製造方法 | |
| JP6222771B2 (ja) | 炭化珪素半導体装置の製造方法 | |
| JP6099298B2 (ja) | SiC半導体デバイス及びその製造方法 | |
| US9129804B2 (en) | Silicon carbide semiconductor device and method for manufacturing same | |
| KR101283774B1 (ko) | SiC 반도체용 오믹 전극, SiC 반도체용 오믹 전극의 제조 방법, 반도체 장치 및 반도체 장치의 제조 방법 | |
| US7935628B2 (en) | Silicon carbide semiconductor device and method for producing the same | |
| US9768260B2 (en) | Fabrication method of silicon carbide semiconductor apparatus and silicon carbide semiconductor apparatus fabricated thereby | |
| JP6160541B2 (ja) | 炭化珪素半導体装置の製造方法 | |
| JP2017175115A (ja) | 炭化珪素半導体素子および炭化珪素半導体素子の製造方法 | |
| JP6060476B2 (ja) | 電極形成方法 | |
| JP4501488B2 (ja) | 炭化珪素半導体のオーミック電極及びその製造方法 | |
| JP6808952B2 (ja) | 炭化珪素半導体装置の製造方法 | |
| JP6648574B2 (ja) | 炭化珪素半導体装置の製造方法 | |
| US9741578B2 (en) | Manufacturing method of semiconductor device | |
| JP4038498B2 (ja) | 半導体素子および半導体素子の製造方法 | |
| JP2015070026A (ja) | 半導体装置およびその製造方法 | |
| JP2015115374A (ja) | 炭化珪素半導体装置の製造方法 | |
| JP2008227405A (ja) | n型4H−SiC基板上にオーミック電極を形成する方法 | |
| JP2017168679A (ja) | 炭化珪素半導体素子および炭化珪素半導体素子の製造方法 | |
| WO2013190901A1 (ja) | 炭化珪素半導体装置およびその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 13772949 Country of ref document: EP Kind code of ref document: A1 |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 14390715 Country of ref document: US |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 1120130019272 Country of ref document: DE Ref document number: 112013001927 Country of ref document: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 13772949 Country of ref document: EP Kind code of ref document: A1 |