CN104303269B - 碳化硅半导体装置的制造方法 - Google Patents

碳化硅半导体装置的制造方法 Download PDF

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CN104303269B
CN104303269B CN201380018024.3A CN201380018024A CN104303269B CN 104303269 B CN104303269 B CN 104303269B CN 201380018024 A CN201380018024 A CN 201380018024A CN 104303269 B CN104303269 B CN 104303269B
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silicon carbide
nickel
target
semiconductor device
metal
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CN104303269A (zh
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吕民雅
仲俣伸
仲俣伸一
木下明将
福田宪司
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Fuji Electric Co Ltd
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Abstract

通过溅射由镍、和使镍的磁导率降低并且生成碳化物的金属被调整至给定的组成比而得到的混合体或合金构成的靶，在碳化硅基板(1)上形成欧姆金属膜，通过对欧姆金属膜实施热处理，进行烧成，来制造碳化硅半导体装置的欧姆电极(6)。由此，能制造膜厚均匀、无剥离且能提升靶的使用效率的碳化硅半导体装置的欧姆电极(6)。

Description

碳化硅半导体装置的制造方法
技术领域
本发明涉及碳化硅半导体装置的制造方法，特别涉及碳化硅半导体装置的欧姆电极的制造方法。
背景技术
过去，以高频、大功率的控制为目的，使用硅(Si)基板的功率器件(以下称作硅功率器件)的高性能化不断进展。但是，由于硅功率器件不能在高温下使用，因此，应对要求更高性能的功率器件的呼声，研究了新的半导体材料的运用。
碳化硅(SiC)由于具有硅的约3倍这样宽的禁带宽度，因而在高温下的电导率的控制性卓越，由于具有比硅大约一个数量级的绝缘击穿电压，因此能作为高耐压元件用的基板材料运用。进而，碳化硅由于具有硅的约2倍的电子饱和漂移速度，因此还能运用在高频且大功率的控制用的元件中。
关于形成使用碳化硅基板的功率器件的背面电极的技术，已知通过使碳化硅基板中的硅与镍(Ni)膜中的镍反应来形成由硅化镍构成的反应层从而得到碳化硅基板和镍膜的欧姆特性的方法。但是，在通过该方法形成的欧姆电极中，由于偏析在欧姆电极表面的游离碳(C)而使得与形成在欧姆电极上的布线金属层的密接性降低，有布线金属层变得易于剥离这样的问题。为了解决该问题，提出以下的手法。
例如，在下述专利文献1中，公开了如下方法：在碳化硅基板的表面，在由镍或镍合金构成的第1金属膜上形成由钛(Ti)、钽(Ta)或钨(W)的任一者构成的第2金属膜，并进行热处理。记载了根据该方法，由于通过硅化镍的生成而游离的碳与第2金属膜反应而生成碳化物，因此能防止碳成分在金属膜表面偏析，能防止欧姆电极和布线金属层的剥离。
先行技术文献
专利文献
专利文献1：JP特开2006-344688号公报
发明的概要
发明要解决的课题
但是，在上述专利文献1记载的制造方法中，为了同时防止成为剥离的原因的游离碳的偏析、和第2金属膜的过剩残留所引起的接触电阻的增大，需要高精度地控制镍膜和第2金属膜的膜厚比率。在金属膜的成膜一般所用的磁控溅射法中，已知通过反复进行强磁性体的镍的成膜来减少靶外周部的泄漏磁力线，从而侵蚀会集中到靶中心部，膜厚均匀性变差。另外，由于在靶外周部的堆积速度减少，另一方面偏向靶中央而堆积速度增加，因此还发生靶寿命变短，靶的使用效率变差这样的问题。
发明内容
本发明目的在于，为了消除上述的现有技术中的问题点，提供一种在形成欧姆电极时膜厚均匀、无剥离且能提升靶的使用效率的碳化硅半导体装置的制造方法。
用于解决课题的手段
为了解决上述课题，达成本发明的目的，本发明所涉及的碳化硅半导体装置的制造方法具有如下特征。通过溅射由将镍、和使镍的磁导率降低并且生成碳化物的金属调整为给定的组成比而得到的混合体或合金构成的靶，来在碳化硅基板上形成欧姆金属膜。并且，对所述欧姆金属膜实施热处理来进行烧成。
为了解决上述课题、达成本发明的目的，本发明所涉及的碳化硅半导体装置的制造方法具有如下特征。在碳化硅基板的第1主面使外延层生长。然后，通过在所述碳化硅基板的第2主面溅射由将镍、和使镍的磁导率降低并且生成碳化物的金属调整为给定的组成比而得到的混合体或合金构成的靶，来在所述碳化硅基板上形成欧姆金属膜。进而，对所述欧姆金属膜实施热处理来进行烧成。
本发明所涉及的碳化硅半导体装置的制造方法在上述的发明的基础上，其特征在于，使所述镍的磁导率降低并且生成碳化物的金属是从钼、钨、钽、钒、锆、钛、铬、铝选定的1种或2种以上的金属。
本发明所涉及的碳化硅半导体装置的制造方法在上述的发明的基础上，其特征在于，使所述镍的磁导率降低并且生成碳化物的金属是钛，所述靶中的钛比率为8at％以上50at％以下。
本发明所涉及的碳化硅半导体装置的制造方法在上述的发明的基础上，其特征在于，实施所述热处理的温度为1050℃以上。
根据上述的本发明，能在碳化硅基板上形成膜厚均匀、无剥离的欧姆电极。另外，能提升靶的使用效率。进而，根据上述的本发明，能精度良好地控制欧姆电极材料的镍：钛组成比，能在抑制成为电极的剥离的原因的欧姆电极层表面的碳析出的同时抑制成为接触电阻增大的原因的钛的过剩残留。
发明的效果
根据本发明所涉及的碳化硅半导体装置的制造方法，能实现在形成欧姆电极时膜厚均匀、无剥离且使靶的使用效率提高这样的效果。
附图说明
图1是用于说明本发明的实施方式所涉及的碳化硅肖特基势垒二极管的制造工序的截面示意图。
图2是用于说明本发明的实施方式所涉及的碳化硅肖特基势垒二极管的制造工序的截面示意图。
图3是用于说明本发明的实施方式所涉及的碳化硅肖特基势垒二极管的制造工序的截面示意图。
图4是用于说明本发明的实施方式所涉及的碳化硅肖特基势垒二极管的制造工序的截面示意图。
图5是用于说明本发明的实施方式所涉及的碳化硅肖特基势垒二极管的制造工序的截面示意图。
图6是用于说明本发明的实施方式所涉及的碳化硅肖特基势垒二极管的制造工序的截面示意图。
图7是表征本发明的实施例所涉及的欧姆电极中的钛比镍比率的比例与电极膜的密接性的关系的图。
图8是表征本发明的实施例所涉及的欧姆电极中的钛比镍比率的比例与接触电阻的关系的图。
具体实施方式
以下参考附图来详细说明发明所涉及的碳化硅半导体装置的制造方法的合适的实施方式。在本说明书以及附图中，在标记n或p的层或区域中，分别意味着电子或空穴为多数载流子。另外，在以下的实施方式的说明以及附图中，对相同的构成标注相同的标号，省略重复的说明。
(实施方式)
例示碳化硅肖特基势垒二极管的制造方法，以下详细说明本发明的实施方式所涉及的碳化硅半导体装置的制造方法。
图1～6是用于说明本发明的实施方式所涉及的碳化硅肖特基势垒二极管的制造工序的截面示意图。首先，如图1所示，准备掺杂了例如1×1018cm-3的氮的厚度为350μm的具有(0001)面的高浓度n型碳化硅基板1。接下来，在高浓度n型碳化硅基板1的第1主面上堆积掺杂了例如1.8×1016cm-3的氮的厚度为6μm的低浓度n型碳化硅漂移层2。
接下来，如图2所示，为了形成沟道阻止层(channel stopper)用的n型区域3.通过离子注入法在低浓度n型碳化硅漂移层2中注入例如磷(P)。接下来，如图3所示，为了形成终端构造用的p型区域4和FLR(场限环)构造用的p型区域5，通过离子注入法注入例如铝(A1)。接下来，为了使为了形成沟道阻止层用的n型区域3而注入的磷、和为了形成终端构造用的p型区域4以及FLR构造用的p型区域5而注入的铝活化，在氩(Ar)气氛中，在例如1650℃的温度进行240秒钟的活化处理。
接下来，如图4所示那样，在高浓度n型碳化硅基板1的第2主面上，通过磁控溅射法在真空中溅射基于由镍∶钛＝80∶20(at％)构成的混合体或合金的溅射靶，堆积80nm的第1金属膜。
之后，使用快速加热处理(RTA：Rapid Thermal Anneal)装置，以例如1℃/秒的升温速度升温，在到达1050℃以上的温度、例如1100℃后保持2分钟。由此，第1金属层被烧成，与高浓度n型碳化硅基板1中的硅反应而硅化物化，从而在高浓度n型碳化硅基板1的第2主面形成低电阻的欧姆电极6。
进而，在所述高浓度n型碳化硅基板1的第1主面上形成层间绝缘膜7，对层间绝缘膜7图案形成来形成在形成肖特基电极8的部分开口的接触孔。接下来，在通过对形成肖特基电极8的部分蒸镀例如钛而形成第2金属层后，以例如8℃/秒的升温时间升温，在到达500℃后保持5分钟，从而形成肖特基电极8。肖特基电极8的终端部分为了使肖特基势垒二极管作为高耐压元件动作而在p型区域4上延伸地形成，肖特基电极8的端部与p型区域4重叠。
接下来，如图5所示，在肖特基电极8上以例如5μm的厚度形成由例如铝-硅构成的电极焊盘9，作为键合用电极焊盘，从层间绝缘膜7起跨到电极焊盘9形成由聚酰亚胺构成的钝化膜10。
虽未图示，但在经过这里的众多工序的过程中，在欧姆电极6表面附着例如抗蚀剂残渣等的污染物质。这样的污染物质能用使离子化的氩撞击来进行杂质除去的逆溅射法对背面进行处理来除去。
接下来，如图6所示那样，在欧姆电极6上以例如200nm的厚度形成金(Au)膜。由此形成无剥离、电阻少的用于与外部装置连接的外部电极11。
在此，针对使用图1～6所示的实施方式所涉及的碳化硅半导体装置的制造方法、使欧姆电极6中钛相对于镍的比率在0～60at％的范围内变化而制造的碳化硅肖特基势垒二极管(以下设为实施例)进行剥离耐久性试验。
具体地，按欧姆电极6中钛相对于镍的比率的每个条件准备10个碳化硅肖特基势垒二极管，在覆盖二极管的外部电极11的表面地使透明胶带紧贴后，各进行10次用透明胶带剥取外部电极11这样的试验，在图7示出结果。图7是表征本发明的实施例所涉及的欧姆电极中的钛比镍比率的比例与电极膜的密接性的关系的图。根据图7所知，在欧姆电极6中的钛相对于镍的比率为8～50at％的碳化硅肖特基势垒二极管中，不发生外部电极11的剥离。
进而，针对使用图1～6所示的实施方式所涉及的碳化硅半导体装置的制造方法、使欧姆电极6中的钛相对于镍的比率在0～60at％的范围内变化而制造的碳化硅肖特基势垒二极管进行接触电阻测定，在图8示出结果。图8是表征本发明的实施例所涉及的欧姆电极中的钛比镍比率的比例与接触电阻的关系的图。根据图8所知，在欧姆电极6中的钛相对于镍的比率超过50at％时接触电阻增大。
如此，由于使用调整为给定的镍：钛组成比的靶能够精度良好地控制欧姆电极材料的镍：钛组成比，因此能抑制成为电极的剥离的原因的欧姆电极层表面的碳的析出。另外，能抑制由于钛在欧姆电极层表面过剩残留所引起的接触电阻的增大。
图1～6中公开的碳化硅肖特基势垒二极管的制造工序是为了理解本申请发明而例示的，在此公开的制造条件能适当变更，这不言自明。另外，在实施方式中，作为高浓度n型碳化硅基板的主面以(0001)面为例进行了叙述，但是作为高浓度n型碳化硅基板的主面，也可以使用(000-1)面。
进而，在实施方式中叙述了制造碳化硅肖特基势垒二极管的情况，但也能用于制造在高浓度n型碳化硅基板的主面上形成其它MOS栅(由金属-氧化膜-半导体构成的绝缘栅)构造等的半导体装置的碳化硅半导体装置的欧姆电极。
即，在本说明书中，将碳化硅肖特基势垒二极管作为实施方式以及实施例来例示，详述了其制造方法，但本发明并不限定于所述实施方式以及实施例，只要不脱离本发明的主旨，就能进行各种设计变更。
例如，在实施例中，作为溅射靶，例示了为了降低磁导率而在作为强磁性材料的镍中添加钛，但也可以在作为强磁性材料的镍中添加其他的钼(Mo)、钨、钽、钒(V)、锆(Zr)、铬(Cr)、铝这样的材料来使磁导率降低。另外，也可以将这些材料组合2种以上来添加。
如以上说明那样，根据本发明，通过使用为了降低磁导率而在作为强磁性材料的镍中添加钛、钼、钨、钽、钒、锆、铬、铝从而降低了磁导率的溅射靶，能使靶的侵蚀偏差降低，能在提升欧姆电极层的均匀性的同时提升靶的使用效率。
产业上的利用可能性
如以上那样，本发明所涉及的碳化硅半导体装置的制造方法对于在高温下使用、高频且大功率的控制用的功率半导体装置是有用的。
标号的说明
1 高浓度n型碳化硅基板
2 低浓度n型碳化硅漂移层
3 n型区域
4 p型区域(终端)
5 p型区域(FLR)
6 欧姆电极
7 层间绝缘膜
8 肖特基电极
9 电极焊盘
10 钝化膜
11 外部电极

Claims (3)

1.一种碳化硅半导体装置的制造方法，其特征在于，包含：
通过对靶进行溅射而在碳化硅基板上形成欧姆金属膜的工序，该靶由镍和使镍的磁导率降低并且生成碳化物的金属被调整至给定的组成比而得到的混合体或合金构成；和
对所述欧姆金属膜实施热处理来进行烧成的工序，
使所述镍的磁导率降低并且生成碳化物的金属是钛，所述靶中的钛比率为8at％以上且50at％以下，
实施所述热处理的温度为1050℃以上。
2.一种碳化硅半导体装置的制造方法，其特征在于，包含：
在碳化硅基板的第1主面使外延层生长的工序；
通过在所述碳化硅基板的第2主面对靶进行溅射而在所述碳化硅基板上形成欧姆金属膜的工序，该靶由镍和使镍的磁导率降低并且生成碳化物的金属被调整至给定的组成比而得到的混合体或合金构成；和
对所述欧姆金属膜实施热处理来进行烧成的工序，
使所述镍的磁导率降低并且生成碳化物的金属是钛，所述靶中的钛比率为8at％以上且50at％以下，
实施所述热处理的温度为1050℃以上。
3.根据权利要求1或2所述的碳化硅半导体装置的制造方法，其特征在于，
使所述镍的磁导率降低并且生成碳化物的金属是从钼、钨、钽、钒、锆、钛、铬、铝中选定的1种或2种以上的金属。
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