CN113728441A - SiC半导体装置 - Google Patents

SiC半导体装置 Download PDF

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Publication number
CN113728441A
CN113728441A CN202080029447.5A CN202080029447A CN113728441A CN 113728441 A CN113728441 A CN 113728441A CN 202080029447 A CN202080029447 A CN 202080029447A CN 113728441 A CN113728441 A CN 113728441A
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layer
main surface
electrode
region
semiconductor device
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CN202080029447.5A
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永田敏雄
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Rohm Co Ltd
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Rohm Co Ltd
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Abstract

本发明提供一种SiC半导体装置，其包含：具有一侧的第一主面和另一侧的第二主面的SiC芯片，包含第一Al层且形成于前述第一主面上的第一主面电极，形成于前述第一主面电极上且与导线连接的焊盘电极，以及包含第二Al层且形成于前述第二主面上的第二主面电极。

Description

SiC半导体装置
技术领域
本发明涉及SiC半导体装置。
背景技术
专利文献1公开了一种SiC半导体装置，其包含：SiC基板(SiC芯片)；包含Al且形成在SiC基板的表面上的焊盘电极；以及形成在SiC基板的背面上的欧姆电极。焊盘电极接合有接合线(导线)。
现有技术文献
专利文献
专利文献1：日本特开2015-207780号公报
发明内容
发明要解决的课题
后续工序(组装工序)中，对SiC半导体装置施加各种外力。例如，在安装SiC半导体装置时，使用具备吸嘴的安装机。SiC半导体装置以被吸嘴吸附保持的状态被搬运至连接对象物后，按压安装于连接对象部。此时，从吸嘴朝向连接对象物的外力以及从连接对象物朝向吸嘴的外力被施加至SiC半导体装置。
此外，在安装SiC半导体装置后，利用焊针(キャピラリ)将导线按压接合于焊盘电极。此时，从焊针朝向连接对象物的外力以及从连接对象物朝向焊针的外力被施加至SiC半导体装置。如果对SiC半导体装置施加超出SiC芯片的强度的外力，则SiC芯片产生裂纹。
本发明的一个实施方式提供能够缓和外力的SiC半导体装置。
用于解决课题的方法
本发明的一个实施方式提供一种SiC半导体装置，其包含：SiC芯片，具有一侧的第一主面和另一侧的第二主面；第一主面电极，包含第一Al层且形成在前述第一主面上；焊盘电极，形成在前述第一主面电极上且与导线连接；以及第二主面电极，包含第二Al层且形成在前述第二主面上。
根据该SiC半导体装置，第一Al层作为在第一主面侧缓和外力的第一缓冲层来形成，第二Al层作为在第二主面侧缓和外力的第二缓冲层来形成。由此，能够缓和从第一主面朝向第二主面方向的外力以及从第二主面朝向第一主面方向的外力。
本发明的上述或者进一步的其他目的、特征以及效果将参照附图并通过以下描述的实施方式的说明来阐明。
附图说明
[图1]图1是示出本发明的第1实施方式涉及的SiC半导体装置的俯视图。
[图2]图2是沿图1所示的II-II线的截面图，示出了第1方式例涉及的组装有第二主面电极的形态。
[图3]图3是图解性示出图2所示的第二主面电极的截面图。
[图4A]图4A是图解性示出第2方式例涉及的第二主面电极的截面图。
[图4B]图4B是图解性示出第3方式例涉及的第二主面电极的截面图。
[图4C]图4C是图解性示出第4方式例涉及的第二主面电极的截面图。
[图4D]图4D是图解性示出第5方式例涉及的第二主面电极的截面图。
[图4E]图4E是图解性示出第6方式例涉及的第二主面电极的截面图。
[图4F]图4F是图解性示出第7方式例涉及的第二主面电极的截面图。
[图4G]图4G是图解性示出第8方式例涉及的第二主面电极的截面图。
[图4H]图4H是图解性示出第9方式例涉及的第二主面电极的截面图。
[图4I]图4I是图解性示出第10方式例涉及的第二主面电极的截面图。
[图5]图5是示出组装有图1所示的SiC半导体装置的半导体封装的图。
[图6]图6是本发明的第2实施方式涉及的SiC半导体装置的立体图，示出了第1方式例涉及的组装有第二主面电极的形态。
[图7]图7是图6所示的SiC半导体装置的俯视图。
[图8]图8是将第一主面电极上的结构去掉后的俯视图。
[图9]图9是示出图8所示的区域IX的内部结构的放大俯视图。
[图10]图10是沿图9所示的X-X线的截面图。
[图11]图11是沿图9所示的XI-XI线的截面图。
[图12]图12是图10所示的区域XII的放大图。
[图13]图13是沿图7所示的XIII-XIII线的截面图。
[图14]图14是示出栅极焊盘电极的截面图。
[图15]图15是示出源极焊盘电极的截面图。
[图16]图16是图解性示出第二主面电极的截面图。
[图17A]图17A是图解性示出第2方式例涉及的第二主面电极的截面图。
[图17B]图17B是图解性示出第3方式例涉及的第二主面电极的截面图。
[图17C]图17C是图解性示出第4方式例涉及的第二主面电极的截面图。
[图17D]图17D是图解性示出第5方式例涉及的第二主面电极的截面图。
[图17E]图17E是图解性示出第6方式例涉及的第二主面电极的截面图。
[图17F]图17F是图解性示出第7方式例涉及的第二主面电极的截面图。
[图17G]图17G是图解性示出第8方式例涉及的第二主面电极的截面图。
[图17H]图17H是图解性示出第9方式例涉及的第二主面电极的截面图。
[图17I]图17I是图解性示出第10方式例涉及的第二主面电极的截面图。
[图18]图18是示出组装有图6所示的SiC半导体装置的半导体封装的图。
具体实施方式
图1是示出本发明的第1实施方式涉及的SiC半导体装置的俯视图。图2是沿图1所示的II-II线的截面图，示出了第1方式例涉及的组装有第二主面电极31的形态。图3是图解性示出图2所示的第二主面电极31的截面图。
参照图1和图2，SiC半导体装置1包含SiC芯片2。SiC芯片2包含由六方晶构成的SiC单晶。由六方晶构成的SiC单晶根据原子排列的周期具有包括2H(Hexagonal，六方晶系)-SiC单晶、4H-SiC单晶、6H-SiC单晶等在内的多种多型体。SiC芯片2在本实施方式(thisembodiment)中由4H-SiC单晶构成，但并非将其他多型体除外。
SiC芯片2形成为长方体形状的芯片状。SiC芯片2具有一侧的第一主面3、另一侧的第二主面4以及将第一主面3和第二主面4连接的侧面5A、5B、5C、5D。第一主面3和第二主面4在从它们的法线方向Z观察的俯视(以下，简称为“俯视”。)中形成为四边形(该方式中为正方形)。
SiC芯片2的厚度可以为40μm以上300μm以下。SiC芯片2的厚度可以为40μm以上100μm以下、100μm以上150μm以下、150μm以上200μm以下、200μm以上250μm以下、或者250μm以上300μm以下。SiC芯片2的厚度优选为60μm以上150μm以下。
第一主面3和第二主面4面向SiC单晶的c面。第一主面3面向SiC单晶的硅面((0001)面)。第一主面3为非安装面。第二主面4面向SiC单晶的碳面((000-1)面)。第二主面4为安装面。第二主面4可以为具有研磨痕和退火痕中的任一者或者两者的粗糙面。退火痕为激光照射痕。第二主面4可以为具有退火痕的欧姆面。
第一主面3和第二主面4具有相对于SiC单晶的c面在a轴方向([11-20]方向)上以0°以上10°以下的角度倾斜的偏离角。法线方向Z相对于SiC单晶的c轴([0001]方向)仅倾斜偏离角的量。
偏离角可以为0°以上6°以下。偏离角可以为0°以上2°以下、2°以上4°以下、或者4°以上6°以下。偏离角优选大于0°且为4.5°以下。偏离角可以为3°以上4.5°以下。该情况下，偏离角优选为3°以上3.5°以下、或者3.5°以上4°以下。偏离角可以为1.5°以上3°以下。该情况下，偏离角优选为1.5°以上2°以下、或者2°以上2.5°以下。
侧面5A～5D包含第一侧面5A、第二侧面5B、第三侧面5C和第四侧面5D。第一侧面5A和第二侧面5B沿第一方向X延伸，在与第一方向X交叉的第二方向Y上彼此对置。第三侧面5C和第四侧面5D沿第二方向Y延伸，在第一方向X上彼此对置。更具体地，第二方向Y与第一方向X正交。
第一侧面5A和第二侧面5B由SiC单晶的a面形成。第一侧面5A和第二侧面5B以法线方向Z为基准时可以形成相对于法线方向Z朝向SiC单晶的c轴方向([0001]方向)倾斜的倾斜面。第一侧面5A和第二侧面5B在将法线方向Z设为0°时可以相对于法线方向Z按照与偏离角对应的角度倾斜。与偏离角对应的角度可以等于偏离角，也可以为大于0°且小于偏离角的角度。
第三侧面5C和第四侧面5D可以由SiC单晶的m面形成。第三侧面5C和第四侧面5D沿法线方向Z平面地延伸。更具体地，第三侧面5C和第四侧面5D与第一主面3和第二主面4大致垂直地形成。
侧面5A～5D可以由解理面或研磨面构成。侧面5A～5D的长度可以为0.1mm以上10mm以下。侧面5A～5D的长度优选为0.5mm以上2.5mm以下。
SiC芯片2在该方式中具有包含n+型的SiC半导体基板6和n型的SiC外延层7的层叠结构。由SiC半导体基板6形成SiC芯片2的第二主面4。由SiC外延层7形成SiC芯片2的第一主面3。由SiC半导体基板6和SiC外延层7形成SiC芯片2的侧面5A～5D。
SiC外延层7的n型杂质浓度小于SiC半导体基板6的n型杂质浓度。SiC半导体基板6的n型杂质浓度可以为1.0×1018cm-3以上1.0×1021cm-3以下。SiC外延层7的n型杂质浓度可以为1.0×1015cm-3以上1.0×1018cm-3以下。
SiC半导体基板6的厚度可以为40μm以上250μm以下。SiC半导体基板6的厚度可以为40μm以上100μm以下、100μm以上150μm以下、150μm以上200μm以下、或200μm以上250μm以下。SiC半导体基板6的厚度优选为40μm以上150μm以下。通过将SiC半导体基板6薄化，能够减小SiC半导体基板6的电阻值。
SiC外延层7的厚度可以为1μm以上50μm以下。SiC外延层7的厚度可以为1μm以上5μm以下、5μm以上10μm以下、10μm以上15μm以下、15μm以上20μm以下、20μm以上30μm以下、30μm以上40μm以下、或40μm以上50μm以下。SiC外延层7的厚度优选为5μm以上15μm以下。
SiC芯片2包含有源区域8和外侧区域9。有源区域8是包含作为功能器件(二极管)的一例的肖特基势垒二极管(Schottky Barrier Diode，SBD)的区域。有源区域8在俯视中在侧面5A～5D的内部与侧面5A～5D留有间隔地形成于SiC芯片2的中央部。有源区域8形成为在俯视中具有与侧面5A～5D平行的4条边的四边形。
外侧区域9为有源区域8的外侧的区域。外侧区域9形成于侧面5A～5D与有源区域8之间的区域。外侧区域9形成为在俯视中围绕有源区域8的环状(更具体为无端状)。
SiC半导体装置1包含在有源区域8中形成于第一主面3的表层部的n型的二极管区域10。二极管区域10形成于第一主面3的中央部。二极管区域10的平面形状是任意的。二极管区域10在俯视中可以形成为具有与侧面5A～5D平行的4条边的四边形。
二极管区域10在该方式中利用SiC外延层7的一部分来形成。二极管区域10的n型杂质浓度等于SiC外延层7的n型杂质浓度。二极管区域10的n型杂质浓度也可以大于SiC外延层7的n型杂质浓度。该情况下，二极管区域10可以通过对于SiC外延层7的表层部导入n型杂质来形成。
在外侧区域9中在第一主面3的表层部，形成有包含p型杂质的防护区域11。防护区域11的p型杂质可以未被活化，也可以被活化。
防护区域11形成为在俯视中沿二极管区域10延伸的带状。更具体地，防护区域11形成为在俯视中围绕二极管区域10的环状(更具体为无端状)。由此，防护区域11作为防护环区域形成。
有源区域8(二极管区域10)由防护区域11划定。有源区域8(二极管区域10)的平面形状由防护区域11的平面形状进行调整。防护区域11在俯视中可以形成为多边环状、圆环状。
SiC半导体装置1包含形成于第一主面3上的主面绝缘层12。主面绝缘层12可以具有包含氧化硅层和氮化硅层的层叠结构。主面绝缘层12也可以具有由氧化硅层或氮化硅层构成的单层结构。主面绝缘层12在该方式中具有由氧化硅层构成的单层结构。
主面绝缘层12包含使二极管区域10露出的接触开口13。接触开口13也使防护区域11的内周缘露出。接触开口13的平面形状是任意的。接触开口13在俯视中可以形成为具有与侧面5A～5D平行的4条边的四边形。
主面绝缘层12的周缘从侧面5A～5D露出。主面绝缘层12的周缘在该方式中与侧面5A～5D相连。主面绝缘层12的周缘也可以在侧面5A～5D的内部与侧面5A～5D留有间隔地形成。该情况下，主面绝缘层12使第一主面3中位于外侧区域9的部分露出。
主面绝缘层12的厚度可以为0.1μm以上10μm以下。主面绝缘层12的厚度可以为0.1μm以上1μm以下、1μm以上2μm以下、2μm以上4μm以下、4μm以上6μm以下、6μm以上8μm以下、或者8μm以上10μm以下。主面绝缘层12的厚度优选为0.5μm以上5μm以下。
SiC半导体装置1包含形成于第一主面3上的第一主面电极14。第一主面电极14在接触开口13内与二极管区域10和防护区域11连接。第一主面电极14从接触开口13向主面绝缘层12上引出。第一主面电极14的周缘在侧面5A～5D的内部与侧面5A～5D留有间隔地形成于主面绝缘层12上。
更具体地，第一主面电极14具有包含从第一主面3侧依次层叠的肖特基势垒层15(势垒层)和第一Al层16的层叠结构。第一Al层16作为第一缓冲层来形成，其利用具有较小杨氏模量(刚性模量)的Al的缓冲性从第一主面3侧缓和施加于SiC芯片2的外力。
肖特基势垒层15沿第一主面3和主面绝缘层12形成为膜状。肖特基势垒层15与二极管区域10之间形成肖特基结。由此，形成以第一主面电极14为阳极、以二极管区域10为阴极的SBD。即，第一主面电极14为SBD的阳极电极。
肖特基势垒层15可以包含Ti层、Pd层、Cr层、V层、Mo层、W层、Pt层和Ni层中的至少一者。肖特基势垒层15的厚度可以为0.01μm以上5μm以下。肖特基势垒层15的厚度可以为0.01μm以上0.1μm以下、0.1μm以上1μm以下、1μm以上2μm以下、2μm以上3μm以下、3μm以上4μm以下、或者4μm以上5μm以下。
第一Al层16形成于肖特基势垒层15上。第一Al层16沿肖特基势垒层15形成为膜状。第一Al层16被覆肖特基势垒层15的主面的整个区域。第一主面电极14的周缘由肖特基势垒层15和第一Al层16形成。
第一Al层16包含纯Al层(指由纯度为99％以上的Al构成的Al层。以下相同。)、AlSi合金层、AlCu合金层和AlSiCu合金层中的至少一者。第一Al层16可以具有纯Al层、AlSi合金层、AlCu合金层和AlSiCu合金层中的两者以上以任意的顺序层叠而成的层叠结构。
第一Al层16也可以具有由纯Al层、AlSi合金层、AlCu合金层或AlSiCu合金层构成的单层结构。第一Al层16优选具有由AlSi合金层、AlCu合金层或AlSiCu合金层构成的单层结构。
第一Al层16的厚度大于肖特基势垒层15的厚度。第一Al层16的厚度可以为0.05μm以上10μm以下。第一Al层16的厚度可以为0.05μm以上0.1μm以下、0.1μm以上1μm以下、1μm以上2μm以下、2μm以上4μm以下、4μm以上6μm以下、6μm以上8μm以下、或者8μm以上10μm以下。第一Al层16的厚度优选为1μm以上8μm以下。
SiC半导体装置1包含在第一主面3上被覆第一主面电极14的绝缘层17。图1中，绝缘层17由阴影来表示。更具体地，绝缘层17形成于主面绝缘层12上。绝缘层17的周缘在侧面5A～5D的内部与侧面5A～5D留有间隔地形成。由此，绝缘层17使主面绝缘层12中被覆外侧区域9的部分露出。
绝缘层17的周缘在与侧面5A～5D之间划分出划片通道DS。借助划片通道DS，在从SiC晶片切出SiC半导体装置1时，无需物理切断绝缘层17。由此，能够从SiC晶片顺畅地切出SiC半导体装置1，同时能够抑制绝缘层17的剥离、劣化。其结果是，能够利用绝缘层17来适宜保护SiC芯片2、第一主面电极14等保护对象物。
划片通道DS的宽度可以为1μm以上25μm以下。划片通道DS的宽度为与划片通道DS延伸的方向正交的方向的宽度。划片通道DS的宽度可以为1μm以上5μm以下、5μm以上10μm以下、10μm以上15μm以下、15μm以上20μm以下、或者20μm以上25μm以下。
绝缘层17具有使第一主面电极14露出的焊盘开口18。焊盘开口18在该方式中在俯视中在由接触开口13围绕的区域内使第一主面电极14露出。焊盘开口18在俯视中可以在接触开口13外的区域围绕接触开口13。焊盘开口18的平面形状是任意的。焊盘开口18在俯视中可以形成为具有与侧面5A～5D平行的4条边的四边形。
绝缘层17在该方式中具有包含从SiC芯片2侧依次层叠的钝化层19和树脂层20的层叠结构。
钝化层19可以包含氧化硅层和氮化硅层中的至少一者。钝化层19可以具有包含氧化硅层和氮化硅层的层叠结构。钝化层19也可以具有由氧化硅层或氮化硅层构成的单层结构。钝化层19优选包含与主面绝缘层12不同的绝缘材料。钝化层19在该方式中具有由氮化硅层构成的单层结构。
钝化层19沿主面绝缘层12和第一主面电极14形成为膜状。钝化层19具有使第一主面电极14的一部分露出的第一开口21。第一开口21的平面形状是任意的。第一开口21在俯视中可以形成为具有与侧面5A～5D平行的4条边的四边形。
钝化层19的厚度可以为0.1μm以上20μm以下。钝化层19的厚度可以为0.1μm以上1μm以下、1μm以上5μm以下、5μm以上10μm以下、10μm以上15μm以下、或者15μm以上20μm以下。
树脂层20沿钝化层19的主面形成为膜状。树脂层20可以包含感光性树脂。感光性树脂可以为负型或正型。树脂层20可以包含聚酰亚胺、聚酰胺和聚苯并
Figure BDA0003307685030000092
唑中的至少一种。树脂层20在该方式中包含聚苯并
Figure BDA0003307685030000091
唑。
树脂层20的周缘在该方式中使钝化层19的周缘露出。绝缘层17的周缘由树脂层20的周缘和钝化层19的周缘形成。树脂层20也可以被覆钝化层19的周缘。
树脂层20具有使第一主面电极14的一部分露出的第二开口22。第二开口22的平面形状是任意的。第二开口22在俯视中可以形成为具有与侧面5A～5D平行的4条边的四边形。第二开口22与钝化层19的第一开口21连通，在与第一开口21之间形成有1个焊盘开口18。
第二开口22的内壁可以形成为与第一开口21的内壁齐平。第二开口22的内壁也可以相对于第一开口21的内壁位于侧面5A～5D侧。第二开口22的内壁也可以相对于第一开口21的内壁位于SiC芯片2的内部。即，树脂层20可以被覆第一开口21的内壁。
树脂层20的厚度可以为1μm以上50μm以下。树脂层20的厚度可以为1μm以上10μm以下、10μm以上20μm以下、20μm以上30μm以下、30μm以上40μm以下、或者40μm以上50μm以下。
SiC半导体装置1包含形成于第一主面电极14上的焊盘电极23。焊盘电极23与第一主面电极14电连接。焊盘电极23在焊盘开口18内形成于第一主面电极14上。焊盘电极23具有与导线进行外部连接的端子面24。
端子面24相对于绝缘层17(树脂层20)的主面位于第一主面电极14侧。端子面24可以比绝缘层17(树脂层20)的主面更向上方突出。端子面24还可以具有被覆绝缘层17(树脂层20)的主面的重叠部。
焊盘电极23包含与第一主面电极14不同的金属材料。焊盘电极23在该方式中具有包含从第一主面电极14侧依次层叠的Ni层25、Pd层26和Au层27的层叠结构。Ni、Pd和Au分别具有大于Al的杨氏模量(刚性模量)的杨氏模量(刚性模量)。Ni层25、Pd层26和Au层27可以为利用镀覆法形成的镀覆层。
焊盘电极23只要包含Ni层25、Pd层26和Au层27中的至少一者即可。焊盘电极23可以具有将Ni层25、Pd层26和Au层27中至少两种以任意的顺序层叠而成的层叠结构。焊盘电极23也可以具有由Ni层25、Pd层26或Au层27构成的单层结构。
焊盘电极23优选具有由Au层27形成的端子面24。焊盘电极23优选具有至少包含从第一主面电极14侧依次层叠的Ni层25和Au层27的层叠结构。
Ni层25的厚度可以为0.1μm以上10μm以下。Ni层25的厚度可以为0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、2μm以上4μm以下、4μm以上6μm以下、6μm以上8μm以下、或者8μm以上10μm以下。
Pd层26的厚度可以为0.1μm以上10μm以下。Pd层26的厚度可以为0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、2μm以上4μm以下、4μm以上6μm以下、6μm以上8μm以下、或者8μm以上10μm以下。
Au层27的厚度可以为0.01μm以上3μm以下。Au层27的厚度可以为0.01μm以上0.05μm以下、0.05μm以上0.1μm以下、0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、或者2μm以上3μm以下。Au层27的厚度优选小于Ni层25的厚度。Au层27的厚度优选小于Pd层26的厚度。
参照图2和图3，SiC半导体装置1包含形成于第二主面4上的第二主面电极31。第二主面电极31作为SBD的阴极电极来形成。第二主面电极31在该方式中被覆第二主面4的整个区域。
第二主面电极31可以在侧面5A～5D的内部与侧面5A～5D留有间隔地形成，使第二主面4的周缘部露出。该情况下，在从SiC晶片切出SiC半导体装置1时，无需物理切断第二主面电极31。由此，能够从SiC晶片顺畅地切出SiC半导体装置1，同时能够抑制第二主面电极31的剥离、劣化。其结果是，能够使第二主面电极31与第二主面4适宜连接。
作为一例，这样的第二主面电极31可以通过在制造过程中利用隔着抗蚀剂掩模的蚀刻法将第二主面电极31的不需要的部分去除来获得。此外，作为其他例，第二主面电极31可以通过在制造过程中利用使用抗蚀剂掩模的剥离(lift-off)法形成部分被覆第二主面4的第二主面电极31来获得。
第二主面电极31包含被覆第二主面4的第二Al层32。第二Al层32隔着SiC芯片2与第一主面电极14的第一Al层16对置。第二Al层32作为第二缓冲层来形成，其利用具有较小杨氏模量(刚性模量)的Al的缓冲性而从第二主面4侧缓和施加于SiC芯片2的外力。
第二Al层32包含纯Al层、AlSi合金层、AlCu合金层和AlSiCu合金层中的至少一者。第二Al层32可以具有纯Al层、AlSi合金层、AlCu合金层和AlSiCu合金层中的两者以上以任意的顺序层叠而成的层叠结构。第二Al层32可以利用溅射法和/或蒸镀法来形成。
第二Al层32也可以具有由纯Al层、AlSi合金层、AlCu合金层或AlSiCu合金层构成的单层结构。第二Al层32的Al系金属材料可以与第一Al层16的Al系金属材料不同。第二Al层32优选具有由纯Al层构成的单层结构。
第二Al层32可以具有小于第一Al层16的厚度的厚度。第二Al层32的厚度可以为0.01μm以上5μm以下。第二Al层32的厚度可以为0.01μm以上0.1μm以下、0.1μm以上1μm以下、1μm以上2μm以下、2μm以上3μm以下、3μm以上4μm以下、或者4μm以上5μm以下。
第二主面电极31除了第二Al层32以外进一步包含由与第二Al层32不同的金属材料构成的一个或多个电极层。作为多个电极层的一例，第二主面电极31在该方式中包含从第二主面4侧依次层叠的Ti层33、Ni层34、Pd层35、Au层36和Ag层37。
Ti层33是与第二主面4之间形成欧姆接触的欧姆电极。第二Al层32隔着Ti层33、Ni层34、Pd层35、Au层36和Ag层37被覆第二主面4。
Ti、Ni、Pd、Au和Ag分别具有大于Al的杨氏模量(刚性模量)的杨氏模量(刚性模量)。Ti层33、Ni层34、Pd层35、Au层36和Ag层37可以利用溅射法、蒸镀法和/或镀覆法来形成。
作为一个或多个电极层，第二主面电极31只要包含Ti层33、Ni层34、Pd层35、Au层36和Ag层37中的至少一者即可。第二Al层32优选隔着至少Ti层33被覆第二主面4。
在第二主面电极31包含Ni层34、Pd层35和Au层36中的至少一者的情况下，Ni层34、Pd层35和Au层36中的至少一者可以为与焊盘电极23的Ni层25、Pd层26和Au层27同时形成的镀覆层。
Ti层33的厚度可以为0.01μm以上3μm以下。Ti层33的厚度可以为0.01μm以上0.05μm以下、0.05μm以上0.1μm以下、0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、或者2μm以上3μm以下。
Ni层34的厚度可以为0.1μm以上10μm以下。Ni层34的厚度可以为0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、2μm以上4μm以下、4μm以上6μm以下、6μm以上8μm以下、或者8μm以上10μm以下。Ni层34的厚度优选大于Ti层33的厚度。
Pd层35的厚度可以为0.1μm以上10μm以下。Pd层35的厚度可以为0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、2μm以上4μm以下、4μm以上6μm以下、6μm以上8μm以下、或者8μm以上10μm以下。Pd层35的厚度优选大于Ti层33的厚度。
Au层36的厚度可以为0.01μm以上3μm以下。Au层36的厚度可以为0.01μm以上0.05μm以下、0.05μm以上0.1μm以下、0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、或者2μm以上3μm以下。Au层36的厚度优选小于Ni层34的厚度。Au层36的厚度优选小于Pd层35的厚度。
Ag层37的厚度可以为0.01μm以上3μm以下。Ag层37的厚度可以为0.01μm以上0.05μm以下、0.05μm以上0.1μm以下、0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、或者2μm以上3μm以下。Ag层37的厚度优选小于Ni层34的厚度。Ag层37的厚度优选小于Pd层35的厚度。
第二主面电极31可以具有图4A～图4I所示的结构。
图4A是图解性示出第2方式例涉及的第二主面电极31的截面图。以下，对于与图1～图3中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图4A，第二主面电极31在该方式中具有包含第二Al层32、Ti层33、Ni层34、Pd层35和Au层36的层叠结构。Ti层33、Ni层34、Pd层35和Au层36从第二主面4侧依次层叠。第二Al层32隔着Ti层33、Ni层34、Pd层35和Au层36被覆第二主面4。
图4B是图解性示出第3方式例涉及的第二主面电极31的截面图。以下，对于与图1～图3中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图4B，第二主面电极31在该方式中具有包含第二Al层32、Ti层33、Ni层34、Au层36和Ag层37的层叠结构。Ti层33、Ni层34、Au层36和Ag层37从第二主面4侧依次层叠。第二Al层32隔着Ti层33、Ni层34、Au层36和Ag层37被覆第二主面4。
图4C是图解性示出第4方式例涉及的第二主面电极31的截面图。以下，对于与图1～图3中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图4C，第二主面电极31在该方式中具有包含第二Al层32、Ti层33、Ni层34和Au层36的层叠结构。Ti层33、Ni层34和Au层36从第二主面4侧依次层叠。第二Al层32隔着Ti层33、Ni层34和Au层36被覆第二主面4。
图4D是图解性示出第5方式例涉及的第二主面电极31的截面图。以下，对于与图1～图3中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图4D，第二主面电极31在该方式中具有包含第二Al层32和Ti层33的层叠结构。Ti层33与第二主面4连接。第二Al层32隔着Ti层33被覆第二主面4。
图4E是图解性示出第6方式例涉及的第二主面电极31的截面图。以下，对于与图1～图3中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图4E，第二主面电极31在该方式中包含第二Al层32、Ti层33、Ni层34和Au层36。Ti层33、Ni层34和Au层36从第二主面4侧依次层叠。第二Al层32介于Ti层33和Ni层34之间，隔着Ti层33被覆第二主面4。
该情况下，焊盘电极23优选具有由从第一主面电极14侧依次层叠的Ni层25和Au层27构成的2层结构。第二主面电极31的Ni层34和Au层36可以利用镀覆法与焊盘电极23的Ni层25和Au层27同时形成。
图4F是图解性示出第7方式例涉及的第二主面电极31的截面图。以下，对于与图1～图3中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图4F，第二主面电极31在该方式中包含第二Al层32、Ti层33、Ni层34、Au层36和Ag层37。Ti层33、Ni层34、Au层36和Ag层37从第二主面4侧依次层叠。第二Al层32介于Ti层33和Ni层34之间，隔着Ti层33被覆第二主面4。
该情况下，焊盘电极23优选具有由从第一主面电极14侧依次层叠的Ni层25和Au层27构成的2层结构。第二主面电极31的Ni层34和Au层36可以利用镀覆法与焊盘电极23的Ni层25和Au层27同时形成。
图4G是图解性示出第8方式例涉及的第二主面电极31的截面图。以下，对于与图1～图3中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图4G，第二主面电极31在该方式中包含第二Al层32、Ti层33、Ni层34、Pd层35、Au层36和Ag层37。Ti层33、Ni层34、Au层36和Ag层37从第二主面4侧依次层叠。第二Al层32介于Ti层33和Ni层34之间，隔着Ti层33被覆第二主面4。
该情况下，焊盘电极23优选具有由从第一主面电极14侧依次层叠的Ni层25、Pd层26和Au层27构成的3层结构。第二主面电极31的Ni层34、Pd层35和Au层36可以利用镀覆法与焊盘电极23的Ni层25、Pd层26和Au层27同时形成。
图4H是图解性示出第9方式例涉及的第二主面电极31的截面图。以下，对于与图1～图3中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图4H，第二主面电极31在该方式中包含第二Al层32、Ti层33、Ni层34、Pd层35和Au层36。Ti层33、Ni层34、Pd层35和Au层36从第二主面4侧依次层叠。第二Al层32介于Ti层33和Ni层34之间，隔着Ti层33被覆第二主面4。
该情况下，焊盘电极23优选具有由从第一主面电极14侧依次层叠的Ni层25、Pd层26和Au层27构成的3层结构。第二主面电极31的Ni层34、Pd层35和Au层36可以利用镀覆法与焊盘电极23的Ni层25、Pd层26和Au层27同时形成。
图4I是图解性示出第10方式例涉及的第二主面电极31的截面图。以下，对于与图1～图3中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图4I，第二主面电极31在该方式中包含第二Al层32和硅化物层38。硅化物层38形成于第二主面4。硅化物层38是从第二主面4露出的SiC被金属材料进行硅化物化而成的层。硅化物层38可以包含FeSi2层、NiSi层、NiSi2层、CoSi2层、CrSi2层、WSi2层、MoSi2层、MnSi2层、NbSi2层、TiSi2层和VSi2层中的至少一者。
第二Al层32隔着硅化物层38被覆第二主面4。第二主面电极31除了第二Al层32和硅化物层38以外可以包含Ti层33、Ni层34、Pd层35、Au层36和Ag层37中的至少一者。第二Al层32、Ti层33、Ni层34、Pd层35、Au层36和Ag层37的层叠顺序是任意的。作为被覆硅化物层38的结构，可以采用第1～第10方式例中的任一种层叠结构。
图5是示出组装有图1所示的SiC半导体装置1的半导体封装41的图。图5中，半导体封装41的内部结构透过封装主体42而示出。
参照图5，半导体封装41在该方式中为2端子型的TO-220。半导体封装41包含封装主体42、金属板43、第一端子44、第二端子45、SiC半导体装置1、导电接合材46和导线47。
封装主体42由模制树脂构成。封装主体42可以包含作为模制树脂的一例的环氧树脂。封装主体42形成为长方体形状。封装主体42包含一侧的第一面48和另一侧的第二面49以及将第一面48和第二面49连接的4个侧面50A、50B、50C、50D。
更具体地，4个侧面50A～50D包含第一侧面50A、第二侧面50B、第三侧面50C和第四侧面50D。第一侧面50A和第二侧面50B彼此对置。第三侧面50C和第四侧面50D彼此对置。
金属板43可以包含Fe、Au、Ag、Cu和Al中的至少一种。金属板43可以具有形成有镀Ni膜、镀Au膜、镀Ag膜和镀Cu膜中的至少一种的外表面。金属板43的平面形状是任意的。金属板43在该方式中在俯视中形成为四边形(长方形)。
金属板43一体地包含位于封装主体42内的焊盘部51以及位于封装主体42外的散热部52。散热部52从焊盘部51横穿第二侧面50B而引出至封装主体42外。散热部52包含贯通孔52a。贯通孔52a形成为圆形。
金属板43在该方式中以从第二面49露出的方式配置于封装主体42内。金属板43也可以以不从第二面49露出的方式配置于封装主体42内。
第一端子44可以包含Fe、Au、Ag、Cu和Al中的至少一种。第一端子44可以具有形成有镀Ni膜、镀Au膜、镀Ag膜和镀Cu膜中的至少一种的外表面。第一端子44从封装主体42内横穿第一侧面50A而引出至封装主体42外。第一端子44在俯视中配置于第四侧面50D侧的区域。第一端子44相对于金属板43的板面配置于第一面48侧的区域。
第一端子44包含第一内端部53、第一外端部54和第一带状部55。第一内端部53在封装主体42内与金属板43连接。第一外端部54配置于封装主体42外。第一带状部55在第一内端部53和第一外端部54之间在与第一侧面50A正交的方向上延伸。
第二端子45可以包含Fe、Au、Ag、Cu和Al中的至少一种。第二端子45还可以包含镀Ni膜、镀Au膜、镀Ag膜和镀Cu膜中的至少一种。第二端子45从封装主体42内横穿第一侧面50A而引出至封装主体42外。
第二端子45在俯视中与第一端子44留有间隔地配置于第三侧面50C侧的区域。第二端子45相对于金属板43的板面配置于第一面48侧的区域。
第二端子45包含第二内端部56、第二外端部57和第二带状部58。第二内端部56与金属板43留有间隔地配置于封装主体42内。第二外端部57配置于封装主体42外。第二带状部58在第二内端部56和第二外端部57之间在与第一侧面50A正交的方向上延伸。
SiC半导体装置1在封装主体42内配置于金属板43的焊盘部51上。导电接合材46介于SiC半导体装置1和焊盘部51之间，使SiC半导体装置1的第二主面电极31与焊盘部51接合。由此，SiC半导体装置1经由金属板43与第一端子44电连接。
导电接合材46可以为金属膏或焊料。金属膏可以包含Au、Ag和Cu中的至少一种。导电接合材46优选由焊料构成。焊料可以为无铅焊料。焊料可以包含SnAgCu、SnZnBi、SnCu、SnCuNi和SnSbNi中的至少一种。
导线47由金属丝(接合线)或金属夹构成。金属丝可以为Al丝、Au丝、Cu丝或焊料丝。焊料丝可以为无铅焊料丝。焊料丝可以包含SnAgCu、SnZnBi、SnCu、SnCuNi和SnSbNi中的至少一种。金属夹可以为Al夹、Au夹或Cu夹。导线47在该方式中由焊料丝构成。
导线47在封装主体42内与第二端子45的第二内端部56以及SiC半导体装置1的焊盘电极23连接。由此，SiC半导体装置1与第二端子45电连接。
图6中，示出了1个导线47与第二内端部56以及焊盘电极23连接的例子，但导线47的个数是任意的。也可以是2个以上的导线47与第二内端部56以及焊盘电极23连接。
半导体封装41也可以采用TO-220以外的形态。半导体封装41可以具有小外型封装(Small Outline Package，SOP)、方型扁平无引脚封装(Quad For Non Lead Package，QFN)、双侧引脚扁平封装(Dual Flat Package，DFP)、双直插式封装(Dual InlinePackage，DIP)、方型扁平封装(Quad Flat Package，QFP)、单列直插式封装(Single InlinePackage，SIP)或J型引脚小外型封装(Small Outline J-leaded Package，SOJ)、或者与它们相类似的各种各样的形态。
以上，根据SiC半导体装置1，第一Al层16作为在第一主面3侧缓和外力的第一缓冲层来形成，第二Al层32作为在第二主面4侧缓和外力的第二缓冲层来形成。由此，能够缓和从第一主面3朝向第二主面4的方向的外力以及从第二主面4朝向第一主面3的方向的外力。
作为一例，在将SiC半导体装置1安装于金属板43的焊盘部51时能够借助第一Al层16和第二Al层32来缓和施加于SiC芯片2的外力。此外，在将导线47与SiC半导体装置1的焊盘电极23接合时能够借助第一Al层16和第二Al层32来缓和施加于SiC芯片2的外力。其结果是，能够抑制SiC芯片2的裂纹。
此外，SiC半导体装置1包含与导线47外部接合的焊盘电极23。焊盘电极23包含Ni层25、Pd层26和Au层27中至少一者。由此，能够将导线47与焊盘电极23适宜连接。
另一方面，Ni、Pd和Au分别具有大于Al的杨氏模量(刚性模量)的杨氏模量(刚性模量)。因此，在具备焊盘电极23的结构中，无法适当缓和导线47接合时所施加的外力。
对此，SiC半导体装置1中，在介于SiC芯片2与焊盘电极23之间存在包含Al的第一Al层16。借助第一Al层16，能够利用具有较小的杨氏模量(刚性模量)的Al的缓冲性来从第一主面3侧缓和施加于SiC芯片2的外力。由此，能够使导线47与焊盘电极23适宜接合，同时能够抑制SiC芯片2的裂纹。
此外，SiC半导体装置1除了第二Al层32以外还包含具有由与第二Al层32不同的金属材料构成的1个或多个电极层的第二主面电极31。1个或多个电极层包含Ti层33、Ni层34、Pd层35、Au层36和Ag层37中的至少一者。由此，能够适当提高导电接合材46对于第二主面电极31的密合力。其结果是，能够将SiC半导体装置1适宜安装于金属板43的焊盘部51。
另一方面，Ti、Ni、Pd、Au和Ag分别具有大于Al的杨氏模量(刚性模量)的杨氏模量(刚性模量)。因此，在第二主面电极31包含Ti层33、Ni层34、Pd层35、Au层36和Ag层37中的至少1者的结构中，无法适当缓和SiC半导体装置1安装时、导线47接合时所施加的外力。
对此，SiC半导体装置1中，形成除了Ti层33、Ni层34、Pd层35、Au层36和Ag层37中的至少一者以外还包含第二Al层32的第二主面电极31。借助第二Al层32，能够利用具有较小的杨氏模量(刚性模量)的Al的缓冲性来从第二主面4侧缓和施加于SiC芯片2的外力。由此，能够将SiC半导体装置1适宜安装于焊盘部51，同时能够抑制SiC芯片2的裂纹。
图6是本发明的第二实施方式涉及的SiC半导体装置61的立体图，示出了第1方式例涉及的组装有第二主面电极200的形态。图7是图6所示的SiC半导体装置61的俯视图。图8是将第一主面电极150上的结构去掉后的俯视图。
图9是示出图8所示的区域IX的内部结构的放大俯视图。图10是沿图9所示的X-X线的截面图。图11是沿图9所示的XI-XI线的截面图。图12是图10所示的区域XII的放大图。
图13是沿图7所示的XIII-XIII线的截面图。图14是示出栅极焊盘电极191的截面图。图15是示出源极焊盘电极192的截面图。图16是图解性示出第二主面电极200的截面图。图14和图15是示出栅极焊盘电极191和源极焊盘电极192的概略结构的截面图，没有示出特定部位的截面。
参照图6～图13，SiC半导体装置61包含SiC芯片62。SiC芯片62包含由六方晶构成的SiC单晶。由六方晶构成的SiC单晶根据原子排列的周期具有包括2H(Hexagonal，六方晶系)-SiC单晶、4H-SiC单晶、6H-SiC单晶等在内的多种多型体。SiC芯片62在该方式中由4H-SiC单晶构成，但并非将其他多型体排除。
SiC芯片62具有一侧的第一主面63、另一侧的第二主面64、以及将第一主面63和第二主面64连接的侧面65A、65B、65C、65D。第一主面63和第二主面64在从它们的法线方向Z观察的俯视(以下，简称为“俯视”。)中形成为四边形(该方式中为长方形)。
SiC芯片62的厚度可以为40μm以上300μm以下。SiC芯片62的厚度可以为40μm以上100μm以下、100μm以上150μm以下、150μm以上200μm以下、200μm以上250μm以下、或者250μm以上300μm以下。SiC芯片62的厚度优选为60μm以上150μm以下。
第一主面63和第二主面64在该方式中面向SiC单晶的c面。第一主面63面向SiC单晶的硅面((0001)面)。第一主面63为非安装面。第二主面64面向SiC单晶的碳面((000-1)面)。第二主面64为安装面。第二主面64可以为具有研磨痕和退火痕中的任一者或者两者的粗糙面。退火痕为激光照射痕。第二主面64可以为具有退火痕的欧姆面。
第一主面63和第二主面64具有相对于SiC单晶的c面在a轴方向([11-20]方向)上以0°以上10°以下的角度倾斜的偏离角。法线方向Z相对于SiC单晶的c轴([0001]方向)仅倾斜偏离角的量。
偏离角可以为0°以上6°以下。偏离角可以为0°以上2°以下、2°以上4°以下、或者4°以上6°以下。偏离角优选大于0°且为4.5°以下。偏离角可以为3°以上4.5°以下。该情况下，偏离角优选为3°以上3.5°以下、或者3.5°以上4°以下。偏离角可以为1.5°以上3°以下。该情况下，偏离角优选为1.5°以上2°以下、或者2°以上2.5°以下。
侧面65A～65D包含第一侧面65A、第二侧面65B、第三侧面65C和第四侧面65D。第一侧面65A和第二侧面65B沿第一方向X延伸，在与第一方向X交叉的第二方向Y上对置。第一侧面65A和第二侧面65B在俯视中形成SiC芯片62的短边。第三侧面65C和第四侧面65D沿第二方向Y延伸，在第一方向X上对置。第三侧面65C和第四侧面65D在俯视中形成SiC芯片62的长边。更具体地，第二方向Y与第一方向X正交。
第一方向X在该方式中为SiC单晶的m轴方向([1-100]方向)。第二方向Y为SiC单晶的a轴方向([11-20]方向)。即，第一侧面65A和第二侧面65B由SiC单晶的a面形成，在SiC单晶的a轴方向上对置。此外，第三侧面65C和第四侧面65D由SiC单晶的m面形成，在SiC单晶的m轴方向上对置。
第一侧面65A和第二侧面65B以法线方向Z为基准时可以形成相对于法线方向Z朝向SiC单晶的c轴方向([0001]方向)倾斜的倾斜面。第一侧面65A和第二侧面65B在将法线方向Z设为0°时可以相对于法线方向Z按照与偏离角对应的角度倾斜。与偏离角对应的角度可以等于偏离角，也可以为大于0°且小于偏离角的角度。
第三侧面65C和第四侧面65D沿法线方向Z平面地延伸。更具体地，第三侧面65C和第四侧面65D相对于第一主面63和第二主面64大致垂直地形成。
侧面65A～65D可以由解理面或研磨面构成。侧面65A～65D的长度可以为0.1mm以上10mm以下。侧面65A～65D的长度优选为0.5mm以上2.5mm以下。
SiC芯片62在该方式中具有包含n+型的SiC半导体基板66和n型的SiC外延层67的层叠结构。SiC半导体基板66作为漏极区域68来形成。SiC外延层67作为漂移区域69来形成。
由SiC半导体基板66形成SiC芯片62的第二主面64。由SiC外延层67形成SiC芯片62的第一主面63。由SiC半导体基板66和SiC外延层67形成SiC芯片62的侧面65A～65D。
SiC半导体基板66的厚度可以为40μm以上250μm以下。SiC半导体基板66的厚度可以为40μm以上100μm以下、100μm以上150μm以下、150μm以上200μm以下、或者200μm以上250μm以下。SiC半导体基板66的厚度优选为40μm以上150μm以下。通过将SiC半导体基板66薄化，能够减小SiC半导体基板66的电阻值。
SiC外延层67的厚度可以为1μm以上50μm以下。SiC外延层67的厚度可以为1μm以上5μm以下、5μm以上10μm以下、10μm以上15μm以下、15μm以上20μm以下、20μm以上30μm以下、30μm以上40μm以下、或者40μm以上50μm以下。SiC外延层67的厚度优选为5μm以上15μm以下。
SiC外延层67的n型杂质浓度小于SiC半导体基板66的n型杂质浓度。SiC半导体基板66的n型杂质浓度可以为1.0×1018cm-3以上1.0×1021cm-3以下。SiC外延层67的n型杂质浓度可以为1.0×1015cm-3以上1.0×1018cm-3以下。
SiC外延层67在该方式中具有沿法线方向Z具有不同的n型杂质浓度的多个区域。更具体地，SiC外延层67包含n型杂质浓度较高的高浓度区域70以及n型杂质浓度比高浓度区域70低的低浓度区域71。
高浓度区域70形成于第一主面63侧的区域。低浓度区域71相对于高浓度区域70形成于第二主面64侧的区域。高浓度区域70的厚度小于低浓度区域71的厚度。高浓度区域70的厚度小于SiC外延层67的总厚度的2分之1。
高浓度区域70的n型杂质浓度的峰值可以为1.0×1016cm-3以上1.0×1018cm-3以下。低浓度区域71的n型杂质浓度的峰值可以为1.0×1015cm-3以上1.0×1016cm-3以下。
SiC芯片62包含有源区域72和外侧区域73。有源区域72是形成有作为功能器件(晶体管)的一例的金属绝缘体半导体场效应晶体管(Metal Insulator Semiconductor FieldEffect Transistor，MISFET)的区域。
有源区域72在俯视中在侧面65A～65D的内部与侧面65A～65D留有间隔地形成于SiC芯片62的中央部。有源区域72形成为在俯视中具有与侧面65A～65D平行的4条边的四边形(该方式中为长方形)。
外侧区域73为有源区域72的外侧的区域。外侧区域73形成于侧面65A～65D与有源区域72的周缘之间的区域。外侧区域73形成为在俯视中围绕有源区域72的环状(更具体地为无端状)。
SiC半导体装置61在有源区域72中包含形成于第一主面63的表层部的p型的主体区域74。主体区域74划定有源区域72。主体区域74的p型杂质浓度的峰值可以为1.0×1017cm-3以上1.0×1019cm-3以下。主体区域74的p型杂质浓度的峰值优选为1.0×1018cm-3以上。
参照图9～图12，SiC半导体装置61在有源区域72中包含形成于第一主面63的多个沟槽栅极结构75。多个沟槽栅极结构75分别形成为沿第一方向X延伸的带状，沿第二方向Y留有间隔地形成。多个沟槽栅极结构75在俯视中整体上形成为条带状。
多个沟槽栅极结构75在该方式中在有源区域72中从一侧(第三侧面65C侧)的周缘部朝向另一侧(第四侧面65D侧)的周缘部以带状延伸。多个沟槽栅极结构75在有源区域72中横穿一侧的周缘部与另一侧的周缘部之间的中间部。
各沟槽栅极结构75的长度可以为1mm以上10mm以下。各沟槽栅极结构75的长度可以为1mm以上2mm以下、2mm以上4mm以下、4mm以上6mm以下、6mm以上8mm以下、或者8mm以上10mm以下。各沟槽栅极结构75的长度优选为2mm以上6mm以下。1个沟槽栅极结构75的每单位面积的总延长可以为0.5μm/μm2以上0.75μm/μm2以下。
各沟槽栅极结构75包含有源部76和接触部77。有源部76为沿MISFET的沟道的部分。接触部77为MISFET的沟道外的部分。接触部77为沟槽栅极结构75的端部，以外部连接作为主要目的。
各沟槽栅极结构75包含栅极沟槽78、栅极绝缘层79和栅电极80。图9中，由阴影示出了栅极绝缘层79和栅电极80。
栅极沟槽78以贯通主体区域74的方式形成于SiC外延层67。栅极沟槽78包含侧壁和底壁。形成栅极沟槽78的长边的侧壁由SiC单晶的a面形成。形成栅极沟槽78的短边的侧壁由SiC单晶的m面形成。
栅极沟槽78的侧壁可以沿法线方向Z延伸。在SiC芯片62内栅极沟槽78的侧壁与第一主面63所成的角度可以为90°以上95°以下(例如91°以上93°以下)。栅极沟槽78的侧壁可以形成为与第一主面63大体垂直。栅极沟槽78在截面图中可以形成为底壁侧的开口面积小于开口侧的开口面积的锥面形状。
栅极沟槽78的底壁位于高浓度区域70。栅极沟槽78的底壁面向SiC单晶的c面。栅极沟槽78的底壁具有相对于SiC单晶的(0001)面在[11-20]方向上倾斜的偏离角。栅极沟槽78的底壁可以与第一主面63平行地形成。栅极沟槽78的底壁可以形成为朝向第二主面64的弯曲状。
在法线方向Z上，栅极沟槽78的深度可以为0.5μm以上3.0μm以下。栅极沟槽78的深度可以为0.5μm以上1.0μm以下、1.0μm以上1.5μm以下、1.5μm以上2.0μm以下、2.0μm以上2.5μm以下、或者2.5μm以上3.0μm以下。
栅极沟槽78的沿第二方向Y的宽度可以为0.1μm以上2μm以下。栅极沟槽78的宽度可以为0.1μm以上0.5μm以下、0.5μm以上1.0μm以下、1.0μm以上1.5μm以下、或者1.5μm以上2μm以下。
栅极沟槽78的开口边缘部包含从第一主面63朝向栅极沟槽78的内部向下倾斜的倾斜部。栅极沟槽78的开口边缘部是连接第一主面63与栅极沟槽78的侧壁的部分。
栅极沟槽78的倾斜部形成为朝向SiC芯片62的内部的弯曲状。栅极沟槽78的倾斜部也可以形成为朝向栅极沟槽78的内部的弯曲状。栅极沟槽78的倾斜部缓和对于栅极沟槽78的开口边缘部的电场集中。
栅极绝缘层79包含氧化硅、氮化硅、氧化铝、氧化锆和氧化钽中的至少一种。栅极绝缘层79可以具有包含氮化硅层和氧化硅层的层叠结构。栅极绝缘层79也可以具有由氧化硅层或氮化硅层构成的单层结构。栅极绝缘层79在该方式中具有由氧化硅层构成的单层结构。
栅极绝缘层79沿栅极沟槽78的内壁形成为膜状，在栅极沟槽78内划分出凹槽空间。栅极绝缘层79包含第一区域81、第二区域82和第三区域83。
第一区域81沿栅极沟槽78的侧壁形成。第二区域82沿栅极沟槽78的底壁形成。第三区域83沿第一主面63形成。
第一区域81的厚度小于第二区域82的厚度和第三区域83的厚度。第一区域81的厚度可以为0.01μm以上0.2μm以下。第二区域82的厚度可以为0.05μm以上0.5μm以下。第三区域83的厚度可以为0.05μm以上0.5μm以下。
栅极绝缘层79包含在开口边缘部朝向栅极沟槽78内鼓出的鼓出部84。鼓出部84形成于连接栅极绝缘层79的第一区域81与第三区域83的角部。鼓出部84形成为朝向栅极沟槽78的内部的弯曲状。鼓出部84在开口边缘部使栅极沟槽78的开口变窄。也可以形成没有鼓出部84的栅极绝缘层79。也可以形成具有一样的厚度的栅极绝缘层79。
栅电极80隔着栅极绝缘层79埋入于栅极沟槽78。更具体地，栅电极80在栅极沟槽78内埋入于由栅极绝缘层79划分出的凹槽空间。
栅电极80具有位于栅极沟槽78的开口侧的上端部。栅电极80的上端部形成为朝向栅极沟槽78的底壁凹陷的弯曲状。栅电极80的上端部具有沿栅极绝缘层79的鼓出部84内缩的内缩部。
栅电极80包含添加有p型杂质的p型多晶硅。栅电极80的p型杂质可以包含硼、铝、铟和镓中的至少一种。
栅电极80的p型杂质浓度大于主体区域74的p型杂质浓度。栅电极80的p型杂质浓度可以为1.0×1018cm-3以上1.0×1022cm-3以下。栅电极80的薄层电阻可以为10Ω/□以上500Ω/□以下(该方式中为200Ω/□左右)。栅电极80的厚度可以为0.5μm以上3μm以下。
参照图9和图11，SiC半导体装置61在有源区域72中包含形成于第一主面63上的栅极配线85。图9中，由阴影示出了栅极配线85。更具体地，栅极配线85形成于栅极绝缘层79的第三区域83上。栅极配线85在有源区域72中沿第一侧面65A、第三侧面65C和第四侧面65D形成，从3个方向划分出形成有多个沟槽栅极结构75的区域。
栅极配线85与从沟槽栅极结构75的接触部77露出的栅电极80连接。栅极配线85在该方式中由从栅极沟槽78引出至第一主面63上的栅电极80的引出部形成。栅极配线85的上端部与栅电极80的上端部连接。
SiC半导体装置61包含被覆栅电极80的低电阻层86。低电阻层86在栅极沟槽78内被覆栅电极80的上端部。低电阻层86形成沟槽栅极结构75的一部分。
低电阻层86包含具有小于栅电极80的薄层电阻的薄层电阻的导电材料。低电阻层86的薄层电阻可以为0.01Ω/□以上10Ω/□以下。
更具体地，低电阻层86包含多晶硅化金属层。多晶硅化金属层通过形成栅电极80的表层部的部分被金属材料进行硅化物化而形成。更具体地，多晶硅化金属层由包含添加于栅电极80(p型多晶硅)的p型杂质的p型多晶硅化金属层构成。多晶硅化金属层优选具有10μΩ·cm以上110μΩ·cm以下的电阻率。
埋入有栅电极80和低电阻层86的栅极沟槽78内的薄层电阻为栅电极80单独的薄层电阻以下。栅极沟槽78内的薄层电阻优选为添加有n型杂质的n型多晶硅的薄层电阻以下。
栅极沟槽78内的薄层电阻近似于低电阻层86的薄层电阻。即，栅极沟槽78内的薄层电阻可以为0.01Ω/□以上10Ω/□以下。栅极沟槽78内的薄层电阻优选小于10Ω/□。
低电阻层86可以包含TiSi、TiSi2、NiSi、CoSi、CoSi2、MoSi2和WSi2中的至少一种。尤其，这些种类中的NiSi、CoSi2和TiSi2的电阻率值以及温度依赖性较小，因此适合作为形成低电阻层86的多晶硅化金属层。低电阻层86最优选由具有向其他区域的扩散少的性质的CoSi2构成。
低电阻层86包含与栅极绝缘层79相接的接触部。更具体地，低电阻层86的接触部与栅极绝缘层79的第三区域83(鼓出部84)相接。低电阻层86的接触部相对于主体区域74的底部形成于第一主面63侧的区域。更具体地，低电阻层86的接触部相对于后述的源极区域97的底部形成于第一主面63侧的区域。低电阻层86隔着栅极绝缘层79与主体区域74对置。
由此，能够抑制在低电阻层86与主体区域74之间形成电流通路。特别是，使低电阻层86的接触部与栅极绝缘层79中较厚的角部连接的设计在降低电流通路的风险方面是有效的。
在法线方向Z上，低电阻层86的厚度优选小于栅电极80的厚度。低电阻层86的厚度可以为0.01μm以上3μm以下。
低电阻层86也被覆栅极配线85的上端部。低电阻层86中被覆栅极配线85的上端部的部分与低电阻层86中被覆栅电极80的上端部的部分一体地形成。由此，低电阻层86被覆栅电极80的整个区域和栅极配线85的整个区域。
通过将具有与n型多晶硅不同的功函数的p型多晶硅埋入至栅极沟槽78，能够使栅极阈值电压Vth增加1V左右。但是，p型多晶硅具有比n型多晶硅的薄层电阻高数十倍(大约20倍)的薄层电阻。因此，在采用p型多晶硅作为栅电极80的材料的情况下，伴随栅极沟槽78内的寄生电阻(以下，简称为“栅极电阻”。)的增加而能量损失增大。
因此，SiC半导体装置61中，在栅电极80(p型多晶硅)上形成低电阻层86(p型多晶硅化金属)。利用低电阻层86，能够在允许栅极阈值电压Vth增加(例如增加1V左右)的同时，减小栅极沟槽78内的薄层电阻。
例如，利用具有低电阻层86的结构，与没有低电阻层86的情况相比，能够使薄层电阻降低至100分之1以下。此外，利用具有低电阻层86的结构，与包含n型多晶硅的栅电极80相比，能够使薄层电阻降低至5分之1以下。
由此，能够减小栅极电阻，因此能够使电流沿沟槽栅极结构75有效扩散。即，低电阻层86作为在栅极沟槽78内扩散电流的电流扩散层来形成。特别是，在具有毫米量级的长度(1mm以上的长度)的栅极沟槽78的情况下，电流的传递需要时间，但利用低电阻层86，能够适当抑制开关延迟。
此外，利用具有低电阻层86的结构，在提高栅极阈值电压Vth方面无需增加主体区域74的p型杂质浓度。因此，能够在抑制沟道电阻的增加的同时，适当增加栅极阈值电压Vth。
SiC半导体装置61包含在彼此相邻的多个沟槽栅极结构75之间的区域分别形成的多个沟槽源极结构91。多个沟槽源极结构91按照夹持1个沟槽栅极结构75的方式在第二方向Y(SiC单晶的a轴方向)上留有间隔地形成。
多个沟槽源极结构91分别形成为沿第一方向X(SiC单晶的m轴方向)延伸的带状。多个沟槽源极结构91在俯视中整体上形成为条带状。在第二方向Y上，彼此相邻的沟槽源极结构91的中央部间的间距可以为1.5μm以上3μm以下。
各沟槽源极结构91包含源极沟槽92、源极绝缘层93和源电极94。图9中，由阴影示出了源极绝缘层93和源电极94。
源极沟槽92以贯通主体区域74的方式形成于SiC外延层67。源极沟槽92包含侧壁和底壁。形成源极沟槽92的长边的侧壁由SiC单晶的a面形成。形成源极沟槽92的短边的侧壁由SiC单晶的m面形成。
源极沟槽92的侧壁可以沿法线方向Z延伸。在SiC芯片62内源极沟槽92的侧壁与第一主面63所成的角度可以为90°以上95°以下(例如91°以上93°以下)。源极沟槽92的侧壁可以形成为与第一主面63大体垂直。源极沟槽92在截面图中可以形成为底壁侧的开口面积小于开口侧的开口面积的锥面形状。
源极沟槽92的底壁位于高浓度区域70。源极沟槽92的底壁相对于栅极沟槽78的底壁位于第二主面64侧的区域。源极沟槽92的底壁在法线方向Z上位于栅极沟槽78的底壁与低浓度区域71之间的区域。
源极沟槽92的底壁面向SiC单晶的c面。源极沟槽92的底壁具有相对于SiC单晶的(0001)面在[11-20]方向上倾斜的偏离角。源极沟槽92的底壁可以相对于第一主面63平行地形成。源极沟槽92的底壁可以形成为朝向第二主面64的弯曲状。
源极沟槽92的深度大于栅极沟槽78的深度。源极沟槽92的深度与栅极沟槽78的深度之比在源极沟槽92位于高浓度区域70内的这样的条件下可以为1.5以上。源极沟槽92的深度与栅极沟槽78的深度之比优选为2以上。源极沟槽92的深度也可以等于栅极沟槽78的深度。在法线方向Z上，源极沟槽92的深度可以为0.5μm以上10μm以下(例如2μm左右)。
源极沟槽92的沿第二方向Y的宽度可以大于栅极沟槽78的沿第二方向Y的宽度，也可以小于栅极沟槽78的沿第二方向Y的宽度。源极沟槽92的沿第二方向Y的宽度优选等于栅极沟槽78的沿第二方向Y的宽度。源极沟槽92的沿第二方向Y的宽度可以为0.1μm以上2μm以下(例如0.5μm左右)。
源极绝缘层93包含氧化硅、氮化硅、氧化铝、氧化锆或氧化钽中的至少一种。源极绝缘层93可以具有包含氮化硅层和氧化硅层的层叠结构。源极绝缘层93也可以具有由氧化硅层或氮化硅层构成的单层结构。源极绝缘层93在该方式中具有由氧化硅层构成的单层结构。
源极绝缘层93沿源极沟槽92的内壁形成为膜状，在源极沟槽92内划分出凹槽空间。源极绝缘层93包含第一区域95和第二区域96。
第一区域95沿源极沟槽92的侧壁形成。第二区域96沿源极沟槽92的底壁形成。第一区域95的厚度小于第二区域96的厚度。第一区域95的厚度可以为0.01μm以上0.2μm以下。第二区域96的厚度可以为0.05μm以上0.5μm以下。
第一区域95的厚度可以与栅极绝缘层79的第一区域95的厚度大体相等。第二区域96的厚度可以与栅极绝缘层79的第二区域96的厚度大体相等。可以形成具有一样的厚度的源极绝缘层93。
源电极94隔着源极绝缘层93埋入于源极沟槽92。更具体地，源电极94在源极沟槽92中埋入于被源极绝缘层93划分出的凹槽空间。
源电极94具有位于源极沟槽92的开口侧的上端部。源电极94的上端部相对于第一主面63形成于源极沟槽92的底壁侧。源电极94的上端部可以位于比第一主面63更上方。
源电极94的上端部形成为朝向源极沟槽92的底壁凹陷的弯曲状。源电极94的上端部可以与第一主面63平行地形成。在法线方向Z上，源电极94的厚度可以为0.5μm以上10μm以下(例如1μm左右)。
源电极94优选包含材质上具有与SiC相近的性质的多晶硅。由此，能够减小SiC芯片62内产生的应力。源电极94在该方式中包含添加有p型杂质的p型多晶硅。该情况下，可以与栅电极80同时形成源电极94。
源电极94的p型杂质浓度大于主体区域74的p型杂质浓度。源电极94的p型杂质浓度可以等于栅电极80的p型杂质浓度。源电极94的p型杂质浓度可以为1.0×1018cm-3以上1.0×1022cm-3以下。
源电极94的p型杂质可以包含硼、铝、铟和镓中的至少一种。源电极94的薄层电阻可以为10Ω/□以上500Ω/□以下(该方式中为200Ω/□左右)。源电极94的薄层电阻可以等于栅电极80的薄层电阻。
源电极94可以包含n型多晶硅、钨、铝、铜、铝合金和铜合金中的至少一种来代替p型多晶硅或者除了p型多晶硅以外进一步包含n型多晶硅、钨、铝、铜、铝合金和铜合金中的至少一种。
SiC半导体装置61包含在主体区域74的表层部形成于沿栅极沟槽78的侧壁的区域的n+型的源极区域97。源极区域97的n型杂质浓度的峰值可以为1.0×1018cm-3以上1.0×1021cm-3以下。源极区域97的n型杂质浓度的峰值优选为1.0×1020cm-3以上。
源极区域97沿栅极沟槽78的一侧的侧壁和另一侧的侧壁形成有多个。多个源极区域97分别形成为沿第一方向X延伸的带状。多个源极区域97在俯视中整体上形成为条带状。各源极区域97从栅极沟槽78的侧壁和各源极沟槽92的侧壁露出。
源极区域97中沿栅极沟槽78的侧壁的部分与高浓度区域70之间划定MISFET的沟道。沟道的ON/OFF由栅电极80控制。
SiC半导体装置61包含在第一主面63的表层部形成于沿各源极沟槽92的区域的p+型的接触区域98。各接触区域98的p型杂质浓度的峰值大于主体区域74的p型杂质浓度的峰值。各接触区域98的p型杂质浓度的峰值可以为1.0×1018cm-3以上1.0×1021cm-3以下。
接触区域98在该方式中相对于1个源极沟槽92形成有多个。多个接触区域98沿所对应的源极沟槽92留有间隔地形成。多个接触区域98与栅极沟槽78留有间隔地形成。
各接触区域98被覆所对应的源极沟槽92的侧壁和底壁。各接触区域98的底部可以与所对应的源极沟槽92的底壁平行地形成。
各接触区域98中被覆源极沟槽92的侧壁的部分相对于主体区域74的底部形成于第一主面63侧的区域。各接触区域98中被覆源极沟槽92的侧壁的部分朝向相邻的栅极沟槽78引出。各接触区域98中被覆源极沟槽92的侧壁的部分可以延伸至栅极沟槽78与源极沟槽92之间的中间区域。各接触区域98与主体区域74和源极区域97电连接。
SiC半导体装置61包含在有源区域72中形成于第一主面63的表层部的深阱区域99。深阱区域99相对于多个源极沟槽92以1对1对应的关系形成有多个。各深阱区域99形成为在俯视中沿所对应的源极沟槽92延伸的带状。
各深阱区域99形成于高浓度区域70。各深阱区域99隔着各接触区域98被覆各源极沟槽92。各深阱区域99隔着所对应的接触区域98被覆源极沟槽92的侧壁和底壁。各深阱区域99在第一主面3的表层部与主体区域74相连。
各深阱区域99具有相对于栅极沟槽78的底壁位于第二主面64侧的底部。各深阱区域99的底部可以与各源极沟槽92的底壁平行地形成。多个深阱区域99优选按照固定的深度形成。
各深阱区域99的p型杂质浓度的峰值可以小于接触区域98的p型杂质浓度的峰值。各深阱区域99的p型杂质浓度的峰值可以等于主体区域74的p型杂质浓度的峰值。各深阱区域99的p型杂质浓度的峰值也可以大于主体区域74的p型杂质浓度的峰值，也可以小于主体区域74的p型杂质浓度的峰值。
各深阱区域99的p型杂质浓度的峰值可以为1.0×1017cm-3以上1.0×1019cm-3以下。各深阱区域99的p型杂质浓度的峰值优选为1.0×1018cm-3以上。
各深阱区域99与高浓度区域70之间形成pn结部。从该pn结部开始，耗尽层朝向栅极沟槽78扩展。耗尽层可以与栅极沟槽78的底壁重叠。
SiC半导体装置61包含在有源区域72的周缘部形成于第一主面63的表层部的p型的周缘阱区域100。周缘阱区域100被覆沟槽栅极结构75的接触部77，使有源部76露出。
周缘阱区域100在所对应的接触部77中被覆栅极沟槽78的侧壁和底壁。周缘阱区域100的底部相对于深阱区域99的底壁位于第一主面63侧。各周缘阱区域100在第一主面63的表层部与主体区域74和深阱区域99电连接。
周缘阱区域100的p型杂质浓度可以与深阱区域99的p型杂质浓度大体相等。周缘阱区域100的p型杂质浓度的峰值可以为1.0×1017cm-3以上1.0×1019cm-3以下。周缘阱区域100的p型杂质浓度的峰值优选为1.0×1018cm-3以上。
在仅具备pn结二极管的SiC半导体装置中，由于是不具备沟槽的这样的结构，因此SiC芯片62内的电场集中的问题少。各深阱区域99使沟槽栅极型的MISFET接近于pn结二极管的结构。
由此，在沟槽栅极型的MISFET中，能够缓和SiC芯片62内的电场。因此，使彼此相邻的多个深阱区域99之间的间距变窄在缓和电场集中方面是有效的。
此外，利用相对于栅极沟槽78的底壁在第二主面64侧具有底部的深阱区域99，能够通过耗尽层适当缓和对于栅极沟槽78的电场集中。多个深阱区域99优选以固定的深度形成。由此，能够抑制SiC芯片62的耐压性(例如抗断裂性)受到各深阱区域99的限制，因此能够适当实现耐压性的提高。周缘阱区域100也起到与深阱区域99同样的效果。
通过利用源极沟槽92，能够在SiC芯片62的较深的区域适当形成深阱区域99。此外，由于可以沿源极沟槽92形成深阱区域99，因此能够适当抑制多个深阱区域99的深度产生偏差。
此外，高浓度区域70的一部分介于彼此相邻的多个深阱区域99之间的区域。由此，在彼此相邻的多个深阱区域99之间的区域，能够降低结型场效应晶体管(Junction FieldEffect Transistor，JFET)电阻。
此外，在该方式中，各深阱区域99的底部位于高浓度区域70。由此，能够在高浓度区域70中的各深阱区域99的正下方的区域在与第一主面63平行的横向上形成电流路径。其结果是，能够使电流扩展电阻降低。低浓度区域71在这样的结构中提高SiC芯片62的耐压性。
SiC半导体装置61包含在有源区域72中以与源电极94的上端部接壤的方式形成于第一主面63的多个源极子沟槽101。多个源极子沟槽101相对于多个源电极94按照1对1对应的关系形成。源极子沟槽101与所对应的源极沟槽92连通，形成所对应的源极沟槽92的侧壁的一部分。
源极子沟槽101在该方式中形成为在俯视中围绕源电极94的上端部的环状(更具体为无端状)。源极子沟槽101通过对源极绝缘层93的一部分进行下挖而形成。更具体地，源极子沟槽101通过从第一主面63对源极绝缘层93的上端部和源电极94的上端部进行下挖而形成。
源极子沟槽101在截面图中形成为底面积小于开口面积的尖头形状。源极子沟槽101的底壁可以形成为朝向第二主面64的弯曲状。源极子沟槽101使源极区域97、接触区域98、源极绝缘层93、源电极94和接触区域98露出。
源电极94的上端部具有相对于源电极94的下端部向内侧收缩的形状。源电极94的下端部是在源电极94中位于各源极沟槽92的底壁侧的部分。源电极94的上端部的沿第二方向Y的宽度可以小于源电极94的下端部的沿第二方向Y的宽度。
各源极沟槽92的开口边缘部包含从第一主面63朝向各源极沟槽92的内部向下倾斜的倾斜部。各源极沟槽92的开口边缘部是将第一主面63和各源极沟槽92的侧壁连接的部分。各源极沟槽92的倾斜部由源极子沟槽101形成。
各源极沟槽92的倾斜部在该方式中形成为朝向SiC芯片62的内部凹陷的弯曲状。各源极沟槽92的倾斜部也可以形成为朝向源极子沟槽101的弯曲状。各源极沟槽92的倾斜部缓和对于各源极沟槽92的开口边缘部的电场集中。
参照图13，有源区域72具有形成第一主面63的一部分的有源主面111。外侧区域73具有形成第一主面63的一部分的外侧主面112。外侧主面112与侧面65A～65D连接。
有源主面111和外侧主面112分别面向SiC单晶的c面。有源主面111和外侧主面112分别具有相对于SiC单晶的(0001)面在[11-20]方向上倾斜的偏离角。
外侧区域73通过将第一主面63向第二主面64侧下挖而形成。因此，外侧主面112形成于相对于有源主面111向第二主面64侧凹陷的区域。外侧主面112相对于栅极沟槽78的底壁位于第二主面64侧。
外侧主面112在该方式中形成于与各源极沟槽92的底壁大体相等的深度位置。外侧主面112位于与各源极沟槽92的底壁大体同一平面上。外侧主面112相对于各源极沟槽92的底壁可以以0μm以上1μm以下的范围位于第二主面64侧。外侧主面112使高浓度区域70露出。
有源区域72在该方式中被外侧区域73划分成台地状。有源区域72作为比外侧主面112更向上方突出的台地状的有源台地113来形成。
有源台地113包含将有源主面111和外侧主面112连接的有源侧壁114。有源侧壁114划分出有源区域72与外侧区域73之间的边界区域。第一主面63由有源主面111、外侧主面112和有源侧壁114形成。
有源侧壁114在该方式中沿有源主面111(外侧主面112)的法线方向Z延伸。有源侧壁114由SiC单晶的m面和a面形成。有源侧壁114可以具有从有源主面111朝向外侧主面112向下倾斜的倾斜面。有源侧壁114使高浓度区域70露出。有源侧壁114也可以使主体区域74露出。
SiC半导体装置61包含形成于外侧主面112的表层部的p+型的二极管区域121。二极管区域121形成于高浓度区域70。二极管区域121在外侧区域73中形成于有源侧壁114与侧面65A～65D之间的区域。
二极管区域121与有源侧壁114和侧面65A～65D留有间隔地形成。二极管区域121在俯视中沿有源区域72以带状延伸。二极管区域121在该方式中形成为在俯视中围绕有源区域72的环状(更具体为无端状)。
二极管区域121相对于栅极沟槽78的底壁位于第二主面64侧。二极管区域121的底部相对于各源极沟槽92的底壁位于第二主面64侧。二极管区域121的底部可以形成于与接触区域98的底部大体相等的深度位置。
二极管区域121的底部可以位于与接触区域98的底部大体同一平面上。二极管区域121的底部相对于接触区域98的底部可以位于第二主面64侧。二极管区域121的底部相对于接触区域98的底部可以以0μm以上1μm以下的范围位于第二主面64侧。
二极管区域121与高浓度区域70之间形成pn结部。由此，形成以二极管区域121作为阳极、以高浓度区域70作为阴极的pn结二极管。二极管区域121的p型杂质浓度的峰值可以为1.0×1017cm-3以上1.0×1021cm-3以下。
SiC半导体装置61包含形成于外侧主面112的表层部的p型的外侧阱区域122。外侧阱区域122的p型杂质浓度的峰值可以为1.0×1017cm-3以上1.0×1019cm-3以下。外侧阱区域122的p型杂质浓度的峰值可以小于二极管区域121的p型杂质浓度的峰值。外侧阱区域122的p型杂质浓度的峰值可以与深阱区域99的p型杂质浓度的峰值大体相等。
外侧阱区域122在俯视中形成于有源侧壁114与二极管区域121之间的区域。外侧阱区域122在俯视中沿有源区域72以带状延伸。外侧阱区域122在该方式中形成为在俯视中围绕有源区域72的环状(更具体为无端状)。
外侧阱区域122形成于高浓度区域70。外侧阱区域122相对于栅极沟槽78的底壁位于第二主面64侧。外侧阱区域122的底部相对于各源极沟槽92的底壁位于第二主面64侧。外侧阱区域122的底部相对于二极管区域121的底部位于第二主面64侧。外侧阱区域122的底部可以形成于与深阱区域99的底部大体相等的深度位置。
外侧阱区域122的内周缘被覆将有源侧壁114与外侧主面112连接的角部。外侧阱区域122的内周缘进一步沿有源侧壁114延伸、与主体区域74连接。外侧阱区域122的内周缘可以与有源侧壁114留有间隔地朝向二极管区域121侧形成。
外侧阱区域122的外周缘从第二主面64侧被覆二极管区域121。外侧阱区域122与二极管区域121电连接。外侧阱区域122可以形成pn结二极管的一部分。外侧阱区域122的外周缘可以与二极管区域121留有间隔地在有源侧壁114侧形成。
SiC半导体装置61包含形成于外侧主面112的表层部的FL结构123(场限制结构(field limit structure))。FL结构123在俯视中形成于二极管区域121与侧面65A～65D之间的区域。FL结构123在该方式中与侧面65A～65D留有间隔地朝向二极管区域121形成。FL结构123形成于高浓度区域70。
FL结构123包含1个或多个(例如2个以上20个以下)的FL区域124(场限制区域(field limit region))。FL结构123在该方式中包含具有5个FL区域124A、124B、124C、124D、124E的FL区域组。FL区域124A～124E沿远离二极管区域121的方向留有间隔地依次形成。
FL区域124A～124E在俯视中沿有源区域72的周缘分别以带状延伸。更具体地，FL区域124A～124E在俯视中分别形成为围绕有源区域72的环状(更具体为无端状)。FL区域124A～124E分别也称为FLR区域(场限制环区域(field limiting ring region))。
FL区域124A～124E的底部相对于二极管区域121的底部位于第二主面64侧。FL区域124A～124E中的最内侧的FL区域124A从第二主面64侧被覆二极管区域121。由此，FL区域124A与二极管区域121电连接。FL区域124A可以形成pn结二极管的一部分。
FL区域124A～124E整体相对于栅极沟槽78的底壁位于第二主面64侧。FL区域124A～124E的底部相对于源极沟槽92的底壁位于第二主面64侧。
FL结构123在外侧区域73缓和电场集中。FL区域124的个数、宽度、深度、p型杂质浓度等可以根据要缓和的电场取各种值。FL结构123可以包含在俯视中形成于有源侧壁114与二极管区域121之间的区域的1个或多个FL区域124。
SiC半导体装置61包含被覆外侧主面112的外侧绝缘层131。外侧绝缘层131沿有源侧壁114和外侧主面112形成为膜状。外侧绝缘层131在有源主面111上与栅极绝缘层79(第三区域83)相连。外侧绝缘层131在外侧区域73中被覆二极管区域121、外侧阱区域122和FL结构123。
外侧绝缘层131可以包含氧化硅。外侧绝缘层131也可以包含氮化硅等的其他绝缘膜。外侧绝缘层131在该方式中由与栅极绝缘层79相同的绝缘材料种类形成。
外侧绝缘层131的周缘从侧面65A～65D露出。外侧绝缘层131的周缘在该方式中与侧面65A～65D相连。外侧绝缘层131的周缘也可以在侧面65A～65D的内部与侧面65A～65D留有间隔地形成。该情况下，外侧绝缘层131使外侧主面112露出。
SiC半导体装置61进一步包含被覆有源侧壁114的边壁结构132。边壁结构132从外侧区域73侧保护、增强有源台地113。此外，边壁结构132形成对形成于有源主面111与外侧主面112之间的高低差进行缓和的高低差缓和结构。
在形成被覆有源区域72与外侧区域73之间的边界区域的上层结构(被覆层)的情况下，上层结构被覆边壁结构132。边壁结构132提高上层结构的平坦性。边壁结构132可以具有从有源主面111朝向外侧主面112向下倾斜的倾斜面。利用边壁结构132的倾斜面，能够适当缓和高低差。
边壁结构132的倾斜面可以形成为朝向SiC芯片62侧凹陷的弯曲状。边壁结构132的倾斜面也可以形成为朝向与SiC芯片62相反侧的弯曲状。边壁结构132的倾斜面可以从有源主面111侧朝向外侧主面112侧平面地延伸。
边壁结构132沿有源侧壁114形成。边壁结构132在该方式中形成为在俯视中围绕有源区域72的环状(更具体为无端状)。边壁结构132优选包含多晶硅。该情况下，可以与栅电极80、源电极94同时形成边壁结构132。
SiC半导体装置61包含形成于第一主面63上的层间绝缘层140。层间绝缘层140被覆有源区域72和外侧区域73。层间绝缘层140沿有源主面111和外侧主面112形成为膜状。
层间绝缘层140在有源区域72与外侧区域73之间的边界区域沿边壁结构132形成。层间绝缘层140形成被覆边壁结构132的上层结构的一部分。
层间绝缘层140的周缘从侧面65A～65D露出。层间绝缘层140的周缘与侧面65A～65D相连。层间绝缘层140的周缘可以在侧面65A～65D的内部与侧面65A～65D留有间隔地形成。该情况下，层间绝缘层140使外侧主面112(外侧绝缘层131)露出。
层间绝缘层140可以包含氧化硅或氮化硅。层间绝缘层140可以包含作为氧化硅的一例的无掺杂硅酸盐玻璃(Undoped Silicate Glass，USG)、磷硅酸盐玻璃(PhosphorSilicate Glass，PSG)和/或硼磷硅酸盐玻璃(Boron Phosphor Silicate Glass，BPSG)。
层间绝缘层140包含栅极接触孔141、源极接触孔142和二极管接触孔143。栅极接触孔141在有源区域72中使栅极配线85露出。栅极接触孔141可以形成为沿栅极配线85的带状。栅极接触孔141的开口边缘部形成为朝向栅极接触孔141内的弯曲状。
源极接触孔142在有源区域72中使源极区域97、接触区域98和沟槽源极结构91露出。源极接触孔142可以形成为沿沟槽源极结构91延伸的带状。源极接触孔142的开口边缘部形成为朝向源极接触孔142内的弯曲状。
二极管接触孔143在外侧区域73中使二极管区域121露出。二极管接触孔143可以形成为沿二极管区域121延伸的带状(更具体为无端状)。二极管接触孔143可以使外侧阱区域122和/或FL结构123露出。二极管接触孔143的开口边缘部形成为朝向二极管接触孔143内的弯曲状。
SiC半导体装置61包含形成于第一主面63上的第一主面电极150。更具体地，第一主面电极150形成于层间绝缘层140上。第一主面电极150包含彼此电绝缘的栅极主面电极151和源极主面电极152。
对栅极主面电极151施加栅电压。栅电压可以为10V以上50V以下(例如30V左右)。对源极主面电极152施加源电压。源电压可以为基准电压(例如GND电压)。
栅极主面电极151形成于有源区域72。栅极主面电极151包含栅极焊盘153和栅极指154。栅极焊盘153在俯视中形成于第一侧面65A侧的区域。更具体地，栅极焊盘153在俯视中沿着沿第一侧面65A的中央部的区域形成。栅极焊盘153在俯视中可以形成于沿着将侧面65A～65D中的任意2个连接的角部的区域。栅极焊盘153在俯视中可以形成为四边形。
栅极指154从栅极焊盘153引出，沿有源区域72的周缘以带状延伸。栅极指154在该方式中沿第一侧面65A、第三侧面65C和第四侧面65D形成以从3个方向划分有源区域72的内部。
栅极指154具有一对开放端155、156。一对开放端155、156形成于隔着有源区域72的内部与栅极焊盘153对置的区域。一对开放端155、156在该方式中在俯视中形成于沿第二侧面65B的区域。
栅极指154从层间绝缘层140上进入栅极接触孔141。栅极指154在栅极接触孔141内与栅极配线85电连接。由此，来自栅极焊盘153的电信号经由栅极指154传递至栅电极80和栅极配线85。
源极主面电极152形成于有源区域72和外侧区域73。源极主面电极152包含源极焊盘157、源极配线158和源极连接部159。源极焊盘157与栅极主面电极151留有间隔地形成于有源区域72。源极焊盘157以被覆由栅极主面电极151划分出的C字形状的区域的方式在俯视中以C字形状形成。
源极焊盘157从层间绝缘层140上进入源极接触孔142和源极子沟槽101。源极焊盘157在源极接触孔142和源极子沟槽101内与源极区域97、接触区域98和源电极94电连接。
前述的源电极94可以利用源极焊盘157的一部分区域来形成。源电极94可以由源极焊盘157中进入各源极沟槽92的部分来形成。
源极配线158形成于外侧区域73。源极配线158沿有源区域72以带状延伸。源极配线158形成为在俯视中围绕有源区域72的环状(更具体为无端状)。
源极配线158从层间绝缘层140上进入二极管接触孔143。源极配线158在二极管接触孔143内与二极管区域121电连接。
源极连接部159将源极焊盘157和源极配线158连接。源极连接部159从源极焊盘157横穿栅极指154的开放端155、156，与源极配线158连接。源极连接部159从有源区域72横穿边壁结构132，向外侧区域73引出。源极连接部159形成被覆边壁结构132的上层结构的一部分。
形成于有源区域72的MISFET在结构上包含npn型的寄生晶体管。如果在外侧区域73产生的雪崩电流流入有源区域72，则寄生晶体管呈导通状态。该情况下，MISFET的启动会因闩锁而变得不稳定。对此，SiC半导体装置61中，利用源极主面电极152的结构来形成雪崩电流吸收结构。
在外侧区域73产生的雪崩电流经由二极管区域121被源极配线158吸收。被源极配线158吸收的雪崩电流经由源极连接部159到达源极焊盘157。在源极焊盘157电连接有导线的情况下，雪崩电流经由导线到达外部。
由此，能够抑制由雪崩电流引起的寄生晶体管的驱动。因此，能够抑制闩锁，能够提高MISFET的稳定性。
参照图14和图15，第一主面电极150(栅极主面电极151和源极主面电极152)具有包含从SiC芯片62侧依次层叠的势垒层160和第一Al层161的层叠结构。第一Al层161作为第一缓冲层来形成，其利用具有较小的杨氏模量(刚性模量)的Al的缓冲性来从第一主面63侧缓和施加于SiC芯片62的外力。
势垒层160可以具有包含Ti层或TiN层的单层结构。势垒层160可以具有包含从SiC芯片62侧依次层叠的Ti层和TiN层的层叠结构。势垒层160的厚度可以为0.01μm以上6μm以下。势垒层160的厚度可以为0.01μm以上0.1μm以下、0.1μm以上2μm以下、2μm以上4μm以下、或者4μm以上6μm以下。
第一Al层161具有小于势垒层160的电阻值的电阻值。第一Al层161包含纯Al层、AlSi合金层、AlCu合金层和AlSiCu合金层中的至少一者。第一Al层161可以具有纯Al层、AlSi合金层、AlCu合金层和AlSiCu合金层中的2者以上以任意的顺序层叠而成的层叠结构。
第一Al层161也可以具有由纯Al层、AlSi合金层、AlCu合金层或AlSiCu合金层构成的单层结构。第一Al层161优选具有由AlSi合金层、AlCu合金层或AlSiCu合金层构成的单层结构。
第一Al层161的厚度大于势垒层160的厚度。第一Al层161的厚度可以为0.05μm以上10μm以下。第一Al层161的厚度可以为0.05μm以上0.1μm以下、0.1μm以上1μm以下、1μm以上2μm以下、2μm以上4μm以下、4μm以上6μm以下、6μm以上8μm以下、或者8μm以上10μm以下。第一Al层161的厚度可以为1μm以上8μm以下。
SiC半导体装置61包含形成于层间绝缘层140上的绝缘层170。图9中，由阴影示出了绝缘层170。绝缘层170的周缘在侧面65A～65D的内部与侧面65A～65D留有间隔地形成。由此，绝缘层170在俯视中使SiC芯片62(更具体为层间绝缘层140)的周缘露出。
绝缘层170的周缘在与侧面65A～65D之间划分出划片通道DS。借助划片通道DS，在从SiC晶片切出SiC半导体装置61时无需物理切断绝缘层170。由此，能够从SiC晶片将SiC半导体装置61顺畅地切出，同时能够抑制绝缘层170的剥离、劣化。其结果是，能够利用绝缘层170来适当保护SiC芯片102、第一主面电极150等保护对象物。
划片通道DS的宽度可以为1μm以上25μm以下。划片通道DS的宽度是与划片通道DS延伸的方向正交的方向的宽度。划片通道DS的宽度可以为1μm以上5μm以下、5μm以上10μm以下、10μm以上15μm以下、15μm以上20μm以下、或者20μm以上25μm以下。
绝缘层170选择性被覆栅极主面电极151和源极主面电极152。绝缘层170包含焊盘开口171。更具体地，焊盘开口171包含栅极焊盘开口172和源极焊盘开口173。栅极焊盘开口172使栅极焊盘153露出。源极焊盘开口173使源极焊盘157露出。栅极焊盘开口172的平面形状是任意的。源极焊盘开口173的平面形状是任意的。
绝缘层170在该方式中具有包含从SiC芯片62侧依次层叠的钝化层174和树脂层175的层叠结构。
钝化层174可以包含氧化硅层和氮化硅层中的至少一者。钝化层174可以具有包含氧化硅层和氮化硅层的层叠结构。钝化层174也可以具有由氧化硅层或氮化硅层构成的单层结构。钝化层174优选包含与层间绝缘层140不同的绝缘材料。钝化层174在该方式中具有由氮化硅层构成的单层结构。
钝化层174沿层间绝缘层140形成为膜状。钝化层174隔着层间绝缘层140被覆有源区域72和外侧区域73。钝化层174从有源区域72横穿边壁结构132，向外侧区域73引出。钝化层174形成被覆边壁结构132的上层结构的一部分。
钝化层174具有第一栅极开口176和第一源极开口177。第一栅极开口176使栅极焊盘153露出。第一源极开口177使源极焊盘157露出。第一栅极开口176的平面形状是任意的。第一源极开口177的平面形状是任意的。
钝化层174的厚度可以为0.1μm以上20μm以下。钝化层174的厚度可以为0.1μm以上1μm以下、1μm以上5μm以下、5μm以上10μm以下、10μm以上15μm以下、或者15μm以上20μm以下。
树脂层175沿钝化层174的主面形成为膜状。树脂层175从有源区域72横穿边壁结构132，向外侧区域73引出。树脂层175形成被覆边壁结构132的上层结构的一部分。
树脂层175可以包含感光性树脂。感光性树脂可以为负型或正型。树脂层175可以包含聚酰亚胺、聚酰胺和聚苯并
Figure BDA0003307685030000401
唑中的至少一种。树脂层175在该方式中包含聚苯并
Figure BDA0003307685030000402
唑。
树脂层175的周缘在该方式中使钝化层174的周缘露出。绝缘层170的周缘由树脂层175的周缘和钝化层174的周缘形成。树脂层175可以被覆钝化层174的周缘。
树脂层175具有第二栅极开口178和第二源极开口179。第二栅极开口178与钝化层174的第一栅极开口176连通，在与第一栅极开口176之间形成栅极焊盘开口172。第二源极开口179与钝化层174的第一源极开口177连通，在与第一源极开口177之间形成源极焊盘开口173。
第二栅极开口178的内壁可以形成为与第一栅极开口176的内壁齐平。第二栅极开口178的内壁在俯视中可以位于第一栅极开口176外。第二栅极开口178的内壁在俯视中可以位于第一栅极开口176内。即，树脂层175可以被覆第一栅极开口176的内壁。
第二源极开口179的内壁可以形成为与第一源极开口177的内壁齐平。第二源极开口179的内壁在俯视中可以位于第一源极开口177外。第二源极开口179的内壁在俯视中可以位于第一源极开口177内。即，树脂层175可以被覆第一源极开口177的内壁。
树脂层175的厚度可以为1μm以上50μm以下。树脂层175的厚度可以为1μm以上10μm以下、10μm以上20μm以下、20μm以上30μm以下、30μm以上40μm以下、或者40μm以上50μm以下。
SiC半导体装置61包含形成于外侧主面112的凹凸结构180(Uneven Structure)。更具体地，凹凸结构180包含利用被覆外侧主面112的层间绝缘层140而形成的凹凸(Unevenness)。更具体地，凹凸结构180包含形成于层间绝缘层140的锚固孔181。
锚固孔181通过将层间绝缘层140中被覆外侧区域73的部分下挖而形成。锚固孔181在俯视中可以形成于二极管区域121与侧面65A～65D之间的区域。锚固孔181在该方式中在俯视中形成于FL结构123与侧面65A～65D之间的区域。
锚固孔181可以由层间绝缘层140划分。锚固孔181在该方式中使外侧主面112露出。锚固孔181可以将外侧主面112朝向第二主面64下挖。锚固孔181的开口边缘部形成为朝向锚固孔181内的弯曲状。
锚固孔181在俯视中沿有源区域72以带状延伸。锚固孔181在该方式中形成为在俯视中围绕有源区域72的环状(更具体为无端状)。锚固孔181的个数是任意的。可以有1个锚固孔181形成于层间绝缘层140，也可以有多个锚固孔181形成于层间绝缘层140。
树脂层175具有与锚固孔181啮合的锚固部182。树脂层175在该方式中隔着钝化层174与锚固孔181啮合。更具体地，钝化层174从层间绝缘层140上进入锚固孔181。钝化层174在锚固孔181内与外侧主面112相接。在钝化层174的主面中被覆锚固孔181的部分，形成有朝向锚固孔181凹陷的凹槽183。
树脂层175的一部分在钝化层174的凹槽183内形成锚固部182。由此，能够提高树脂层175对于第一主面63的连接强度，因此能够适宜抑制树脂层175的剥离。
参照图14和图15，SiC半导体装置61包含形成于第一主面电极150上的焊盘电极190。更具体地，焊盘电极190包含栅极焊盘电极191和源极焊盘电极192。
栅极焊盘电极191形成于栅极主面电极151上，与栅极主面电极151电连接。更具体地，栅极焊盘电极191在栅极焊盘开口172内形成于栅极焊盘153上。栅极焊盘电极191具有与导线进行外部连接的栅极端子面193。
栅极端子面193相对于绝缘层170(树脂层175)的主面位于栅极焊盘153侧。栅极端子面193可以比绝缘层170(树脂层175)的主面更向上方突出。栅极端子面193可以具有被覆绝缘层170(树脂层175)的主面的重叠部。
源极焊盘电极192形成于源极主面电极152上，与源极主面电极152电连接。更具体地，源极焊盘电极192在源极焊盘开口173内形成于源极焊盘157上。源极焊盘电极192具有与导线进行外部连接的源极端子面194。
源极端子面194相对于绝缘层170(树脂层175)的主面位于源极焊盘157侧。源极端子面194可以比绝缘层170(树脂层175)的主面更向上方突出。源极端子面194可以具有被覆绝缘层170(树脂层175)的主面的重叠部。
焊盘电极190(栅极焊盘电极191和源极焊盘电极192)包含与第一主面电极150不同的金属材料。焊盘电极190在该方式中具有包含从第一主面电极150侧依次层叠的Ni层195、Pd层196和Au层197的层叠结构。Ni、Pd和Au分别具有大于Al的杨氏模量(刚性模量)的杨氏模量(刚性模量)。Ni层195、Pd层196和Au层197可以为利用镀覆法形成的镀覆层。
焊盘电极190只要包含Ni层195、Pd层196和Au层197中的至少一者即可。焊盘电极190可以具有Ni层195、Pd层196和Au层197中的至少两者以任意的顺序层叠而成的层叠结构。焊盘电极190也可以具有由Ni层195、Pd层196或Au层197构成的单层结构。
栅极焊盘电极191优选具有由Au层197形成的栅极端子面193。源极焊盘电极192优选具有由Au层197形成的源极端子面194。焊盘电极190优选具有至少包含从第一主面电极150侧依次层叠的Ni层195和Au层197的层叠结构。
Ni层195的厚度可以为0.1μm以上10μm以下。Ni层195的厚度可以为0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、2μm以上4μm以下、4μm以上6μm以下、6μm以上8μm以下、或者8μm以上10μm以下。
Pd层196的厚度可以为0.1μm以上10μm以下。Pd层196的厚度可以为0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、2μm以上4μm以下、4μm以上6μm以下、6μm以上8μm以下、或者8μm以上10μm以下。
Au层197的厚度可以为0.01μm以上3μm以下。Au层197的厚度可以为0.01μm以上0.05μm以下、0.05μm以上0.1μm以下、0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、或者2μm以上3μm以下。Au层197的厚度优选小于Ni层195的厚度。Au层197的厚度优选小于Pd层196的厚度。
SiC半导体装置61包含形成于第二主面64上的第二主面电极200。第二主面电极200作为MISFET的漏电极来形成。第二主面电极200在该方式中被覆第二主面64的整个区域。
第二主面电极200在侧面65A～65D的内部与侧面65A～65D留有间隔地形成，可以使第二主面64的周缘部露出。该情况下，在从SiC晶片切出SiC半导体装置61时无需物理切断第二主面电极200。由此，能够从SiC晶片将SiC半导体装置61顺畅地切出，同时能够抑制第二主面电极200的剥离、劣化。其结果是，能够使第二主面电极200与第二主面64适宜连接。
作为一例，这样的第二主面电极200可以通过在制造过程中利用隔着抗蚀剂掩模的蚀刻法将第二主面电极200的不需要的部分去除来获得。此外，作为另一例，第二主面电极200可以通过在制造过程中利用使用抗蚀剂掩模的剥离法形成部分被覆第二主面64的第二主面电极200来获得。
第二主面电极200包含被覆第二主面64的第二Al层201。第二Al层201隔着SiC芯片62与栅极主面电极151的第一Al层161和源极主面电极152的第一Al层161对置。第二Al层201作为第二缓冲层来形成，其利用具有较小的杨氏模量(刚性模量)的Al的缓冲性来从第二主面64侧缓和施加于SiC芯片62的外力。
第二Al层201包含纯Al层、AlSi合金层、AlCu合金层和AlSiCu合金层中的至少一者。第二Al层201可以具有纯Al层、AlSi合金层、AlCu合金层和AlSiCu合金层中的两者以上以任意的顺序层叠而成的层叠结构。第二Al层201可以利用溅射法和/或蒸镀法来形成。
第二Al层201也可以具有由纯Al层、AlSi合金层、AlCu合金层或AlSiCu合金层构成的单层结构。第二Al层201的Al系金属材料可以与第一Al层161的Al系金属材料不同。第二Al层201优选具有由纯Al层构成的单层结构。
第二Al层201可以具有小于第一Al层161的厚度的厚度。第二Al层201的厚度可以为0.01μm以上5μm以下。第二Al层201的厚度可以为0.01μm以上0.1μm以下、0.1μm以上1μm以下、1μm以上2μm以下、2μm以上3μm以下、3μm以上4μm以下、或者4μm以上5μm以下。
第二主面电极200除了第二Al层201以外进一步包含由与第二Al层201不同的金属材料构成的1个或多个电极层。作为多个电极层的一例，第二主面电极200在该方式中包含从第二主面64侧依次层叠的Ti层202、Ni层203、Pd层204、Au层205和Ag层206。
Ti层202是与第二主面64之间形成欧姆接触的欧姆电极。第二Al层201隔着Ti层202、Ni层203、Pd层204、Au层205和Ag层206被覆第二主面64。
Ti、Ni、Pd、Au和Ag分别具有大于Al的杨氏模量(刚性模量)的杨氏模量(刚性模量)。Ti层202、Ni层203、Pd层204、Au层205和Ag层206可以利用溅射法、蒸镀法和/或镀覆法来形成。
第二主面电极200可以包含Ti层202、Ni层203、Pd层204、Au层205和Ag层206中的至少一者作为1个或多个电极层。第二Al层201优选隔着至少Ti层202被覆第二主面64。
在第二主面电极200包含Ni层203、Pd层204和Au层205中的至少一者的情况下，Ni层203、Pd层204和Au层205中的至少一者可以为与焊盘电极190的Ni层195、Pd层196和Au层197同时形成的镀覆层。
Ti层202的厚度可以为0.01μm以上3μm以下。Ti层202的厚度可以为0.01μm以上0.05μm以下、0.05μm以上0.1μm以下、0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、或者2μm以上3μm以下。
Ni层203的厚度可以为0.1μm以上10μm以下。Ni层203的厚度可以为0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、2μm以上4μm以下、4μm以上6μm以下、6μm以上8μm以下、或者8μm以上10μm以下。Ni层203的厚度优选大于Ti层202的厚度。
Pd层204的厚度可以为0.1μm以上10μm以下。Pd层204的厚度可以为0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、2μm以上4μm以下、4μm以上6μm以下、6μm以上8μm以下、或者8μm以上10μm以下。Pd层204的厚度优选大于Ti层202的厚度。
Au层205的厚度可以为0.01μm以上3μm以下。Au层205的厚度可以为0.01μm以上0.05μm以下、0.05μm以上0.1μm以下、0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、或者2μm以上3μm以下。Au层205的厚度优选小于Ni层203的厚度。Au层205的厚度优选小于Pd层204的厚度。
Ag层206的厚度可以为0.01μm以上3μm以下。Ag层206的厚度可以为0.01μm以上0.05μm以下、0.05μm以上0.1μm以下、0.1μm以上0.5μm以下、0.5μm以上1μm以下、1μm以上2μm以下、或者2μm以上3μm以下。Ag层206的厚度优选小于Ni层203的厚度。Ag层206的厚度优选小于Pd层204的厚度。
第二主面电极200可以具有图17A～图17I所示的结构。
图17A是图解性示出第2方式例涉及的第二主面电极200的截面图。以下，对于与图6～图16中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图17A，第二主面电极200在该方式中具有包含第二Al层201、Ti层202、Ni层203、Pd层204和Au层205的层叠结构。Ti层202、Ni层203、Pd层204和Au层205从第二主面64侧依次层叠。第二Al层201隔着Ti层202、Ni层203、Pd层204和Au层205被覆第二主面64。
图17B是图解性示出第3方式例涉及的第二主面电极200的截面图。以下，对于与图6～图16中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图17B，第二主面电极200在该方式中具有包含第二Al层201、Ti层202、Ni层203、Au层205和Ag层206的层叠结构。Ti层202、Ni层203、Au层205和Ag层206从第二主面64侧依次层叠。第二Al层201隔着Ti层202、Ni层203、Au层205和Ag层206被覆第二主面64。
图17C是图解性示出第4方式例涉及的第二主面电极200的截面图。以下，对于与图6～图16中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图17C，第二主面电极200在该方式中具有包含第二Al层201、Ti层202、Ni层203和Au层205的层叠结构。Ti层202、Ni层203和Au层205从第二主面64侧依次层叠。第二Al层201隔着Ti层202、Ni层203和Au层205被覆第二主面64。
图17D图解性示出第5方式例涉及的第二主面电极200的截面图。以下，对于与图6～图16中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图17D，第二主面电极200在该方式中具有包含第二Al层201和Ti层202的层叠结构。Ti层202与第二主面64连接。第二Al层201隔着Ti层202被覆第二主面64。
图17E是图解性示出第6方式例涉及的第二主面电极200的截面图。以下，对于与图6～图16中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图17E，第二主面电极200在该方式中包含第二Al层201、Ti层202、Ni层203和Au层205。Ti层202、Ni层203和Au层205从第二主面64侧依次层叠。第二Al层201介于Ti层202与Ni层203之间，隔着Ti层202被覆第二主面64。
该情况下，焊盘电极190优选具有由从第一主面电极150侧依次层叠的Ni层195和Au层197构成的2层结构。第二主面电极200的Ni层203和Au层205可以利用镀覆法与焊盘电极190的Ni层195和Au层197同时形成。
图17F是图解性示出第7方式例涉及的第二主面电极200的截面图。以下，对于与图6～图16中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图17F，第二主面电极200在该方式中包含第二Al层201、Ti层202、Ni层203、Au层205和Ag层206。Ti层202、Ni层203、Au层205和Ag层206从第二主面64侧依次层叠。第二Al层201介于Ti层202与Ni层203之间，隔着Ti层202被覆第二主面64。
该情况下，焊盘电极190优选具有由从第一主面电极150侧依次层叠的Ni层195和Au层197构成的2层结构。第二主面电极200的Ni层203和Au层205可以利用镀覆法与焊盘电极190的Ni层195和Au层197同时形成。
图17G是图解性示出第8方式例涉及的第二主面电极200的截面图。以下，对于与图6～图16中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图17G，第二主面电极200在该方式中包含第二Al层201、Ti层202、Ni层203、Pd层204、Au层205和Ag层206。Ti层202、Ni层203、Au层205和Ag层206从第二主面64侧依次层叠。第二Al层201介于Ti层202与Ni层203之间，隔着Ti层202被覆第二主面64。
该情况下，焊盘电极190优选具有由从第一主面电极150侧依次层叠的Ni层195、Pd层196和Au层197构成的3层结构。第二主面电极200的Ni层203、Pd层204和Au层205可以利用镀覆法与焊盘电极190的Ni层195、Pd层196和Au层197同时形成。
图17H是图解性示出第9方式例涉及的第二主面电极200的截面图。以下，对于与图6～图16中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图17H，第二主面电极200在该方式中包含第二Al层201、Ti层202、Ni层203、Pd层204和Au层205。Ti层202、Ni层203、Pd层204和Au层205从第二主面64侧依次层叠。第二Al层201介于Ti层202与Ni层203之间，隔着Ti层202被覆第二主面64。
该情况下，焊盘电极190优选具有由从第一主面电极150侧依次层叠的Ni层195、Pd层196和Au层197构成的3层结构。第二主面电极200的Ni层203、Pd层204和Au层205可以利用镀覆法与焊盘电极190的Ni层195、Pd层196和Au层197同时形成。
图17I是图解性示出第10方式例涉及的第二主面电极200的截面图。以下，对于与图6～图16中描述的结构相对应的结构赋予相同的参照符号，省略说明。
参照图17I，第二主面电极200在该方式中包含第二Al层201和硅化物层207。硅化物层207形成于第二主面64。硅化物层207通过将从第二主面64露出的SiC利用金属材料进行硅化物而形成。硅化物层207可以包含FeSi2层、NiSi层、NiSi2层、CoSi2层、CrSi2层、WSi2层、MoSi2层、MnSi2层、NbSi2层、TiSi2层和VSi2层中的至少一者。
第二Al层201隔着硅化物层207被覆第二主面64。第二主面电极200除了第二Al层201和硅化物层207之外还可以包含Ti层202、Ni层203、Pd层204、Au层205和Ag层206中的至少一者。第二Al层201、Ti层202、Ni层203、Pd层204、Au层205和Ag层206的层叠顺序是任意的。作为被覆硅化物层207的结构，可以采用第1～第10方式例中的任一种层叠结构。
图18是示出组装有图6所示的SiC半导体装置61的半导体封装211的图。图18中，透过封装主体212来示出半导体封装211的内部结构。
参照图18，半导体封装211在该方式中为3端子型的TO-220。半导体封装211包含封装主体212、金属板213、第一端子214、第二端子215、第三端子216、SiC半导体装置61、导电接合材217、第一导线218和第二导线219。
封装主体212由模制树脂构成。封装主体212可以包含作为模制树脂的一例的环氧树脂。封装主体212形成为长方体形状。封装主体212包含一侧的第一面221和另一侧的第二面222以及将第一面221和第二面222连接的4个侧面223A、223B、223C、223D。
更具体地，4个侧面223A～223D包含第一侧面223A、第二侧面223B、第三侧面223C和第四侧面223D。第一侧面223A和第二侧面223B彼此对置。
第三侧面223C和第四侧面223D彼此对置。
金属板213可以包含Fe、Au、Ag、Cu和Al中的至少一种。金属板213可以具有形成有镀Ni膜、镀Au膜、镀Ag膜和镀Cu膜中的至少一种的外表面。金属板213的平面形状是任意的。金属板213在该方式中在俯视中形成为四边形(长方形)。
更具体地，金属板213一体地包含位于封装主体212内的焊盘部224以及位于封装主体212外的散热部225。散热部225从焊盘部224横穿第二侧面223B而向封装主体212外引出。散热部225包含贯通孔225a。贯通孔225a形成为圆形。散热部225的平面面积可以大于焊盘部224的平面面积。
金属板213在该方式中以从第二面222露出的方式配置于封装主体212内。金属板213也可以以不从第二面222露出的方式配置于封装主体212内。
第一端子214可以包含Fe、Au、Ag、Cu和Al中的至少一种。第一端子214可以具有形成有镀Ni膜、镀Au膜、镀Ag膜和镀Cu膜中的至少一种的外表面。第一端子214从封装主体212内横穿第一侧面223A而向封装主体212外引出。
第一端子214在俯视中配置于第一侧面223A的中央部。第一端子214相对于金属板213的板面配置于第一面221侧的区域。
第一端子214包含第一内端部226、第一外端部227和第一带状部228。第一内端部226在封装主体212内与金属板213连接。第一外端部227配置于封装主体212外。第一带状部228在第一内端部226与第一外端部227之间在与第一侧面223A正交的方向上延伸。
第二端子215可以包含Fe、Au、Ag、Cu和Al中的至少一种。第二端子215可以具有形成有镀Ni膜、镀Au膜、镀Ag膜和镀Cu膜中的至少一种的外表面。第二端子215从封装主体212内横穿第一侧面223A而向封装主体212外引出。
第二端子215在俯视中与第一端子214留有间隔地配置于第三侧面223C侧的区域。第二端子215相对于金属板213的板面配置于第一面221侧的区域。
第二端子215包含第二内端部229、第二外端部230和第二带状部231。第二内端部229与金属板213留有间隔地配置于封装主体212内。第二外端部230配置于封装主体212外。第二带状部231在第二内端部229与第二外端部230之间在与第一侧面223A正交的方向上延伸。
第三端子216可以包含Fe、Au、Ag、Cu和Al中的至少一种。第三端子216可以具有形成有镀Ni膜、镀Au膜、镀Ag膜和镀Cu膜中的至少一种的外表面。第三端子216从封装主体212内横穿第一侧面223A而向封装主体212外引出。
第三端子216在俯视中与第一端子214留有间隔地配置于第四侧面223D侧的区域。第三端子216相对于金属板213的板面配置于第一面221侧的区域。
第三端子216包含第三内端部232、第三外端部233和第三带状部234。第三内端部232与金属板213留有间隔地配置于封装主体212内。第三外端部233配置于封装主体212外。第三带状部234在第三内端部232与第三外端部233之间在与第一侧面223A正交的方向上延伸。
SiC半导体装置61在封装主体212内配置于金属板213的焊盘部224上。导电接合材217介于SiC半导体装置61与焊盘部224之间，使SiC半导体装置61的第二主面电极200与焊盘部224接合。由此，SiC半导体装置61经由金属板213与第一端子214电连接。
导电接合材217可以为金属膏或焊料。金属膏可以包含Au、Ag和Cu中的至少一种。导电接合材217优选由焊料构成。焊料可以为无铅焊料。焊料可以包含SnAgCu、SnZnBi、SnCu、SnCuNi和SnSbNi中的至少一种。
第一导线218由金属丝(接合线)或金属夹构成。金属丝可以为Al丝、Au丝、Cu丝或焊料丝。焊料丝可以为无铅焊料丝。焊料丝可以包含SnAgCu、SnZnBi、SnCu、SnCuNi和SnSbNi中的至少一种。金属夹可以为Al夹、Au夹或Cu夹。第一导线218在该方式中由焊料丝构成。
第一导线218在封装主体212内与第二端子215的第二内端部229以及SiC半导体装置61的栅极焊盘电极191连接。由此，SiC半导体装置61与第二端子215电连接。
图18中，示出了1个第一导线218与第二内端部229以及栅极焊盘电极191连接的例子，但第一导线218的个数是任意的。也可以是2个以上的第一导线218与第二内端部229和栅极焊盘电极191连接。
第二导线219由金属丝(接合线)或金属夹构成。金属丝可以为Al丝、Au丝、Cu丝或焊料丝。焊料丝可以为无铅焊料丝。焊料丝可以包含SnAgCu、SnZnBi、SnCu、SnCuNi和SnSbNi中的至少一种。金属夹可以为Al夹、Au夹或Cu夹。第二导线219在该方式中由焊料丝构成。
第二导线219在封装主体212内与第三端子216的第三内端部232以及SiC半导体装置61的源极焊盘电极192连接。由此，SiC半导体装置61与第三端子216电连接。
图18中，示出了2个第二导线219与第三内端部232以及源极焊盘电极192连接的例子，但第二导线219的个数是任意的。也可以是1个或3个以上的第二导线219与第三内端部232和源极焊盘电极192连接。
半导体封装211也可以采用TO-220以外的形态。半导体封装211可以具有SOP(小外型封装)、QFN(方型扁平无引脚封装)、DFP(双侧引脚扁平封装)、DIP(双直插式封装)、QFP(方型扁平封装)、SIP(单列直插式封装)或SOJ(J型引脚小外型封装)、或者与它们相类似的各种各样的形态。
以上，根据SiC半导体装置61，第一Al层161作为在第一主面63侧缓和外力的第一缓冲层来形成，第二Al层201作为在第二主面64侧缓和外力的第二缓冲层来形成。由此，能够缓和从第一主面63朝向第二主面64的方向的外力以及从第二主面64朝向第一主面63的方向的外力。
作为一例，在将SiC半导体装置61安装于金属板213的焊盘部224时能够利用第一Al层161和第二Al层201来缓和施加于SiC芯片62的外力。此外，在将第一导线218和第二导线219与SiC半导体装置61的焊盘电极190接合时能够利用第一Al层161和第二Al层201来缓和施加于SiC芯片62的外力。其结果是，能够抑制SiC芯片62的裂纹。
此外，SiC半导体装置61包含与第一导线218和第二导线219进行外部接合的焊盘电极190(栅极焊盘电极191和源极焊盘电极192)。焊盘电极190包含Ni层195、Pd层196和Au层197中的至少一种。由此，能够将第一导线218和第二导线219与焊盘电极190适宜连接。
另一方面，Ni、Pd和Au分别具有大于Al的杨氏模量(刚性模量)的杨氏模量(刚性模量)。因此，在具备焊盘电极190的结构中，无法适当缓和在第一导线218和第二导线219接合时所施加的外力。
对此，SiC半导体装置61中，使包含Al的第一Al层161介于SiC芯片62与焊盘电极190之间。借助第一Al层161，能够利用具有较小的杨氏模量(刚性模量)的Al的缓冲性来从第一主面63侧缓和施加于SiC芯片62的外力。因此，能够使第一导线218和第二导线219与焊盘电极190适宜接合，同时能够抑制SiC芯片62的裂纹。
此外，SiC半导体装置61除了第二Al层201以外还包含第二主面电极200，该第二主面电极200具有由与第二Al层201不同的金属材料构成的1个或多个电极层。1个或多个电极层包含Ti层202、Ni层203、Pd层204、Au层205和Ag层206中的至少一者。由此，能够适当提高导电接合材217对于第二主面电极200的密合力。其结果是，能够将SiC半导体装置61适宜安装于金属板213的焊盘部224。
另一方面，Ti、Ni、Pd、Au和Ag分别具有大于Al的杨氏模量(刚性模量)的杨氏模量(刚性模量)。因此，在第二主面电极200包含Ti层202、Ni层203、Pd层204、Au层205和Ag层206中的至少一者的结构中，无法适当缓和SiC半导体装置61安装时、第一导线218和第二导线219接合时所施加的外力。
因此，SiC半导体装置61中，形成除了Ti层202、Ni层203、Pd层204、Au层205和Ag层206中的至少一者之外还包含第二Al层201的第二主面电极200。借助第二Al层201，能够利用具有较小的杨氏模量(刚性模量)的Al的缓冲性来从第二主面64侧缓和施加于SiC芯片62的外力。因此，能够将SiC半导体装置61适宜安装于焊盘部224，同时能够抑制SiC芯片62的裂纹。
本发明的实施方式也可以进一步以其他的方式来实施。
前述的第1实施方式中，对于绝缘层17具有包含钝化层19和树脂层20的层叠结构的例子进行了说明。但是，绝缘层17也可以具有由钝化层19或树脂层20构成的单层结构。
前述的第1实施方式中，对于形成有作为二极管的一例的SBD的例子进行了说明。但是，也可以形成p型的二极管区域10来代替n型的二极管区域10。该情况下，可以提供pn结二极管来代替SBD。
前述的第2实施方式中，对于绝缘层170具有包含钝化层174和树脂层175的层叠结构的例子进行了说明。但是，绝缘层170也可以具有由钝化层174或树脂层175构成的单层结构。
前述的第2实施方式中，对于形成包含添加了p型杂质的p型多晶硅的栅电极80和栅极配线85的例子进行了说明。但是，在不重视栅极阈值电压Vth的增加的情况下，栅电极80和栅极配线85也可以包含添加了n型杂质的n型多晶硅来代替p型多晶硅或者除了p型多晶硅以外还包含添加了n型杂质的n型多晶硅。
该情况下，低电阻层86可以通过将在栅电极80(n型多晶硅)中形成表层部的部分利用金属材料进行硅化物化来形成。即，低电阻层86可以包含n型多晶硅化金属。在这样的结构的情况下，能够降低栅极电阻。
前述的第2实施方式中，对于形成有作为绝缘栅型晶体管的一例的MISFET的例子进行了说明。但是，可以采用p+型的集电极区域来代替n+型的漏极区域68。利用该结构，可以提供绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)来代替MISFET。该情况下，前述的第2实施方式中，将MISFET的“源极”改称为IGBT的“发射极”，将MISFET的“漏极”改称为“集电极”。
前述的各实施方式中，可以采用将各半导体部分的导电型反转后的结构。即，可以将p型的部分设为n型，将n型的部分设为p型。
以下，示出从本说明书和附图中提取的特征的例子。
后续工序(组装工序)中，各种各样的外力被施加于半导体装置。例如，在半导体装置安装时，使用具备吸嘴的安装机。半导体装置在以被吸嘴吸附保持的状态搬运至连接对象物后，按压安装于连接对象部。此时，从吸嘴朝向连接对象物的外力以及从连接对象物朝向吸嘴的外力被施加于半导体装置。
此外，在半导体装置安装后，利用焊针将导线按压接合于焊盘电极。此时，从焊针朝向连接对象物的外力以及从连接对象物朝向焊针的外力被施加于半导体装置。如果大于芯片强度的外力被施加于半导体装置，则芯片产生裂纹。以下，提供能够缓和外力的半导体装置。
[A1]一种半导体装置，其包含：具有一侧的第一主面和另一侧的第二主面的芯片，包含第一Al层且形成于前述第一主面上的第一主面电极，形成于前述第一主面电极上且与导线连接的焊盘电极，以及包含第二Al层且形成于前述第二主面上的第二主面电极。
根据该半导体装置，第一Al层作为在第一主面侧缓和外力的第一缓冲层来形成，第二Al层作为在第二主面侧缓和外力的第二缓冲层来形成。由此，能够缓和从第一主面朝向第二主面的方向的外力以及从第二主面朝向第一主面的方向的外力。
[A2]如A1所述的半导体装置，其进一步包含在前述第一主面上被覆前述第一主面电极且具有使前述第一主面电极的一部分露出的焊盘开口的绝缘层，前述焊盘电极在前述焊盘开口内形成于前述第一主面电极上。
[A3]如A2所述的半导体装置，前述芯片具有将前述第一主面和前述第二主面连接的侧面，前述绝缘层在前述第一主面上具有与前述侧面留有间隔地形成的周缘。
[A4]如A2或A3所述的半导体装置，前述绝缘层包含树脂层。
[A5]如A1～A4中任一项所述的半导体装置，前述焊盘电极包含与前述第一主面电极不同的金属材料。
[A6]如A1～A5中任一项所述的半导体装置，前述焊盘电极包含Ni层、Pd层和Au层中的至少一者。
[A7]如A1～A6中任一项所述的半导体装置，前述焊盘电极包含从前述第一主面电极侧依次层叠的Ni层和Au层。
[A8]如A1～A7中任一项所述的半导体装置，前述焊盘电极包含从前述第一主面电极侧依次层叠的Ni层、Pd层和Au层。
[A9]如A1～A8中任一项所述的半导体装置，前述第二主面电极包含由与前述第二Al层不同的金属材料构成的1个或多个电极层，前述第二Al层被覆1个或多个前述电极层。
[A10]如A9所述的半导体装置，1个或多个前述电极层包含Ti层、Ni层、Pd层、Au层和Ag层中的至少一者。
[A11]如A9或A10所述的半导体装置，1个或多个前述电极层至少包含与前述第二主面之间形成欧姆接触的欧姆电极层，前述第二Al层至少被覆前述欧姆电极层。
[A12]如A1～A11中任一项所述的半导体装置，前述第二Al层具有小于前述第一Al层的厚度。
[A13]如A1～A12中任一项所述的半导体装置，前述第二Al层包含纯Al层、AlSi合金层、AlCu合金层和AlSiCu合金层中的至少一者。
[A14]如A1～A13中任一项所述的半导体装置，前述第二Al层由纯Al层构成。
[A15]如A1～A14中任一项所述的半导体装置，前述第一Al层包含纯Al层、AlSi合金层、AlCu合金层和AlSiCu合金层中的至少一者。
[A16]如A1～A15中任一项所述的半导体装置，其进一步包含形成于前述第一主面的二极管，前述第一主面电极形成与前述二极管的阳极电连接的阳极电极，前述第二主面电极形成与前述二极管的阴极电连接的阴极电极。
[A17]如A1～A16中任一项所述的半导体装置，其进一步包含形成于前述第一主面的MISFET，前述第一主面电极包含与前述MISFET的栅极电连接的栅极主面电极以及与前述MISFET的源极电连接的源极主面电极，前述焊盘电极包含形成于前述栅极主面电极上的栅极焊盘电极以及形成于前述源极主面电极上的源极焊盘电极，前述第二主面电极形成与前述MISFET的漏极电连接的漏电极。
[A18]如A1～A17中任一项所述的半导体装置，前述芯片具有包含从前述第二主面侧朝向前述第一主面侧依次层叠的半导体基板和外延层的层叠结构。
[A19]如A1～A18中任一项所述的半导体装置，前述芯片的厚度为300μm以下。
[A20]如A1～A19中任一项所述的半导体装置，前述芯片由利用SiC单晶形成的SiC芯片构成。
本申请与2019年4月19日在日本专利局提出的特愿2019-080227号相对应，该申请的全部公开内容通过引用并入至此。对于本发明的实施方式进行了详细说明，但这些只不过是为了明确本发明的技术内容而使用的具体例，本发明不应解释成受到这些具体例的限定，本发明的范围仅由随附的权利要求的范围来限定。
符号说明
1SiC半导体装置；2SiC芯片；3第一主面；4第二主面；5A第一侧面；5B第二侧面；5C第三侧面；5D第四侧面；6SiC半导体基板；7SiC外延层；14第一主面电极；16第一Al层；17绝缘层；18焊盘开口；20树脂层；23焊盘电极；25Ni层；26Pd层；27Au层；31第二主面电极；32第二Al层；33Ti层；34Ni层；35Pd层；36Au层；37Ag层；61SiC半导体装置；62SiC芯片；63第一主面；64第二主面；65A第一侧面；65B第二侧面；65C第三侧面；65D第四侧面；66SiC半导体基板；67SiC外延层；150第一主面电极；151栅极主面电极；152源极主面电极；161第一Al层；170绝缘层；171焊盘开口；172栅极焊盘开口；173源极焊盘开口；175树脂层；190焊盘电极；191栅极焊盘电极；192源极焊盘电极；195Ni层；196Pd层；197Au层；200第二主面电极；201第二Al层；202Ti层；203Ni层；204Pd层；205Au层；206Ag层。

Claims (19)

1.一种SiC半导体装置，其包含：
具有一侧的第一主面和另一侧的第二主面的SiC芯片，
包含第一Al层且形成于所述第一主面上的第一主面电极，
形成于所述第一主面电极上且与导线连接的焊盘电极，以及
包含第二Al层且形成于所述第二主面上的第二主面电极。
2.根据权利要求1所述的SiC半导体装置，其进一步包含在所述第一主面上被覆所述第一主面电极且具有使所述第一主面电极的一部分露出的焊盘开口的绝缘层，
所述焊盘电极在所述焊盘开口内形成于所述第一主面电极上。
3.根据权利要求2所述的SiC半导体装置，所述SiC芯片具有将所述第一主面和所述第二主面连接的侧面，
所述绝缘层在所述第一主面上具有与所述侧面留有间隔地形成的周缘。
4.根据权利要求2或3所述的SiC半导体装置，所述绝缘层包含树脂层。
5.根据权利要求1～4中任一项所述的SiC半导体装置，所述焊盘电极包含与所述第一主面电极不同的金属材料。
6.根据权利要求1～5中任一项所述的SiC半导体装置，所述焊盘电极包含Ni层、Pd层和Au层中的至少一者。
7.根据权利要求1～6中任一项所述的SiC半导体装置，所述焊盘电极包含从所述第一主面电极侧依次层叠的Ni层和Au层。
8.根据权利要求1～7中任一项所述的SiC半导体装置，所述焊盘电极包含从所述第一主面电极侧依次层叠的Ni层、Pd层和Au层。
9.根据权利要求1～8中任一项所述的SiC半导体装置，所述第二主面电极包含由与所述第二Al层不同的金属材料构成的1个或多个电极层，
所述第二Al层被覆1个或多个所述电极层。
10.根据权利要求9所述的SiC半导体装置，1个或多个所述电极层包含Ti层、Ni层、Pd层、Au层和Ag层中的至少一者。
11.根据权利要求9或10所述的SiC半导体装置，1个或多个所述电极层至少包含与所述第二主面之间形成欧姆接触的欧姆电极层，
所述第二Al层至少被覆所述欧姆电极层。
12.根据权利要求1～11中任一项所述的SiC半导体装置，所述第二Al层具有小于所述第一Al层的厚度。
13.根据权利要求1～12中任一项所述的SiC半导体装置，所述第二Al层包含纯Al层、AlSi合金层、AlCu合金层和AlSiCu合金层中的至少一者。
14.根据权利要求1～13中任一项所述的SiC半导体装置，所述第二Al层由纯Al层构成。
15.根据权利要求1～14中任一项所述的SiC半导体装置，所述第一Al层包含纯Al层、AlSi合金层、AlCu合金层和AlSiCu合金层中的至少一者。
16.根据权利要求1～15中任一项所述的SiC半导体装置，其进一步包含形成于所述第一主面的二极管，
所述第一主面电极形成与所述二极管的阳极电连接的阳极电极，
所述第二主面电极形成与所述二极管的阴极电连接的阴极电极。
17.根据权利要求1～16中任一项所述的SiC半导体装置，其进一步包含形成于所述第一主面的MISFET，
所述第一主面电极包含与所述MISFET的栅极电连接的栅极主面电极以及与所述MISFET的源极电连接的源极主面电极，
所述焊盘电极包含形成于所述栅极主面电极上的栅极焊盘电极以及形成于所述源极主面电极上的源极焊盘电极，
所述第二主面电极形成与所述MISFET的漏极电连接的漏电极。
18.根据权利要求1～17中任一项所述的SiC半导体装置，所述SiC芯片具有包含从所述第二主面侧朝向所述第一主面侧依次层叠的SiC半导体基板和SiC外延层的层叠结构。
19.根据权利要求1～18中任一项所述的SiC半导体装置，所述SiC芯片的厚度为300μm以下。
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