WO2020213603A1 - ＳｉＣ半導体装置 - Google Patents

ＳｉＣ半導体装置 Download PDF

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Publication number
WO2020213603A1
WO2020213603A1 PCT/JP2020/016433 JP2020016433W WO2020213603A1 WO 2020213603 A1 WO2020213603 A1 WO 2020213603A1 JP 2020016433 W JP2020016433 W JP 2020016433W WO 2020213603 A1 WO2020213603 A1 WO 2020213603A1
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Prior art keywords
layer
main surface
electrode
less
region
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PCT/JP2020/016433
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English (en)
French (fr)
Inventor
永田　敏雄
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ローム株式会社
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Application filed by ローム株式会社 filed Critical ローム株式会社
Priority to US17/598,028 priority Critical patent/US20220181447A1/en
Priority to CN202080029447.5A priority patent/CN113728441A/zh
Priority to DE112020001334.0T priority patent/DE112020001334T5/de
Priority to JP2021514171A priority patent/JPWO2020213603A1/ja
Priority to DE212020000212.6U priority patent/DE212020000212U1/de
Publication of WO2020213603A1 publication Critical patent/WO2020213603A1/ja
Priority to JP2023193753A priority patent/JP2024003158A/ja

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    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Definitions

  • the present invention relates to a SiC semiconductor device.
  • Patent Document 1 includes a SiC semiconductor (SiC chip), a pad electrode containing Al and formed on the front surface of the SiC substrate, and an ohmic electrode formed on the back surface of the SiC substrate. The device is disclosed. A bonding wire (lead wire) is bonded to the pad electrode.
  • various external forces are applied to the SiC semiconductor device.
  • a mounting machine provided with a suction nozzle is used.
  • the SiC semiconductor device is conveyed to the object to be connected while being attracted and held by the suction nozzle, and then pressed and mounted on the object to be connected.
  • an external force from the suction nozzle toward the connection target and an external force from the connection target toward the suction nozzle are applied to the SiC semiconductor device.
  • the lead wire is press-bonded to the pad electrode by the capillary.
  • an external force from the capillary toward the connection object and an external force from the connection object toward the capillary are applied to the SiC semiconductor device.
  • an external force exceeding the strength of the SiC chip is applied to the SiC semiconductor device, cracks occur in the SiC chip.
  • One embodiment of the present invention provides a SiC semiconductor device capable of alleviating an external force.
  • One embodiment of the present invention includes a SiC chip having a first main surface on one side and a second main surface on the other side, a first Al layer, and a first main surface formed on the first main surface. Includes an electrode, a pad electrode formed on the first main surface electrode and connected to a lead wire, and a second main surface electrode including a second Al layer and formed on the second main surface. , SiC semiconductor device.
  • the first Al layer is formed as a first buffer layer that relaxes an external force on the first main surface side
  • the second Al layer is formed as a second buffer layer that relaxes an external force on the second main surface side.
  • FIG. 1 is a plan view showing a SiC semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG. 1, showing a form in which the second main surface electrode according to the first embodiment is incorporated.
  • FIG. 3 is a cross-sectional view schematically showing the second main surface electrode shown in FIG.
  • FIG. 4A is a cross-sectional view schematically showing the second main surface electrode according to the second embodiment.
  • FIG. 4B is a cross-sectional view schematically showing the second main surface electrode according to the third embodiment.
  • FIG. 4C is a cross-sectional view schematically showing the second main surface electrode according to the fourth embodiment.
  • FIG. 1 is a plan view showing a SiC semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG. 1, showing a form in which the second main surface electrode according to the first embodiment is incorporated.
  • FIG. 4D is a cross-sectional view schematically showing the second main surface electrode according to the fifth embodiment.
  • FIG. 4E is a cross-sectional view schematically showing the second main surface electrode according to the sixth embodiment.
  • FIG. 4F is a cross-sectional view schematically showing the second main surface electrode according to the seventh embodiment.
  • FIG. 4G is a cross-sectional view schematically showing the second main surface electrode according to the eighth embodiment.
  • FIG. 4H is a cross-sectional view schematically showing the second main surface electrode according to the ninth embodiment.
  • FIG. 4I is a cross-sectional view schematically showing the second main surface electrode according to the tenth embodiment.
  • FIG. 5 is a diagram showing a semiconductor package in which the SiC semiconductor device shown in FIG. 1 is incorporated.
  • FIG. 5 is a diagram showing a semiconductor package in which the SiC semiconductor device shown in FIG. 1 is incorporated.
  • FIG. 5 is a diagram showing a semiconductor package in which the SiC semiconductor device shown in FIG. 1
  • FIG. 6 is a perspective view of the SiC semiconductor device according to the second embodiment of the present invention, showing a form in which the second main surface electrode according to the first embodiment is incorporated.
  • FIG. 7 is a plan view of the SiC semiconductor device shown in FIG.
  • FIG. 8 is a plan view in which the structure on the first main surface electrode is removed.
  • FIG. 9 is an enlarged plan view showing the internal structure of the region IX shown in FIG.
  • FIG. 10 is a cross-sectional view taken along the line XX shown in FIG.
  • FIG. 11 is a cross-sectional view taken along the line XI-XI shown in FIG.
  • FIG. 12 is an enlarged view of the region XII shown in FIG. FIG.
  • FIG. 13 is a cross-sectional view taken along the line XIII-XIII shown in FIG.
  • FIG. 14 is a cross-sectional view showing a gate pad electrode.
  • FIG. 15 is a cross-sectional view showing a source pad electrode.
  • FIG. 16 is a cross-sectional view illustrating the second main surface electrode graphically.
  • FIG. 17A is a cross-sectional view schematically showing the second main surface electrode according to the second embodiment.
  • FIG. 17B is a cross-sectional view schematically showing the second main surface electrode according to the third embodiment.
  • FIG. 17C is a cross-sectional view schematically showing the second main surface electrode according to the fourth embodiment.
  • FIG. 17D is a cross-sectional view schematically showing the second main surface electrode according to the fifth embodiment.
  • FIG. 17A is a cross-sectional view schematically showing the second main surface electrode according to the second embodiment.
  • FIG. 17B is a cross-sectional view schematically showing the second main surface electrode according to the third
  • FIG. 17E is a cross-sectional view schematically showing the second main surface electrode according to the sixth embodiment.
  • FIG. 17F is a cross-sectional view schematically showing the second main surface electrode according to the seventh embodiment.
  • FIG. 17G is a cross-sectional view schematically showing the second main surface electrode according to the eighth embodiment.
  • FIG. 17H is a cross-sectional view schematically showing the second main surface electrode according to the ninth embodiment.
  • FIG. 17I is a cross-sectional view schematically showing the second main surface electrode according to the tenth embodiment.
  • FIG. 18 is a diagram showing a semiconductor package in which the SiC semiconductor device shown in FIG. 6 is incorporated.
  • FIG. 1 is a plan view showing the SiC semiconductor device 1 according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG. 1, showing a form in which the second main surface electrode 31 according to the first embodiment is incorporated.
  • FIG. 3 is a cross-sectional view schematically showing the second main surface electrode 31 shown in FIG.
  • the SiC semiconductor device 1 includes a SiC chip 2.
  • the SiC chip 2 contains a SiC single crystal composed of hexagonal crystals.
  • the SiC single crystal composed of hexagonal crystals has a plurality of polytypes including 2H (Hexagonal) -SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc., depending on the period of the atomic arrangement. ..
  • the SiC chip 2 is composed of a 4H-SiC single crystal in this form (this embodiment), but does not exclude other polytypes.
  • the SiC chip 2 is formed in the shape of a rectangular parallelepiped chip.
  • the SiC chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4. ing.
  • the first main surface 3 and the second main surface 4 are formed in a square shape (in this form, a square shape) in a plan view (hereinafter, simply referred to as "plan view”) viewed from their normal direction Z. ..
  • the thickness of the SiC chip 2 may be 40 ⁇ m or more and 300 ⁇ m or less.
  • the thickness of the SiC chip 2 may be 40 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, 200 ⁇ m or more and 250 ⁇ m or less, or 250 ⁇ m or more and 300 ⁇ m or less.
  • the thickness of the SiC chip 2 is preferably 60 ⁇ m or more and 150 ⁇ m or less.
  • the first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal.
  • the first main surface 3 faces the silicon surface ((0001) surface) of the SiC single crystal.
  • the first main surface 3 is a non-mounting surface.
  • the second main surface 4 faces the carbon surface ((000-1) surface) of the SiC single crystal.
  • the second main surface 4 is a mounting surface.
  • the second main surface 4 may be a rough surface having either or both of grinding marks and annealing marks.
  • the annealing marks are laser irradiation marks.
  • the second main surface 4 may be an ohmic surface having annealing marks.
  • the first main surface 3 and the second main surface 4 have an off angle inclined at an angle of 0 ° or more and 10 ° or less in the a-axis direction ([11-20] direction) with respect to the c-plane of the SiC single crystal. ing.
  • the normal direction Z is inclined by an off angle with respect to the c-axis ([0001] direction) of the SiC single crystal.
  • the off angle may be 0 ° or more and 6 ° or less.
  • the off angle may be 0 ° or more and 2 ° or less, 2 ° or more and 4 ° or less, or 4 ° or more and 6 ° or less.
  • the off angle is preferably more than 0 ° and 4.5 ° or less.
  • the off angle may be 3 ° or more and 4.5 ° or less. In this case, the off angle is preferably 3 ° or more and 3.5 ° or less, or 3.5 ° or more and 4 ° or less.
  • the off angle may be 1.5 ° or more and 3 ° or less. In this case, the off angle is preferably 1.5 ° or more and 2 ° or less, or 2 ° or more and 2.5 ° or less.
  • Side surfaces 5A to 5D include a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D.
  • the first side surface 5A and the second side surface 5B extend along the first direction X and face each other in the second direction Y intersecting the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is orthogonal to the first direction X.
  • the first side surface 5A and the second side surface 5B are formed by the a-plane of the SiC single crystal.
  • the first side surface 5A and the second side surface 5B form an inclined surface inclined toward the c-axis direction ([0001] direction) of the SiC single crystal with respect to the normal direction Z with respect to the normal direction Z. You may be doing it.
  • the first side surface 5A and the second side surface 5B may be inclined at an angle corresponding to the off angle with respect to the normal direction Z when the normal direction Z is 0 °.
  • the angle according to the off angle may be equal to the off angle, or may be an angle exceeding 0 ° and less than the off angle.
  • the third side surface 5C and the fourth side surface 5D may be formed by the m-plane of the SiC single crystal.
  • the third side surface 5C and the fourth side surface 5D extend in a plane along the normal direction Z. More specifically, the third side surface 5C and the fourth side surface 5D are formed substantially perpendicular to the first main surface 3 and the second main surface 4.
  • the side surfaces 5A to 5D may consist of a cleavage surface or a ground surface.
  • the length of the side surfaces 5A to 5D may be 0.1 mm or more and 10 mm or less.
  • the length of the side surfaces 5A to 5D is preferably 0.5 mm or more and 2.5 mm or less.
  • the SiC chip 2 has a laminated structure including an n + type SiC semiconductor substrate 6 and an n-type SiC epitaxial layer 7.
  • the second main surface 4 of the SiC chip 2 is formed by the SiC semiconductor substrate 6.
  • the first main surface 3 of the SiC chip 2 is formed by the SiC epitaxial layer 7.
  • the side surfaces 5A to 5D of the SiC chip 2 are formed by the SiC semiconductor substrate 6 and the SiC epitaxial layer 7.
  • the concentration of n-type impurities in the SiC epitaxial layer 7 is less than the concentration of n-type impurities in the SiC semiconductor substrate 6.
  • the concentration of n-type impurities in the SiC semiconductor substrate 6 may be 1.0 ⁇ 10 18 cm -3 or more and 1.0 ⁇ 10 21 cm -3 or less.
  • the concentration of n-type impurities in the SiC epitaxial layer 7 may be 1.0 ⁇ 10 15 cm -3 or more and 1.0 ⁇ 10 18 cm -3 or less.
  • the thickness of the SiC semiconductor substrate 6 may be 40 ⁇ m or more and 250 ⁇ m or less.
  • the thickness of the SiC semiconductor substrate 6 may be 40 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, or 200 ⁇ m or more and 250 ⁇ m or less.
  • the thickness of the SiC semiconductor substrate 6 is preferably 40 ⁇ m or more and 150 ⁇ m or less.
  • the thickness of the SiC epitaxial layer 7 may be 1 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the SiC epitaxial layer 7 may be 1 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 15 ⁇ m or less, 15 ⁇ m or more and 20 ⁇ m or less, 20 ⁇ m or more and 30 ⁇ m or less, 30 ⁇ m or more and 40 ⁇ m or less, or 40 ⁇ m or more and 50 ⁇ m or less. ..
  • the thickness of the SiC epitaxial layer 7 is preferably 5 ⁇ m or more and 15 ⁇ m or less.
  • the SiC chip 2 includes an active region 8 and an outer region 9.
  • the active region 8 is an region including an SBD (Schottky Barrier Diode) as an example of a functional device (diode).
  • the active region 8 is formed in the central portion of the SiC chip 2 at intervals inward from the side surfaces 5A to 5D in a plan view.
  • the active region 8 is formed in a quadrangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.
  • the outer region 9 is an region outside the active region 8.
  • the outer region 9 is formed in the region between the side surfaces 5A to 5D and the active region 8.
  • the outer region 9 is formed in an annular shape (more specifically, an endless shape) surrounding the active region 8 in a plan view.
  • the SiC semiconductor device 1 includes an n-type diode region 10 formed on the surface layer portion of the first main surface 3 in the active region 8.
  • the diode region 10 is formed in the central portion of the first main surface 3.
  • the planar shape of the diode region 10 is arbitrary.
  • the diode region 10 may be formed in a quadrangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.
  • the diode region 10 is formed by utilizing a part of the SiC epitaxial layer 7.
  • the n-type impurity concentration in the diode region 10 is equal to the n-type impurity concentration in the SiC epitaxial layer 7.
  • the n-type impurity concentration in the diode region 10 may exceed the n-type impurity concentration in the SiC epitaxial layer 7.
  • the diode region 10 is formed by introducing an n-type impurity into the surface layer portion of the SiC epitaxial layer 7.
  • a guard region 11 containing p-type impurities is formed on the surface layer portion of the first main surface 3.
  • the p-type impurity in the guard region 11 may not be activated or may be activated.
  • the guard region 11 is formed in a band shape extending along the diode region 10 in a plan view. More specifically, the guard region 11 is formed in an annular shape (more specifically, an endless shape) surrounding the diode region 10 in a plan view. As a result, the guard region 11 is formed as a guard ring region.
  • the active region 8 (diode region 10) is defined by the guard region 11.
  • the planar shape of the active region 8 (diode region 10) is adjusted by the planar shape of the guard region 11.
  • the guard region 11 may be formed in a polygonal ring or an annular shape in a plan view.
  • the SiC semiconductor device 1 includes a main surface insulating layer 12 formed on the first main surface 3.
  • the main surface insulating layer 12 may have a laminated structure including a silicon oxide layer and a silicon nitride layer.
  • the main surface insulating layer 12 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. In this form, the main surface insulating layer 12 has a single-layer structure composed of a silicon oxide layer.
  • the peripheral edge of the main surface insulating layer 12 is exposed from the side surfaces 5A to 5D.
  • the peripheral edge of the main surface insulating layer 12 is continuous with the side surfaces 5A to 5D.
  • the peripheral edge of the main surface insulating layer 12 may be formed at intervals inward from the side surfaces 5A to 5D. In this case, the main surface insulating layer 12 exposes a portion of the first main surface 3 located in the outer region 9.
  • the thickness of the main surface insulating layer 12 may be 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the main surface insulating layer 12 may be 0.1 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, or 8 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the main surface insulating layer 12 is preferably 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the SiC semiconductor device 1 includes a first main surface electrode 14 formed on the first main surface 3.
  • the first main surface electrode 14 is connected to the diode region 10 and the guard region 11 in the contact opening 13.
  • the first main surface electrode 14 is drawn out from the contact opening 13 onto the main surface insulating layer 12.
  • the peripheral edge of the first main surface electrode 14 is formed on the main surface insulating layer 12 at intervals inward from the side surfaces 5A to 5D.
  • the Schottky barrier layer 15 is formed in a film shape along the first main surface 3 and the main surface insulating layer 12.
  • the Schottky barrier layer 15 forms a Schottky junction with the diode region 10.
  • an SBD having the first main surface electrode 14 as the anode and the diode region 10 as the cathode is formed. That is, the first main surface electrode 14 is the anode electrode of the SBD.
  • the Schottky barrier layer 15 may include at least one of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer.
  • the thickness of the Schottky barrier layer 15 may be 0.01 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the Schottky barrier layer 15 is 0.01 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 4 ⁇ m or less, or 4 ⁇ m or more and 5 ⁇ m or less. May be good.
  • the first Al layer 16 is formed on the Schottky barrier layer 15.
  • the first Al layer 16 is formed in a film shape along the Schottky barrier layer 15.
  • the first Al layer 16 covers the entire main surface of the Schottky barrier layer 15.
  • the peripheral edge of the first main surface electrode 14 is formed by the Schottky barrier layer 15 and the first Al layer 16.
  • the first Al layer 16 includes at least one of a pure Al layer (meaning an Al layer composed of Al having a purity of 99% or more; the same applies hereinafter), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. ..
  • the first Al layer 16 may have a laminated structure in which two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer and an AlSiCu alloy layer are laminated in any order.
  • the first Al layer 16 may have a single layer structure composed of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.
  • the first Al layer 16 preferably has a single-layer structure composed of an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.
  • the thickness of the first Al layer 16 exceeds the thickness of the Schottky barrier layer 15.
  • the thickness of the first Al layer 16 may be 0.05 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the first Al layer 16 is 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, or 8 ⁇ m or more and 10 ⁇ m. It may be as follows.
  • the thickness of the first Al layer 16 is preferably 1 ⁇ m or more and 8 ⁇ m or less.
  • the SiC semiconductor device 1 includes an insulating layer 17 that covers the first main surface electrode 14 on the first main surface 3.
  • the insulating layer 17 is shown by hatching. More specifically, the insulating layer 17 is formed on the main surface insulating layer 12. The peripheral edge of the insulating layer 17 is formed at intervals inward from the side surfaces 5A to 5D. As a result, the insulating layer 17 exposes the portion of the main surface insulating layer 12 that covers the outer region 9.
  • the peripheral edge of the insulating layer 17 partitions the dicing street DS between the side surfaces 5A to 5D. According to the dicing street DS, when cutting out the SiC semiconductor device 1 from the SiC wafer, it is not necessary to physically cut the insulating layer 17. As a result, the SiC semiconductor device 1 can be smoothly cut out from the SiC wafer, and at the same time, peeling and deterioration of the insulating layer 17 can be suppressed. As a result, the insulating layer 17 can appropriately protect the object to be protected such as the SiC chip 2 and the first main surface electrode 14.
  • the width of the dicing street DS may be 1 ⁇ m or more and 25 ⁇ m or less.
  • the width of the dicing street DS is the width in the direction orthogonal to the direction in which the dicing street DS extends.
  • the width of the dicing street DS may be 1 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 15 ⁇ m or less, 15 ⁇ m or more and 20 ⁇ m or less, or 20 ⁇ m or more and 25 ⁇ m or less.
  • the insulating layer 17 has a pad opening 18 that exposes the first main surface electrode 14.
  • the pad opening 18 exposes the first main surface electrode 14 in the region surrounded by the contact opening 13 in a plan view.
  • the pad opening 18 may surround the contact opening 13 in a region outside the contact opening 13 in a plan view.
  • the planar shape of the pad opening 18 is arbitrary.
  • the pad opening 18 may be formed in a quadrangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.
  • the insulating layer 17 has a laminated structure including a passivation layer 19 and a resin layer 20 laminated in this order from the SiC chip 2 side.
  • the passivation layer 19 may include at least one of a silicon oxide layer and a silicon nitride layer.
  • the passivation layer 19 may have a laminated structure including a silicon oxide layer and a silicon nitride layer.
  • the passivation layer 19 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer.
  • the passivation layer 19 preferably contains an insulating material different from that of the main surface insulating layer 12. In this form, the passivation layer 19 has a single-layer structure composed of a silicon nitride layer.
  • the passivation layer 19 is formed in a film shape along the main surface insulating layer 12 and the first main surface electrode 14.
  • the passivation layer 19 has a first opening 21 that exposes a part of the first main surface electrode 14.
  • the planar shape of the first opening 21 is arbitrary.
  • the first opening 21 may be formed in a quadrangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.
  • the thickness of the passivation layer 19 may be 0.1 ⁇ m or more and 20 ⁇ m or less.
  • the thickness of the passivation layer 19 may be 0.1 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 15 ⁇ m or less, or 15 ⁇ m or more and 20 ⁇ m or less.
  • the resin layer 20 is formed in a film shape along the main surface of the passivation layer 19.
  • the resin layer 20 may contain a photosensitive resin.
  • the photosensitive resin may be a negative type or a positive type.
  • the resin layer 20 may contain at least one of polyimide, polyamide and polybenzoxazole.
  • the resin layer 20 contains polybenzoxazole in this form.
  • the peripheral edge of the resin layer 20 exposes the peripheral edge of the passivation layer 19.
  • the peripheral edge of the insulating layer 17 is formed by the peripheral edge of the resin layer 20 and the peripheral edge of the passivation layer 19.
  • the resin layer 20 may cover the peripheral edge of the passivation layer 19.
  • the resin layer 20 has a second opening 22 that exposes a part of the first main surface electrode 14.
  • the planar shape of the second opening 22 is arbitrary.
  • the second opening 22 may be formed in a quadrangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.
  • the second opening 22 communicates with the first opening 21 of the passivation layer 19 and forms one pad opening 18 with the first opening 21.
  • the inner wall of the second opening 22 may be formed flush with the inner wall of the first opening 21.
  • the inner wall of the second opening 22 may be located on the side surface 5A to 5D side with respect to the inner wall of the first opening 21.
  • the inner wall of the second opening 22 may be located inside the SiC chip 2 with respect to the inner wall of the first opening 21. That is, the resin layer 20 may cover the inner wall of the first opening 21.
  • the thickness of the resin layer 20 may be 1 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the resin layer 20 may be 1 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 20 ⁇ m or less, 20 ⁇ m or more and 30 ⁇ m or less, 30 ⁇ m or more and 40 ⁇ m or less, or 40 ⁇ m or more and 50 ⁇ m or less.
  • the SiC semiconductor device 1 includes a pad electrode 23 formed on the first main surface electrode 14.
  • the pad electrode 23 is electrically connected to the first main surface electrode 14.
  • the pad electrode 23 is formed on the first main surface electrode 14 in the pad opening 18.
  • the pad electrode 23 has a terminal surface 24 that is externally connected to the conducting wire.
  • the terminal surface 24 is located on the first main surface electrode 14 side with respect to the main surface of the insulating layer 17 (resin layer 20).
  • the terminal surface 24 may project above the main surface of the insulating layer 17 (resin layer 20).
  • the terminal surface 24 may have an overlapping portion that covers the main surface of the insulating layer 17 (resin layer 20).
  • the pad electrode 23 contains a metal material different from that of the first main surface electrode 14.
  • the pad electrode 23 has a laminated structure including a Ni layer 25, a Pd layer 26, and an Au layer 27 that are laminated in this order from the first main surface electrode 14 side.
  • Ni, Pd, and Au each have a Young's modulus (rigidity) that exceeds the Young's modulus (rigidity) of Al.
  • the Ni layer 25, the Pd layer 26, and the Au layer 27 may be plating layers formed by a plating method.
  • the pad electrode 23 may include at least one of the Ni layer 25, the Pd layer 26, and the Au layer 27.
  • the pad electrode 23 may have a laminated structure in which at least two of the Ni layer 25, the Pd layer 26, and the Au layer 27 are laminated in any order.
  • the pad electrode 23 may have a single-layer structure composed of a Ni layer 25, a Pd layer 26, or an Au layer 27.
  • the pad electrode 23 preferably has a terminal surface 24 formed by the Au layer 27.
  • the pad electrode 23 preferably has a laminated structure including a Ni layer 25 and an Au layer 27 laminated in this order from at least the first main surface electrode 14 side.
  • the thickness of the Ni layer 25 may be 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the Ni layer 25 is 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, or 8 ⁇ m or more and 10 ⁇ m or less. It may be.
  • the thickness of the Pd layer 26 may be 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the Pd layer 26 is 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, or 8 ⁇ m or more and 10 ⁇ m or less. It may be.
  • the thickness of the Au layer 27 may be 0.01 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the Au layer 27 is 0.01 ⁇ m or more and 0.05 ⁇ m or less, 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, or 2 ⁇ m. It may be 3 ⁇ m or more.
  • the thickness of the Au layer 27 is preferably less than the thickness of the Ni layer 25.
  • the thickness of the Au layer 27 is preferably less than the thickness of the Pd layer 26.
  • the SiC semiconductor device 1 includes a second main surface electrode 31 formed on the second main surface 4.
  • the second main surface electrode 31 is formed as a cathode electrode of the SBD. In this form, the second main surface electrode 31 covers the entire area of the second main surface 4.
  • the second main surface electrode 31 may be formed at intervals inward from the side surfaces 5A to 5D to expose the peripheral edge portion of the second main surface 4. In this case, it is not necessary to physically cut the second main surface electrode 31 when cutting out the SiC semiconductor device 1 from the SiC wafer. As a result, the SiC semiconductor device 1 can be smoothly cut out from the SiC wafer, and at the same time, peeling and deterioration of the second main surface electrode 31 can be suppressed. As a result, the second main surface electrode 31 can be appropriately connected to the second main surface 4.
  • Such a second main surface electrode 31 can be obtained, for example, by removing an unnecessary portion of the second main surface electrode 31 by an etching method using a resist mask during the manufacturing process. Further, as another example, the second main surface electrode 31 is formed by forming the second main surface electrode 31 that partially covers the second main surface 4 by a lift-off method using a resist mask during the manufacturing process. Obtainable.
  • the second main surface electrode 31 includes a second Al layer 32 that covers the second main surface 4.
  • the second Al layer 32 faces the first Al layer 16 of the first main surface electrode 14 with the SiC chip 2 interposed therebetween.
  • the second Al layer 32 is formed as a second buffer layer that relaxes the external force applied to the SiC chip 2 from the second main surface 4 side by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity). There is.
  • the second Al layer 32 includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.
  • the second Al layer 32 may have a laminated structure in which two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer and an AlSiCu alloy layer are laminated in any order.
  • the second Al layer 32 may be formed by a sputtering method and / or a vapor deposition method.
  • the second Al layer 32 may have a single layer structure composed of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.
  • the Al-based metal material of the second Al layer 32 may be different from the Al-based metal material of the first Al layer 16.
  • the second Al layer 32 preferably has a single-layer structure composed of a pure Al layer.
  • the second Al layer 32 may have a thickness less than the thickness of the first Al layer 16.
  • the thickness of the second Al layer 32 may be 0.01 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the second Al layer 32 may be 0.01 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 4 ⁇ m or less, or 4 ⁇ m or more and 5 ⁇ m or less. Good.
  • the second main surface electrode 31 further includes one or more electrode layers made of a metal material different from that of the second Al layer 32, in addition to the second Al layer 32.
  • the second main surface electrode 31 is a Ti layer 33, a Ni layer 34, a Pd layer 35, an Au layer 36, and an Ag layer 37, which are laminated in this order from the second main surface 4 side as an example of a plurality of electrode layers. including.
  • the Ti layer 33 is an ohmic electrode that forms ohmic contact with the second main surface 4.
  • the second Al layer 32 covers the second main surface 4 with the Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36, and the Ag layer 37 interposed therebetween.
  • Ti, Ni, Pd, Au and Ag each have a Young's modulus (rigidity) that exceeds the Young's modulus (rigidity) of Al.
  • the Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36 and the Ag layer 37 may be formed by a sputtering method, a vapor deposition method and / or a plating method.
  • the second main surface electrode 31 may include at least one of the Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36, and the Ag layer 37 as one or more electrode layers.
  • the second Al layer 32 preferably covers the second main surface 4 with at least the Ti layer 33 interposed therebetween.
  • the second main surface electrode 31 includes at least one of the Ni layer 34, the Pd layer 35 and the Au layer 36, at least one of the Ni layer 34, the Pd layer 35 and the Au layer 36 is the pad electrode 23.
  • the plating layer may be formed at the same time as the Ni layer 25, the Pd layer 26, and the Au layer 27.
  • the thickness of the Ti layer 33 may be 0.01 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the Ti layer 33 is 0.01 ⁇ m or more and 0.05 ⁇ m or less, 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, or 2 ⁇ m. It may be 3 ⁇ m or more.
  • the thickness of the Au layer 36 may be 0.01 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the Au layer 36 is 0.01 ⁇ m or more and 0.05 ⁇ m or less, 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, or 2 ⁇ m. It may be 3 ⁇ m or more.
  • the thickness of the Au layer 36 is preferably less than the thickness of the Ni layer 34.
  • the thickness of the Au layer 36 is preferably less than the thickness of the Pd layer 35.
  • the thickness of the Ag layer 37 may be 0.01 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the Ag layer 37 is 0.01 ⁇ m or more and 0.05 ⁇ m or less, 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, or 2 ⁇ m. It may be 3 ⁇ m or more.
  • the thickness of the Ag layer 37 is preferably less than the thickness of the Ni layer 34.
  • the thickness of the Ag layer 37 is preferably less than the thickness of the Pd layer 35.
  • the second main surface electrode 31 may have the structure shown in FIGS. 4A to 4I.
  • FIG. 4A is a cross-sectional view schematically showing the second main surface electrode 31 according to the second embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 1 to 3, and the description thereof will be omitted.
  • the second main surface electrode 31 has a laminated structure including the second Al layer 32, the Ti layer 33, the Ni layer 34, the Pd layer 35, and the Au layer 36 in this form.
  • the Ti layer 33, the Ni layer 34, the Pd layer 35, and the Au layer 36 are laminated in this order from the second main surface 4 side.
  • the second Al layer 32 covers the second main surface 4 with the Ti layer 33, the Ni layer 34, the Pd layer 35, and the Au layer 36 interposed therebetween.
  • FIG. 4B is a cross-sectional view schematically showing the second main surface electrode 31 according to the third embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 1 to 3, and the description thereof will be omitted.
  • the second main surface electrode 31 has a laminated structure including the second Al layer 32, the Ti layer 33, the Ni layer 34, the Au layer 36, and the Ag layer 37 in this form.
  • the Ti layer 33, the Ni layer 34, the Au layer 36, and the Ag layer 37 are laminated in this order from the second main surface 4 side.
  • the second Al layer 32 covers the second main surface 4 with the Ti layer 33, the Ni layer 34, the Au layer 36, and the Ag layer 37 interposed therebetween.
  • FIG. 4C is a cross-sectional view schematically showing the second main surface electrode 31 according to the fourth embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 1 to 3, and the description thereof will be omitted.
  • the second main surface electrode 31 has a laminated structure including the second Al layer 32, the Ti layer 33, the Ni layer 34, and the Au layer 36 in this form.
  • the Ti layer 33, the Ni layer 34, and the Au layer 36 are laminated in this order from the second main surface 4 side.
  • the second Al layer 32 covers the second main surface 4 with the Ti layer 33, the Ni layer 34, and the Au layer 36 interposed therebetween.
  • FIG. 4D is a cross-sectional view schematically showing the second main surface electrode 31 according to the fifth embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 1 to 3, and the description thereof will be omitted.
  • FIG. 4E is a cross-sectional view schematically showing the second main surface electrode 31 according to the sixth embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 1 to 3, and the description thereof will be omitted.
  • the second main surface electrode 31 includes a second Al layer 32, a Ti layer 33, a Ni layer 34 and an Au layer 36 in this form.
  • the Ti layer 33, the Ni layer 34, and the Au layer 36 are laminated in this order from the second main surface 4 side.
  • the second Al layer 32 is interposed between the Ti layer 33 and the Ni layer 34, and covers the second main surface 4 with the Ti layer 33 interposed therebetween.
  • the pad electrode 23 has a two-layer structure composed of a Ni layer 25 and an Au layer 27 laminated in this order from the first main surface electrode 14 side.
  • the Ni layer 34 and the Au layer 36 of the second main surface electrode 31 can be formed at the same time as the Ni layer 25 and the Au layer 27 of the pad electrode 23 by the plating method.
  • the second main surface electrode 31 includes a second Al layer 32, a Ti layer 33, a Ni layer 34, an Au layer 36, and an Ag layer 37 in this form.
  • the Ti layer 33, the Ni layer 34, the Au layer 36, and the Ag layer 37 are laminated in this order from the second main surface 4 side.
  • the second Al layer 32 is interposed between the Ti layer 33 and the Ni layer 34, and covers the second main surface 4 with the Ti layer 33 interposed therebetween.
  • FIG. 4G is a cross-sectional view schematically showing the second main surface electrode 31 according to the eighth embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 1 to 3, and the description thereof will be omitted.
  • the pad electrode 23 preferably has a three-layer structure composed of a Ni layer 25, a Pd layer 26, and an Au layer 27 laminated in this order from the first main surface electrode 14 side.
  • the Ni layer 34, the Pd layer 35, and the Au layer 36 of the second main surface electrode 31 can be formed at the same time as the Ni layer 25, the Pd layer 26, and the Au layer 27 of the pad electrode 23 by the plating method.
  • FIG. 4H is a cross-sectional view schematically showing the second main surface electrode 31 according to the ninth embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 1 to 3, and the description thereof will be omitted.
  • the second main surface electrode 31 includes a second Al layer 32, a Ti layer 33, a Ni layer 34, a Pd layer 35 and an Au layer 36 in this form.
  • the Ti layer 33, the Ni layer 34, the Pd layer 35, and the Au layer 36 are laminated in this order from the second main surface 4 side.
  • the second Al layer 32 is interposed between the Ti layer 33 and the Ni layer 34, and covers the second main surface 4 with the Ti layer 33 interposed therebetween.
  • the pad electrode 23 preferably has a three-layer structure composed of a Ni layer 25, a Pd layer 26, and an Au layer 27 laminated in this order from the first main surface electrode 14 side.
  • the Ni layer 34, the Pd layer 35, and the Au layer 36 of the second main surface electrode 31 can be formed at the same time as the Ni layer 25, the Pd layer 26, and the Au layer 27 of the pad electrode 23 by the plating method.
  • FIG. 4I is a cross-sectional view schematically showing the second main surface electrode 31 according to the tenth embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 1 to 3, and the description thereof will be omitted.
  • the second main surface electrode 31 includes a second Al layer 32 and a VDD layer 38 in this form.
  • the silicide layer 38 is formed on the second main surface 4.
  • the silicide layer 38 is a layer in which SiC exposed from the second main surface 4 is silicidalized with a metal material.
  • the silicide layer 38 is among the FeSi 2 layer, NiSi layer, NiSi 2 layer, CoSi 2 layer, CrSi 2 layer, WSi 2 layer, MoSi 2 layer, MnSi 2 layer, NbSi 2 layer, TiSi 2 layer and VSi 2 layer. At least one may be included.
  • the second Al layer 32 covers the second main surface 4 with the VDD layer 38 interposed therebetween.
  • the second main surface electrode 31 may include at least one of the Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36, and the Ag layer 37, in addition to the second Al layer 32 and the VDD layer 38. ..
  • the stacking order of the second Al layer 32, the Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36, and the Ag layer 37 is arbitrary.
  • any one of the laminated structures of the first to tenth embodiments may be adopted.
  • FIG. 5 is a diagram showing a semiconductor package 41 in which the SiC semiconductor device 1 shown in FIG. 1 is incorporated.
  • the internal structure of the semiconductor package 41 is shown through the package body 42.
  • the semiconductor package 41 is a 2-terminal type TO-220 in this form.
  • the semiconductor package 41 includes a package body 42, a metal plate 43, a first terminal 44, a second terminal 45, a SiC semiconductor device 1, a conductive bonding material 46, and a conducting wire 47.
  • the package body 42 is made of mold resin.
  • the package body 42 may contain an epoxy resin as an example of the mold resin.
  • the package body 42 is formed in a rectangular parallelepiped shape.
  • the package body 42 includes a first surface 48 on one side and a second surface 49 on the other side, and four sides 50A, 50B, 50C, 50D connecting the first surface 48 and the second surface 49.
  • the metal plate 43 is arranged in the package body 42 so as to be exposed from the second surface 49.
  • the metal plate 43 may be arranged in the package body 42 so as not to be exposed from the second surface 49.
  • the first terminal 44 may contain at least one of Fe, Au, Ag, Cu and Al.
  • the first terminal 44 may have an outer surface on which at least one of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film is formed.
  • the first terminal 44 is pulled out from the inside of the package body 42 across the first side surface 50A to the outside of the package body 42.
  • the first terminal 44 is arranged in a region on the fourth side surface 50D side in a plan view.
  • the first terminal 44 is arranged in a region on the first surface 48 side with respect to the plate surface of the metal plate 43.
  • the first terminal 44 includes a first inner end portion 53, a first outer end portion 54, and a first band-shaped portion 55.
  • the first inner end portion 53 is connected to the metal plate 43 in the package main body 42.
  • the first outer end portion 54 is arranged outside the package main body 42.
  • the first band-shaped portion 55 extends between the first inner end portion 53 and the first outer end portion 54 in a direction orthogonal to the first side surface 50A.
  • the second terminal 45 may contain at least one of Fe, Au, Ag, Cu and Al.
  • the second terminal 45 may include at least one of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film. The second terminal 45 is pulled out from the inside of the package body 42 across the first side surface 50A to the outside of the package body 42.
  • the second terminal 45 is arranged in the area on the third side surface 50C side at a distance from the first terminal 44 in a plan view.
  • the second terminal 45 is arranged in a region on the first surface 48 side with respect to the plate surface of the metal plate 43.
  • the second terminal 45 includes a second inner end portion 56, a second outer end portion 57, and a second band-shaped portion 58.
  • the second inner end portion 56 is arranged in the package main body 42 at a distance from the metal plate 43.
  • the second outer end portion 57 is arranged outside the package main body 42.
  • the second band-shaped portion 58 extends between the second inner end portion 56 and the second outer end portion 57 in a direction orthogonal to the first side surface 50A.
  • the SiC semiconductor device 1 is arranged on the pad portion 51 of the metal plate 43 in the package main body 42.
  • the conductive bonding material 46 is interposed between the SiC semiconductor device 1 and the pad portion 51, and the second main surface electrode 31 of the SiC semiconductor device 1 is bonded to the pad portion 51.
  • the SiC semiconductor device 1 is electrically connected to the first terminal 44 via the metal plate 43.
  • the conductive bonding material 46 may be a metal paste or solder.
  • the metal paste may contain at least one of Au, Ag and Cu.
  • the conductive bonding material 46 is preferably made of solder.
  • the solder may be lead-free solder.
  • the solder may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi and SnSbNi.
  • the lead wire 47 is made of a metal wire (bonding wire) or a metal clip.
  • the metal wire may be an Al wire, an Au wire, a Cu wire or a solder wire.
  • the solder wire may be a lead-free solder wire.
  • the solder wire may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi and SnSbNi.
  • the metal clip may be an Al clip, an Au clip or a Cu clip.
  • the lead wire 47 is made of a solder wire in this form.
  • the lead wire 47 is connected to the second inner end portion 56 of the second terminal 45 and the pad electrode 23 of the SiC semiconductor device 1 in the package main body 42. As a result, the SiC semiconductor device 1 is electrically connected to the second terminal 45.
  • FIG. 6 shows an example in which one lead wire 47 is connected to the second inner end portion 56 and the pad electrode 23, but the number of lead wires 47 is arbitrary. Two or more lead wires 47 may be connected to the second inner end portion 56 and the pad electrode 23.
  • the semiconductor package 41 may take a form other than TO-220.
  • the semiconductor package 41 includes SOP (Small Outline Package), QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package) or SOJ. (Small Outline J-leaded Package), or may have various forms similar to these.
  • the first Al layer 16 is formed as a first buffer layer that relaxes the external force on the first main surface 3 side
  • the second Al layer 32 relaxes the external force on the second main surface 4 side. It is formed as a second buffer layer.
  • the external force applied to the SiC chip 2 when the SiC semiconductor device 1 is mounted on the pad portion 51 of the metal plate 43 can be relaxed by the first Al layer 16 and the second Al layer 32. Further, the external force applied to the SiC chip 2 when the lead wire 47 is joined to the pad electrode 23 of the SiC semiconductor device 1 can be relaxed by the first Al layer 16 and the second Al layer 32. As a result, cracks in the SiC chip 2 can be suppressed.
  • the SiC semiconductor device 1 includes a pad electrode 23 externally bonded to the lead wire 47.
  • the pad electrode 23 includes at least one of the Ni layer 25, the Pd layer 26 and the Au layer 27.
  • the lead wire 47 can be appropriately connected to the pad electrode 23.
  • Ni, Pd and Au each have a Young's modulus (rigidity) that exceeds the Young's modulus (rigidity) of Al. Therefore, in the structure provided with the pad electrode 23, the external force applied at the time of joining the lead wires 47 cannot be appropriately relaxed.
  • the first Al layer 16 containing Al is interposed between the SiC chip 2 and the pad electrode 23.
  • the external force applied to the SiC chip 2 can be relaxed from the first main surface 3 side by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity). Therefore, the lead wire 47 can be appropriately bonded to the pad electrode 23, and at the same time, cracks in the SiC chip 2 can be suppressed.
  • the SiC semiconductor device 1 includes, in addition to the second Al layer 32, a second main surface electrode 31 having one or more electrode layers made of a metal material different from the second Al layer 32.
  • the one or more electrode layers include at least one of the Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36 and the Ag layer 37.
  • Ti, Ni, Pd, Au and Ag each have a Young's modulus (rigidity) exceeding the Young's modulus (rigidity) of Al. Therefore, in a structure in which the second main surface electrode 31 includes at least one of the Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36, and the Ag layer 37, when the SiC semiconductor device 1 is mounted or the lead wire 47 The external force applied at the time of joining cannot be properly relaxed.
  • the second main surface electrode 31 including the second Al layer 32 is provided in addition to at least one of the Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36, and the Ag layer 37. Is forming. According to the second Al layer 32, the external force applied to the SiC chip 2 can be relaxed from the second main surface 4 side by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity). Therefore, the SiC semiconductor device 1 can be appropriately mounted on the pad portion 51, and at the same time, cracks in the SiC chip 2 can be suppressed.
  • FIG. 6 is a perspective view of the SiC semiconductor device 61 according to the second embodiment of the present invention, showing a form in which the second main surface electrode 200 according to the first embodiment is incorporated.
  • FIG. 7 is a plan view of the SiC semiconductor device 61 shown in FIG.
  • FIG. 8 is a plan view of the first main surface electrode 150 with the structure above it removed.
  • FIG. 9 is an enlarged plan view showing the internal structure of the region IX shown in FIG.
  • FIG. 10 is a cross-sectional view taken along the line XX shown in FIG.
  • FIG. 11 is a cross-sectional view taken along the line XI-XI shown in FIG.
  • FIG. 12 is an enlarged view of the region XII shown in FIG.
  • FIG. 13 is a cross-sectional view taken along the line XIII-XIII shown in FIG.
  • FIG. 14 is a cross-sectional view showing the gate pad electrode 191.
  • FIG. 15 is a cross-sectional view showing the source pad electrode 192.
  • FIG. 16 is a cross-sectional view illustrating the second main surface electrode 200 graphically. 14 and 15 are cross-sectional views showing a schematic structure of the gate pad electrode 191 and the source pad electrode 192, and do not show a cross section of a specific portion.
  • the SiC semiconductor device 61 includes a SiC chip 62.
  • the SiC chip 62 contains a SiC single crystal composed of hexagonal crystals.
  • the SiC single crystal composed of hexagonal crystals has a plurality of polytypes including 2H (Hexagonal) -SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc., depending on the period of the atomic arrangement. ..
  • the SiC chip 62 is composed of a 4H-SiC single crystal in this form, but does not exclude other polytypes.
  • the SiC chip 62 has a first main surface 63 on one side, a second main surface 64 on the other side, and side surfaces 65A, 65B, 65C, 65D connecting the first main surface 63 and the second main surface 64. ing.
  • the first main surface 63 and the second main surface 64 are formed in a rectangular shape (rectangular shape in this form) in a plan view (hereinafter, simply referred to as “planar view”) viewed from their normal direction Z. ..
  • the thickness of the SiC chip 62 may be 40 ⁇ m or more and 300 ⁇ m or less.
  • the thickness of the SiC chip 62 may be 40 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, 200 ⁇ m or more and 250 ⁇ m or less, or 250 ⁇ m or more and 300 ⁇ m or less.
  • the thickness of the SiC chip 62 is preferably 60 ⁇ m or more and 150 ⁇ m or less.
  • the first main surface 63 and the second main surface 64 face the c-plane of the SiC single crystal in this form.
  • the first main surface 63 faces the silicon surface ((0001) surface) of the SiC single crystal.
  • the first main surface 63 is a non-mounting surface.
  • the second main surface 64 faces the carbon surface ((000-1) surface) of the SiC single crystal.
  • the second main surface 64 is a mounting surface.
  • the second main surface 64 may be a rough surface having either or both of grinding marks and annealing marks.
  • the annealing marks are laser irradiation marks.
  • the second main surface 64 may be an ohmic surface having annealing marks.
  • the first main surface 63 and the second main surface 64 have an off angle inclined at an angle of 0 ° or more and 10 ° or less in the a-axis direction ([11-20] direction) with respect to the c-plane of the SiC single crystal. ing.
  • the normal direction Z is inclined by an off angle with respect to the c-axis ([0001] direction) of the SiC single crystal.
  • the off angle may be 0 ° or more and 6 ° or less.
  • the off angle may be 0 ° or more and 2 ° or less, 2 ° or more and 4 ° or less, or 4 ° or more and 6 ° or less.
  • the off angle is preferably more than 0 ° and 4.5 ° or less.
  • the off angle may be 3 ° or more and 4.5 ° or less. In this case, the off angle is preferably 3 ° or more and 3.5 ° or less, or 3.5 ° or more and 4 ° or less.
  • the off angle may be 1.5 ° or more and 3 ° or less. In this case, the off angle is preferably 1.5 ° or more and 2 ° or less, or 2 ° or more and 2.5 ° or less.
  • the side surfaces 65A to 65D include the first side surface 65A, the second side surface 65B, the third side surface 65C, and the fourth side surface 65D.
  • the first side surface 65A and the second side surface 65B extend along the first direction X and face the second direction Y intersecting the first direction X.
  • the first side surface 65A and the second side surface 65B form the short side of the SiC chip 62 in a plan view.
  • the third side surface 65C and the fourth side surface 65D extend along the second direction Y and face the first direction X.
  • the third side surface 65C and the fourth side surface 65D form the long side of the SiC chip 62 in a plan view. More specifically, the second direction Y is orthogonal to the first direction X.
  • the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal.
  • the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. That is, the first side surface 65A and the second side surface 65B are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction of the SiC single crystal. Further, the third side surface 65C and the fourth side surface 65D are formed by the m-plane of the SiC single crystal and face each other in the m-axis direction of the SiC single crystal.
  • the first side surface 65A and the second side surface 65B form an inclined surface inclined toward the c-axis direction ([0001] direction) of the SiC single crystal with respect to the normal direction Z with respect to the normal direction Z. You may be doing it.
  • the first side surface 65A and the second side surface 65B may be inclined at an angle corresponding to the off angle with respect to the normal direction Z when the normal direction Z is 0 °.
  • the angle according to the off angle may be equal to the off angle, or may be an angle exceeding 0 ° and less than the off angle.
  • the third side surface 65C and the fourth side surface 65D extend in a plane along the normal direction Z. More specifically, the third side surface 65C and the fourth side surface 65D are formed substantially perpendicular to the first main surface 63 and the second main surface 64.
  • the SiC chip 62 has a laminated structure including an n + type SiC semiconductor substrate 66 and an n-type SiC epitaxial layer 67.
  • the SiC semiconductor substrate 66 is formed as a drain region 68.
  • the SiC epitaxial layer 67 is formed as a drift region 69.
  • the second main surface 64 of the SiC chip 62 is formed by the SiC semiconductor substrate 66.
  • the SiC epitaxial layer 67 forms the first main surface 63 of the SiC chip 62.
  • the side surfaces 65A to 65D of the SiC chip 62 are formed by the SiC semiconductor substrate 66 and the SiC epitaxial layer 67.
  • the thickness of the SiC semiconductor substrate 66 may be 40 ⁇ m or more and 250 ⁇ m or less.
  • the thickness of the SiC semiconductor substrate 66 may be 40 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, or 200 ⁇ m or more and 250 ⁇ m or less.
  • the thickness of the SiC semiconductor substrate 66 is preferably 40 ⁇ m or more and 150 ⁇ m or less.
  • the thickness of the SiC epitaxial layer 67 may be 1 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the SiC epitaxial layer 67 may be 1 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 15 ⁇ m or less, 15 ⁇ m or more and 20 ⁇ m or less, 20 ⁇ m or more and 30 ⁇ m or less, 30 ⁇ m or more and 40 ⁇ m or less, or 40 ⁇ m or more and 50 ⁇ m or less. ..
  • the thickness of the SiC epitaxial layer 67 is preferably 5 ⁇ m or more and 15 ⁇ m or less.
  • the concentration of n-type impurities in the SiC epitaxial layer 67 is less than the concentration of n-type impurities in the SiC semiconductor substrate 66.
  • the concentration of n-type impurities in the SiC semiconductor substrate 66 may be 1.0 ⁇ 10 18 cm -3 or more and 1.0 ⁇ 10 21 cm -3 or less.
  • the concentration of n-type impurities in the SiC epitaxial layer 67 may be 1.0 ⁇ 10 15 cm -3 or more and 1.0 ⁇ 10 18 cm -3 or less.
  • the SiC epitaxial layer 67 has a plurality of regions having different n-type impurity concentrations along the normal direction Z. More specifically, the SiC epitaxial layer 67 includes a high concentration region 70 having a relatively high n-type impurity concentration and a low concentration region 71 having a low n-type impurity concentration with respect to the high concentration region 70.
  • the high concentration region 70 is formed in the region on the first main surface 63 side.
  • the low concentration region 71 is formed in a region on the second main surface 64 side with respect to the high concentration region 70.
  • the thickness of the high concentration region 70 is less than the thickness of the low concentration region 71.
  • the thickness of the high concentration region 70 is less than half the total thickness of the SiC epitaxial layer 67.
  • the peak value of the n-type impurity concentration in the high concentration region 70 may be 1.0 ⁇ 10 16 cm -3 or more and 1.0 ⁇ 10 18 cm -3 or less.
  • the peak value of the n-type impurity concentration in the low concentration region 71 may be 1.0 ⁇ 10 15 cm -3 or more and 1.0 ⁇ 10 16 cm -3 or less.
  • the SiC chip 62 includes an active region 72 and an outer region 73.
  • the active region 72 is a region in which a MISFET (Metal Insulator Semiconductor Field Effect Transistor) as an example of a functional device (transistor) is formed.
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • the active region 72 is formed in the central portion of the SiC chip 62 with a space inward from the side surfaces 65A to 65D in a plan view.
  • the active region 72 is formed in a rectangular shape (rectangular shape in this form) having four sides parallel to the side surfaces 65A to 65D in a plan view.
  • the outer region 73 is an region outside the active region 72.
  • the outer region 73 is formed in the region between the side surfaces 65A to 65D and the periphery of the active region 72.
  • the outer region 73 is formed in an annular shape (more specifically, an endless shape) surrounding the active region 72 in a plan view.
  • the SiC semiconductor device 61 includes a p-shaped body region 74 formed on the surface layer portion of the first main surface 63 in the active region 72.
  • the body region 74 defines the active region 72.
  • the peak value of the p-type impurity concentration in the body region 74 may be 1.0 ⁇ 10 17 cm -3 or more and 1.0 ⁇ 10 19 cm -3 or less.
  • the peak value of the p-type impurity concentration in the body region 74 is preferably 1.0 ⁇ 10 18 cm -3 or more.
  • the SiC semiconductor device 61 includes a plurality of trench gate structures 75 formed on the first main surface 63 in the active region 72.
  • the plurality of trench gate structures 75 are each formed in a band shape extending along the first direction X, and are formed at intervals along the second direction Y.
  • the plurality of trench gate structures 75 are formed in a striped shape as a whole in a plan view.
  • the plurality of trench gate structures 75 extend in a band shape from the peripheral edge portion on one side (third side surface 65C side) to the peripheral edge portion on the other side (fourth side surface 65D side) in the active region 72.
  • the plurality of trench gate structures 75 cross an intermediate portion between one peripheral edge and the other peripheral edge in the active region 72.
  • the length of each trench gate structure 75 may be 1 mm or more and 10 mm or less.
  • the length of each trench gate structure 75 may be 1 mm or more and 2 mm or less, 2 mm or more and 4 mm or less, 4 mm or more and 6 mm or less, 6 mm or more and 8 mm or less, or 8 mm or more and 10 mm or less.
  • the length of each trench gate structure 75 is preferably 2 mm or more and 6 mm or less.
  • the total length of one trench gate structure 75 per unit area may be 0.5 ⁇ m / ⁇ m 2 or more and 0.75 ⁇ m / ⁇ m 2 or less.
  • Each trench gate structure 75 includes an active portion 76 and a contact portion 77.
  • the active portion 76 is a portion along the channel of the MISFET.
  • the contact portion 77 is a portion outside the channel of the MISFET.
  • the contact portion 77 is an end portion of the trench gate structure 75, and its main purpose is external connection.
  • Each trench gate structure 75 includes a gate trench 78, a gate insulating layer 79, and a gate electrode 80.
  • the gate insulating layer 79 and the gate electrode 80 are shown by hatching.
  • the gate trench 78 is formed in the SiC epitaxial layer 67 so as to penetrate the body region 74.
  • the gate trench 78 includes a side wall and a bottom wall.
  • the side wall forming the long side of the gate trench 78 is formed by the a-plane of the SiC single crystal.
  • the side wall forming the short side of the gate trench 78 is formed by the m-plane of the SiC single crystal.
  • the side wall of the gate trench 78 may extend along the normal direction Z.
  • the angle formed by the side wall of the gate trench 78 with respect to the first main surface 63 in the SiC chip 62 may be 90 ° or more and 95 ° or less (for example, 91 ° or more and 93 ° or less).
  • the side wall of the gate trench 78 may be formed substantially perpendicular to the first main surface 63.
  • the gate trench 78 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in cross-sectional view.
  • the bottom wall of the gate trench 78 is located in the high concentration region 70.
  • the bottom wall of the gate trench 78 faces the c-plane of the SiC single crystal.
  • the bottom wall of the gate trench 78 has an off angle inclined in the [11-20] direction with respect to the (0001) plane of the SiC single crystal.
  • the bottom wall of the gate trench 78 may be formed parallel to the first main surface 63.
  • the bottom wall of the gate trench 78 may be formed in a curved shape toward the second main surface 64.
  • the depth of the gate trench 78 may be 0.5 ⁇ m or more and 3.0 ⁇ m or less.
  • the depth of the gate trench 78 is 0.5 ⁇ m or more and 1.0 ⁇ m or less, 1.0 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2.0 ⁇ m or less, 2.0 ⁇ m or more and 2.5 ⁇ m or less, or 2.5 ⁇ m or more. It may be 3.0 ⁇ m or less.
  • the width of the gate trench 78 along the second direction Y may be 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the width of the gate trench 78 may be 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1.0 ⁇ m or less, 1.0 ⁇ m or more and 1.5 ⁇ m or less, or 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the opening edge portion of the gate trench 78 includes an inclined portion that is inclined downward from the first main surface 63 toward the inside of the gate trench 78.
  • the opening edge portion of the gate trench 78 is a portion connecting the first main surface 63 and the side wall of the gate trench 78.
  • the inclined portion of the gate trench 78 is formed in a curved shape toward the inside of the SiC chip 62.
  • the inclined portion of the gate trench 78 may be formed in a curved shape toward the inside of the gate trench 78.
  • the inclined portion of the gate trench 78 relaxes the electric field concentration on the opening edge portion of the gate trench 78.
  • the gate insulating layer 79 contains at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide and tantalum oxide.
  • the gate insulating layer 79 may have a laminated structure including a silicon nitride layer and a silicon oxide layer.
  • the gate insulating layer 79 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. In this form, the gate insulating layer 79 has a single-layer structure composed of a silicon oxide layer.
  • the gate insulating layer 79 is formed in a film shape along the inner wall of the gate trench 78, and partitions the recess space in the gate trench 78.
  • the gate insulating layer 79 includes a first region 81, a second region 82, and a third region 83.
  • the first region 81 is formed along the side wall of the gate trench 78.
  • the second region 82 is formed along the bottom wall of the gate trench 78.
  • the third region 83 is formed along the first main surface 63.
  • the thickness of the first region 81 is less than the thickness of the second region 82 and the thickness of the third region 83.
  • the thickness of the first region 81 may be 0.01 ⁇ m or more and 0.2 ⁇ m or less.
  • the thickness of the second region 82 may be 0.05 ⁇ m or more and 0.5 ⁇ m or less.
  • the thickness of the third region 83 may be 0.05 ⁇ m or more and 0.5 ⁇ m or less.
  • the gate insulating layer 79 includes a bulging portion 84 that bulges toward the inside of the gate trench 78 at the opening edge portion.
  • the bulging portion 84 is formed at a corner portion connecting the first region 81 and the third region 83 of the gate insulating layer 79.
  • the bulging portion 84 is formed in a curved shape toward the inside of the gate trench 78.
  • the bulging portion 84 narrows the opening of the gate trench 78 at the opening edge portion.
  • a gate insulating layer 79 having no bulging portion 84 may be formed.
  • a gate insulating layer 79 having a uniform thickness may be formed.
  • the gate electrode 80 is embedded in the gate trench 78 with the gate insulating layer 79 interposed therebetween. More specifically, the gate electrode 80 is embedded in the recess space partitioned by the gate insulating layer 79 in the gate trench 78.
  • the gate electrode 80 has an upper end portion located on the opening side of the gate trench 78.
  • the upper end of the gate electrode 80 is formed in a curved shape recessed toward the bottom wall of the gate trench 78.
  • the upper end portion of the gate electrode 80 has a constricted portion confined along the bulging portion 84 of the gate insulating layer 79.
  • the gate electrode 80 contains p-type polysilicon to which p-type impurities have been added.
  • the p-type impurity of the gate electrode 80 may contain at least one of boron, aluminum, indium and gallium.
  • the p-type impurity concentration of the gate electrode 80 exceeds the p-type impurity concentration of the body region 74.
  • the p-type impurity concentration of the gate electrode 80 may be 1.0 ⁇ 10 18 cm -3 or more and 1.0 ⁇ 10 22 cm -3 or less.
  • the sheet resistance of the gate electrode 80 may be 10 ⁇ / ⁇ or more and 500 ⁇ / ⁇ or less (about 200 ⁇ / ⁇ in this form).
  • the thickness of the gate electrode 80 may be 0.5 ⁇ m or more and 3 ⁇ m or less.
  • the SiC semiconductor device 61 includes a gate wiring 85 formed on the first main surface 63 in the active region 72.
  • the gate wiring 85 is shown by hatching. More specifically, the gate wiring 85 is formed on the third region 83 of the gate insulating layer 79.
  • the gate wiring 85 is formed in the active region 72 along the first side surface 65A, the third side surface 65C, and the fourth side surface 65D, and divides the region in which the plurality of trench gate structures 75 are formed from three directions.
  • the gate wiring 85 is connected to the gate electrode 80 exposed from the contact portion 77 of the trench gate structure 75.
  • the gate wiring 85 is formed by a lead-out portion of the gate electrode 80 drawn out from the gate trench 78 onto the first main surface 63.
  • the upper end of the gate wiring 85 is connected to the upper end of the gate electrode 80.
  • the low resistance layer 86 contains a conductive material having a sheet resistance less than the sheet resistance of the gate electrode 80.
  • the sheet resistance of the low resistance layer 86 may be 0.01 ⁇ / ⁇ or more and 10 ⁇ / ⁇ or less.
  • the low resistance layer 86 includes a polyside layer.
  • the polyside layer is formed by silicidizing a portion forming the surface layer portion of the gate electrode 80 with a metal material. More specifically, the polyside layer is composed of a p-type polyside layer containing p-type impurities added to the gate electrode 80 (p-type polysilicon).
  • the polyside layer preferably has a specific resistance of 10 ⁇ ⁇ cm or more and 110 ⁇ ⁇ cm or less.
  • the sheet resistance in the gate trench 78 in which the gate electrode 80 and the low resistance layer 86 are embedded is less than or equal to the sheet resistance of the gate electrode 80 alone.
  • the sheet resistance in the gate trench 78 is preferably equal to or less than the sheet resistance of n-type polysilicon to which n-type impurities are added.
  • the sheet resistance in the gate trench 78 is approximated to the sheet resistance of the low resistance layer 86. That is, the sheet resistance in the gate trench 78 may be 0.01 ⁇ / ⁇ or more and 10 ⁇ / ⁇ or less. The sheet resistance in the gate trench 78 is preferably less than 10 ⁇ / ⁇ .
  • the low resistance layer 86 includes a contact portion in contact with the gate insulating layer 79. More specifically, the contact portion of the low resistance layer 86 is in contact with the third region 83 (bulging portion 84) of the gate insulating layer 79.
  • the contact portion of the low resistance layer 86 is formed in a region on the first main surface 63 side with respect to the bottom portion of the body region 74. More specifically, the contact portion of the low resistance layer 86 is formed in a region on the first main surface 63 side with respect to the bottom portion of the source region 97, which will be described later.
  • the low resistance layer 86 does not face the body region 74 with the gate insulating layer 79 interposed therebetween.
  • the thickness of the low resistance layer 86 is preferably less than the thickness of the gate electrode 80.
  • the thickness of the low resistance layer 86 may be 0.01 ⁇ m or more and 3 ⁇ m or less.
  • the low resistance layer 86 also covers the upper end of the gate wiring 85.
  • the portion of the low resistance layer 86 that covers the upper end of the gate wiring 85 is integrally formed with the portion of the low resistance layer 86 that covers the upper end of the gate electrode 80. As a result, the low resistance layer 86 covers the entire area of the gate electrode 80 and the entire area of the gate wiring 85.
  • the gate threshold voltage Vth can be increased by about 1 V.
  • the p-type polysilicon has a sheet resistance that is several tens of times (approximately 20 times) higher than the sheet resistance of the n-type polysilicon. Therefore, when p-type polysilicon is used as the material for the gate electrode 80, the energy loss increases as the parasitic resistance in the gate trench 78 (hereinafter, simply referred to as “gate resistance”) increases.
  • a low resistance layer 86 (p-type polysilicon) is formed on the gate electrode 80 (p-type polysilicon). According to the low resistance layer 86, the sheet resistance in the gate trench 78 can be reduced while allowing an increase in the gate threshold voltage Vth (for example, an increase of about 1 V).
  • the sheet resistance can be reduced to 1/100 or less as compared with the case where the low resistance layer 86 is not provided. Further, according to the structure having the low resistance layer 86, the sheet resistance can be reduced to one-fifth or less as compared with the gate electrode 80 containing n-type polysilicon.
  • the gate resistance can be reduced, so that the current can be efficiently diffused along the trench gate structure 75. That is, the low resistance layer 86 is formed as a current diffusion layer that diffuses a current in the gate trench 78.
  • the gate trench 78 having a length on the order of millimeters (length of 1 mm or more), it takes time to transmit the current, but the low resistance layer 86 can appropriately suppress the switching delay.
  • the gate threshold voltage Vth can be appropriately increased while suppressing the increase in the channel resistance.
  • the SiC semiconductor device 61 includes a plurality of trench source structures 91 each formed in a region between a plurality of trench gate structures 75 adjacent to each other.
  • the plurality of trench source structures 91 are formed so as to sandwich one trench gate structure 75 at intervals in the second direction Y (a-axis direction of the SiC single crystal).
  • the plurality of trench source structures 91 are each formed in a band shape extending along the first direction X (m-axis direction of the SiC single crystal).
  • the plurality of trench source structures 91 are formed in a striped shape as a whole in a plan view.
  • the pitch between the central portions of the trench source structures 91 adjacent to each other may be 1.5 ⁇ m or more and 3 ⁇ m or less.
  • Each trench source structure 91 includes a source trench 92, a source insulating layer 93, and a source electrode 94.
  • the source insulating layer 93 and the source electrode 94 are shown by hatching.
  • the source trench 92 is formed in the SiC epitaxial layer 67 so as to penetrate the body region 74.
  • the source trench 92 includes a side wall and a bottom wall.
  • the side wall forming the long side of the source trench 92 is formed by the a-plane of the SiC single crystal.
  • the side wall forming the short side of the source trench 92 is formed by the m-plane of the SiC single crystal.
  • the side wall of the source trench 92 may extend along the normal direction Z.
  • the angle formed by the side wall of the source trench 92 with respect to the first main surface 63 in the SiC chip 62 may be 90 ° or more and 95 ° or less (for example, 91 ° or more and 93 ° or less).
  • the side wall of the source trench 92 may be formed substantially perpendicular to the first main surface 63.
  • the source trench 92 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in cross-sectional view.
  • the bottom wall of the source trench 92 is located in the high concentration region 70.
  • the bottom wall of the source trench 92 is located in a region on the second main surface 64 side with respect to the bottom wall of the gate trench 78.
  • the bottom wall of the source trench 92 is located in the region between the bottom wall of the gate trench 78 and the low concentration region 71 with respect to the normal direction Z.
  • the bottom wall of the source trench 92 faces the c-plane of the SiC single crystal.
  • the bottom wall of the source trench 92 has an off angle inclined in the [11-20] direction with respect to the (0001) plane of the SiC single crystal.
  • the bottom wall of the source trench 92 may be formed parallel to the first main surface 63.
  • the bottom wall of the source trench 92 may be formed in a curved shape toward the second main surface 64.
  • the depth of the source trench 92 exceeds the depth of the gate trench 78.
  • the ratio of the depth of the source trench 92 to the depth of the gate trench 78 may be 1.5 or more, provided that the source trench 92 is located within the high concentration region 70.
  • the ratio of the depth of the source trench 92 to the depth of the gate trench 78 is preferably 2 or more.
  • the depth of the source trench 92 may be equal to the depth of the gate trench 78.
  • the depth of the source trench 92 may be 0.5 ⁇ m or more and 10 ⁇ m or less (for example, about 2 ⁇ m).
  • the width of the source trench 92 along the second direction Y may exceed the width of the gate trench 78 along the second direction Y, or may be less than the width of the gate trench 78 along the second direction Y.
  • the width of the source trench 92 along the second direction Y is preferably equal to the width of the gate trench 78 along the second direction Y.
  • the width of the source trench 92 along the second direction Y may be 0.1 ⁇ m or more and 2 ⁇ m or less (for example, about 0.5 ⁇ m).
  • the source insulating layer 93 contains at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide and tantalum oxide.
  • the source insulating layer 93 may have a laminated structure including a silicon nitride layer and a silicon oxide layer.
  • the source insulating layer 93 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. In this form, the source insulating layer 93 has a single-layer structure composed of a silicon oxide layer.
  • the source insulating layer 93 is formed in a film shape along the inner wall of the source trench 92, and partitions the recess space in the source trench 92.
  • the source insulating layer 93 includes a first region 95 and a second region 96.
  • the first region 95 is formed along the side wall of the source trench 92.
  • the second region 96 is formed along the bottom wall of the source trench 92.
  • the thickness of the first region 95 is smaller than the thickness of the second region 96.
  • the thickness of the first region 95 may be 0.01 ⁇ m or more and 0.2 ⁇ m or less.
  • the thickness of the second region 96 may be 0.05 ⁇ m or more and 0.5 ⁇ m or less.
  • the thickness of the first region 95 may be substantially equal to the thickness of the first region 95 of the gate insulating layer 79.
  • the thickness of the second region 96 may be substantially equal to the thickness of the second region 96 of the gate insulating layer 79.
  • a source insulating layer 93 having a uniform thickness may be formed.
  • the source electrode 94 is embedded in the source trench 92 with the source insulating layer 93 interposed therebetween. More specifically, the source electrode 94 is embedded in the recess space partitioned by the source insulating layer 93 in the source trench 92.
  • the source electrode 94 has an upper end portion located on the opening side of the source trench 92.
  • the upper end portion of the source electrode 94 is formed on the bottom wall side of the source trench 92 with respect to the first main surface 63.
  • the upper end of the source electrode 94 may be located above the first main surface 63.
  • the upper end of the source electrode 94 is formed in a curved shape recessed toward the bottom wall of the source trench 92.
  • the upper end portion of the source electrode 94 may be formed parallel to the first main surface 63.
  • the thickness of the source electrode 94 may be 0.5 ⁇ m or more and 10 ⁇ m or less (for example, about 1 ⁇ m).
  • the source electrode 94 preferably contains polysilicon, which has properties similar to SiC in terms of material. As a result, the stress generated in the SiC chip 62 can be reduced.
  • the source electrode 94 contains p-type polysilicon to which p-type impurities have been added. In this case, the source electrode 94 can be formed at the same time as the gate electrode 80.
  • the p-type impurity concentration of the source electrode 94 exceeds the p-type impurity concentration of the body region 74.
  • the p-type impurity concentration of the source electrode 94 may be equal to the p-type impurity concentration of the gate electrode 80.
  • the p-type impurity concentration of the source electrode 94 may be 1.0 ⁇ 10 18 cm -3 or more and 1.0 ⁇ 10 22 cm -3 or less.
  • the p-type impurity of the source electrode 94 may contain at least one of boron, aluminum, indium and gallium.
  • the sheet resistance of the source electrode 94 may be 10 ⁇ / ⁇ or more and 500 ⁇ / ⁇ or less (about 200 ⁇ / ⁇ in this form).
  • the sheet resistance of the source electrode 94 may be equal to the sheet resistance of the gate electrode 80.
  • the source electrode 94 may contain at least one of n-type polysilicon, tungsten, aluminum, copper, aluminum alloy and copper alloy in place of or in addition to p-type polysilicon.
  • the SiC semiconductor device 61 includes an n + type source region 97 formed in a region along the side wall of the gate trench 78 in the surface layer portion of the body region 74.
  • the peak value of the n-type impurity concentration in the source region 97 may be 1.0 ⁇ 10 18 cm -3 or more and 1.0 ⁇ 10 21 cm -3 or less.
  • the peak value of the n-type impurity concentration in the source region 97 is preferably 1.0 ⁇ 10 20 cm -3 or more.
  • a plurality of source regions 97 are formed along the side wall on one side and the side wall on the other side of the gate trench 78.
  • the plurality of source regions 97 are each formed in a band shape extending along the first direction X.
  • the plurality of source regions 97 are formed in a striped shape as a whole in a plan view. Each source region 97 is exposed from the side wall of the gate trench 78 and the side wall of each source trench 92.
  • the portion of the source region 97 along the side wall of the gate trench 78 defines the channel of the MISFET with the high concentration region 70. ON / OFF of the channel is controlled by the gate electrode 80.
  • the SiC semiconductor device 61 includes a p + type contact region 98 formed in a region along each source trench 92 in the surface layer portion of the first main surface 63.
  • the peak value of the p-type impurity concentration in each contact region 98 exceeds the peak value of the p-type impurity concentration in the body region 74.
  • the peak value of the p-type impurity concentration in each contact region 98 may be 1.0 ⁇ 10 18 cm -3 or more and 1.0 ⁇ 10 21 cm -3 or less.
  • a plurality of contact regions 98 are formed for one source trench 92.
  • the plurality of contact regions 98 are formed at intervals along the corresponding source trench 92.
  • the plurality of contact regions 98 are formed at intervals from the gate trench 78.
  • Each contact area 98 covers the side wall and bottom wall of the corresponding source trench 92.
  • the bottom of each contact region 98 may be formed parallel to the bottom wall of the corresponding source trench 92.
  • each contact region 98 that covers the side wall of the source trench 92 is formed in the region on the first main surface 63 side with respect to the bottom of the body region 74.
  • the portion of each contact region 98 that covers the side wall of the source trench 92 is drawn toward the adjacent gate trench 78.
  • the portion of each contact region 98 that covers the side wall of the source trench 92 may extend to an intermediate region between the gate trench 78 and the source trench 92.
  • Each contact region 98 is electrically connected to the body region 74 and the source region 97.
  • the SiC semiconductor device 61 includes a deep well region 99 formed on the surface layer portion of the first main surface 63 in the active region 72.
  • a plurality of deep well regions 99 are formed in a one-to-one correspondence with a plurality of source trenches 92.
  • Each deep well region 99 is formed in a strip shape extending along the corresponding source trench 92 in plan view.
  • Each deep well region 99 is formed in a high concentration region 70. Each deep well region 99 covers each source trench 92 with each contact region 98 interposed therebetween. Each deep well region 99 covers the side wall and bottom wall of the source trench 92 with the corresponding contact region 98 in between. Each deep well region 99 is connected to the body region 74 in the surface layer portion of the first main surface 3.
  • Each deep well region 99 has a bottom portion located on the second main surface 64 side with respect to the bottom wall of the gate trench 78.
  • the bottom of each deep well region 99 may be formed parallel to the bottom wall of each source trench 92.
  • the plurality of deep well regions 99 are preferably formed at a constant depth.
  • the peak value of the p-type impurity concentration in each deep well region 99 may be less than the peak value of the p-type impurity concentration in the contact region 98.
  • the peak value of the p-type impurity concentration in each deep well region 99 may be equal to the peak value of the p-type impurity concentration in the body region 74.
  • the peak value of the p-type impurity concentration in each deep well region 99 may exceed the peak value of the p-type impurity concentration in the body region 74, or may be less than the peak value of the p-type impurity concentration in the body region 74. Good.
  • the peak value of the p-type impurity concentration in each deep well region 99 may be 1.0 ⁇ 10 17 cm -3 or more and 1.0 ⁇ 10 19 cm -3 or less.
  • the peak value of the p-type impurity concentration in each deep well region 99 is preferably 1.0 ⁇ 10 18 cm -3 or more.
  • Each deep well region 99 forms a pn junction with the high concentration region 70. From this pn junction, a depletion layer extends toward the gate trench 78. The depletion layer may overlap the bottom wall of the gate trench 78.
  • the SiC semiconductor device 61 includes a p-type peripheral well region 100 formed on the surface layer portion of the first main surface 63 at the peripheral edge portion of the active region 72.
  • the peripheral well region 100 covers the contact portion 77 of the trench gate structure 75 and exposes the active portion 76.
  • the peripheral well region 100 covers the side wall and bottom wall of the gate trench 78 at the corresponding contact portion 77.
  • the bottom of the peripheral well region 100 is located on the first main surface 63 side with respect to the bottom wall of the deep well region 99.
  • Each peripheral well region 100 is electrically connected to the body region 74 and the deep well region 99 at the surface layer portion of the first main surface 63.
  • the p-type impurity concentration in the peripheral well region 100 may be substantially equal to the p-type impurity concentration in the deep well region 99.
  • the peak value of the p-type impurity concentration in the peripheral well region 100 may be 1.0 ⁇ 10 17 cm -3 or more and 1.0 ⁇ 10 19 cm -3 or less.
  • the peak value of the p-type impurity concentration in the peripheral well region 100 is preferably 1.0 ⁇ 10 18 cm -3 or more.
  • the electric field in the SiC chip 62 can be relaxed. Therefore, narrowing the pitch between the plurality of deep well regions 99 adjacent to each other is effective in alleviating the electric field concentration.
  • the depletion layer can appropriately relax the electric field concentration on the gate trench 78.
  • the plurality of deep well regions 99 are preferably formed at a constant depth. As a result, it is possible to prevent the withstand voltage (for example, fracture resistance) of the SiC chip 62 from being limited by each deep well region 99, so that the withstand voltage can be appropriately improved.
  • the peripheral well region 100 also has the same effect as the deep well region 99.
  • the deep well region 99 can be appropriately formed in a relatively deep region of the SiC chip 62. Further, since the deep well region 99 can be formed along the source trench 92, it is possible to appropriately suppress the occurrence of variation in the depths of the plurality of deep well regions 99.
  • the high concentration region 70 is interposed in the region between the plurality of deep well regions 99 adjacent to each other.
  • the JFET Joint Field Effect Transistor
  • the source sub-trench 101 is formed in a tapered shape whose bottom area is smaller than the opening area in cross-sectional view.
  • the bottom wall of the source sub-trench 101 may be formed in a curved shape toward the second main surface 64.
  • the source sub-trench 101 exposes the source region 97, the contact region 98, the source insulating layer 93, the source electrode 94, and the contact region 98.
  • each source trench 92 includes an inclined portion inclined downward from the first main surface 63 toward the inside of each source trench 92.
  • the opening edge of each source trench 92 is a portion connecting the first main surface 63 and the side wall of each source trench 92.
  • the inclined portion of each source trench 92 is formed by the source sub-trench 101.
  • the active region 72 has an active main surface 111 that forms a part of the first main surface 63.
  • the outer region 73 has an outer main surface 112 that forms part of the first main surface 63.
  • the outer main surface 112 is connected to the side surfaces 65A to 65D.
  • the active main surface 111 and the outer main surface 112 face the c-plane of the SiC single crystal, respectively.
  • the active main surface 111 and the outer main surface 112 each have an off angle inclined in the [11-20] direction with respect to the (0001) plane of the SiC single crystal.
  • the outer region 73 is formed by digging the first main surface 63 toward the second main surface 64. Therefore, the outer main surface 112 is formed in a region recessed on the second main surface 64 side with respect to the active main surface 111. The outer main surface 112 is located on the second main surface 64 side with respect to the bottom wall of the gate trench 78.
  • the outer main surface 112 is formed at a depth position substantially equal to the bottom wall of each source trench 92.
  • the outer main surface 112 is located on substantially the same plane as the bottom wall of each source trench 92.
  • the outer main surface 112 may be located on the second main surface 64 side in a range of 0 ⁇ m or more and 1 ⁇ m or less with respect to the bottom wall of each source trench 92.
  • the outer main surface 112 exposes the high density region 70.
  • the active region 72 is divided into a plateau shape by the outer region 73.
  • the active region 72 is formed as a plateau-like active plateau 113 protruding upward from the outer main surface 112.
  • the active plateau 113 includes an active side wall 114 connecting the active main surface 111 and the outer main surface 112.
  • the active side wall 114 partitions a boundary region between the active region 72 and the outer region 73.
  • the first main surface 63 is formed by an active main surface 111, an outer main surface 112, and an active side wall 114.
  • the active side wall 114 extends along the normal direction Z of the active main surface 111 (outer main surface 112).
  • the active side wall 114 is formed by the m-plane and the a-plane of the SiC single crystal.
  • the active side wall 114 may have an inclined surface that is inclined downward from the active main surface 111 toward the outer main surface 112.
  • the active side wall 114 exposes the high concentration region 70.
  • the active side wall 114 may expose the body region 74.
  • the SiC semiconductor device 61 includes a p + type diode region 121 formed on the surface layer portion of the outer main surface 112.
  • the diode region 121 is formed in the high concentration region 70.
  • the diode region 121 is formed in the outer region 73 in the region between the active side wall 114 and the sides 65A-65D.
  • the diode region 121 is formed at intervals from the active side wall 114 and the side surfaces 65A to 65D.
  • the diode region 121 extends in a strip shape along the active region 72 in a plan view.
  • the diode region 121 is formed in an annular shape (more specifically, an endless shape) surrounding the active region 72 in a plan view.
  • the diode region 121 is located on the second main surface 64 side with respect to the bottom wall of the gate trench 78.
  • the bottom of the diode region 121 is located on the second main surface 64 side with respect to the bottom wall of each source trench 92.
  • the bottom of the diode region 121 may be formed at a depth substantially equal to the bottom of the contact region 98.
  • the bottom of the diode region 121 may be located on substantially the same plane as the bottom of the contact region 98.
  • the bottom portion of the diode region 121 may be located on the second main surface 64 side with respect to the bottom portion of the contact region 98.
  • the bottom portion of the diode region 121 may be located on the second main surface 64 side in a range of 0 ⁇ m or more and 1 ⁇ m or less with respect to the bottom portion of the contact region 98.
  • the diode region 121 forms a pn junction with the high concentration region 70.
  • a pn junction diode having the diode region 121 as the anode and the high concentration region 70 as the cathode is formed.
  • the peak value of the p-type impurity concentration in the diode region 121 may be 1.0 ⁇ 10 17 cm -3 or more and 1.0 ⁇ 10 21 cm -3 or less.
  • the SiC semiconductor device 61 includes a p-shaped outer well region 122 formed on the surface layer portion of the outer main surface 112.
  • the peak value of the p-type impurity concentration in the outer well region 122 may be 1.0 ⁇ 10 17 cm -3 or more and 1.0 ⁇ 10 19 cm -3 or less.
  • the peak value of the p-type impurity concentration in the outer well region 122 may be less than the peak value of the p-type impurity concentration in the diode region 121.
  • the peak value of the p-type impurity concentration in the outer well region 122 may be substantially equal to the peak value of the p-type impurity concentration in the deep well region 99.
  • the outer well region 122 is formed in a region between the active side wall 114 and the diode region 121 in a plan view.
  • the outer well region 122 extends in a strip shape along the active region 72 in a plan view.
  • the outer well region 122 is formed in an annular shape (more specifically, an endless shape) surrounding the active region 72 in a plan view.
  • the outer well region 122 is formed in the high concentration region 70.
  • the outer well region 122 is located on the second main surface 64 side with respect to the bottom wall of the gate trench 78.
  • the bottom of the outer well region 122 is located on the second main surface 64 side with respect to the bottom wall of each source trench 92.
  • the bottom of the outer well region 122 is located on the second main surface 64 side with respect to the bottom of the diode region 121.
  • the bottom of the outer well region 122 may be formed at a depth substantially equal to the bottom of the deep well region 99.
  • the inner peripheral edge of the outer well region 122 covers the corners connecting the active side wall 114 and the outer main surface 112.
  • the inner peripheral edge of the outer well region 122 further extends along the active side wall 114 and is connected to the body region 74.
  • the inner peripheral edge of the outer well region 122 may be formed at a distance from the active side wall 114 toward the diode region 121 side.
  • the SiC semiconductor device 61 includes an FL structure 123 (field limit structure) formed on the surface layer portion of the outer main surface 112.
  • the FL structure 123 is formed in a region between the diode region 121 and the side surfaces 65A to 65D in a plan view. In this form, the FL structure 123 is formed at intervals from the side surfaces 65A to 65D toward the diode region 121 side.
  • the FL structure 123 is formed in the high concentration region 70.
  • the FL structure 123 includes one or more (for example, 2 or more and 20 or less) FL regions 124 (field limit regions).
  • the FL structure 123 includes, in this form, a group of FL regions having five FL regions 124A, 124B, 124C, 124D, 124E.
  • the FL regions 124A to 124E are formed in this order at intervals along the direction away from the diode region 121.
  • the FL regions 124A to 124E extend in a strip shape along the peripheral edge of the active region 72 in a plan view. More specifically, the FL regions 124A to 124E are formed in an annular shape (more specifically, an endless shape) surrounding the active region 72 in a plan view.
  • the FL regions 124A to 124E are also referred to as FLR regions (field limiting ring regions), respectively.
  • the bottom of the FL regions 124A to 124E is located on the second main surface 64 side with respect to the bottom of the diode region 121.
  • the innermost FL region 124A of the FL regions 124A to 124E covers the diode region 121 from the second main surface 64 side.
  • the FL region 124A is electrically connected to the diode region 121.
  • the FL region 124A may form a part of the pn junction diode.
  • the entire FL region 124A to 124E is located on the second main surface 64 side with respect to the bottom wall of the gate trench 78.
  • the bottom of the FL regions 124A to 124E is located on the second main surface 64 side with respect to the bottom wall of the source trench 92.
  • the FL structure 123 relaxes the electric field concentration in the outer region 73.
  • the number, width, depth, p-type impurity concentration, etc. of the FL region 124 can take various values depending on the electric field to be relaxed.
  • the FL structure 123 may include one or more FL regions 124 formed in the region between the active side wall 114 and the diode region 121 in plan view.
  • the SiC semiconductor device 61 includes an outer insulating layer 131 that covers the outer main surface 112.
  • the outer insulating layer 131 is formed in a film shape along the active side wall 114 and the outer main surface 112.
  • the outer insulating layer 131 is connected to the gate insulating layer 79 (third region 83) on the active main surface 111.
  • the outer insulating layer 131 covers the diode region 121, the outer well region 122, and the FL structure 123 in the outer region 73.
  • the outer insulating layer 131 may contain silicon oxide.
  • the outer insulating layer 131 may include another insulating film such as silicon nitride. In this form, the outer insulating layer 131 is formed of the same insulating material type as the gate insulating layer 79.
  • the peripheral edge of the outer insulating layer 131 is exposed from the side surfaces 65A to 65D.
  • the peripheral edge of the outer insulating layer 131 is continuous with the side surfaces 65A to 65D in this form.
  • the peripheral edge of the outer insulating layer 131 may be formed at intervals inward from the side surfaces 65A to 65D. In this case, the outer insulating layer 131 exposes the outer main surface 112.
  • the SiC semiconductor device 61 further includes a sidewall structure 132 that covers the active side wall 114.
  • the sidewall structure 132 protects and reinforces the active plateau 113 from the outer region 73 side. Further, the sidewall structure 132 forms a step relaxation structure that relaxes the step formed between the active main surface 111 and the outer main surface 112.
  • the upper layer structure covers the sidewall structure 132.
  • the sidewall structure 132 enhances the flatness of the upper layer structure.
  • the sidewall structure 132 may have an inclined surface that is inclined downward from the active main surface 111 toward the outer main surface 112. The inclined surface of the sidewall structure 132 can appropriately reduce the step.
  • the inclined surface of the sidewall structure 132 may be formed in a curved shape recessed toward the SiC chip 62 side.
  • the inclined surface of the sidewall structure 132 may be formed in a curved shape toward the side opposite to the SiC chip 62.
  • the inclined surface of the sidewall structure 132 may extend in a plane from the active main surface 111 side toward the outer main surface 112 side.
  • the sidewall structure 132 is formed along the active side wall 114.
  • the sidewall structure 132 is formed in an annular shape (more specifically, an endless shape) surrounding the active region 72 in a plan view.
  • the sidewall structure 132 preferably contains polysilicon.
  • the sidewall structure 132 can be formed at the same time as the gate electrode 80 and the source electrode 94.
  • the SiC semiconductor device 61 includes an interlayer insulating layer 140 formed on the first main surface 63.
  • the interlayer insulating layer 140 covers the active region 72 and the outer region 73.
  • the interlayer insulating layer 140 is formed in a film shape along the active main surface 111 and the outer main surface 112.
  • the interlayer insulating layer 140 is formed along the sidewall structure 132 in the boundary region between the active region 72 and the outer region 73.
  • the interlayer insulating layer 140 forms a part of the upper layer structure that covers the sidewall structure 132.
  • the peripheral edge of the interlayer insulating layer 140 is exposed from the side surfaces 65A to 65D.
  • the peripheral edge of the interlayer insulating layer 140 is continuous with the side surfaces 65A to 65D.
  • the peripheral edge of the interlayer insulating layer 140 may be formed at intervals inward from the side surfaces 65A to 65D. In this case, the interlayer insulating layer 140 exposes the outer main surface 112 (outer insulating layer 131).
  • the interlayer insulating layer 140 may contain silicon oxide or silicon nitride.
  • the interlayer insulating layer 140 may contain USG (Undoped Silicate Glass), PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide.
  • the interlayer insulating layer 140 includes a gate contact hole 141, a source contact hole 142, and a diode contact hole 143.
  • the gate contact hole 141 exposes the gate wiring 85 in the active region 72.
  • the gate contact hole 141 may be formed in a band shape along the gate wiring 85.
  • the opening edge portion of the gate contact hole 141 is formed in a curved shape toward the inside of the gate contact hole 141.
  • the source contact hole 142 exposes the source region 97, the contact region 98, and the trench source structure 91 in the active region 72.
  • the source contact hole 142 may be formed in a strip shape extending along the trench source structure 91.
  • the opening edge of the source contact hole 142 is formed in a curved shape toward the inside of the source contact hole 142.
  • the diode contact hole 143 exposes the diode region 121 in the outer region 73.
  • the diode contact hole 143 may be formed in a band shape (more specifically, an endless shape) extending along the diode region 121.
  • the diode contact hole 143 may expose the outer well region 122 and / or the FL structure 123.
  • the opening edge of the diode contact hole 143 is formed in a curved shape toward the inside of the diode contact hole 143.
  • the SiC semiconductor device 61 includes a first main surface electrode 150 formed on the first main surface 63. More specifically, the first main surface electrode 150 is formed on the interlayer insulating layer 140.
  • the first main surface electrode 150 includes a gate main surface electrode 151 and a source main surface electrode 152 that are electrically insulated from each other.
  • a gate voltage is applied to the gate main surface electrode 151.
  • the gate voltage may be 10 V or more and 50 V or less (for example, about 30 V).
  • a source voltage is applied to the source main surface electrode 152.
  • the source voltage may be a reference voltage (eg, GND voltage).
  • the gate main surface electrode 151 is formed in the active region 72.
  • the gate main surface electrode 151 includes a gate pad 153 and a gate finger 154.
  • the gate pad 153 is formed in a region on the first side surface 65A side in a plan view. More specifically, the gate pad 153 is formed along a region along the central portion of the first side surface 65A in a plan view.
  • the gate pad 153 may be formed in a region along a corner portion connecting any two of the side surfaces 65A to 65D in a plan view.
  • the gate pad 153 may be formed in a rectangular shape in a plan view.
  • the gate finger 154 is pulled out from the gate pad 153 and extends in a band shape along the peripheral edge of the active region 72.
  • the gate finger 154 is formed along the first side surface 65A, the third side surface 65C, and the fourth side surface 65D so as to partition the inside of the active region 72 from three directions.
  • the gate finger 154 has a pair of open ends 155 and 156.
  • the pair of open ends 155 and 156 are formed in a region facing the gate pad 153 with the inner side of the active region 72 interposed therebetween.
  • the pair of open ends 155 and 156 are formed in a region along the second side surface 65B in a plan view.
  • the gate finger 154 has entered the gate contact hole 141 from above the interlayer insulating layer 140.
  • the gate finger 154 is electrically connected to the gate wiring 85 in the gate contact hole 141.
  • the electric signal from the gate pad 153 is transmitted to the gate electrode 80 and the gate wiring 85 via the gate finger 154.
  • the source main surface electrode 152 is formed in the active region 72 and the outer region 73.
  • the source main surface electrode 152 includes a source pad 157, a source wiring 158, and a source connection portion 159.
  • the source pad 157 is formed in the active region 72 at a distance from the gate main surface electrode 151.
  • the source pad 157 is formed in a C-shape in a plan view so as to cover a C-shaped region defined by the gate main surface electrode 151.
  • the source pad 157 enters the source contact hole 142 and the source sub-trench 101 from above the interlayer insulating layer 140.
  • the source pad 157 is electrically connected to the source region 97, the contact region 98, and the source electrode 94 in the source contact hole 142 and the source subtrench 101.
  • the source electrode 94 described above may be formed by utilizing a part of the region of the source pad 157.
  • the source electrode 94 may be formed by a portion of the source pad 157 that has entered each source trench 92.
  • the source wiring 158 is formed in the outer region 73.
  • the source wiring 158 extends in a strip shape along the active region 72.
  • the source wiring 158 is formed in an annular shape (more specifically, an endless shape) surrounding the active region 72 in a plan view.
  • the source wiring 158 enters the diode contact hole 143 from above the interlayer insulating layer 140.
  • the source wiring 158 is electrically connected to the diode region 121 in the diode contact hole 143.
  • the source connection unit 159 connects the source pad 157 and the source wiring 158.
  • the source connection portion 159 crosses the open ends 155 and 156 of the gate fingers 154 from the source pad 157 and is connected to the source wiring 158.
  • the source connection portion 159 is drawn from the active region 72 across the sidewall structure 132 to the outer region 73.
  • the source connection portion 159 forms a part of the upper layer structure that covers the sidewall structure 132.
  • the MISFET formed in the active region 72 includes an npn type parasitic transistor due to its structure.
  • the parasitic transistor is turned on. In this case, the operation of the MISFET becomes unstable due to the latch-up. Therefore, in the SiC semiconductor device 61, an avalanche current absorption structure is formed by utilizing the structure of the source main surface electrode 152.
  • the avalanche current generated in the outer region 73 is absorbed by the source wiring 158 via the diode region 121.
  • the avalanche current absorbed by the source wiring 158 reaches the source pad 157 via the source connection 159.
  • the lead wire is electrically connected to the source pad 157, the avalanche current reaches the outside through the lead wire.
  • the first main surface electrode 150 (gate main surface electrode 151 and source main surface electrode 152) has a barrier layer 160 and a first Al layer 161 laminated in this order from the SiC chip 62 side. It has a laminated structure including.
  • the first Al layer 161 is formed as a first buffer layer that relaxes an external force applied to the SiC chip 62 from the first main surface 63 side by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity). There is.
  • the barrier layer 160 may have a single-layer structure including a Ti layer or a TiN layer.
  • the barrier layer 160 may have a laminated structure including a Ti layer and a TiN layer laminated in this order from the SiC chip 62 side.
  • the thickness of the barrier layer 160 may be 0.01 ⁇ m or more and 6 ⁇ m or less.
  • the thickness of the barrier layer 160 may be 0.01 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, or 4 ⁇ m or more and 6 ⁇ m or less.
  • the first Al layer 161 has a resistance value smaller than the resistance value of the barrier layer 160.
  • the first Al layer 161 includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.
  • the first Al layer 161 may have a laminated structure in which two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer and an AlSiCu alloy layer are laminated in any order.
  • the first Al layer 161 may have a single layer structure composed of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.
  • the first Al layer 161 preferably has a single-layer structure composed of an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.
  • the thickness of the first Al layer 161 exceeds the thickness of the barrier layer 160.
  • the thickness of the first Al layer 161 may be 0.05 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the first Al layer 161 is 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, or 8 ⁇ m or more and 10 ⁇ m. It may be as follows.
  • the thickness of the first Al layer 161 is preferably 1 ⁇ m or more and 8 ⁇ m or less.
  • the SiC semiconductor device 61 includes an insulating layer 170 formed on the interlayer insulating layer 140.
  • the insulating layer 170 is shown by hatching.
  • the peripheral edge of the insulating layer 170 is formed at intervals inward from the side surfaces 65A to 65D.
  • the insulating layer 170 exposes the peripheral edge of the SiC chip 62 (more specifically, the interlayer insulating layer 140) in a plan view.
  • the peripheral edge of the insulating layer 170 partitions the dicing street DS between the side surfaces 65A to 65D. According to the dicing street DS, it is not necessary to physically cut the insulating layer 170 when cutting out the SiC semiconductor device 61 from the SiC wafer. As a result, the SiC semiconductor device 61 can be smoothly cut out from the SiC wafer, and at the same time, peeling and deterioration of the insulating layer 170 can be suppressed. As a result, the insulating layer 170 can appropriately protect the object to be protected such as the SiC chip 102 and the first main surface electrode 150.
  • the width of the dicing street DS may be 1 ⁇ m or more and 25 ⁇ m or less.
  • the width of the dicing street DS may be 1 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 15 ⁇ m or less, 15 ⁇ m or more and 20 ⁇ m or less, or 20 ⁇ m or more and 25 ⁇ m or less.
  • the insulating layer 170 selectively covers the gate main surface electrode 151 and the source main surface electrode 152.
  • the insulating layer 170 includes a pad opening 171. More specifically, the pad opening 171 includes a gate pad opening 172 and a source pad opening 173.
  • the gate pad opening 172 exposes the gate pad 153.
  • the source pad opening 173 exposes the source pad 157.
  • the planar shape of the gate pad opening 172 is arbitrary.
  • the planar shape of the source pad opening 173 is arbitrary.
  • the insulating layer 170 has a laminated structure including a passivation layer 174 and a resin layer 175 laminated in this order from the SiC chip 62 side.
  • the passivation layer 174 may include at least one of a silicon oxide layer and a silicon nitride layer.
  • the passivation layer 174 may have a laminated structure including a silicon oxide layer and a silicon nitride layer.
  • the passivation layer 174 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer.
  • the passivation layer 174 preferably contains an insulating material different from that of the interlayer insulating layer 140. In this form, the passivation layer 174 has a single-layer structure composed of a silicon nitride layer.
  • the passivation layer 174 is formed in a film shape along the interlayer insulating layer 140.
  • the passivation layer 174 covers the active region 72 and the outer region 73 with the interlayer insulating layer 140 interposed therebetween.
  • the passivation layer 174 is drawn from the active region 72 across the sidewall structure 132 into the outer region 73.
  • the passivation layer 174 forms part of the upper layer structure that covers the sidewall structure 132.
  • the passivation layer 174 has a first gate opening 176 and a first source opening 177.
  • the first gate opening 176 exposes the gate pad 153.
  • the first source opening 177 exposes the source pad 157.
  • the planar shape of the first gate opening 176 is arbitrary.
  • the planar shape of the first source opening 177 is arbitrary.
  • the thickness of the passivation layer 174 may be 0.1 ⁇ m or more and 20 ⁇ m or less.
  • the thickness of the passivation layer 174 may be 0.1 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 15 ⁇ m or less, or 15 ⁇ m or more and 20 ⁇ m or less.
  • the resin layer 175 is formed in a film shape along the main surface of the passivation layer 174.
  • the resin layer 175 is drawn from the active region 72 across the sidewall structure 132 to the outer region 73.
  • the resin layer 175 forms a part of the upper layer structure that covers the sidewall structure 132.
  • the resin layer 175 may contain a photosensitive resin.
  • the photosensitive resin may be a negative type or a positive type.
  • the resin layer 175 may contain at least one of polyimide, polyamide and polybenzoxazole.
  • the resin layer 175 contains polybenzoxazole in this form.
  • the peripheral edge of the resin layer 175 exposes the peripheral edge of the passivation layer 174.
  • the peripheral edge of the insulating layer 170 is formed by the peripheral edge of the resin layer 175 and the peripheral edge of the passivation layer 174.
  • the resin layer 175 may cover the peripheral edge of the passivation layer 174.
  • the resin layer 175 has a second gate opening 178 and a second source opening 179.
  • the second gate opening 178 communicates with the first gate opening 176 of the passivation layer 174 and forms a gate pad opening 172 with the first gate opening 176.
  • the second source opening 179 communicates with the first source opening 177 of the passivation layer 174 and forms a source pad opening 173 with the first source opening 177.
  • the inner wall of the second gate opening 178 may be formed flush with the inner wall of the first gate opening 176.
  • the inner wall of the second gate opening 178 may be located outside the first gate opening 176 in a plan view.
  • the inner wall of the second gate opening 178 may be located within the first gate opening 176 in a plan view. That is, the resin layer 175 may cover the inner wall of the first gate opening 176.
  • the inner wall of the second source opening 179 may be formed flush with the inner wall of the first source opening 177.
  • the inner wall of the second source opening 179 may be located outside the first source opening 177 in a plan view.
  • the inner wall of the second source opening 179 may be located within the first source opening 177 in plan view. That is, the resin layer 175 may cover the inner wall of the first source opening 177.
  • the thickness of the resin layer 175 may be 1 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the resin layer 175 may be 1 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 20 ⁇ m or less, 20 ⁇ m or more and 30 ⁇ m or less, 30 ⁇ m or more and 40 ⁇ m or less, or 40 ⁇ m or more and 50 ⁇ m or less.
  • the SiC semiconductor device 61 includes an uneven structure 180 (Uneven Structure) formed on the outer main surface 112. More specifically, the uneven structure 180 includes unevenness (Unevenness) formed by utilizing the interlayer insulating layer 140 that covers the outer main surface 112. More specifically, the uneven structure 180 includes an anchor hole 181 formed in the interlayer insulating layer 140.
  • the anchor hole 181 is formed by digging down a portion of the interlayer insulating layer 140 that covers the outer region 73.
  • the anchor hole 181 may be formed in a region between the diode region 121 and the side surfaces 65A to 65D in a plan view. In this form, the anchor hole 181 is formed in the region between the FL structure 123 and the side surfaces 65A to 65D in a plan view.
  • the anchor hole 181 may be partitioned by the interlayer insulating layer 140.
  • the anchor hole 181 exposes the outer main surface 112 in this form.
  • the anchor hole 181 may be dug down from the outer main surface 112 toward the second main surface 64.
  • the opening edge portion of the anchor hole 181 is formed in a curved shape toward the inside of the anchor hole 181.
  • the anchor hole 181 extends in a strip shape along the active region 72 in a plan view.
  • the anchor hole 181 is formed in an annular shape (more specifically, an endless shape) surrounding the active region 72 in a plan view.
  • the number of anchor holes 181 is arbitrary.
  • One anchor hole 181 may be formed in the interlayer insulating layer 140, or a plurality of anchor holes 181 may be formed in the interlayer insulating layer 140.
  • the resin layer 175 has an anchor portion 182 that meshes with the anchor hole 181.
  • the resin layer 175 meshes with the anchor hole 181 via the passivation layer 174. More specifically, the passivation layer 174 penetrates into the anchor hole 181 from above the interlayer insulating layer 140.
  • the passivation layer 174 is in contact with the outer main surface 112 in the anchor hole 181.
  • a recess 183 recessed toward the anchor hole 181 is formed in a portion of the main surface of the passivation layer 174 that covers the anchor hole 181.
  • a part of the resin layer 175 forms an anchor portion 182 in the recess 183 of the passivation layer 174.
  • the connection strength of the resin layer 175 to the first main surface 63 can be increased, so that peeling of the resin layer 175 can be appropriately suppressed.
  • the SiC semiconductor device 61 includes a pad electrode 190 formed on the first main surface electrode 150. More specifically, the pad electrode 190 includes a gate pad electrode 191 and a source pad electrode 192.
  • the gate pad electrode 191 is formed on the gate main surface electrode 151 and is electrically connected to the gate main surface electrode 151. More specifically, the gate pad electrode 191 is formed on the gate pad 153 in the gate pad opening 172. The gate pad electrode 191 has a gate terminal surface 193 that is externally connected to the lead wire.
  • the gate terminal surface 193 is located on the gate pad 153 side with respect to the main surface of the insulating layer 170 (resin layer 175).
  • the gate terminal surface 193 may protrude upward from the main surface of the insulating layer 170 (resin layer 175).
  • the gate terminal surface 193 may have an overlapping portion that covers the main surface of the insulating layer 170 (resin layer 175).
  • the source pad electrode 192 is formed on the source main surface electrode 152 and is electrically connected to the source main surface electrode 152. More specifically, the source pad electrode 192 is formed on the source pad 157 in the source pad opening 173. The source pad electrode 192 has a source terminal surface 194 that is externally connected to the lead wire.
  • the source terminal surface 194 is located on the source pad 157 side with respect to the main surface of the insulating layer 170 (resin layer 175).
  • the source terminal surface 194 may protrude upward from the main surface of the insulating layer 170 (resin layer 175).
  • the source terminal surface 194 may have an overlapping portion that covers the main surface of the insulating layer 170 (resin layer 175).
  • the pad electrode 190 (gate pad electrode 191 and source pad electrode 192) contains a metal material different from that of the first main surface electrode 150.
  • the pad electrode 190 has a laminated structure including a Ni layer 195, a Pd layer 196, and an Au layer 197 laminated in this order from the first main surface electrode 150 side.
  • Ni, Pd, and Au each have a Young's modulus (rigidity) that exceeds the Young's modulus (rigidity) of Al.
  • the Ni layer 195, the Pd layer 196 and the Au layer 197 may be plating layers formed by a plating method.
  • the pad electrode 190 may include at least one of the Ni layer 195, the Pd layer 196, and the Au layer 197.
  • the pad electrode 190 may have a laminated structure in which at least two of the Ni layer 195, the Pd layer 196 and the Au layer 197 are laminated in any order.
  • the pad electrode 190 may have a single-layer structure including a Ni layer 195, a Pd layer 196, or an Au layer 197.
  • the gate pad electrode 191 preferably has a gate terminal surface 193 formed by the Au layer 197.
  • the source pad electrode 192 preferably has a source terminal surface 194 formed by the Au layer 197.
  • the pad electrode 190 preferably has a laminated structure including a Ni layer 195 and an Au layer 197 laminated in this order from at least the first main surface electrode 150 side.
  • the thickness of the Ni layer 195 may be 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the Ni layer 195 is 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, or 8 ⁇ m or more and 10 ⁇ m or less. It may be.
  • the thickness of the Pd layer 196 may be 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the Pd layer 196 is 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, or 8 ⁇ m or more and 10 ⁇ m or less. It may be.
  • the thickness of the Au layer 197 may be 0.01 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the Au layer 197 is 0.01 ⁇ m or more and 0.05 ⁇ m or less, 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, or 2 ⁇ m. It may be 3 ⁇ m or more.
  • the thickness of the Au layer 197 is preferably less than the thickness of the Ni layer 195.
  • the thickness of the Au layer 197 is preferably less than the thickness of the Pd layer 196.
  • the SiC semiconductor device 61 includes a second main surface electrode 200 formed on the second main surface 64.
  • the second main surface electrode 200 is formed as a drain electrode of the MISFET.
  • the second main surface electrode 200 covers the entire area of the second main surface 64.
  • the second main surface electrode 200 may be formed at intervals inward from the side surfaces 65A to 65D to expose the peripheral edge portion of the second main surface 64. In this case, it is not necessary to physically cut the second main surface electrode 200 when cutting out the SiC semiconductor device 61 from the SiC wafer. As a result, the SiC semiconductor device 61 can be smoothly cut out from the SiC wafer, and at the same time, peeling and deterioration of the second main surface electrode 200 can be suppressed. As a result, the second main surface electrode 200 can be appropriately connected to the second main surface 64.
  • Such a second main surface electrode 200 can be obtained, for example, by removing an unnecessary portion of the second main surface electrode 200 by an etching method using a resist mask during the manufacturing process. Further, as another example, the second main surface electrode 200 is formed by forming the second main surface electrode 200 that partially covers the second main surface 64 by a lift-off method using a resist mask during the manufacturing process. Obtainable.
  • the second main surface electrode 200 includes a second Al layer 201 that covers the second main surface 64.
  • the second Al layer 201 faces the first Al layer 161 of the gate main surface electrode 151 and the first Al layer 161 of the source main surface electrode 152 with the SiC chip 62 interposed therebetween.
  • the second Al layer 201 is formed as a second buffer layer that relaxes the external force applied to the SiC chip 62 from the second main surface 64 side by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity). There is.
  • the second Al layer 201 includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.
  • the second Al layer 201 may have a laminated structure in which two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer are laminated in any order.
  • the second Al layer 201 may be formed by a sputtering method and / or a vapor deposition method.
  • the second Al layer 201 may have a single layer structure composed of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.
  • the Al-based metal material of the second Al layer 201 may be different from the Al-based metal material of the first Al layer 161.
  • the second Al layer 201 preferably has a single-layer structure composed of a pure Al layer.
  • the second Al layer 201 may have a thickness less than the thickness of the first Al layer 161.
  • the thickness of the second Al layer 201 may be 0.01 ⁇ m or more and 5 ⁇ m or less. Even if the thickness of the second Al layer 201 is 0.01 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 4 ⁇ m or less, or 4 ⁇ m or more and 5 ⁇ m or less. Good.
  • the second main surface electrode 200 further includes one or more electrode layers made of a metal material different from that of the second Al layer 201 in addition to the second Al layer 201.
  • the second main surface electrode 200 is a Ti layer 202, a Ni layer 203, a Pd layer 204, an Au layer 205, and an Ag layer 206 laminated in this order from the second main surface 64 side as an example of a plurality of electrode layers. including.
  • the Ti layer 202 is an ohmic electrode that forms ohmic contact with the second main surface 64.
  • the second Al layer 201 covers the second main surface 64 with the Ti layer 202, the Ni layer 203, the Pd layer 204, the Au layer 205, and the Ag layer 206 interposed therebetween.
  • Ti, Ni, Pd, Au and Ag each have a Young's modulus (rigidity) that exceeds the Young's modulus (rigidity) of Al.
  • the Ti layer 202, the Ni layer 203, the Pd layer 204, the Au layer 205, and the Ag layer 206 may be formed by a sputtering method, a vapor deposition method, and / or a plating method.
  • the second main surface electrode 200 may include at least one of the Ti layer 202, the Ni layer 203, the Pd layer 204, the Au layer 205, and the Ag layer 206 as one or more electrode layers.
  • the second Al layer 201 preferably covers the second main surface 64 with at least the Ti layer 202 interposed therebetween.
  • the second main surface electrode 200 includes at least one of Ni layer 203, Pd layer 204 and Au layer 205
  • at least one of Ni layer 203, Pd layer 204 and Au layer 205 is a pad electrode 190. It may be a plating layer formed at the same time as the Ni layer 195, the Pd layer 196 and the Au layer 197.
  • the thickness of the Ti layer 202 may be 0.01 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the Ti layer 202 is 0.01 ⁇ m or more and 0.05 ⁇ m or less, 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, or 2 ⁇ m. It may be 3 ⁇ m or more.
  • the thickness of the Ni layer 203 may be 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the Ni layer 203 is 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, or 8 ⁇ m or more and 10 ⁇ m or less. It may be.
  • the thickness of the Ni layer 203 preferably exceeds the thickness of the Ti layer 202.
  • the thickness of the Pd layer 204 may be 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the Pd layer 204 is 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, or 8 ⁇ m or more and 10 ⁇ m or less. It may be.
  • the thickness of the Pd layer 204 preferably exceeds the thickness of the Ti layer 202.
  • the thickness of the Au layer 205 may be 0.01 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the Au layer 205 is 0.01 ⁇ m or more and 0.05 ⁇ m or less, 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, or 2 ⁇ m. It may be 3 ⁇ m or more.
  • the thickness of the Au layer 205 is preferably less than the thickness of the Ni layer 203.
  • the thickness of the Au layer 205 is preferably less than the thickness of the Pd layer 204.
  • the thickness of the Ag layer 206 may be 0.01 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the Ag layer 206 is 0.01 ⁇ m or more and 0.05 ⁇ m or less, 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, or 2 ⁇ m. It may be 3 ⁇ m or more.
  • the thickness of the Ag layer 206 is preferably less than the thickness of the Ni layer 203.
  • the thickness of the Ag layer 206 is preferably less than the thickness of the Pd layer 204.
  • the second main surface electrode 200 may have the structure shown in FIGS. 17A to 17I.
  • FIG. 17A is a cross-sectional view schematically showing the second main surface electrode 200 according to the second embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 6 to 16, and the description thereof will be omitted.
  • the second main surface electrode 200 has a laminated structure including a second Al layer 201, a Ti layer 202, a Ni layer 203, a Pd layer 204, and an Au layer 205 in this form.
  • the Ti layer 202, the Ni layer 203, the Pd layer 204, and the Au layer 205 are laminated in this order from the second main surface 64 side.
  • the second Al layer 201 covers the second main surface 64 with the Ti layer 202, the Ni layer 203, the Pd layer 204, and the Au layer 205 interposed therebetween.
  • FIG. 17B is a cross-sectional view schematically showing the second main surface electrode 200 according to the third embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 6 to 16, and the description thereof will be omitted.
  • the second main surface electrode 200 has a laminated structure including the second Al layer 201, the Ti layer 202, the Ni layer 203, the Au layer 205, and the Ag layer 206 in this form.
  • the Ti layer 202, the Ni layer 203, the Au layer 205, and the Ag layer 206 are laminated in this order from the second main surface 64 side.
  • the second Al layer 201 covers the second main surface 64 with the Ti layer 202, the Ni layer 203, the Au layer 205, and the Ag layer 206 interposed therebetween.
  • FIG. 17C is a cross-sectional view schematically showing the second main surface electrode 200 according to the fourth embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 6 to 16, and the description thereof will be omitted.
  • the second main surface electrode 200 has a laminated structure including the second Al layer 201, the Ti layer 202, the Ni layer 203, and the Au layer 205 in this form.
  • the Ti layer 202, the Ni layer 203, and the Au layer 205 are laminated in this order from the second main surface 64 side.
  • the second Al layer 201 covers the second main surface 64 with the Ti layer 202, the Ni layer 203, and the Au layer 205 interposed therebetween.
  • FIG. 17D is a cross-sectional view schematically showing the second main surface electrode 200 according to the fifth embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 6 to 16, and the description thereof will be omitted.
  • the second main surface electrode 200 has a laminated structure including the second Al layer 201 and the Ti layer 202 in this form.
  • the Ti layer 202 is connected to the second main surface 64.
  • the second Al layer 201 covers the second main surface 64 with the Ti layer 202 interposed therebetween.
  • FIG. 17E is a cross-sectional view schematically showing the second main surface electrode 200 according to the sixth embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 6 to 16, and the description thereof will be omitted.
  • the second main surface electrode 200 includes a second Al layer 201, a Ti layer 202, a Ni layer 203 and an Au layer 205 in this form.
  • the Ti layer 202, the Ni layer 203, and the Au layer 205 are laminated in this order from the second main surface 64 side.
  • the second Al layer 201 is interposed between the Ti layer 202 and the Ni layer 203, and covers the second main surface 64 with the Ti layer 202 interposed therebetween.
  • the pad electrode 190 has a two-layer structure composed of a Ni layer 195 and an Au layer 197 laminated in this order from the first main surface electrode 150 side.
  • the Ni layer 203 and the Au layer 205 of the second main surface electrode 200 can be formed at the same time as the Ni layer 195 and the Au layer 197 of the pad electrode 190 by the plating method.
  • FIG. 17F is a cross-sectional view schematically showing the second main surface electrode 200 according to the seventh embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 6 to 16, and the description thereof will be omitted.
  • the second main surface electrode 200 includes a second Al layer 201, a Ti layer 202, a Ni layer 203, an Au layer 205, and an Ag layer 206 in this form.
  • the Ti layer 202, the Ni layer 203, the Au layer 205, and the Ag layer 206 are laminated in this order from the second main surface 64 side.
  • the second Al layer 201 is interposed between the Ti layer 202 and the Ni layer 203, and covers the second main surface 64 with the Ti layer 202 interposed therebetween.
  • the pad electrode 190 has a two-layer structure composed of a Ni layer 195 and an Au layer 197 laminated in this order from the first main surface electrode 150 side.
  • the Ni layer 203 and the Au layer 205 of the second main surface electrode 200 can be formed at the same time as the Ni layer 195 and the Au layer 197 of the pad electrode 190 by the plating method.
  • FIG. 17G is a cross-sectional view schematically showing the second main surface electrode 200 according to the eighth embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 6 to 16, and the description thereof will be omitted.
  • the second main surface electrode 200 includes a second Al layer 201, a Ti layer 202, a Ni layer 203, a Pd layer 204, an Au layer 205, and an Ag layer 206 in this form.
  • the Ti layer 202, the Ni layer 203, the Au layer 205, and the Ag layer 206 are laminated in this order from the second main surface 64 side.
  • the second Al layer 201 is interposed between the Ti layer 202 and the Ni layer 203, and covers the second main surface 64 with the Ti layer 202 interposed therebetween.
  • the pad electrode 190 has a three-layer structure including a Ni layer 195, a Pd layer 196, and an Au layer 197 laminated in this order from the first main surface electrode 150 side.
  • the Ni layer 203, the Pd layer 204, and the Au layer 205 of the second main surface electrode 200 can be formed at the same time as the Ni layer 195, the Pd layer 196, and the Au layer 197 of the pad electrode 190 by the plating method.
  • FIG. 17H is a cross-sectional view schematically showing the second main surface electrode 200 according to the ninth embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 6 to 16, and the description thereof will be omitted.
  • the second main surface electrode 200 includes a second Al layer 201, a Ti layer 202, a Ni layer 203, a Pd layer 204, and an Au layer 205 in this form.
  • the Ti layer 202, the Ni layer 203, the Pd layer 204, and the Au layer 205 are laminated in this order from the second main surface 64 side.
  • the second Al layer 201 is interposed between the Ti layer 202 and the Ni layer 203, and covers the second main surface 64 with the Ti layer 202 interposed therebetween.
  • the pad electrode 190 has a three-layer structure including a Ni layer 195, a Pd layer 196, and an Au layer 197 laminated in this order from the first main surface electrode 150 side.
  • the Ni layer 203, the Pd layer 204, and the Au layer 205 of the second main surface electrode 200 can be formed at the same time as the Ni layer 195, the Pd layer 196, and the Au layer 197 of the pad electrode 190 by the plating method.
  • FIG. 17I is a cross-sectional view schematically showing the second main surface electrode 200 according to the tenth embodiment.
  • the same reference numerals will be given to the structures corresponding to the structures described in FIGS. 6 to 16, and the description thereof will be omitted.
  • the second main surface electrode 200 includes a second Al layer 201 and a VDD layer 207 in this form.
  • the silicide layer 207 is formed on the second main surface 64.
  • the silicide layer 207 is formed by silicating the SiC exposed from the second main surface 64 with a metal material.
  • the silicide layer 207 is one of the FeSi 2 layer, NiSi layer, NiSi 2 layer, CoSi 2 layer, CrSi 2 layer, WSi 2 layer, MoSi 2 layer, MnSi 2 layer, NbSi 2 layer, TiSi 2 layer and VSi 2 layer. At least one may be included.
  • the second Al layer 201 covers the second main surface 64 with the VDD layer 207 interposed therebetween.
  • the second main surface electrode 200 may include at least one of the Ti layer 202, the Ni layer 203, the Pd layer 204, the Au layer 205, and the Ag layer 206, in addition to the second Al layer 201 and the VDD layer 207. ..
  • the stacking order of the second Al layer 201, Ti layer 202, Ni layer 203, Pd layer 204, Au layer 205, and Ag layer 206 is arbitrary.
  • any one of the laminated structures of the first to tenth embodiments may be adopted.
  • FIG. 18 is a diagram showing a semiconductor package 211 in which the SiC semiconductor device 61 shown in FIG. 6 is incorporated.
  • the internal structure of the semiconductor package 211 is shown through the package body 212.
  • the semiconductor package 211 is a 3-terminal type TO-220 in this form.
  • the semiconductor package 211 includes a package body 212, a metal plate 213, a first terminal 214, a second terminal 215, a third terminal 216, a SiC semiconductor device 61, a conductive bonding material 217, a first conducting wire 218 and a second conducting wire 219.
  • the package body 212 is made of molded resin.
  • the package body 212 may contain an epoxy resin as an example of the mold resin.
  • the package body 212 is formed in a rectangular parallelepiped shape.
  • the package body 212 includes a first surface 221 on one side and a second surface 222 on the other side, and four side surfaces 223A, 223B, 223C, 223D connecting the first surface 221 and the second surface 222.
  • the four side surfaces 223A to 223D include a first side surface 223A, a second side surface 223B, a third side surface 223C, and a fourth side surface 223D.
  • the first side surface 223A and the second side surface 223B face each other.
  • the third side surface 223C and the fourth side surface 223D face each other.
  • the metal plate 213 may contain at least one of Fe, Au, Ag, Cu and Al.
  • the metal plate 213 may have an outer surface on which at least one of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film is formed.
  • the planar shape of the metal plate 213 is arbitrary. In this form, the metal plate 213 is formed in a rectangular shape (rectangular shape) in a plan view.
  • the metal plate 213 integrally includes a pad portion 224 located inside the package body 212 and a heat sink portion 225 located outside the package body 212.
  • the heat sink portion 225 is pulled out from the pad portion 224 across the second side surface 223B to the outside of the package body 212.
  • the heat sink portion 225 includes a through hole 225a.
  • the through hole 225a is formed in a circular shape.
  • the plane area of the heat sink portion 225 may exceed the plane area of the pad portion 224.
  • the metal plate 213 is arranged in the package body 212 so as to be exposed from the second surface 222.
  • the metal plate 213 may be arranged in the package body 212 so as not to be exposed from the second surface 222.
  • the first terminal 214 may contain at least one of Fe, Au, Ag, Cu and Al.
  • the first terminal 214 may have an outer surface on which at least one of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film is formed.
  • the first terminal 214 is drawn out of the package body 212 across the first side surface 223A from the inside of the package body 212.
  • the first terminal 214 includes a first inner end portion 226, a first outer end portion 227, and a first band-shaped portion 228.
  • the first inner end portion 226 is connected to the metal plate 213 in the package body 212.
  • the first outer end portion 227 is arranged outside the package main body 212.
  • the first band-shaped portion 228 extends between the first inner end portion 226 and the first outer end portion 227 in a direction orthogonal to the first side surface 223A.
  • the second terminal 215 may contain at least one of Fe, Au, Ag, Cu and Al.
  • the second terminal 215 may have an outer surface on which at least one of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film is formed.
  • the second terminal 215 is pulled out from the inside of the package main body 212 across the first side surface 223A to the outside of the package main body 212.
  • the second terminal 215 is arranged in the area on the third side surface 223C side at a distance from the first terminal 214 in a plan view.
  • the second terminal 215 is arranged in the region on the first surface 221 side with respect to the plate surface of the metal plate 213.
  • the third terminal 216 may contain at least one of Fe, Au, Ag, Cu and Al.
  • the third terminal 216 may have an outer surface on which at least one of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film is formed.
  • the third terminal 216 is pulled out from the inside of the package main body 212 across the first side surface 223A to the outside of the package main body 212.
  • the third terminal 216 is arranged in the area on the 223D side of the fourth side surface at a distance from the first terminal 214 in a plan view.
  • the third terminal 216 is arranged in the region on the first surface 221 side with respect to the plate surface of the metal plate 213.
  • the third terminal 216 includes a third inner end portion 232, a third outer end portion 233, and a third strip-shaped portion 234.
  • the third inner end portion 232 is arranged in the package main body 212 at a distance from the metal plate 213.
  • the third outer end portion 233 is arranged outside the package main body 212.
  • the third band-shaped portion 234 extends between the third inner end portion 232 and the third outer end portion 233 in a direction orthogonal to the first side surface 223A.
  • the SiC semiconductor device 61 is arranged on the pad portion 224 of the metal plate 213 in the package main body 212.
  • the conductive bonding material 217 is interposed between the SiC semiconductor device 61 and the pad portion 224, and the second main surface electrode 200 of the SiC semiconductor device 61 is bonded to the pad portion 224.
  • the SiC semiconductor device 61 is electrically connected to the first terminal 214 via the metal plate 213.
  • the conductive bonding material 217 may be a metal paste or solder.
  • the metal paste may contain at least one of Au, Ag and Cu.
  • the conductive bonding material 217 is preferably made of solder.
  • the solder may be lead-free solder.
  • the solder may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi and SnSbNi.
  • the first lead wire 218 is made of a metal wire (bonding wire) or a metal clip.
  • the metal wire may be an Al wire, an Au wire, a Cu wire or a solder wire.
  • the solder wire may be a lead-free solder wire.
  • the solder wire may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi and SnSbNi.
  • the metal clip may be an Al clip, an Au clip or a Cu clip.
  • the first lead wire 218 is made of a solder wire in this form.
  • the first lead wire 218 is connected to the second inner end portion 229 of the second terminal 215 and the gate pad electrode 191 of the SiC semiconductor device 61 in the package main body 212. As a result, the SiC semiconductor device 61 is electrically connected to the second terminal 215.
  • FIG. 18 shows an example in which one first lead wire 218 is connected to the second inner end portion 229 and the gate pad electrode 191.
  • the number of the first lead wires 218 is arbitrary. Two or more first lead wires 218 may be connected to the second inner end portion 229 and the gate pad electrode 191.
  • the second lead wire 219 is made of a metal wire (bonding wire) or a metal clip.
  • the metal wire may be an Al wire, an Au wire, a Cu wire or a solder wire.
  • the solder wire may be a lead-free solder wire.
  • the solder wire may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi and SnSbNi.
  • the metal clip may be an Al clip, an Au clip or a Cu clip.
  • the second lead wire 219 is made of a solder wire in this form.
  • the second lead wire 219 is connected to the third inner end portion 232 of the third terminal 216 and the source pad electrode 192 of the SiC semiconductor device 61 in the package main body 212. As a result, the SiC semiconductor device 61 is electrically connected to the third terminal 216.
  • FIG. 18 shows an example in which two second conducting wires 219 are connected to the third inner end portion 232 and the source pad electrode 192, but the number of the second conducting wires 219 is arbitrary.
  • One or more second conductors 219 may be connected to the third inner end 232 and the source pad electrode 192.
  • the first Al layer 161 is formed as a first buffer layer that relaxes the external force on the first main surface 63 side
  • the second Al layer 201 relaxes the external force on the second main surface 64 side. It is formed as a second buffer layer.
  • the external force applied to the SiC chip 62 when the SiC semiconductor device 61 is mounted on the pad portion 224 of the metal plate 213 can be relaxed by the first Al layer 161 and the second Al layer 201. Further, the external force applied to the SiC chip 62 when the first lead wire 218 and the second lead wire 219 are joined to the pad electrode 190 of the SiC semiconductor device 61 can be relaxed by the first Al layer 161 and the second Al layer 201. As a result, cracks in the SiC chip 62 can be suppressed.
  • the SiC semiconductor device 61 includes a pad electrode 190 (gate pad electrode 191 and source pad electrode 192) externally bonded to the first lead wire 218 and the second lead wire 219.
  • the pad electrode 190 includes at least one of a Ni layer 195, a Pd layer 196 and an Au layer 197. Thereby, the first lead wire 218 and the second lead wire 219 can be appropriately connected to the pad electrode 190.
  • Ni, Pd and Au each have a Young's modulus (rigidity) that exceeds the Young's modulus (rigidity) of Al. Therefore, in the structure provided with the pad electrode 190, the external force applied at the time of joining the first lead wire 218 and the second lead wire 219 cannot be appropriately relaxed.
  • a first Al layer 161 containing Al is interposed between the SiC chip 62 and the pad electrode 190.
  • the external force applied to the SiC chip 62 can be relaxed from the first main surface 63 side by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity). Therefore, the first lead wire 218 and the second lead wire 219 can be appropriately bonded to the pad electrode 190, and at the same time, cracks in the SiC chip 62 can be suppressed.
  • the SiC semiconductor device 61 includes, in addition to the second Al layer 201, a second main surface electrode 200 having one or more electrode layers made of a metal material different from the second Al layer 201.
  • the one or more electrode layers include at least one of the Ti layer 202, the Ni layer 203, the Pd layer 204, the Au layer 205, and the Ag layer 206.
  • the adhesion of the conductive bonding material 217 to the second main surface electrode 200 can be appropriately increased.
  • the SiC semiconductor device 61 can be appropriately mounted on the pad portion 224 of the metal plate 213.
  • Ti, Ni, Pd, Au and Ag each have a Young's modulus (rigidity) exceeding the Young's modulus (rigidity) of Al. Therefore, in a structure in which the second main surface electrode 200 includes at least one of the Ti layer 202, the Ni layer 203, the Pd layer 204, the Au layer 205, and the Ag layer 206, when the SiC semiconductor device 61 is mounted or the first lead wire The external force applied at the time of joining 218 and the second lead wire 219 cannot be appropriately relaxed.
  • the second main surface electrode 200 including the second Al layer 201 is provided in addition to at least one of the Ti layer 202, the Ni layer 203, the Pd layer 204, the Au layer 205, and the Ag layer 206. Is forming. According to the second Al layer 201, the external force applied to the SiC chip 62 can be relaxed from the second main surface 64 side by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity). Therefore, the SiC semiconductor device 61 can be appropriately mounted on the pad portion 224, and at the same time, cracks in the SiC chip 62 can be suppressed.
  • an SBD is formed as an example of a diode
  • a p-type diode region 10 may be formed instead of the n-type diode region 10.
  • a pn junction diode can be provided instead of the SBD.
  • the insulating layer 170 has a laminated structure including the passivation layer 174 and the resin layer 175 has been described.
  • the insulating layer 170 may have a single-layer structure composed of a passivation layer 174 or a resin layer 175.
  • the gate electrode 80 and the gate wiring 85 containing the p-type polysilicon to which the p-type impurity is added has been formed.
  • the gate electrode 80 and the gate wiring 85 include n-type polysilicon to which n-type impurities are added in place of or in addition to the p-type polysilicon. You may be.
  • the low resistance layer 86 may be formed by silicating the portion of the gate electrode 80 (n-type polysilicon) that forms the surface layer portion with a metal material. That is, the low resistance layer 86 may include an n-type polyside. In the case of such a structure, the gate resistance can be reduced.
  • a MISFET is formed as an example of an insulated gate transistor.
  • a p + type collector region may be adopted instead of the n + type drain region 68.
  • an IGBT Insulated Gate Bipolar Transistor
  • the "source" of the MISFET is read as the "emitter” of the IGBT, and the "drain” of the MISFET is read as the "collector” of the IGBT.
  • the p-type portion may be n-type and the n-type portion may be p-type.
  • various external forces are applied to the semiconductor device.
  • a mounting machine equipped with a suction nozzle is used.
  • the semiconductor device is conveyed to the object to be connected while being attracted and held by the suction nozzle, and then pressed and mounted on the object to be connected.
  • an external force from the suction nozzle toward the connection target and an external force from the connection target toward the suction nozzle are applied to the semiconductor device.
  • the lead wire is pressed and joined to the pad electrode by the capillary.
  • an external force from the capillary toward the connection object and an external force from the connection object toward the capillary are applied to the semiconductor device.
  • an external force exceeding the strength of the chip is applied to the semiconductor device, the chip cracks.
  • a semiconductor device capable of alleviating an external force will be provided.
  • a chip having a first main surface on one side and a second main surface on the other side, a first main surface electrode including a first Al layer and formed on the first main surface, and the first surface.
  • a semiconductor device including a pad electrode formed on a main surface electrode and connected to a lead wire, and a second main surface electrode including a second Al layer and formed on the second main surface.
  • the first Al layer is formed as a first buffer layer that relaxes an external force on the first main surface side
  • the second Al layer is formed as a second buffer layer that relaxes an external force on the second main surface side.
  • An insulating layer having a pad opening for covering the first main surface electrode on the first main surface and exposing a part of the first main surface electrode is further included, and the pad electrode is the pad.
  • the semiconductor device according to A1 which is formed on the first main surface electrode in the opening.
  • the chip has a side surface connecting the first main surface and the second main surface, and the insulating layer is a peripheral edge formed on the first main surface at a distance from the side surface.
  • A6 The semiconductor device according to any one of A1 to A5, wherein the pad electrode includes at least one of a Ni layer, a Pd layer, and an Au layer.
  • the second main surface electrode includes one or more electrode layers made of a metal material different from the second Al layer, and the second Al layer covers one or more of the electrode layers.
  • the semiconductor device according to any one of A1 to A8.
  • the one or more electrode layers include at least one of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer.
  • the one or more electrode layers include at least an ohmic electrode layer that forms ohmic contact with the second main surface, and the second Al layer covers at least the ohmic electrode layer. , A9 or A10.
  • the semiconductor device according to any one of A1 to A12, wherein the second Al layer includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.
  • the semiconductor device according to any one of A1 to A14, wherein the first Al layer includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.
  • the first main surface electrode forms an anode electrode electrically connected to the anode of the diode
  • the second main surface electrode is The semiconductor device according to any one of A1 to A15, which forms a cathode electrode electrically connected to the anode of the diode.
  • the MISFET formed on the first main surface is further included, and the first main surface electrode is electrically connected to the gate main surface electrode electrically connected to the gate of the MISFET and the source of the MISFET.
  • the pad electrode includes a gate pad electrode formed on the gate main surface electrode and a source pad electrode formed on the source main surface electrode.
  • A18 Any one of A1 to A17, wherein the chip has a laminated structure including a semiconductor substrate and an epitaxial layer laminated in this order from the second main surface side to the first main surface side.

Abstract

ＳｉＣ半導体装置は、一方側の第１主面および他方側の第２主面を有するＳｉＣチップと、第１Ａｌ層を含み、前記第１主面の上に形成された第１主面電極と、前記第１主面電極の上に形成され、導線に接続されるパッド電極と、第２Ａｌ層を含み、前記第２主面の上に形成された第２主面電極と、を含む。

Description

ＳｉＣ半導体装置
　本発明は、ＳｉＣ半導体装置に関する。
　特許文献１は、ＳｉＣ基板（ＳｉＣチップ）と、Ａｌを含み、ＳｉＣ基板の表面の上に形成されたパッド電極と、ＳｉＣ基板の裏面の上に形成されたオーミック電極と、を含む、ＳｉＣ半導体装置を開示している。パッド電極には、ボンディングワイヤ（導線）が接合される。
特開２０１５－２０７７８０号公報
　後工程（アセンブリ工程）では、様々な外力がＳｉＣ半導体装置に加えられる。たとえば、ＳｉＣ半導体装置の実装時には、吸着ノズルを備えた実装機が使用される。ＳｉＣ半導体装置は、吸着ノズルに吸着保持された状態で接続対象物まで搬送された後、接続対象部に押圧実装される。この時、吸着ノズルから接続対象物に向かう外力、および、接続対象物から吸着ノズルに向かう外力がＳｉＣ半導体装置に加えられる。
　また、ＳｉＣ半導体装置の実装後には、キャピラリによって導線がパッド電極に押圧接合される。この時、キャピラリから接続対象物に向かう外力、および、接続対象物からキャピラリに向かう外力がＳｉＣ半導体装置に加えられる。ＳｉＣチップの強度を超える外力がＳｉＣ半導体装置に加えられると、ＳｉＣチップにクラックが発生する。
　本発明の一実施形態は、外力を緩和できるＳｉＣ半導体装置を提供する。
　本発明の一実施形態は、一方側の第１主面および他方側の第２主面を有するＳｉＣチップと、第１Ａｌ層を含み、前記第１主面の上に形成された第１主面電極と、前記第１主面電極の上に形成され、導線に接続されるパッド電極と、第２Ａｌ層を含み、前記第２主面の上に形成された第２主面電極と、を含む、ＳｉＣ半導体装置を提供する。
　このＳｉＣ半導体装置によれば、第１Ａｌ層が第１主面側で外力を緩和する第１緩衝層として形成され、第２Ａｌ層が第２主面側で外力を緩和する第２緩衝層として形成されている。これにより、第１主面から第２主面に向かう方向の外力、および、第２主面から第１主面に向かう方向の外力を緩和できる。
　本発明における上述の、またはさらに他の目的、特徴および効果は、添付図面を参照して次に述べる実施形態の説明により明らかにされる。
図１は、本発明の第１実施形態に係るＳｉＣ半導体装置を示す平面図である。 図２は、図１に示すII-II線に沿う断面図であって、第１形態例に係る第２主面電極が組み込まれた形態を示している。 図３は、図２に示す第２主面電極を図解的に示す断面図である。 図４Ａは、第２形態例に係る第２主面電極を図解的に示す断面図である。 図４Ｂは、第３形態例に係る第２主面電極を図解的に示す断面図である。 図４Ｃは、第４形態例に係る第２主面電極を図解的に示す断面図である。 図４Ｄは、第５形態例に係る第２主面電極を図解的に示す断面図である。 図４Ｅは、第６形態例に係る第２主面電極を図解的に示す断面図である。 図４Ｆは、第７形態例に係る第２主面電極を図解的に示す断面図である。 図４Ｇは、第８形態例に係る第２主面電極を図解的に示す断面図である。 図４Ｈは、第９形態例に係る第２主面電極を図解的に示す断面図である。 図４Ｉは、第１０形態例に係る第２主面電極を図解的に示す断面図である。 図５は、図１に示すＳｉＣ半導体装置が組み込まれた半導体パッケージを示す図である。 図６は、本発明の第２実施形態に係るＳｉＣ半導体装置の斜視図であって、第１形態例に係る第２主面電極が組み込まれた形態を示している。 図７は、図６に示すＳｉＣ半導体装置の平面図である。 図８は、第１主面電極の上の構造を取り除いた平面図である。 図９は、図８に示す領域IXの内部構造を示す拡大平面図である。 図１０は、図９に示すX-X線に沿う断面図である。 図１１は、図９に示すXI-XI線に沿う断面図である。 図１２は、図１０に示す領域XIIの拡大図である。 図１３は、図７に示すXIII-XIII線に沿う断面図である。 図１４は、ゲートパッド電極を示す断面図である。 図１５は、ソースパッド電極を示す断面図である。 図１６は、第２主面電極を図解的に示す断面図である。 図１７Ａは、第２形態例に係る第２主面電極を図解的に示す断面図である。 図１７Ｂは、第３形態例に係る第２主面電極を図解的に示す断面図である。 図１７Ｃは、第４形態例に係る第２主面電極を図解的に示す断面図である。 図１７Ｄは、第５形態例に係る第２主面電極を図解的に示す断面図である。 図１７Ｅは、第６形態例に係る第２主面電極を図解的に示す断面図である。 図１７Ｆは、第７形態例に係る第２主面電極を図解的に示す断面図である。 図１７Ｇは、第８形態例に係る第２主面電極を図解的に示す断面図である。 図１７Ｈは、第９形態例に係る第２主面電極を図解的に示す断面図である。 図１７Ｉは、第１０形態例に係る第２主面電極を図解的に示す断面図である。 図１８は、図６に示すＳｉＣ半導体装置が組み込まれた半導体パッケージを示す図である。
　図１は、本発明の第１実施形態に係るＳｉＣ半導体装置１を示す平面図である。図２は、図１に示すII-II線に沿う断面図であって、第１形態例に係る第２主面電極３１が組み込まれた形態を示している。図３は、図２に示す第２主面電極３１を図解的に示す断面図である。
　図１および図２を参照して、ＳｉＣ半導体装置１は、ＳｉＣチップ２を含む。ＳｉＣチップ２は、六方晶からなるＳｉＣ単結晶を含む。六方晶からなるＳｉＣ単結晶は、原子配列の周期に応じて、２Ｈ（Hexagonal）－ＳｉＣ単結晶、４Ｈ－ＳｉＣ単結晶、６Ｈ－ＳｉＣ単結晶等を含む複数種のポリタイプを有している。ＳｉＣチップ２は、この形態（this embodiment）では、４Ｈ－ＳｉＣ単結晶からなるが、他のポリタイプを除外するものではない。
　ＳｉＣチップ２は、直方体形状のチップ状に形成されている。ＳｉＣチップ２は、一方側の第１主面３、他方側の第２主面４、ならびに、第１主面３および第２主面４を接続する側面５Ａ，５Ｂ，５Ｃ，５Ｄを有している。第１主面３および第２主面４は、それらの法線方向Ｚから見た平面視（以下、単に「平面視」という。）において四角形状（この形態では正方形状）に形成されている。
　ＳｉＣチップ２の厚さは、４０μｍ以上３００μｍ以下であってもよい。ＳｉＣチップ２の厚さは、４０μｍ以上１００μｍ以下、１００μｍ以上１５０μｍ以下、１５０μｍ以上２００μｍ以下、２００μｍ以上２５０μｍ以下、または、２５０μｍ以上３００μｍ以下であってもよい。ＳｉＣチップ２の厚さは、６０μｍ以上１５０μｍ以下であることが好ましい。
　第１主面３および第２主面４は、ＳｉＣ単結晶のｃ面に面している。第１主面３は、ＳｉＣ単結晶のシリコン面（（０００１）面）に面している。第１主面３は、非実装面である。第２主面４は、ＳｉＣ単結晶のカーボン面（（０００－１）面）に面している。第２主面４は、実装面である。第２主面４は、研削痕およびアニール痕のいずれか一方または双方を有する粗面であってもよい。アニール痕は、レーザ照射痕である。第２主面４は、アニール痕を有するオーミック面であってもよい。
　第１主面３および第２主面４は、ＳｉＣ単結晶のｃ面に対してａ軸方向（［１１－２０］方向）に０°以上１０°以下の角度で傾斜したオフ角を有している。法線方向Ｚは、ＳｉＣ単結晶のｃ軸（［０００１］方向）に対してオフ角分だけ傾斜している。
　オフ角は、０°以上６°以下であってもよい。オフ角は、０°以上２°以下、２°以上４°以下、または、４°以上６°以下であってもよい。オフ角は、０°を超えて４．５°以下であることが好ましい。オフ角は、３°以上４．５°以下であってもよい。この場合、オフ角は、３°以上３．５°以下、または、３．５°以上４°以下であることが好ましい。オフ角は、１．５°以上３°以下であってもよい。この場合、オフ角は、１．５°以上２°以下、または、２°以上２．５°以下であることが好ましい。
　側面５Ａ～５Ｄは、第１側面５Ａ、第２側面５Ｂ、第３側面５Ｃおよび第４側面５Ｄを含む。第１側面５Ａおよび第２側面５Ｂは、第１方向Ｘに沿って延び、第１方向Ｘに交差する第２方向Ｙに互いに対向している。第３側面５Ｃおよび第４側面５Ｄは、第２方向Ｙに沿って延び、第１方向Ｘに互いに対向している。第２方向Ｙは、より具体的には、第１方向Ｘに直交している。
　第１側面５Ａおよび第２側面５Ｂは、ＳｉＣ単結晶のａ面によって形成されている。第１側面５Ａおよび第２側面５Ｂは、法線方向Ｚを基準にしたとき、法線方向Ｚに対してＳｉＣ単結晶のｃ軸方向（［０００１］方向）に向けて傾斜した傾斜面を形成していてもよい。第１側面５Ａおよび第２側面５Ｂは、法線方向Ｚを０°としたとき、法線方向Ｚに対してオフ角に応じた角度で傾斜していてもよい。オフ角に応じた角度は、オフ角と等しくてもよいし、０°を超えてオフ角未満の角度であってもよい。
　第３側面５Ｃおよび第４側面５Ｄは、ＳｉＣ単結晶のｍ面によって形成されていてもよい。第３側面５Ｃおよび第４側面５Ｄは、法線方向Ｚに沿って平面的に延びている。第３側面５Ｃおよび第４側面５Ｄは、より具体的には、第１主面３および第２主面４に対して略垂直に形成されている。
　側面５Ａ～５Ｄは、劈開面または研削面からなっていてもよい。側面５Ａ～５Ｄの長さは、０．１ｍｍ以上１０ｍｍ以下であってもよい。側面５Ａ～５Ｄの長さは、０．５ｍｍ以上２．５ｍｍ以下であることが好ましい。
　ＳｉＣチップ２は、この形態では、ｎ＋型のＳｉＣ半導体基板６およびｎ型のＳｉＣエピタキシャル層７を含む積層構造を有している。ＳｉＣ半導体基板６によって、ＳｉＣチップ２の第２主面４が形成されている。ＳｉＣエピタキシャル層７によって、ＳｉＣチップ２の第１主面３が形成されている。ＳｉＣ半導体基板６およびＳｉＣエピタキシャル層７によって、ＳｉＣチップ２の側面５Ａ～５Ｄが形成されている。
　ＳｉＣエピタキシャル層７のｎ型不純物濃度は、ＳｉＣ半導体基板６のｎ型不純物濃度未満である。ＳｉＣ半導体基板６のｎ型不純物濃度は、１．０×１０１８ｃｍ－３以上１．０×１０２１ｃｍ－３以下であってもよい。ＳｉＣエピタキシャル層７のｎ型不純物濃度は、１．０×１０１５ｃｍ－３以上１．０×１０１８ｃｍ－３以下であってもよい。
　ＳｉＣ半導体基板６の厚さは、４０μｍ以上２５０μｍ以下であってもよい。ＳｉＣ半導体基板６の厚さは、４０μｍ以上１００μｍ以下、１００μｍ以上１５０μｍ以下、１５０μｍ以上２００μｍ以下、または、２００μｍ以上２５０μｍ以下であってもよい。ＳｉＣ半導体基板６の厚さは、４０μｍ以上１５０μｍ以下であることが好ましい。ＳｉＣ半導体基板６を薄化することにより、ＳｉＣ半導体基板６の抵抗値を低減できる。
　ＳｉＣエピタキシャル層７の厚さは、１μｍ以上５０μｍ以下であってもよい。ＳｉＣエピタキシャル層７の厚さは、１μｍ以上５μｍ以下、５μｍ以上１０μｍ以下、１０μｍ以上１５μｍ以下、１５μｍ以上２０μｍ以下、２０μｍ以上３０μｍ以下、３０μｍ以上４０μｍ以下、または、４０μｍ以上５０μｍ以下であってもよい。ＳｉＣエピタキシャル層７の厚さは、５μｍ以上１５μｍ以下であることが好ましい。
　ＳｉＣチップ２は、アクティブ領域８および外側領域９を含む。アクティブ領域８は、機能デバイス（ダイオード）の一例としてのＳＢＤ（Schottky Barrier Diode）を含む領域である。アクティブ領域８は、平面視において側面５Ａ～５Ｄから内方に間隔を空けてＳｉＣチップ２の中央部に形成されている。アクティブ領域８は、平面視において側面５Ａ～５Ｄに平行な４辺を有する四角形状に形成されている。
　外側領域９は、アクティブ領域８の外側の領域である。外側領域９は、側面５Ａ～５Ｄおよびアクティブ領域８の間の領域に形成されている。外側領域９は、平面視においてアクティブ領域８を取り囲む環状（より具体的に無端状）に形成されている。
　ＳｉＣ半導体装置１は、アクティブ領域８において第１主面３の表層部に形成されたｎ型のダイオード領域１０を含む。ダイオード領域１０は、第１主面３の中央部に形成されている。ダイオード領域１０の平面形状は任意である。ダイオード領域１０は、平面視において側面５Ａ～５Ｄに平行な４辺を有する四角形状に形成されていてもよい。
　ダイオード領域１０は、この形態では、ＳｉＣエピタキシャル層７の一部を利用して形成されている。ダイオード領域１０のｎ型不純物濃度は、ＳｉＣエピタキシャル層７のｎ型不純物濃度と等しい。ダイオード領域１０のｎ型不純物濃度は、ＳｉＣエピタキシャル層７のｎ型不純物濃度を超えていてもよい。この場合、ダイオード領域１０は、ＳｉＣエピタキシャル層７の表層部に対するｎ型不純物の導入によって形成される。
　外側領域９において第１主面３の表層部には、ｐ型不純物を含むガード領域１１が形成されている。ガード領域１１のｐ型不純物は、活性化されていなくてもよいし、活性化されていてもよい。
　ガード領域１１は、平面視においてダイオード領域１０に沿って延びる帯状に形成されている。ガード領域１１は、より具体的には、平面視においてダイオード領域１０を取り囲む環状（より具体的に無端状）に形成されている。これにより、ガード領域１１は、ガードリング領域として形成されている。
　アクティブ領域８（ダイオード領域１０）は、ガード領域１１によって画定されている。アクティブ領域８（ダイオード領域１０）の平面形状は、ガード領域１１の平面形状によって調整される。ガード領域１１は、平面視において多角環状や円環状に形成されていてもよい。
　ＳｉＣ半導体装置１は、第１主面３の上に形成された主面絶縁層１２を含む。主面絶縁層１２は、酸化シリコン層および窒化シリコン層を含む積層構造を有していてもよい。主面絶縁層１２は、酸化シリコン層または窒化シリコン層からなる単層構造を有していてもよい。主面絶縁層１２は、この形態では、酸化シリコン層からなる単層構造を有している。
　主面絶縁層１２は、ダイオード領域１０を露出させるコンタクト開口１３を含む。コンタクト開口１３は、ガード領域１１の内周縁も露出させている。コンタクト開口１３の平面形状は、任意である。コンタクト開口１３は、平面視において側面５Ａ～５Ｄに平行な４辺を有する四角形状に形成されていてもよい。
　主面絶縁層１２の周縁は、側面５Ａ～５Ｄから露出している。主面絶縁層１２の周縁は、この形態では、側面５Ａ～５Ｄに連なっている。主面絶縁層１２の周縁は、側面５Ａ～５Ｄから内方に間隔を空けて形成されていてもよい。この場合、主面絶縁層１２は、第１主面３において外側領域９に位置する部分を露出させる。
　主面絶縁層１２の厚さは、０．１μｍ以上１０μｍ以下であってもよい。主面絶縁層１２の厚さは、０．１μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上４μｍ以下、４μｍ以上６μｍ以下、６μｍ以上８μｍ以下、または、８μｍ以上１０μｍ以下であってもよい。主面絶縁層１２の厚さは、０．５μｍ以上５μｍ以下であることが好ましい。
　ＳｉＣ半導体装置１は、第１主面３の上に形成された第１主面電極１４を含む。第１主面電極１４は、コンタクト開口１３内においてダイオード領域１０およびガード領域１１に接続されている。第１主面電極１４は、コンタクト開口１３から主面絶縁層１２の上に引き出されている。第１主面電極１４の周縁は、側面５Ａ～５Ｄから内方に間隔を空けて主面絶縁層１２の上に形成されている。
　第１主面電極１４は、より具体的には、第１主面３側からこの順に積層されたショットキーバリア層１５（バリア層）および第１Ａｌ層１６を含む積層構造を有している。第１Ａｌ層１６は、比較的小さいヤング率（剛性率）を有するＡｌのクッション性を利用してＳｉＣチップ２に加えられる外力を第１主面３側から緩和する第１緩衝層として形成されている。
　ショットキーバリア層１５は、第１主面３および主面絶縁層１２に沿って膜状に形成されている。ショットキーバリア層１５は、ダイオード領域１０との間でショットキー接合を形成する。これにより、第１主面電極１４をアノードとし、ダイオード領域１０をカソードとするＳＢＤが形成されている。つまり、第１主面電極１４は、ＳＢＤのアノード電極である。
　ショットキーバリア層１５は、Ｔｉ層、Ｐｄ層、Ｃｒ層、Ｖ層、Ｍｏ層、Ｗ層、Ｐｔ層およびＮｉ層のうちの少なくとも１つを含んでいてもよい。ショットキーバリア層１５の厚さは、０．０１μｍ以上５μｍ以下であってもよい。ショットキーバリア層１５の厚さは、０．０１μｍ以上０．１μｍ以下、０．１μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上３μｍ以下、３μｍ以上４μｍ以下、または、４μｍ以上５μｍ以下であってもよい。
　第１Ａｌ層１６は、ショットキーバリア層１５の上に形成されている。第１Ａｌ層１６は、ショットキーバリア層１５に沿って膜状に形成されている。第１Ａｌ層１６は、ショットキーバリア層１５の主面の全域を被覆している。第１主面電極１４の周縁は、ショットキーバリア層１５および第１Ａｌ層１６によって形成されている。
　第１Ａｌ層１６は、純Ａｌ層（純度が９９％以上のＡｌからなるＡｌ層の事をいう。以下同じ。）、ＡｌＳｉ合金層、ＡｌＣｕ合金層およびＡｌＳｉＣｕ合金層のうちの少なくとも１つを含む。第１Ａｌ層１６は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層およびＡｌＳｉＣｕ合金層のうちの２つ以上が任意の順序で積層された積層構造を有していてもよい。
　第１Ａｌ層１６は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層またはＡｌＳｉＣｕ合金層からなる単層構造を有していてもよい。第１Ａｌ層１６は、ＡｌＳｉ合金層、ＡｌＣｕ合金層またはＡｌＳｉＣｕ合金層からなる単層構造を有していることが好ましい。
　第１Ａｌ層１６の厚さは、ショットキーバリア層１５の厚さを超えている。第１Ａｌ層１６の厚さは、０．０５μｍ以上１０μｍ以下であってもよい。第１Ａｌ層１６の厚さは、０．０５μｍ以上０．１μｍ以下、０．１μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上４μｍ以下、４μｍ以上６μｍ以下、６μｍ以上８μｍ以下、または、８μｍ以上１０μｍ以下であってもよい。第１Ａｌ層１６の厚さは、１μｍ以上８μｍ以下であることが好ましい。
　ＳｉＣ半導体装置１は、第１主面３の上において第１主面電極１４を被覆する絶縁層１７を含む。図１では、絶縁層１７がハッチングによって示されている。絶縁層１７は、より具体的には、主面絶縁層１２の上に形成されている。絶縁層１７の周縁は、側面５Ａ～５Ｄから内方に間隔を空けて形成されている。これにより、絶縁層１７は、主面絶縁層１２において外側領域９を被覆する部分を露出させている。
　絶縁層１７の周縁は、側面５Ａ～５Ｄとの間でダイシングストリートＤＳを区画している。ダイシングストリートＤＳによれば、ＳｉＣウエハからＳｉＣ半導体装置１を切り出す際に、絶縁層１７を物理的に切断せずに済む。これにより、ＳｉＣウエハからＳｉＣ半導体装置１を円滑に切り出すことができると同時に、絶縁層１７の剥離や劣化を抑制できる。その結果、絶縁層１７によってＳｉＣチップ２や第１主面電極１４等の保護対象物を適切に保護できる。
　ダイシングストリートＤＳの幅は、１μｍ以上２５μｍ以下であってもよい。ダイシングストリートＤＳの幅は、ダイシングストリートＤＳが延びる方向に直交する方向の幅である。ダイシングストリートＤＳの幅は、１μｍ以上５μｍ以下、５μｍ以上１０μｍ以下、１０μｍ以上１５μｍ以下、１５μｍ以上２０μｍ以下、または、２０μｍ以上２５μｍ以下であってもよい。
　絶縁層１７は、第１主面電極１４を露出させるパッド開口１８を有している。パッド開口１８は、この形態では、平面視においてコンタクト開口１３によって取り囲まれた領域内において第１主面電極１４を露出させている。パッド開口１８は、平面視においてコンタクト開口１３外の領域でコンタクト開口１３を取り囲んでいてもよい。パッド開口１８の平面形状は任意である。パッド開口１８は、平面視において側面５Ａ～５Ｄに平行な４辺を有する四角形状に形成されていてもよい。
　絶縁層１７は、この形態では、ＳｉＣチップ２側からこの順に積層されたパッシベーション層１９および樹脂層２０を含む積層構造を有している。
　パッシベーション層１９は、酸化シリコン層および窒化シリコン層のうちの少なくとも１つを含んでいてもよい。パッシベーション層１９は、酸化シリコン層および窒化シリコン層を含む積層構造を有していてもよい。パッシベーション層１９は、酸化シリコン層または窒化シリコン層からなる単層構造を有していてもよい。パッシベーション層１９は、主面絶縁層１２とは異なる絶縁材料を含むことが好ましい。パッシベーション層１９は、この形態では、窒化シリコン層からなる単層構造を有している。
　パッシベーション層１９は、主面絶縁層１２および第１主面電極１４に沿って膜状に形成されている。パッシベーション層１９は、第１主面電極１４の一部を露出させる第１開口２１を有している。第１開口２１の平面形状は任意である。第１開口２１は、平面視において側面５Ａ～５Ｄに平行な４辺を有する四角形状に形成されていてもよい。
　パッシベーション層１９の厚さは、０．１μｍ以上２０μｍ以下であってもよい。パッシベーション層１９の厚さは、０．１μｍ以上１μｍ以下、１μｍ以上５μｍ以下、５μｍ以上１０μｍ以下、１０μｍ以上１５μｍ以下、または、１５μｍ以上２０μｍ以下であってもよい。
　樹脂層２０は、パッシベーション層１９の主面に沿って膜状に形成されている。樹脂層２０は、感光性樹脂を含んでいてもよい。感光性樹脂は、ネガティブタイプまたはポジティブタイプであってもよい。樹脂層２０は、ポリイミド、ポリアミドおよびポリベンゾオキサゾールのうちの少なくとも１つを含んでいてもよい。樹脂層２０は、この形態では、ポリベンゾオキサゾールを含む。
　樹脂層２０の周縁は、この形態では、パッシベーション層１９の周縁を露出させている。絶縁層１７の周縁は、樹脂層２０の周縁およびパッシベーション層１９の周縁によって形成されている。樹脂層２０は、パッシベーション層１９の周縁を被覆していてもよい。
　樹脂層２０は、第１主面電極１４の一部を露出させる第２開口２２を有している。第２開口２２の平面形状は任意である。第２開口２２は、平面視において側面５Ａ～５Ｄに平行な４辺を有する四角形状に形成されていてもよい。第２開口２２は、パッシベーション層１９の第１開口２１に連通し、第１開口２１との間で１つのパッド開口１８を形成している。
　第２開口２２の内壁は、第１開口２１の内壁に面一に形成されていてもよい。第２開口２２の内壁は、第１開口２１の内壁に対して側面５Ａ～５Ｄ側に位置していてもよい。第２開口２２の内壁は、第１開口２１の内壁に対してＳｉＣチップ２の内方に位置していてもよい。つまり、樹脂層２０は、第１開口２１の内壁を被覆していてもよい。
　樹脂層２０の厚さは、１μｍ以上５０μｍ以下であってもよい。樹脂層２０の厚さは、１μｍ以上１０μｍ以下、１０μｍ以上２０μｍ以下、２０μｍ以上３０μｍ以下、３０μｍ以上４０μｍ以下、または、４０μｍ以上５０μｍ以下であってもよい。
　ＳｉＣ半導体装置１は、第１主面電極１４の上に形成されたパッド電極２３を含む。パッド電極２３は、第１主面電極１４に電気的に接続されている。パッド電極２３は、パッド開口１８内において第１主面電極１４の上に形成されている。パッド電極２３は、導線に外部接続される端子面２４を有している。
　端子面２４は、絶縁層１７（樹脂層２０）の主面に対して第１主面電極１４側に位置している。端子面２４は、絶縁層１７（樹脂層２０）の主面よりも上方に突出していてもよい。端子面２４は、絶縁層１７（樹脂層２０）の主面を被覆するオーバラップ部を有していてもよい。
　パッド電極２３は、第１主面電極１４とは異なる金属材料を含む。パッド電極２３は、この形態では、第１主面電極１４側からこの順に積層されたＮｉ層２５、Ｐｄ層２６およびＡｕ層２７を含む積層構造を有している。Ｎｉ、ＰｄおよびＡｕは、Ａｌのヤング率（剛性率）を超えるヤング率（剛性率）をそれぞれ有している。Ｎｉ層２５、Ｐｄ層２６およびＡｕ層２７は、めっき法によって形成されためっき層であってもよい。
　パッド電極２３は、Ｎｉ層２５、Ｐｄ層２６およびＡｕ層２７のうちの少なくとも１つを含んでいればよい。パッド電極２３は、Ｎｉ層２５、Ｐｄ層２６およびＡｕ層２７のうちの少なくとも２つを任意の順序で積層した積層構造を有していてもよい。パッド電極２３は、Ｎｉ層２５、Ｐｄ層２６またはＡｕ層２７からなる単層構造を有していてもよい。
　パッド電極２３は、Ａｕ層２７によって形成された端子面２４を有していることが好ましい。パッド電極２３は、少なくとも第１主面電極１４側からこの順に積層されたＮｉ層２５およびＡｕ層２７を含む積層構造を有していることが好ましい。
　Ｎｉ層２５の厚さは、０．１μｍ以上１０μｍ以下であってもよい。Ｎｉ層２５の厚さは、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上４μｍ以下、４μｍ以上６μｍ以下、６μｍ以上８μｍ以下、または、８μｍ以上１０μｍ以下であってもよい。
　Ｐｄ層２６の厚さは、０．１μｍ以上１０μｍ以下であってもよい。Ｐｄ層２６の厚さは、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上４μｍ以下、４μｍ以上６μｍ以下、６μｍ以上８μｍ以下、または、８μｍ以上１０μｍ以下であってもよい。
　Ａｕ層２７の厚さは、０．０１μｍ以上３μｍ以下であってもよい。Ａｕ層２７の厚さは、０．０１μｍ以上０．０５μｍ以下、０．０５μｍ以上０．１μｍ以下、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、または、２μｍ以上３μｍ以下であってもよい。Ａｕ層２７の厚さは、Ｎｉ層２５の厚さ未満であることが好ましい。Ａｕ層２７の厚さは、Ｐｄ層２６の厚さ未満であることが好ましい。
　図２および図３を参照して、ＳｉＣ半導体装置１は、第２主面４の上に形成された第２主面電極３１を含む。第２主面電極３１は、ＳＢＤのカソード電極として形成されている。第２主面電極３１は、この形態では、第２主面４の全域を被覆している。
　第２主面電極３１は、側面５Ａ～５Ｄから内方に間隔を空けて形成され、第２主面４の周縁部を露出させていてもよい。この場合、ＳｉＣウエハからＳｉＣ半導体装置１を切り出す際に第２主面電極３１を物理的に切断せずに済む。これにより、ＳｉＣウエハからＳｉＣ半導体装置１を円滑に切り出すことができると同時に、第２主面電極３１の剥離や劣化を抑制できる。その結果、第２主面電極３１を第２主面４に適切に接続させることができる。
　このような第２主面電極３１は、一例として、製造工程時において、レジストマスクを介するエッチング法によって第２主面電極３１の不要な部分を除去することによって得ることができる。また、第２主面電極３１は、他の例として、製造工程時において、レジストマスクを用いたリフトオフ法によって第２主面４を部分的に被覆する第２主面電極３１を形成することによって得ることができる。
　第２主面電極３１は、第２主面４を被覆する第２Ａｌ層３２を含む。第２Ａｌ層３２は、ＳｉＣチップ２を挟んで第１主面電極１４の第１Ａｌ層１６に対向している。第２Ａｌ層３２は、比較的小さいヤング率（剛性率）を有するＡｌのクッション性を利用してＳｉＣチップ２に加えられる外力を第２主面４側から緩和する第２緩衝層として形成されている。
　第２Ａｌ層３２は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層およびＡｌＳｉＣｕ合金層のうちの少なくとも１つを含む。第２Ａｌ層３２は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層およびＡｌＳｉＣｕ合金層のうちの２つ以上が任意の順序で積層された積層構造を有していてもよい。第２Ａｌ層３２は、スパッタ法および／または蒸着法によって形成されていてもよい。
　第２Ａｌ層３２は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層またはＡｌＳｉＣｕ合金層からなる単層構造を有していてもよい。第２Ａｌ層３２のＡｌ系金属材料は、第１Ａｌ層１６のＡｌ系金属材料とは異なっていてもよい。第２Ａｌ層３２は、純Ａｌ層からなる単層構造を有していることが好ましい。
　第２Ａｌ層３２は、第１Ａｌ層１６の厚さ未満の厚さを有していてもよい。第２Ａｌ層３２の厚さは、０．０１μｍ以上５μｍ以下であってもよい。第２Ａｌ層３２の厚さは、０．０１μｍ以上０．１μｍ以下、０．１μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上３μｍ以下、３μｍ以上４μｍ以下、または、４μｍ以上５μｍ以下であってもよい。
　第２主面電極３１は、第２Ａｌ層３２に加えて、第２Ａｌ層３２とは異なる金属材料からなる１つまたは複数の電極層をさらに含む。第２主面電極３１は、この形態では、複数の電極層の一例として第２主面４側からこの順に積層されたＴｉ層３３、Ｎｉ層３４、Ｐｄ層３５、Ａｕ層３６およびＡｇ層３７を含む。
　Ｔｉ層３３は、第２主面４との間でオーミック接触を形成するオーミック電極である。第２Ａｌ層３２は、Ｔｉ層３３、Ｎｉ層３４、Ｐｄ層３５、Ａｕ層３６およびＡｇ層３７を挟んで第２主面４を被覆している。
　Ｔｉ、Ｎｉ、Ｐｄ、ＡｕおよびＡｇは、Ａｌのヤング率（剛性率）を超えるヤング率（剛性率）をそれぞれ有している。Ｔｉ層３３、Ｎｉ層３４、Ｐｄ層３５、Ａｕ層３６およびＡｇ層３７は、スパッタ法、蒸着法および／またはめっき法によって形成されていてもよい。
　第２主面電極３１は、１つまたは複数の電極層として、Ｔｉ層３３、Ｎｉ層３４、Ｐｄ層３５、Ａｕ層３６およびＡｇ層３７のうちの少なくとも１つを含んでいればよい。第２Ａｌ層３２は、少なくともＴｉ層３３を挟んで第２主面４を被覆していることが好ましい。
　第２主面電極３１がＮｉ層３４、Ｐｄ層３５およびＡｕ層３６のうちの少なくとも１つを含む場合、Ｎｉ層３４、Ｐｄ層３５およびＡｕ層３６のうちの少なくとも１つは、パッド電極２３のＮｉ層２５、Ｐｄ層２６およびＡｕ層２７と同時に形成されためっき層であってもよい。
　Ｔｉ層３３の厚さは、０．０１μｍ以上３μｍ以下であってもよい。Ｔｉ層３３の厚さは、０．０１μｍ以上０．０５μｍ以下、０．０５μｍ以上０．１μｍ以下、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、または、２μｍ以上３μｍ以下であってもよい。
　Ｎｉ層３４の厚さは、０．１μｍ以上１０μｍ以下であってもよい。Ｎｉ層３４の厚さは、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上４μｍ以下、４μｍ以上６μｍ以下、６μｍ以上８μｍ以下、または、８μｍ以上１０μｍ以下であってもよい。Ｎｉ層３４の厚さは、Ｔｉ層３３の厚さを超えていることが好ましい。
　Ｐｄ層３５の厚さは、０．１μｍ以上１０μｍ以下であってもよい。Ｐｄ層３５の厚さは、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上４μｍ以下、４μｍ以上６μｍ以下、６μｍ以上８μｍ以下、または、８μｍ以上１０μｍ以下であってもよい。Ｐｄ層３５の厚さは、Ｔｉ層３３の厚さを超えていることが好ましい。
　Ａｕ層３６の厚さは、０．０１μｍ以上３μｍ以下であってもよい。Ａｕ層３６の厚さは、０．０１μｍ以上０．０５μｍ以下、０．０５μｍ以上０．１μｍ以下、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、または、２μｍ以上３μｍ以下であってもよい。Ａｕ層３６の厚さは、Ｎｉ層３４の厚さ未満であることが好ましい。Ａｕ層３６の厚さは、Ｐｄ層３５の厚さ未満であることが好ましい。
　Ａｇ層３７の厚さは、０．０１μｍ以上３μｍ以下であってもよい。Ａｇ層３７の厚さは、０．０１μｍ以上０．０５μｍ以下、０．０５μｍ以上０．１μｍ以下、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、または、２μｍ以上３μｍ以下であってもよい。Ａｇ層３７の厚さは、Ｎｉ層３４の厚さ未満であることが好ましい。Ａｇ層３７の厚さは、Ｐｄ層３５の厚さ未満であることが好ましい。
　第２主面電極３１は、図４Ａ～図４Ｉに示される構造を有していてもよい。
　図４Ａは、第２形態例に係る第２主面電極３１を図解的に示す断面図である。以下では、図１～図３において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図４Ａを参照して、第２主面電極３１は、この形態では、第２Ａｌ層３２、Ｔｉ層３３、Ｎｉ層３４、Ｐｄ層３５およびＡｕ層３６を含む積層構造を有している。Ｔｉ層３３、Ｎｉ層３４、Ｐｄ層３５およびＡｕ層３６は、第２主面４側からこの順に積層されている。第２Ａｌ層３２は、Ｔｉ層３３、Ｎｉ層３４、Ｐｄ層３５およびＡｕ層３６を挟んで第２主面４を被覆している。
　図４Ｂは、第３形態例に係る第２主面電極３１を図解的に示す断面図である。以下では、図１～図３において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図４Ｂを参照して、第２主面電極３１は、この形態では、第２Ａｌ層３２、Ｔｉ層３３、Ｎｉ層３４、Ａｕ層３６およびＡｇ層３７を含む積層構造を有している。Ｔｉ層３３、Ｎｉ層３４、Ａｕ層３６およびＡｇ層３７は、第２主面４側からこの順に積層されている。第２Ａｌ層３２は、Ｔｉ層３３、Ｎｉ層３４、Ａｕ層３６およびＡｇ層３７を挟んで第２主面４を被覆している。
　図４Ｃは、第４形態例に係る第２主面電極３１を図解的に示す断面図である。以下では、図１～図３において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図４Ｃを参照して、第２主面電極３１は、この形態では、第２Ａｌ層３２、Ｔｉ層３３、Ｎｉ層３４およびＡｕ層３６を含む積層構造を有している。Ｔｉ層３３、Ｎｉ層３４およびＡｕ層３６は、第２主面４側からこの順に積層されている。第２Ａｌ層３２は、Ｔｉ層３３、Ｎｉ層３４およびＡｕ層３６を挟んで第２主面４を被覆している。
　図４Ｄは、第５形態例に係る第２主面電極３１を図解的に示す断面図である。以下では、図１～図３において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図４Ｄを参照して、第２主面電極３１は、この形態では、第２Ａｌ層３２およびＴｉ層３３を含む積層構造を有している。Ｔｉ層３３は、第２主面４に接続されている。第２Ａｌ層３２は、Ｔｉ層３３を挟んで第２主面４を被覆している。
　図４Ｅは、第６形態例に係る第２主面電極３１を図解的に示す断面図である。以下では、図１～図３において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図４Ｅを参照して、第２主面電極３１は、この形態では、第２Ａｌ層３２、Ｔｉ層３３、Ｎｉ層３４およびＡｕ層３６を含む。Ｔｉ層３３、Ｎｉ層３４およびＡｕ層３６は、第２主面４側からこの順に積層されている。第２Ａｌ層３２は、Ｔｉ層３３およびＮｉ層３４の間に介在し、Ｔｉ層３３を挟んで第２主面４を被覆している。
　この場合、パッド電極２３は、第１主面電極１４側からこの順に積層されたＮｉ層２５およびＡｕ層２７からなる２層構造を有していることが好ましい。第２主面電極３１のＮｉ層３４およびＡｕ層３６は、めっき法によって、パッド電極２３のＮｉ層２５およびＡｕ層２７と同時に形成されることができる。
　図４Ｆは、第７形態例に係る第２主面電極３１を図解的に示す断面図である。以下では、図１～図３において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図４Ｆを参照して、第２主面電極３１は、この形態では、第２Ａｌ層３２、Ｔｉ層３３、Ｎｉ層３４、Ａｕ層３６およびＡｇ層３７を含む。Ｔｉ層３３、Ｎｉ層３４、Ａｕ層３６およびＡｇ層３７は、第２主面４側からこの順に積層されている。第２Ａｌ層３２は、Ｔｉ層３３およびＮｉ層３４の間に介在し、Ｔｉ層３３を挟んで第２主面４を被覆している。
　この場合、パッド電極２３は、第１主面電極１４側からこの順に積層されたＮｉ層２５およびＡｕ層２７からなる２層構造を有していることが好ましい。第２主面電極３１のＮｉ層３４およびＡｕ層３６は、めっき法によって、パッド電極２３のＮｉ層２５およびＡｕ層２７と同時に形成されることができる。
　図４Ｇは、第８形態例に係る第２主面電極３１を図解的に示す断面図である。以下では、図１～図３において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図４Ｇを参照して、第２主面電極３１は、この形態では、第２Ａｌ層３２、Ｔｉ層３３、Ｎｉ層３４、Ｐｄ層３５、Ａｕ層３６およびＡｇ層３７を含む。Ｔｉ層３３、Ｎｉ層３４、Ａｕ層３６およびＡｇ層３７は、第２主面４側からこの順に積層されている。第２Ａｌ層３２は、Ｔｉ層３３およびＮｉ層３４の間に介在し、Ｔｉ層３３を挟んで第２主面４を被覆している。
　この場合、パッド電極２３は、第１主面電極１４側からこの順に積層されたＮｉ層２５、Ｐｄ層２６およびＡｕ層２７からなる３層構造を有していることが好ましい。第２主面電極３１のＮｉ層３４、Ｐｄ層３５およびＡｕ層３６は、めっき法によって、パッド電極２３のＮｉ層２５、Ｐｄ層２６およびＡｕ層２７と同時に形成されることができる。
　図４Ｈは、第９形態例に係る第２主面電極３１を図解的に示す断面図である。以下では、図１～図３において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図４Ｈを参照して、第２主面電極３１は、この形態では、第２Ａｌ層３２、Ｔｉ層３３、Ｎｉ層３４、Ｐｄ層３５およびＡｕ層３６を含む。Ｔｉ層３３、Ｎｉ層３４、Ｐｄ層３５およびＡｕ層３６は、第２主面４側からこの順に積層されている。第２Ａｌ層３２は、Ｔｉ層３３およびＮｉ層３４の間に介在し、Ｔｉ層３３を挟んで第２主面４を被覆している。
　この場合、パッド電極２３は、第１主面電極１４側からこの順に積層されたＮｉ層２５、Ｐｄ層２６およびＡｕ層２７からなる３層構造を有していることが好ましい。第２主面電極３１のＮｉ層３４、Ｐｄ層３５およびＡｕ層３６は、めっき法によって、パッド電極２３のＮｉ層２５、Ｐｄ層２６およびＡｕ層２７と同時に形成されることができる。
　図４Ｉは、第１０形態例に係る第２主面電極３１を図解的に示す断面図である。以下では、図１～図３において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図４Ｉを参照して、第２主面電極３１は、この形態では、第２Ａｌ層３２およびシリサイド層３８を含む。シリサイド層３８は、第２主面４に形成されている。シリサイド層３８は、第２主面４から露出するＳｉＣが金属材料によってシリサイド化された層である。シリサイド層３８は、ＦｅＳｉ２層、ＮｉＳｉ層、ＮｉＳｉ２層、ＣｏＳｉ２層、ＣｒＳｉ２層、ＷＳｉ２層、ＭｏＳｉ２層、ＭｎＳｉ２層、ＮｂＳｉ２層、ＴｉＳｉ２層およびＶＳｉ２層のうちの少なくとも１つを含んでいてもよい。
　第２Ａｌ層３２は、シリサイド層３８を挟んで第２主面４を被覆している。第２主面電極３１は、第２Ａｌ層３２およびシリサイド層３８の他、Ｔｉ層３３、Ｎｉ層３４、Ｐｄ層３５、Ａｕ層３６およびＡｇ層３７のうちの少なくとも１つを含んでいてもよい。第２Ａｌ層３２、Ｔｉ層３３、Ｎｉ層３４、Ｐｄ層３５、Ａｕ層３６およびＡｇ層３７の積層順序は任意である。シリサイド層３８を被覆する構造として、第１～第１０形態例のいずれか１つの積層構造が採用されてもよい。
　図５は、図１に示すＳｉＣ半導体装置１が組み込まれた半導体パッケージ４１を示す図である。図５では、半導体パッケージ４１の内部構造が、パッケージ本体４２を透過して示されている。
　図５を参照して、半導体パッケージ４１は、この形態では、２端子型のＴＯ－２２０である。半導体パッケージ４１は、パッケージ本体４２、金属プレート４３、第１端子４４、第２端子４５、ＳｉＣ半導体装置１、導電接合材４６および導線４７を含む。
　パッケージ本体４２は、モールド樹脂からなる。パッケージ本体４２は、モールド樹脂の一例としてのエポキシ樹脂を含んでいてもよい。パッケージ本体４２は、直方体形状に形成されている。パッケージ本体４２は、一方側の第１面４８および他方側の第２面４９、ならびに、第１面４８および第２面４９を接続する４つの側面５０Ａ，５０Ｂ，５０Ｃ，５０Ｄを含む。
　４つの側面５０Ａ～５０Ｄは、より具体的には、第１側面５０Ａ、第２側面５０Ｂ、第３側面５０Ｃおよび第４側面５０Ｄを含む。第１側面５０Ａおよび第２側面５０Ｂは、互いに対向している。第３側面５０Ｃおよび第４側面５０Ｄは、互いに対向している。
　金属プレート４３は、Ｆｅ、Ａｕ、Ａｇ、ＣｕおよびＡｌの少なくとも１つを含んでいてもよい。金属プレート４３は、Ｎｉめっき膜、Ａｕめっき膜、Ａｇめっき膜およびＣｕめっき膜のうちの少なくとも１つが形成された外面を有していてもよい。金属プレート４３の平面形状は任意である。金属プレート４３は、この形態では、平面視において四角形状（長方形状）に形成されている。
　金属プレート４３は、パッケージ本体４２内に位置するパッド部５１、および、パッケージ本体４２外に位置するヒートシンク部５２を一体的に含む。ヒートシンク部５２は、パッド部５１から第２側面５０Ｂを横切ってパッケージ本体４２外に引き出されている。ヒートシンク部５２は、貫通孔５２ａを含む。貫通孔５２ａは、円形状に形成されている。
　金属プレート４３は、この形態では、第２面４９から露出するようにパッケージ本体４２内に配置されている。金属プレート４３は、第２面４９から露出しないようにパッケージ本体４２内に配置されていてもよい。
　第１端子４４は、Ｆｅ、Ａｕ、Ａｇ、ＣｕおよびＡｌのうちの少なくとも１つを含んでいてもよい。第１端子４４は、Ｎｉめっき膜、Ａｕめっき膜、Ａｇめっき膜およびＣｕめっき膜のうちの少なくとも１つが形成された外面を有していてもよい。第１端子４４は、パッケージ本体４２内から第１側面５０Ａを横切ってパッケージ本体４２外に引き出されている。第１端子４４は、平面視において第４側面５０Ｄ側の領域に配置されている。第１端子４４は、金属プレート４３の板面に対して第１面４８側の領域に配置されている。
　第１端子４４は、第１内端部５３、第１外端部５４および第１帯状部５５を含む。第１内端部５３は、パッケージ本体４２内において金属プレート４３に接続されている。第１外端部５４は、パッケージ本体４２外に配置されている。第１帯状部５５は、第１内端部５３および第１外端部５４の間を第１側面５０Ａに直交する方向に延びている。
　第２端子４５は、Ｆｅ、Ａｕ、Ａｇ、ＣｕおよびＡｌのうちの少なくとも１つを含んでいてもよい。第２端子４５は、Ｎｉめっき膜、Ａｕめっき膜、Ａｇめっき膜およびＣｕめっき膜のうちの少なくとも１つを含んでいてもよい。第２端子４５は、パッケージ本体４２内から第１側面５０Ａを横切ってパッケージ本体４２外に引き出されている。
　第２端子４５は、平面視において第１端子４４から間隔を空けて第３側面５０Ｃ側の領域に配置されている。第２端子４５は、金属プレート４３の板面に対して第１面４８側の領域に配置されている。
　第２端子４５は、第２内端部５６、第２外端部５７および第２帯状部５８を含む。第２内端部５６は、金属プレート４３から間隔を空けてパッケージ本体４２内に配置されている。第２外端部５７は、パッケージ本体４２外に配置されている。第２帯状部５８は、第２内端部５６および第２外端部５７の間を第１側面５０Ａに直交する方向に延びている。
　ＳｉＣ半導体装置１は、パッケージ本体４２内において金属プレート４３のパッド部５１の上に配置されている。導電接合材４６は、ＳｉＣ半導体装置１およびパッド部５１の間に介在し、ＳｉＣ半導体装置１の第２主面電極３１をパッド部５１に接合させている。これにより、ＳｉＣ半導体装置１は、金属プレート４３を介して第１端子４４に電気的に接続されている。
　導電接合材４６は、金属ペーストまたは半田であってもよい。金属ペーストは、Ａｕ、ＡｇおよびＣｕのうちの少なくとも１つを含んでいてもよい。導電接合材４６は、半田からなることが好ましい。半田は、鉛フリー半田であってもよい。半田は、ＳｎＡｇＣｕ、ＳｎＺｎＢｉ、ＳｎＣｕ、ＳｎＣｕＮｉおよびＳｎＳｂＮｉのうちの少なくとも１つを含んでいてもよい。
　導線４７は、金属ワイヤ（ボンディングワイヤ）または金属クリップからなる。金属ワイヤは、Ａｌワイヤ、Ａｕワイヤ、Ｃｕワイヤまたは半田ワイヤであってもよい。半田ワイヤは、鉛フリー半田ワイヤであってもよい。半田ワイヤは、ＳｎＡｇＣｕ、ＳｎＺｎＢｉ、ＳｎＣｕ、ＳｎＣｕＮｉおよびＳｎＳｂＮｉのうちの少なくとも１つを含んでいてもよい。金属クリップは、Ａｌクリップ、ＡｕクリップまたはＣｕクリップであってもよい。導線４７は、この形態では、半田ワイヤからなる。
　導線４７は、パッケージ本体４２内において第２端子４５の第２内端部５６およびＳｉＣ半導体装置１のパッド電極２３に接続されている。これにより、ＳｉＣ半導体装置１は、第２端子４５に電気的に接続されている。
　図６では、１つの導線４７が第２内端部５６およびパッド電極２３に接続されている例が示されているが、導線４７の個数は任意である。２つ以上の導線４７が第２内端部５６およびパッド電極２３に接続されていてもよい。
　半導体パッケージ４１は、ＴＯ－２２０以外の形態も採り得る。半導体パッケージ４１は、ＳＯＰ（Small Outline Package）、ＱＦＮ（Quad For Non Lead Package）、ＤＦＰ（Dual Flat Package）、ＤＩＰ（Dual Inline Package）、ＱＦＰ（Quad Flat Package）、ＳＩＰ（Single Inline Package）もしくはＳＯＪ（Small Outline J-leaded Package）、または、これらに類する種々の形態を有していてもよい。
　以上、ＳｉＣ半導体装置１によれば、第１Ａｌ層１６が第１主面３側で外力を緩和する第１緩衝層として形成され、第２Ａｌ層３２が第２主面４側で外力を緩和する第２緩衝層として形成されている。これにより、第１主面３から第２主面４に向かう方向の外力、および、第２主面４から第１主面３に向かう方向の外力を緩和できる。
　一例として、ＳｉＣ半導体装置１を金属プレート４３のパッド部５１に実装する際にＳｉＣチップ２に加えられる外力を第１Ａｌ層１６および第２Ａｌ層３２によって緩和できる。また、ＳｉＣ半導体装置１のパッド電極２３に導線４７を接合する際にＳｉＣチップ２に加えられる外力を第１Ａｌ層１６および第２Ａｌ層３２によって緩和できる。その結果、ＳｉＣチップ２のクラックを抑制できる。
　また、ＳｉＣ半導体装置１は、導線４７に外部接合されるパッド電極２３を含む。パッド電極２３は、Ｎｉ層２５、Ｐｄ層２６およびＡｕ層２７のうちの少なくとも１つを含む。これにより、導線４７をパッド電極２３に適切に接続されることができる。
　一方、Ｎｉ、ＰｄおよびＡｕは、Ａｌのヤング率（剛性率）を超えるヤング率（剛性率）をそれぞれ有している。したがって、パッド電極２３を備えた構造では、導線４７の接合時に加えられる外力を適切に緩和できない。
　そこで、ＳｉＣ半導体装置１では、ＳｉＣチップ２およびパッド電極２３の間にＡｌを含む第１Ａｌ層１６を介在させている。第１Ａｌ層１６によれば、比較的小さいヤング率（剛性率）を有するＡｌのクッション性を利用してＳｉＣチップ２に加えられる外力を第１主面３側から緩和できる。よって、導線４７をパッド電極２３に適切に接合させることができると同時に、ＳｉＣチップ２のクラックを抑制できる。
　また、ＳｉＣ半導体装置１は、第２Ａｌ層３２に加えて、第２Ａｌ層３２とは異なる金属材料からなる１つまたは複数の電極層を有する第２主面電極３１を含む。１つまたは複数の電極層は、Ｔｉ層３３、Ｎｉ層３４、Ｐｄ層３５、Ａｕ層３６およびＡｇ層３７のうちの少なくとも１つを含む。これにより、第２主面電極３１に対する導電接合材４６の密着力を適切に高めることができる。その結果、ＳｉＣ半導体装置１を金属プレート４３のパッド部５１に適切に実装できる。
　一方、Ｔｉ、Ｎｉ、Ｐｄ、ＡｕおよびＡｇは、Ａｌのヤング率（剛性率）を超えるヤング率（剛性率）をそれぞれ有している。したがって、第２主面電極３１がＴｉ層３３、Ｎｉ層３４、Ｐｄ層３５、Ａｕ層３６およびＡｇ層３７のうちの少なくとも１つを含む構造では、ＳｉＣ半導体装置１の実装時や導線４７の接合時に加えられる外力を適切に緩和できない。
　そこで、ＳｉＣ半導体装置１では、Ｔｉ層３３、Ｎｉ層３４、Ｐｄ層３５、Ａｕ層３６およびＡｇ層３７のうちの少なくとも１つに加えて、第２Ａｌ層３２を含む第２主面電極３１を形成している。第２Ａｌ層３２によれば、比較的小さいヤング率（剛性率）を有するＡｌのクッション性を利用してＳｉＣチップ２に加えられる外力を第２主面４側から緩和できる。よって、ＳｉＣ半導体装置１をパッド部５１に適切に実装できると同時に、ＳｉＣチップ２のクラックを抑制できる。
　図６は、本発明の第２実施形態に係るＳｉＣ半導体装置６１の斜視図であって、第１形態例に係る第２主面電極２００が組み込まれた形態を示している。図７は、図６に示すＳｉＣ半導体装置６１の平面図である。図８は、第１主面電極１５０の上の構造を取り除いた平面図である。
　図９は、図８に示す領域IXの内部構造を示す拡大平面図である。図１０は、図９に示すX-X線に沿う断面図である。図１１は、図９に示すXI-XI線に沿う断面図である。図１２は、図１０に示す領域XIIの拡大図である。
　図１３は、図７に示すXIII-XIII線に沿う断面図である。図１４は、ゲートパッド電極１９１を示す断面図である。図１５は、ソースパッド電極１９２を示す断面図である。図１６は、第２主面電極２００を図解的に示す断面図である。図１４および図１５は、ゲートパッド電極１９１およびソースパッド電極１９２の概略構造を示す断面図であり、特定箇所の断面を示していない。
　図６～図１３を参照して、ＳｉＣ半導体装置６１は、ＳｉＣチップ６２を含む。ＳｉＣチップ６２は、六方晶からなるＳｉＣ単結晶を含む。六方晶からなるＳｉＣ単結晶は、原子配列の周期に応じて、２Ｈ（Hexagonal）－ＳｉＣ単結晶、４Ｈ－ＳｉＣ単結晶、６Ｈ－ＳｉＣ単結晶等を含む複数種のポリタイプを有している。ＳｉＣチップ６２は、この形態では、４Ｈ－ＳｉＣ単結晶からなるが、他のポリタイプを除外するものではない。
　ＳｉＣチップ６２は、一方側の第１主面６３、他方側の第２主面６４、ならびに、第１主面６３および第２主面６４を接続する側面６５Ａ，６５Ｂ，６５Ｃ，６５Ｄを有している。第１主面６３および第２主面６４は、それらの法線方向Ｚから見た平面視（以下、単に「平面視」という。）において四角形状（この形態では長方形状）に形成されている。
　ＳｉＣチップ６２の厚さは、４０μｍ以上３００μｍ以下であってもよい。ＳｉＣチップ６２の厚さは、４０μｍ以上１００μｍ以下、１００μｍ以上１５０μｍ以下、１５０μｍ以上２００μｍ以下、２００μｍ以上２５０μｍ以下、または、２５０μｍ以上３００μｍ以下であってもよい。ＳｉＣチップ６２の厚さは、６０μｍ以上１５０μｍ以下であることが好ましい。
　第１主面６３および第２主面６４は、この形態では、ＳｉＣ単結晶のｃ面に面している。第１主面６３は、ＳｉＣ単結晶のシリコン面（（０００１）面）に面している。第１主面６３は、非実装面である。第２主面６４は、ＳｉＣ単結晶のカーボン面（（０００－１）面）に面している。第２主面６４は、実装面である。第２主面６４は、研削痕およびアニール痕のいずれか一方または双方を有する粗面であってもよい。アニール痕は、レーザ照射痕である。第２主面６４は、アニール痕を有するオーミック面であってもよい。
　第１主面６３および第２主面６４は、ＳｉＣ単結晶のｃ面に対してａ軸方向（［１１－２０］方向）に０°以上１０°以下の角度で傾斜したオフ角を有している。法線方向Ｚは、ＳｉＣ単結晶のｃ軸（［０００１］方向）に対してオフ角分だけ傾斜している。
　オフ角は、０°以上６°以下であってもよい。オフ角は、０°以上２°以下、２°以上４°以下、または、４°以上６°以下であってもよい。オフ角は、０°を超えて４．５°以下であることが好ましい。オフ角は、３°以上４．５°以下であってもよい。この場合、オフ角は、３°以上３．５°以下、または、３．５°以上４°以下であることが好ましい。オフ角は、１．５°以上３°以下であってもよい。この場合、オフ角は、１．５°以上２°以下、または、２°以上２．５°以下であることが好ましい。
　側面６５Ａ～６５Ｄは、第１側面６５Ａ、第２側面６５Ｂ、第３側面６５Ｃおよび第４側面６５Ｄを含む。第１側面６５Ａおよび第２側面６５Ｂは、第１方向Ｘに沿って延び、第１方向Ｘに交差する第２方向Ｙに対向している。第１側面６５Ａおよび第２側面６５Ｂは、平面視においてＳｉＣチップ６２の短辺を形成している。第３側面６５Ｃおよび第４側面６５Ｄは、第２方向Ｙに沿って延び、第１方向Ｘに対向している。第３側面６５Ｃおよび第４側面６５Ｄは、平面視においてＳｉＣチップ６２の長辺を形成している。第２方向Ｙは、より具体的には、第１方向Ｘに直交している。
　第１方向Ｘは、この形態では、ＳｉＣ単結晶のｍ軸方向（［１－１００］方向）である。第２方向Ｙは、ＳｉＣ単結晶のａ軸方向（［１１－２０］方向）である。つまり、第１側面６５Ａおよび第２側面６５Ｂは、ＳｉＣ単結晶のａ面によって形成され、ＳｉＣ単結晶のａ軸方向に対向している。また、第３側面６５Ｃおよび第４側面６５Ｄは、ＳｉＣ単結晶のｍ面によって形成され、ＳｉＣ単結晶のｍ軸方向に対向している。
　第１側面６５Ａおよび第２側面６５Ｂは、法線方向Ｚを基準にしたとき、法線方向Ｚに対してＳｉＣ単結晶のｃ軸方向（［０００１］方向）に向けて傾斜した傾斜面を形成していてもよい。第１側面６５Ａおよび第２側面６５Ｂは、法線方向Ｚを０°としたとき、法線方向Ｚに対してオフ角に応じた角度で傾斜していてもよい。オフ角に応じた角度は、オフ角と等しくてもよいし、０°を超えてオフ角未満の角度であってもよい。
　第３側面６５Ｃおよび第４側面６５Ｄは、法線方向Ｚに沿って平面的に延びている。第３側面６５Ｃおよび第４側面６５Ｄは、より具体的には、第１主面６３および第２主面６４に対して略垂直に形成されている。
　側面６５Ａ～６５Ｄは、劈開面または研削面からなっていてもよい。側面６５Ａ～６５Ｄの長さは、０．１ｍｍ以上１０ｍｍ以下であってもよい。側面６５Ａ～６５Ｄの長さは、０．５ｍｍ以上２．５ｍｍ以下であることが好ましい。
　ＳｉＣチップ６２は、この形態では、ｎ＋型のＳｉＣ半導体基板６６およびｎ型のＳｉＣエピタキシャル層６７を含む積層構造を有している。ＳｉＣ半導体基板６６は、ドレイン領域６８として形成されている。ＳｉＣエピタキシャル層６７は、ドリフト領域６９として形成されている。
　ＳｉＣ半導体基板６６によって、ＳｉＣチップ６２の第２主面６４が形成されている。ＳｉＣエピタキシャル層６７によって、ＳｉＣチップ６２の第１主面６３が形成されている。ＳｉＣ半導体基板６６およびＳｉＣエピタキシャル層６７によって、ＳｉＣチップ６２の側面６５Ａ～６５Ｄが形成されている。
　ＳｉＣ半導体基板６６の厚さは、４０μｍ以上２５０μｍ以下であってもよい。ＳｉＣ半導体基板６６の厚さは、４０μｍ以上１００μｍ以下、１００μｍ以上１５０μｍ以下、１５０μｍ以上２００μｍ以下、または、２００μｍ以上２５０μｍ以下であってもよい。ＳｉＣ半導体基板６６の厚さは、４０μｍ以上１５０μｍ以下であることが好ましい。ＳｉＣ半導体基板６６を薄化することにより、ＳｉＣ半導体基板６６の抵抗値を低減できる。
　ＳｉＣエピタキシャル層６７の厚さは、１μｍ以上５０μｍ以下であってもよい。ＳｉＣエピタキシャル層６７の厚さは、１μｍ以上５μｍ以下、５μｍ以上１０μｍ以下、１０μｍ以上１５μｍ以下、１５μｍ以上２０μｍ以下、２０μｍ以上３０μｍ以下、３０μｍ以上４０μｍ以下、または、４０μｍ以上５０μｍ以下であってもよい。ＳｉＣエピタキシャル層６７の厚さは、５μｍ以上１５μｍ以下であることが好ましい。
　ＳｉＣエピタキシャル層６７のｎ型不純物濃度は、ＳｉＣ半導体基板６６のｎ型不純物濃度未満である。ＳｉＣ半導体基板６６のｎ型不純物濃度は、１．０×１０１８ｃｍ－３以上１．０×１０２１ｃｍ－３以下であってもよい。ＳｉＣエピタキシャル層６７のｎ型不純物濃度は、１．０×１０１５ｃｍ－３以上１．０×１０１８ｃｍ－３以下であってもよい。
　ＳｉＣエピタキシャル層６７は、この形態では、法線方向Ｚに沿って異なるｎ型不純物濃度を有する複数の領域を有している。ＳｉＣエピタキシャル層６７は、より具体的には、ｎ型不純物濃度が比較的高い高濃度領域７０、および、高濃度領域７０に対してｎ型不純物濃度が低い低濃度領域７１を含む。
　高濃度領域７０は、第１主面６３側の領域に形成されている。低濃度領域７１は、高濃度領域７０に対して第２主面６４側の領域に形成されている。高濃度領域７０の厚さは、低濃度領域７１の厚さ未満である。高濃度領域７０の厚さは、ＳｉＣエピタキシャル層６７の総厚さの２分の１未満である。
　高濃度領域７０のｎ型不純物濃度のピーク値は、１．０×１０１６ｃｍ－３以上１．０×１０１８ｃｍ－３以下であってもよい。低濃度領域７１のｎ型不純物濃度のピーク値は、１．０×１０１５ｃｍ－３以上１．０×１０１６ｃｍ－３以下であってもよい。
　ＳｉＣチップ６２は、アクティブ領域７２および外側領域７３を含む。アクティブ領域７２は、機能デバイス（トランジスタ）の一例としてのＭＩＳＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor）が形成された領域である。
　アクティブ領域７２は、平面視において側面６５Ａ～６５Ｄから内方に間隔を空けてＳｉＣチップ６２の中央部に形成されている。アクティブ領域７２は、平面視において側面６５Ａ～６５Ｄに平行な４辺を有する四角形状（この形態では長方形状）に形成されている。
　外側領域７３は、アクティブ領域７２の外側の領域である。外側領域７３は、側面６５Ａ～６５Ｄおよびアクティブ領域７２の周縁の間の領域に形成されている。外側領域７３は、平面視においてアクティブ領域７２を取り囲む環状（より具体的に無端状）に形成されている。
　ＳｉＣ半導体装置６１は、アクティブ領域７２において第１主面６３の表層部に形成されたｐ型のボディ領域７４を含む。ボディ領域７４は、アクティブ領域７２を画定している。ボディ領域７４のｐ型不純物濃度のピーク値は、１．０×１０１７ｃｍ－３以上１．０×１０１９ｃｍ－３以下であってもよい。ボディ領域７４のｐ型不純物濃度のピーク値は、１．０×１０１８ｃｍ－３以上であることが好ましい。
　図９～図１２を参照して、ＳｉＣ半導体装置６１は、アクティブ領域７２において第１主面６３に形成された複数のトレンチゲート構造７５を含む。複数のトレンチゲート構造７５は、第１方向Ｘに沿って延びる帯状にそれぞれ形成され、第２方向Ｙに沿って間隔を空けて形成されている。複数のトレンチゲート構造７５は、平面視において全体としてストライプ状に形成されている。
　複数のトレンチゲート構造７５は、この形態では、アクティブ領域７２において一方側（第３側面６５Ｃ側）の周縁部から他方側（第４側面６５Ｄ側）の周縁部に向けて帯状に延びている。複数のトレンチゲート構造７５は、アクティブ領域７２において一方側の周縁部および他方側の周縁部の間の中間部を横切っている。
　各トレンチゲート構造７５の長さは、１ｍｍ以上１０ｍｍ以下であってもよい。各トレンチゲート構造７５の長さは、１ｍｍ以上２ｍｍ以下、２ｍｍ以上４ｍｍ以下、４ｍｍ以上６ｍｍ以下、６ｍｍ以上８ｍｍ以下、または、８ｍｍ以上１０ｍｍ以下であってもよい。各トレンチゲート構造７５の長さは、２ｍｍ以上６ｍｍ以下であることが好ましい。１つのトレンチゲート構造７５の単位面積当たりの総延長は、０．５μｍ／μｍ２以上０．７５μｍ／μｍ２以下であってもよい。
　各トレンチゲート構造７５は、アクティブ部７６およびコンタクト部７７を含む。アクティブ部７６は、ＭＩＳＦＥＴのチャネルに沿う部分である。コンタクト部７７は、ＭＩＳＦＥＴのチャネル外の部分である。コンタクト部７７は、トレンチゲート構造７５の端部であり、外部接続を主たる目的としている。
　各トレンチゲート構造７５は、ゲートトレンチ７８、ゲート絶縁層７９およびゲート電極８０を含む。図９では、ゲート絶縁層７９およびゲート電極８０がハッチングによって示されている。
　ゲートトレンチ７８は、ボディ領域７４を貫通するようにＳｉＣエピタキシャル層６７に形成されている。ゲートトレンチ７８は、側壁および底壁を含む。ゲートトレンチ７８の長辺を形成する側壁は、ＳｉＣ単結晶のａ面によって形成されている。ゲートトレンチ７８の短辺を形成する側壁は、ＳｉＣ単結晶のｍ面によって形成されている。
　ゲートトレンチ７８の側壁は、法線方向Ｚに沿って延びていてもよい。ＳｉＣチップ６２内においてゲートトレンチ７８の側壁が第１主面６３に対して成す角度は、９０°以上９５°以下（たとえば９１°以上９３°以下）であってもよい。ゲートトレンチ７８の側壁は、第１主面６３に対してほぼ垂直に形成されていてもよい。ゲートトレンチ７８は、断面視において底壁側の開口面積が開口側の開口面積よりも小さいテーパ形状に形成されていてもよい。
　ゲートトレンチ７８の底壁は、高濃度領域７０に位置している。ゲートトレンチ７８の底壁は、ＳｉＣ単結晶のｃ面に面している。ゲートトレンチ７８の底壁は、ＳｉＣ単結晶の（０００１）面に対して［１１－２０］方向に傾斜したオフ角を有している。ゲートトレンチ７８の底壁は、第１主面６３に対して平行に形成されていてもよい。ゲートトレンチ７８の底壁は、第２主面６４に向かう湾曲状に形成されていてもよい。
　法線方向Ｚに関して、ゲートトレンチ７８の深さは、０．５μｍ以上３．０μｍ以下であってもよい。ゲートトレンチ７８の深さは、０．５μｍ以上１．０μｍ以下、１．０μｍ以上１．５μｍ以下、１．５μｍ以上２．０μｍ以下、２．０μｍ以上２．５μｍ以下、または、２．５μｍ以上３．０μｍ以下であってもよい。
　ゲートトレンチ７８の第２方向Ｙに沿う幅は、０．１μｍ以上２μｍ以下であってもよい。ゲートトレンチ７８の幅は、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１．０μｍ以下、１．０μｍ以上１．５μｍ以下、または、１．５μｍ以上２μｍ以下であってもよい。
　ゲートトレンチ７８の開口エッジ部は、第１主面６３からゲートトレンチ７８の内方に向かって下り傾斜した傾斜部を含む。ゲートトレンチ７８の開口エッジ部は、第１主面６３およびゲートトレンチ７８の側壁を接続する部分である。
　ゲートトレンチ７８の傾斜部は、ＳｉＣチップ６２の内方に向かう湾曲状に形成されている。ゲートトレンチ７８の傾斜部は、ゲートトレンチ７８の内方に向かう湾曲状に形成されていてもよい。ゲートトレンチ７８の傾斜部は、ゲートトレンチ７８の開口エッジ部に対する電界集中を緩和する。
　ゲート絶縁層７９は、酸化シリコン、窒化シリコン、酸化アルミニウム、酸化ジルコニウムおよび酸化タンタルのうちの少なくとも１種を含む。ゲート絶縁層７９は、窒化シリコン層および酸化シリコン層を含む積層構造を有していてもよい。ゲート絶縁層７９は、酸化シリコン層または窒化シリコン層からなる単層構造を有していてもよい。ゲート絶縁層７９は、この形態では、酸化シリコン層からなる単層構造を有している。
　ゲート絶縁層７９は、ゲートトレンチ７８の内壁に沿って膜状に形成され、ゲートトレンチ７８内においてリセス空間を区画している。ゲート絶縁層７９は、第１領域８１、第２領域８２および第３領域８３を含む。
　第１領域８１は、ゲートトレンチ７８の側壁に沿って形成されている。第２領域８２は、ゲートトレンチ７８の底壁に沿って形成されている。第３領域８３は、第１主面６３に沿って形成されている。
　第１領域８１の厚さは、第２領域８２の厚さおよび第３領域８３の厚さ未満である。第１領域８１の厚さは、０．０１μｍ以上０．２μｍ以下であってもよい。第２領域８２の厚さは、０．０５μｍ以上０．５μｍ以下であってもよい。第３領域８３の厚さは、０．０５μｍ以上０．５μｍ以下であってもよい。
　ゲート絶縁層７９は、開口エッジ部においてゲートトレンチ７８内に向けて膨出した膨出部８４を含む。膨出部８４は、ゲート絶縁層７９の第１領域８１および第３領域８３を接続する角部に形成されている。膨出部８４は、ゲートトレンチ７８の内方に向かう湾曲状に形成されている。膨出部８４は、開口エッジ部においてゲートトレンチ７８の開口を狭めている。膨出部８４を有さないゲート絶縁層７９が形成されていてもよい。一様な厚さを有するゲート絶縁層７９が形成されていてもよい。
　ゲート電極８０は、ゲート絶縁層７９を挟んでゲートトレンチ７８に埋め込まれている。ゲート電極８０は、より具体的には、ゲートトレンチ７８内においてゲート絶縁層７９によって区画されたリセス空間に埋め込まれている。
　ゲート電極８０は、ゲートトレンチ７８の開口側に位置する上端部を有している。ゲート電極８０の上端部は、ゲートトレンチ７８の底壁に向かって窪んだ湾曲状に形成されている。ゲート電極８０の上端部は、ゲート絶縁層７９の膨出部８４に沿って括れた括れ部を有している。
　ゲート電極８０は、ｐ型不純物が添加されたｐ型ポリシリコンを含む。ゲート電極８０のｐ型不純物は、ホウ素、アルミニウム、インジウムおよびガリウムのうちの少なくとも１種を含んでいてもよい。
　ゲート電極８０のｐ型不純物濃度は、ボディ領域７４のｐ型不純物濃度を超えている。ゲート電極８０のｐ型不純物濃度は、１．０×１０１８ｃｍ－３以上１．０×１０２２ｃｍ－３以下であってもよい。ゲート電極８０のシート抵抗は、１０Ω／□以上５００Ω／□以下（この形態では２００Ω／□程度）であってもよい。ゲート電極８０の厚さは、０．５μｍ以上３μｍ以下であってもよい。
　図９および図１１を参照して、ＳｉＣ半導体装置６１は、アクティブ領域７２において第１主面６３の上に形成されたゲート配線８５を含む。図９では、ゲート配線８５がハッチングによって示されている。ゲート配線８５は、より具体的には、ゲート絶縁層７９の第３領域８３の上に形成されている。ゲート配線８５は、アクティブ領域７２において第１側面６５Ａ、第３側面６５Ｃおよび第４側面６５Ｄに沿って形成され、複数のトレンチゲート構造７５が形成された領域を３方向から区画している。
　ゲート配線８５は、トレンチゲート構造７５のコンタクト部７７から露出するゲート電極８０に接続されている。ゲート配線８５は、この形態では、ゲートトレンチ７８から第１主面６３の上に引き出されたゲート電極８０の引き出し部によって形成されている。ゲート配線８５の上端部は、ゲート電極８０の上端部に接続されている。
　ＳｉＣ半導体装置６１は、ゲート電極８０を被覆する低抵抗層８６を含む。低抵抗層８６は、ゲートトレンチ７８内においてゲート電極８０の上端部を被覆している。低抵抗層８６は、トレンチゲート構造７５の一部を形成している。
　低抵抗層８６は、ゲート電極８０のシート抵抗未満のシート抵抗を有する導電材料を含む。低抵抗層８６のシート抵抗は、０．０１Ω／□以上１０Ω／□以下であってもよい。
　低抵抗層８６は、より具体的には、ポリサイド層を含む。ポリサイド層は、ゲート電極８０の表層部を形成する部分が金属材料によってシリサイド化されることによって形成されている。ポリサイド層は、より具体的には、ゲート電極８０（ｐ型ポリシリコン）に添加されたｐ型不純物を含むｐ型ポリサイド層からなる。ポリサイド層は、１０μΩ・ｃｍ以上１１０μΩ・ｃｍ以下の比抵抗を有していることが好ましい。
　ゲート電極８０および低抵抗層８６が埋め込まれたゲートトレンチ７８内のシート抵抗は、ゲート電極８０単体のシート抵抗以下である。ゲートトレンチ７８内のシート抵抗は、ｎ型不純物が添加されたｎ型ポリシリコンのシート抵抗以下であることが好ましい。
　ゲートトレンチ７８内のシート抵抗は、低抵抗層８６のシート抵抗に近似される。つまり、ゲートトレンチ７８内のシート抵抗は、０．０１Ω／□以上１０Ω／□以下であってもよい。ゲートトレンチ７８内のシート抵抗は、１０Ω／□未満であることが好ましい。
　低抵抗層８６は、ＴｉＳｉ、ＴｉＳｉ２、ＮｉＳｉ、ＣｏＳｉ、ＣｏＳｉ２、ＭｏＳｉ２およびＷＳｉ２のうちの少なくとも１種を含んでいてもよい。とりわけ、これらの種のうちのＮｉＳｉ、ＣｏＳｉ２およびＴｉＳｉ２は、比抵抗の値および温度依存性が比較的小さいことから、低抵抗層８６を形成するポリサイド層として適している。低抵抗層８６は、他の領域への拡散が少ない性質を有するＣｏＳｉ２からなることが最も好ましい。
　低抵抗層８６は、ゲート絶縁層７９に接する接触部を含む。低抵抗層８６の接触部は、より具体的には、ゲート絶縁層７９の第３領域８３（膨出部８４）に接している。低抵抗層８６の接触部は、ボディ領域７４の底部に対して第１主面６３側の領域に形成されている。低抵抗層８６の接触部は、より具体的には、後述するソース領域９７の底部に対して第１主面６３側の領域に形成されている。低抵抗層８６はゲート絶縁層７９を挟んでボディ領域７４とは対向していない。
　これにより、低抵抗層８６およびボディ領域７４の間の電流パスの形成を抑制できる。特に、低抵抗層８６の接触部を、ゲート絶縁層７９において比較的厚い角部に接続させる設計は、電流パスのリスクを低減する上で有効である。
　法線方向Ｚに関して、低抵抗層８６の厚さは、ゲート電極８０の厚さ未満であることが好ましい。低抵抗層８６の厚さは、０．０１μｍ以上３μｍ以下であってもよい。
　低抵抗層８６は、ゲート配線８５の上端部も被覆している。低抵抗層８６においてゲート配線８５の上端部を被覆する部分は、低抵抗層８６においてゲート電極８０の上端部を被覆する部分と一体的に形成されている。これにより、低抵抗層８６は、ゲート電極８０の全域およびゲート配線８５の全域を被覆している。
　ｎ型ポリシリコンとは相異なる仕事関数を有するｐ型ポリシリコンをゲートトレンチ７８に埋め込むことにより、ゲート閾値電圧Ｖｔｈを１Ｖ程度増加させることができる。しかし、ｐ型ポリシリコンは、ｎ型ポリシリコンのシート抵抗よりも数十倍（おおよそ２０倍）高いシート抵抗を有している。そのため、ｐ型ポリシリコンをゲート電極８０の材料として採用した場合、ゲートトレンチ７８内の寄生抵抗（以下、単に「ゲート抵抗」という。）の増加に伴ってエネルギ損失が増大する。
　そこで、ＳｉＣ半導体装置６１では、ゲート電極８０（ｐ型ポリシリコン）の上に低抵抗層８６（ｐ型ポリサイド）を形成している。低抵抗層８６によれば、ゲート閾値電圧Ｖｔｈの増加（たとえば１Ｖ程度の増加）を許容させながら、ゲートトレンチ７８内のシート抵抗を低減できる。
　たとえば、低抵抗層８６を有する構造によれば、低抵抗層８６を有さない場合と比較してシート抵抗を１００分の１以下に低下させることができる。また、低抵抗層８６を有する構造によれば、ｎ型ポリシリコンを含むゲート電極８０と比較してシート抵抗を５分の１以下に低下させることができる。
　これにより、ゲート抵抗を低減できるから、トレンチゲート構造７５に沿って電流を効率的に拡散させることができる。つまり、低抵抗層８６は、ゲートトレンチ７８内に電流を拡散する電流拡散層として形成されている。特に、ミリメートルオーダの長さ（１ｍｍ以上の長さ）を有するゲートトレンチ７８の場合には電流の伝達に時間を要するが、低抵抗層８６によればスイッチング遅延を適切に抑制できる。
　また、低抵抗層８６を有する構造によれば、ゲート閾値電圧Ｖｔｈを高める上でボディ領域７４のｐ型不純物濃度を増加させなくて済む。よって、チャネル抵抗の増加を抑制しながら、ゲート閾値電圧Ｖｔｈを適切に増加させることができる。
　ＳｉＣ半導体装置６１は、互いに隣り合う複数のトレンチゲート構造７５の間の領域にそれぞれ形成された複数のトレンチソース構造９１を含む。複数のトレンチソース構造９１は、１つのトレンチゲート構造７５を挟み込む態様で、第２方向Ｙ（ＳｉＣ単結晶のａ軸方向）に間隔を空けて形成されている。
　複数のトレンチソース構造９１は、第１方向Ｘ（ＳｉＣ単結晶のｍ軸方向）に沿って延びる帯状にそれぞれ形成されている。複数のトレンチソース構造９１は、平面視において全体としてストライプ状に形成されている。第２方向Ｙに関して、互いに隣り合うトレンチソース構造９１の中央部間のピッチは、１．５μｍ以上３μｍ以下であってもよい。
　各トレンチソース構造９１は、ソーストレンチ９２、ソース絶縁層９３およびソース電極９４を含む。図９では、ソース絶縁層９３およびソース電極９４がハッチングによって示されている。
　ソーストレンチ９２は、ボディ領域７４を貫通するようにＳｉＣエピタキシャル層６７に形成されている。ソーストレンチ９２は、側壁および底壁を含む。ソーストレンチ９２の長辺を形成する側壁は、ＳｉＣ単結晶のａ面によって形成されている。ソーストレンチ９２の短辺を形成する側壁は、ＳｉＣ単結晶のｍ面によって形成されている。
　ソーストレンチ９２の側壁は、法線方向Ｚに沿って延びていてもよい。ＳｉＣチップ６２内においてソーストレンチ９２の側壁が第１主面６３に対して成す角度は、９０°以上９５°以下（たとえば９１°以上９３°以下）であってもよい。ソーストレンチ９２の側壁は、第１主面６３に対してほぼ垂直に形成されていてもよい。ソーストレンチ９２は、断面視において底壁側の開口面積が開口側の開口面積よりも小さいテーパ形状に形成されていてもよい。
　ソーストレンチ９２の底壁は、高濃度領域７０に位置している。ソーストレンチ９２の底壁は、ゲートトレンチ７８の底壁に対して第２主面６４側の領域に位置している。ソーストレンチ９２の底壁は、法線方向Ｚに関して、ゲートトレンチ７８の底壁および低濃度領域７１の間の領域に位置している。
　ソーストレンチ９２の底壁は、ＳｉＣ単結晶のｃ面に面している。ソーストレンチ９２の底壁は、ＳｉＣ単結晶の（０００１）面に対して［１１－２０］方向に傾斜したオフ角を有している。ソーストレンチ９２の底壁は、第１主面６３に対して平行に形成されていてもよい。ソーストレンチ９２の底壁は、第２主面６４に向かう湾曲状に形成されていてもよい。
　ソーストレンチ９２の深さは、ゲートトレンチ７８の深さを超えている。ゲートトレンチ７８の深さに対するソーストレンチ９２の深さの比は、ソーストレンチ９２が高濃度領域７０内に位置するという条件において、１．５以上であってもよい。ゲートトレンチ７８の深さに対するソーストレンチ９２の深さの比は、２以上であることが好ましい。ソーストレンチ９２の深さは、ゲートトレンチ７８の深さと等しくてもよい。法線方向Ｚに関して、ソーストレンチ９２の深さは、０．５μｍ以上１０μｍ以下（たとえば２μｍ程度）であってもよい。
　ソーストレンチ９２の第２方向Ｙに沿う幅は、ゲートトレンチ７８の第２方向Ｙに沿う幅を超えていてもよいし、ゲートトレンチ７８の第２方向Ｙに沿う幅未満であってもよい。ソーストレンチ９２の第２方向Ｙに沿う幅は、ゲートトレンチ７８の第２方向Ｙに沿う幅と等しいことが好ましい。ソーストレンチ９２の第２方向Ｙに沿う幅は、０．１μｍ以上２μｍ以下（たとえば０．５μｍ程度）であってもよい。
　ソース絶縁層９３は、酸化シリコン、窒化シリコン、酸化アルミニウム、酸化ジルコニウムまたは酸化タンタルのうちの少なくとも１種を含む。ソース絶縁層９３は、窒化シリコン層および酸化シリコン層を含む積層構造を有していてもよい。ソース絶縁層９３は、酸化シリコン層または窒化シリコン層からなる単層構造を有していてもよい。ソース絶縁層９３は、この形態では、酸化シリコン層からなる単層構造を有している。
　ソース絶縁層９３は、ソーストレンチ９２の内壁に沿って膜状に形成され、ソーストレンチ９２内においてリセス空間を区画している。ソース絶縁層９３は、第１領域９５および第２領域９６を含む。
　第１領域９５は、ソーストレンチ９２の側壁に沿って形成されている。第２領域９６は、ソーストレンチ９２の底壁に沿って形成されている。第１領域９５の厚さは、第２領域９６の厚さよりも小さい。第１領域９５の厚さは、０．０１μｍ以上０．２μｍ以下であってもよい。第２領域９６の厚さは、０．０５μｍ以上０．５μｍ以下であってもよい。
　第１領域９５の厚さは、ゲート絶縁層７９の第１領域９５の厚さとほぼ等しくてもよい。第２領域９６の厚さは、ゲート絶縁層７９の第２領域９６の厚さとほぼ等しくてもよい。一様な厚さを有するソース絶縁層９３が形成されていてもよい。
　ソース電極９４は、ソース絶縁層９３を挟んでソーストレンチ９２に埋め込まれている。ソース電極９４は、より具体的には、ソーストレンチ９２においてソース絶縁層９３によって区画されたリセス空間に埋め込まれている。
　ソース電極９４は、ソーストレンチ９２の開口側に位置する上端部を有している。ソース電極９４の上端部は、第１主面６３に対してソーストレンチ９２の底壁側に形成されている。ソース電極９４の上端部は、第１主面６３よりも上方に位置していてもよい。
　ソース電極９４の上端部は、ソーストレンチ９２の底壁に向かって窪んだ湾曲状に形成されている。ソース電極９４の上端部は、第１主面６３に対して平行に形成されていてもよい。法線方向Ｚに関して、ソース電極９４の厚さは、０．５μｍ以上１０μｍ以下（たとえば１μｍ程度）であってもよい。
　ソース電極９４は、材質的にＳｉＣに近い性質を有するポリシリコンを含むことが好ましい。これにより、ＳｉＣチップ６２内において生じる応力を低減できる。ソース電極９４は、この形態では、ｐ型不純物が添加されたｐ型ポリシリコンを含む。この場合、ゲート電極８０と同時にソース電極９４を形成できる。
　ソース電極９４のｐ型不純物濃度は、ボディ領域７４のｐ型不純物濃度を超えている。ソース電極９４のｐ型不純物濃度は、ゲート電極８０のｐ型不純物濃度と等しくてもよい。ソース電極９４のｐ型不純物濃度は、１．０×１０１８ｃｍ－３以上１．０×１０２２ｃｍ－３以下であってもよい。
　ソース電極９４のｐ型不純物は、ホウ素、アルミニウム、インジウムおよびガリウムのうちの少なくとも１種を含んでいてもよい。ソース電極９４のシート抵抗は、１０Ω／□以上５００Ω／□以下（この形態では２００Ω／□程度）であってもよい。ソース電極９４のシート抵抗は、ゲート電極８０のシート抵抗と等しくてもよい。
　ソース電極９４は、ｐ型ポリシリコンに代えてまたはこれに加えて、ｎ型ポリシリコン、タングステン、アルミニウム、銅、アルミニウム合金および銅合金のうちの少なくとも１種を含んでいてもよい。
　ＳｉＣ半導体装置６１は、ボディ領域７４の表層部においてゲートトレンチ７８の側壁に沿う領域に形成されたｎ＋型のソース領域９７を含む。ソース領域９７のｎ型不純物濃度のピーク値は、１．０×１０１８ｃｍ－３以上１．０×１０２１ｃｍ－３以下であってもよい。ソース領域９７のｎ型不純物濃度のピーク値は、１．０×１０２０ｃｍ－３以上であることが好ましい。
　ソース領域９７は、ゲートトレンチ７８の一方側の側壁および他方側の側壁に沿って複数形成されている。複数のソース領域９７は、第１方向Ｘに沿って延びる帯状にそれぞれ形成されている。複数のソース領域９７は、平面視において全体としてストライプ状に形成されている。各ソース領域９７は、ゲートトレンチ７８の側壁および各ソーストレンチ９２の側壁から露出している。
　ソース領域９７においてゲートトレンチ７８の側壁に沿う部分は、高濃度領域７０との間でＭＩＳＦＥＴのチャネルを画定している。チャネルのＯＮ／ＯＦＦは、ゲート電極８０によって制御される。
　ＳｉＣ半導体装置６１は、第１主面６３の表層部において各ソーストレンチ９２に沿う領域に形成されたｐ＋型のコンタクト領域９８を含む。各コンタクト領域９８のｐ型不純物濃度のピーク値は、ボディ領域７４のｐ型不純物濃度のピーク値を超えている。各コンタクト領域９８のｐ型不純物濃度のピーク値は、１．０×１０１８ｃｍ－３以上１．０×１０２１ｃｍ－３以下であってもよい。
　コンタクト領域９８は、この形態では、１つのソーストレンチ９２に対して複数形成されている。複数のコンタクト領域９８は、対応するソーストレンチ９２に沿って間隔を空けて形成されている。複数のコンタクト領域９８は、ゲートトレンチ７８から間隔を空けて形成されている。
　各コンタクト領域９８は、対応するソーストレンチ９２の側壁および底壁を被覆している。各コンタクト領域９８の底部は、対応するソーストレンチ９２の底壁に対して平行に形成されていてもよい。
　各コンタクト領域９８においてソーストレンチ９２の側壁を被覆する部分は、ボディ領域７４の底部に対して第１主面６３側の領域に形成されている。各コンタクト領域９８においてソーストレンチ９２の側壁を被覆する部分は、隣り合うゲートトレンチ７８に向けて引き出されている。各コンタクト領域９８においてソーストレンチ９２の側壁を被覆する部分は、ゲートトレンチ７８およびソーストレンチ９２の間の中間領域まで延びていてもよい。各コンタクト領域９８は、ボディ領域７４およびソース領域９７に電気的に接続されている。
　ＳｉＣ半導体装置６１は、アクティブ領域７２において第１主面６３の表層部に形成されたディープウェル領域９９を含む。ディープウェル領域９９は、複数のソーストレンチ９２に対して１対１対応の関係で複数形成されている。各ディープウェル領域９９は、平面視において対応するソーストレンチ９２に沿って延びる帯状に形成されている。
　各ディープウェル領域９９は、高濃度領域７０に形成されている。各ディープウェル領域９９は、各コンタクト領域９８を挟んで各ソーストレンチ９２を被覆している。各ディープウェル領域９９は、対応するコンタクト領域９８を挟んでソーストレンチ９２の側壁および底壁を被覆している。各ディープウェル領域９９は、第１主面３の表層部においてボディ領域７４に連なっている。
　各ディープウェル領域９９は、ゲートトレンチ７８の底壁に対して第２主面６４側に位置する底部を有している。各ディープウェル領域９９の底部は、各ソーストレンチ９２の底壁に対して平行に形成されていてもよい。複数のディープウェル領域９９は、一定の深さで形成されていることが好ましい。
　各ディープウェル領域９９のｐ型不純物濃度のピーク値は、コンタクト領域９８のｐ型不純物濃度のピーク値未満であってもよい。各ディープウェル領域９９のｐ型不純物濃度のピーク値は、ボディ領域７４のｐ型不純物濃度のピーク値と等しくてもよい。各ディープウェル領域９９のｐ型不純物濃度のピーク値は、ボディ領域７４のｐ型不純物濃度のピーク値を超えていてもよいし、ボディ領域７４のｐ型不純物濃度のピーク値未満であってもよい。
　各ディープウェル領域９９のｐ型不純物濃度のピーク値は、１．０×１０１７ｃｍ－３以上１．０×１０１９ｃｍ－３以下であってもよい。各ディープウェル領域９９のｐ型不純物濃度のピーク値は、１．０×１０１８ｃｍ－３以上であることが好ましい。
　各ディープウェル領域９９は、高濃度領域７０との間でｐｎ接合部を形成している。このｐｎ接合部からは、ゲートトレンチ７８に向けて空乏層が拡がる。空乏層は、ゲートトレンチ７８の底壁にオーバラップしてもよい。
　ＳｉＣ半導体装置６１は、アクティブ領域７２の周縁部において第１主面６３の表層部に形成されたｐ型の周縁ウェル領域１００を含む。周縁ウェル領域１００は、トレンチゲート構造７５のコンタクト部７７を被覆し、アクティブ部７６を露出させている。
　周縁ウェル領域１００は、対応するコンタクト部７７においてゲートトレンチ７８の側壁および底壁を被覆している。周縁ウェル領域１００の底部は、ディープウェル領域９９の底壁に対して第１主面６３側に位置している。各周縁ウェル領域１００は、第１主面６３の表層部においてボディ領域７４およびディープウェル領域９９に電気的に接続されている。
　周縁ウェル領域１００のｐ型不純物濃度は、ディープウェル領域９９のｐ型不純物濃度とほぼ等しくてもよい。周縁ウェル領域１００のｐ型不純物濃度のピーク値は、１．０×１０１７ｃｍ－３以上１．０×１０１９ｃｍ－３以下であってもよい。周縁ウェル領域１００のｐ型不純物濃度のピーク値は、１．０×１０１８ｃｍ－３以上であることが好ましい。
　ｐｎ接合ダイオードだけを備えるＳｉＣ半導体装置では、トレンチを備えていないという構造上、ＳｉＣチップ６２内における電界集中の問題は少ない。各ディープウェル領域９９は、トレンチゲート型のＭＩＳＦＥＴをｐｎ接合ダイオードの構造に近づける。
　これにより、トレンチゲート型のＭＩＳＦＥＴにおいて、ＳｉＣチップ６２内における電界を緩和できる。したがって、互いに隣り合う複数のディープウェル領域９９の間のピッチを狭めることは、電界集中を緩和する上で有効である。
　また、ゲートトレンチ７８の底壁に対して第２主面６４側に底部を有するディープウェル領域９９によれば、空乏層によって、ゲートトレンチ７８に対する電界集中を適切に緩和できる。複数のディープウェル領域９９は、一定の深さで形成されていることが好ましい。これにより、ＳｉＣチップ６２の耐圧（たとえば破壊耐量）が各ディープウェル領域９９によって制限されることを抑制できるから、耐圧の向上を適切に図ることができる。周縁ウェル領域１００も、ディープウェル領域９９と同様の効果を奏する。
　ソーストレンチ９２を利用することにより、ＳｉＣチップ６２の比較的深い領域にディープウェル領域９９を適切に形成できる。また、ソーストレンチ９２に沿ってディープウェル領域９９を形成できるから、複数のディープウェル領域９９の深さにバラツキが生じるのを適切に抑制できる。
　また、高濃度領域７０の一部が、互いに隣り合う複数のディープウェル領域９９の間の領域に介在している。これにより、互いに隣り合う複数のディープウェル領域９９の間の領域において、ＪＦＥＴ（Junction Field Effect Transistor）抵抗を低減できる。
　また、この形態では、各ディープウェル領域９９の底部が高濃度領域７０に位置している。これにより、高濃度領域７０における各ディープウェル領域９９の直下の領域において第１主面６３に対して平行な横方向に電流経路を形成できる。その結果、電流拡がり抵抗を低減できる。低濃度領域７１は、このような構造において、ＳｉＣチップ６２の耐圧を高める。
　ＳｉＣ半導体装置６１は、アクティブ領域７２においてソース電極９４の上端部を縁取るように第１主面６３に形成された複数のソースサブトレンチ１０１を含む。複数のソースサブトレンチ１０１は、複数のソース電極９４に対して１対１対応の関係で形成されている。ソースサブトレンチ１０１は、対応するソーストレンチ９２に連通し、対応するソーストレンチ９２の側壁の一部を形成している。
　ソースサブトレンチ１０１は、この形態では、平面視においてソース電極９４の上端部を取り囲む環状（より具体的に無端状）に形成されている。ソースサブトレンチ１０１は、ソース絶縁層９３の一部を掘り下げることによって形成されている。ソースサブトレンチ１０１は、より具体的には、第１主面６３からソース絶縁層９３の上端部およびソース電極９４の上端部を掘り下げることによって形成されている。
　ソースサブトレンチ１０１は、断面視において底面積が開口面積よりも小さい先細り形状に形成されている。ソースサブトレンチ１０１の底壁は、第２主面６４に向かう湾曲状に形成されていてもよい。ソースサブトレンチ１０１は、ソース領域９７、コンタクト領域９８、ソース絶縁層９３、ソース電極９４およびコンタクト領域９８を露出させている。
　ソース電極９４の上端部は、ソース電極９４の下端部に対して内側に括れた形状を有している。ソース電極９４の下端部は、ソース電極９４において各ソーストレンチ９２の底壁側に位置する部分である。ソース電極９４の上端部の第２方向Ｙに沿う幅は、ソース電極９４の下端部の第２方向Ｙに沿う幅未満であってもよい。
　各ソーストレンチ９２の開口エッジ部は、第１主面６３から各ソーストレンチ９２の内方に向かって下り傾斜した傾斜部を含む。各ソーストレンチ９２の開口エッジ部は、第１主面６３および各ソーストレンチ９２の側壁を接続する部分である。各ソーストレンチ９２の傾斜部は、ソースサブトレンチ１０１によって形成されている。
　各ソーストレンチ９２の傾斜部は、この形態では、ＳｉＣチップ６２の内方に向かって窪んだ湾曲状に形成されている。各ソーストレンチ９２の傾斜部は、ソースサブトレンチ１０１に向かう湾曲状に形成されていてもよい。各ソーストレンチ９２の傾斜部は、各ソーストレンチ９２の開口エッジ部に対する電界集中を緩和する。
　図１３を参照して、アクティブ領域７２は、第１主面６３の一部を形成するアクティブ主面１１１を有している。外側領域７３は、第１主面６３の一部を形成する外側主面１１２を有している。外側主面１１２は、側面６５Ａ～６５Ｄに接続されている。
　アクティブ主面１１１および外側主面１１２は、ＳｉＣ単結晶のｃ面にそれぞれ面している。アクティブ主面１１１および外側主面１１２は、ＳｉＣ単結晶の（０００１）面に対して［１１－２０］方向に傾斜したオフ角をそれぞれ有している。
　外側領域７３は、第１主面６３を第２主面６４側に掘り下げることによって形成されている。したがって、外側主面１１２は、アクティブ主面１１１に対して第２主面６４側に窪んだ領域に形成されている。外側主面１１２は、ゲートトレンチ７８の底壁に対して第２主面６４側に位置している。
　外側主面１１２は、この形態では、各ソーストレンチ９２の底壁とほぼ等しい深さ位置に形成されている。外側主面１１２は、各ソーストレンチ９２の底壁とほぼ同一平面上に位置している。外側主面１１２は、各ソーストレンチ９２の底壁に対して、０μｍ以上１μｍ以下の範囲で、第２主面６４側に位置していてもよい。外側主面１１２は、高濃度領域７０を露出させている。
　アクティブ領域７２は、この形態では、外側領域７３によって台地状に区画されている。アクティブ領域７２は、外側主面１１２よりも上方に向かって突出した台地状のアクティブ台地１１３として形成されている。
　アクティブ台地１１３は、アクティブ主面１１１および外側主面１１２を接続するアクティブ側壁１１４を含む。アクティブ側壁１１４は、アクティブ領域７２および外側領域７３の間の境界領域を区画している。第１主面６３は、アクティブ主面１１１、外側主面１１２およびアクティブ側壁１１４によって形成されている。
　アクティブ側壁１１４は、この形態では、アクティブ主面１１１（外側主面１１２）の法線方向Ｚに沿って延びている。アクティブ側壁１１４は、ＳｉＣ単結晶のｍ面およびａ面によって形成されている。アクティブ側壁１１４は、アクティブ主面１１１から外側主面１１２に向かって下り傾斜した傾斜面を有していてもよい。アクティブ側壁１１４は、高濃度領域７０を露出させている。アクティブ側壁１１４は、ボディ領域７４を露出させていてもよい。
　ＳｉＣ半導体装置６１は、外側主面１１２の表層部に形成されたｐ＋型のダイオード領域１２１を含む。ダイオード領域１２１は、高濃度領域７０に形成されている。ダイオード領域１２１は、外側領域７３においてアクティブ側壁１１４および側面６５Ａ～６５Ｄの間の領域に形成されている。
　ダイオード領域１２１は、アクティブ側壁１１４および側面６５Ａ～６５Ｄから間隔を空けて形成されている。ダイオード領域１２１は、平面視においてアクティブ領域７２に沿って帯状に延びている。ダイオード領域１２１は、この形態では、平面視においてアクティブ領域７２を取り囲む環状（より具体的に無端状）に形成されている。
　ダイオード領域１２１は、ゲートトレンチ７８の底壁に対して第２主面６４側に位置している。ダイオード領域１２１の底部は、各ソーストレンチ９２の底壁に対して第２主面６４側に位置している。ダイオード領域１２１の底部は、コンタクト領域９８の底部とほぼ等しい深さ位置に形成されていてもよい。
　ダイオード領域１２１の底部は、コンタクト領域９８の底部とほぼ同一平面上に位置していてもよい。ダイオード領域１２１の底部は、コンタクト領域９８の底部に対して第２主面６４側に位置していてもよい。ダイオード領域１２１の底部は、コンタクト領域９８の底部に対して、０μｍ以上１μｍ以下の範囲で第２主面６４側に位置していてもよい。
　ダイオード領域１２１は、高濃度領域７０との間でｐｎ接合部を形成している。これにより、ダイオード領域１２１をアノードとし、高濃度領域７０をカソードとするｐｎ接合ダイオードが形成されている。ダイオード領域１２１のｐ型不純物濃度のピーク値は、１．０×１０１７ｃｍ－３以上１．０×１０２１ｃｍ－３以下であってもよい。
　ＳｉＣ半導体装置６１は、外側主面１１２の表層部に形成されたｐ型の外側ウェル領域１２２を含む。外側ウェル領域１２２のｐ型不純物濃度のピーク値は、１．０×１０１７ｃｍ－３以上１．０×１０１９ｃｍ－３以下であってもよい。外側ウェル領域１２２のｐ型不純物濃度のピーク値は、ダイオード領域１２１のｐ型不純物濃度のピーク値未満であってもよい。外側ウェル領域１２２のｐ型不純物濃度のピーク値は、ディープウェル領域９９のｐ型不純物濃度のピーク値とほぼ等しくてもよい。
　外側ウェル領域１２２は、平面視においてアクティブ側壁１１４およびダイオード領域１２１の間の領域に形成されている。外側ウェル領域１２２は、平面視においてアクティブ領域７２に沿って帯状に延びている。外側ウェル領域１２２は、この形態では、平面視においてアクティブ領域７２を取り囲む環状（より具体的に無端状）に形成されている。
　外側ウェル領域１２２は、高濃度領域７０に形成されている。外側ウェル領域１２２は、ゲートトレンチ７８の底壁に対して第２主面６４側に位置している。外側ウェル領域１２２の底部は、各ソーストレンチ９２の底壁に対して第２主面６４側に位置している。外側ウェル領域１２２の底部は、ダイオード領域１２１の底部に対して第２主面６４側に位置している。外側ウェル領域１２２の底部は、ディープウェル領域９９の底部とほぼ等しい深さ位置に形成されていてもよい。
　外側ウェル領域１２２の内周縁は、アクティブ側壁１１４および外側主面１１２を接続する角部を被覆している。外側ウェル領域１２２の内周縁は、さらに、アクティブ側壁１１４に沿って延び、ボディ領域７４に接続されている。外側ウェル領域１２２の内周縁は、アクティブ側壁１１４からダイオード領域１２１側に向けて間隔を空けて形成されていてもよい。
　外側ウェル領域１２２の外周縁は、第２主面６４側からダイオード領域１２１を被覆している。外側ウェル領域１２２は、ダイオード領域１２１に電気的に接続されている。外側ウェル領域１２２は、ｐｎ接合ダイオードの一部を形成していてもよい。外側ウェル領域１２２の外周縁は、ダイオード領域１２１からアクティブ側壁１１４側に間隔を空けて形成されていてもよい。
　ＳｉＣ半導体装置６１は、外側主面１１２の表層部に形成されたＦＬ構造１２３（field limit structure）を含む。ＦＬ構造１２３は、平面視においてダイオード領域１２１および側面６５Ａ～６５Ｄの間の領域に形成されている。ＦＬ構造１２３は、この形態では、側面６５Ａ～６５Ｄからダイオード領域１２１側に向けて間隔を空けて形成されている。ＦＬ構造１２３は、高濃度領域７０に形成されている。
　ＦＬ構造１２３は、１つまたは複数（たとえば２個以上２０個以下）のＦＬ領域１２４（field limit region）を含む。ＦＬ構造１２３は、この形態では、５つのＦＬ領域１２４Ａ，１２４Ｂ，１２４Ｃ，１２４Ｄ，１２４Ｅを有するＦＬ領域群を含む。ＦＬ領域１２４Ａ～１２４Ｅは、ダイオード領域１２１から離れる方向に沿って間隔を空けてこの順に形成されている。
　ＦＬ領域１２４Ａ～１２４Ｅは、平面視においてアクティブ領域７２の周縁に沿って帯状にそれぞれ延びている。ＦＬ領域１２４Ａ～１２４Ｅは、より具体的には、平面視においてアクティブ領域７２を取り囲む環状（より具体的に無端状）にそれぞれ形成されている。ＦＬ領域１２４Ａ～１２４Ｅは、それぞれ、ＦＬＲ領域（field limiting ring region）とも称される。
　ＦＬ領域１２４Ａ～１２４Ｅの底部は、ダイオード領域１２１の底部に対して第２主面６４側に位置している。ＦＬ領域１２４Ａ～１２４Ｅのうちの最内側のＦＬ領域１２４Ａは、第２主面６４側からダイオード領域１２１を被覆している。これにより、ＦＬ領域１２４Ａは、ダイオード領域１２１に電気的に接続されている。ＦＬ領域１２４Ａは、ｐｎ接合ダイオードの一部を形成していてもよい。
　ＦＬ領域１２４Ａ～１２４Ｅの全体は、ゲートトレンチ７８の底壁に対して第２主面６４側に位置している。ＦＬ領域１２４Ａ～１２４Ｅの底部は、ソーストレンチ９２の底壁に対して第２主面６４側に位置している。
　ＦＬ構造１２３は、外側領域７３において電界集中を緩和する。ＦＬ領域１２４の個数、幅、深さ、ｐ型不純物濃度等は、緩和すべき電界に応じて種々の値を取り得る。ＦＬ構造１２３は、平面視においてアクティブ側壁１１４およびダイオード領域１２１の間の領域に形成された１つまたは複数のＦＬ領域１２４を含んでいてもよい。
　ＳｉＣ半導体装置６１は、外側主面１１２を被覆する外側絶縁層１３１を含む。外側絶縁層１３１は、アクティブ側壁１１４および外側主面１１２に沿って膜状に形成されている。外側絶縁層１３１は、アクティブ主面１１１の上において、ゲート絶縁層７９（第３領域８３）に連なっている。外側絶縁層１３１は、外側領域７３においてダイオード領域１２１、外側ウェル領域１２２およびＦＬ構造１２３を被覆している。
　外側絶縁層１３１は、酸化シリコンを含んでいてもよい。外側絶縁層１３１は、窒化シリコン等の他の絶縁膜を含んでいてもよい。外側絶縁層１３１は、この形態では、ゲート絶縁層７９と同一の絶縁材料種によって形成されている。
　外側絶縁層１３１の周縁は、側面６５Ａ～６５Ｄから露出している。外側絶縁層１３１の周縁は、この形態では、側面６５Ａ～６５Ｄに連なっている。外側絶縁層１３１の周縁は、側面６５Ａ～６５Ｄから内方に間隔を空けて形成されていてもよい。この場合、外側絶縁層１３１は、外側主面１１２を露出させる。
　ＳｉＣ半導体装置６１は、アクティブ側壁１１４を被覆するサイドウォール構造１３２をさらに含む。サイドウォール構造１３２は、アクティブ台地１１３を外側領域７３側から保護し、補強する。また、サイドウォール構造１３２は、アクティブ主面１１１および外側主面１１２の間に形成された段差を緩和する段差緩和構造を形成する。
　アクティブ領域７２および外側領域７３の間の境界領域を被覆する上層構造（被覆層）が形成される場合、上層構造は、サイドウォール構造１３２を被覆する。サイドウォール構造１３２は、上層構造の平坦性を高める。サイドウォール構造１３２は、アクティブ主面１１１から外側主面１１２に向かって下り傾斜した傾斜面を有していてもよい。サイドウォール構造１３２の傾斜面によって、段差を適切に緩和できる。
　サイドウォール構造１３２の傾斜面は、ＳｉＣチップ６２側に向かって窪んだ湾曲状に形成されていてもよい。サイドウォール構造１３２の傾斜面は、ＳｉＣチップ６２とは反対側に向かう湾曲状に形成されていてもよい。サイドウォール構造１３２の傾斜面は、アクティブ主面１１１側から外側主面１１２側に向けて平面的に延びていてもよい。
　サイドウォール構造１３２は、アクティブ側壁１１４に沿って形成されている。サイドウォール構造１３２は、この形態では、平面視においてアクティブ領域７２を取り囲む環状（より具体的に無端状）に形成されている。サイドウォール構造１３２は、ポリシリコンを含むことが好ましい。この場合、ゲート電極８０やソース電極９４と同時に、サイドウォール構造１３２を形成できる。
　ＳｉＣ半導体装置６１は、第１主面６３の上に形成された層間絶縁層１４０を含む。層間絶縁層１４０は、アクティブ領域７２および外側領域７３を被覆している。層間絶縁層１４０は、アクティブ主面１１１および外側主面１１２に沿って膜状に形成されている。
　層間絶縁層１４０は、アクティブ領域７２および外側領域７３の間の境界領域において、サイドウォール構造１３２に沿って形成されている。層間絶縁層１４０は、サイドウォール構造１３２を被覆する上層構造の一部を形成している。
　層間絶縁層１４０の周縁は、側面６５Ａ～６５Ｄから露出している。層間絶縁層１４０の周縁は、側面６５Ａ～６５Ｄに連なっている。層間絶縁層１４０の周縁は、側面６５Ａ～６５Ｄから内方に間隔を空けて形成されていてもよい。この場合、層間絶縁層１４０は、外側主面１１２（外側絶縁層１３１）を露出させる。
　層間絶縁層１４０は、酸化シリコンまたは窒化シリコンを含んでいてもよい。層間絶縁層１４０は、酸化シリコンの一例としてのＵＳＧ（Undoped Silicate Glass）、ＰＳＧ（Phosphor Silicate Glass）および／またはＢＰＳＧ（Boron Phosphor Silicate Glass）を含んでいてもよい。
　層間絶縁層１４０は、ゲートコンタクト孔１４１、ソースコンタクト孔１４２およびダイオードコンタクト孔１４３を含む。ゲートコンタクト孔１４１は、アクティブ領域７２においてゲート配線８５を露出させている。ゲートコンタクト孔１４１は、ゲート配線８５に沿う帯状に形成されていてもよい。ゲートコンタクト孔１４１の開口エッジ部は、ゲートコンタクト孔１４１内に向かう湾曲状に形成されている。
　ソースコンタクト孔１４２は、アクティブ領域７２においてソース領域９７、コンタクト領域９８およびトレンチソース構造９１を露出させている。ソースコンタクト孔１４２は、トレンチソース構造９１に沿って延びる帯状に形成されていてもよい。ソースコンタクト孔１４２の開口エッジ部は、ソースコンタクト孔１４２内に向かう湾曲状に形成されている。
　ダイオードコンタクト孔１４３は、外側領域７３においてダイオード領域１２１を露出させている。ダイオードコンタクト孔１４３は、ダイオード領域１２１に沿って延びる帯状（より具体的には無端状）に形成されていてもよい。ダイオードコンタクト孔１４３は、外側ウェル領域１２２および／またはＦＬ構造１２３を露出させていてもよい。ダイオードコンタクト孔１４３の開口エッジ部は、ダイオードコンタクト孔１４３内に向かう湾曲状に形成されている。
　ＳｉＣ半導体装置６１は、第１主面６３の上に形成された第１主面電極１５０を含む。第１主面電極１５０は、より具体的には、層間絶縁層１４０の上に形成されている。第１主面電極１５０は、互いに電気的に絶縁されたゲート主面電極１５１およびソース主面電極１５２を含む。
　ゲート主面電極１５１には、ゲート電圧が印加される。ゲート電圧は、１０Ｖ以上５０Ｖ以下（たとえば３０Ｖ程度）であってもよい。ソース主面電極１５２には、ソース電圧が印加される。ソース電圧は、基準電圧（たとえばＧＮＤ電圧）であってもよい。
　ゲート主面電極１５１は、アクティブ領域７２に形成されている。ゲート主面電極１５１は、ゲートパッド１５３およびゲートフィンガー１５４を含む。ゲートパッド１５３は、平面視において第１側面６５Ａ側の領域に形成されている。ゲートパッド１５３は、より具体的には、平面視において第１側面６５Ａの中央部に沿う領域に沿って形成されている。ゲートパッド１５３は、平面視において側面６５Ａ～６５Ｄのうちの任意の２つを接続する角部に沿う領域に形成されていてもよい。ゲートパッド１５３は、平面視において四角形状に形成されていてもよい。
　ゲートフィンガー１５４は、ゲートパッド１５３から引き出されており、アクティブ領域７２の周縁に沿って帯状に延びている。ゲートフィンガー１５４は、この形態では、アクティブ領域７２の内方を３方向から区画するように第１側面６５Ａ、第３側面６５Ｃおよび第４側面６５Ｄに沿って形成されている。
　ゲートフィンガー１５４は、一対の開放端１５５，１５６を有している。一対の開放端１５５，１５６は、アクティブ領域７２の内方を挟んでゲートパッド１５３と対向する領域に形成されている。一対の開放端１５５，１５６は、この形態では、平面視において第２側面６５Ｂに沿う領域に形成されている。
　ゲートフィンガー１５４は、層間絶縁層１４０の上からゲートコンタクト孔１４１に入り込んでいる。ゲートフィンガー１５４は、ゲートコンタクト孔１４１内においてゲート配線８５に電気的に接続されている。これにより、ゲートパッド１５３からの電気信号は、ゲートフィンガー１５４を介してゲート電極８０およびゲート配線８５に伝達される。
　ソース主面電極１５２は、アクティブ領域７２および外側領域７３に形成されている。ソース主面電極１５２は、ソースパッド１５７、ソース配線１５８およびソース接続部１５９を含む。ソースパッド１５７は、ゲート主面電極１５１から間隔を空けてアクティブ領域７２に形成されている。ソースパッド１５７は、ゲート主面電極１５１によって区画されたＣ字形状の領域を被覆するように、平面視においてＣ字形状に形成されている。
　ソースパッド１５７は、層間絶縁層１４０の上からソースコンタクト孔１４２およびソースサブトレンチ１０１に入り込んでいる。ソースパッド１５７は、ソースコンタクト孔１４２およびソースサブトレンチ１０１内において、ソース領域９７、コンタクト領域９８およびソース電極９４に電気的に接続されている。
　前述のソース電極９４は、ソースパッド１５７の一部の領域を利用して形成されていてもよい。ソース電極９４は、ソースパッド１５７において各ソーストレンチ９２に入り込んだ部分によって形成されていてもよい。
　ソース配線１５８は、外側領域７３に形成されている。ソース配線１５８は、アクティブ領域７２に沿って帯状に延びている。ソース配線１５８は、平面視においてアクティブ領域７２を取り囲む環状（より具体的に無端状）に形成されている。
　ソース配線１５８は、層間絶縁層１４０の上からダイオードコンタクト孔１４３に入り込んでいる。ソース配線１５８は、ダイオードコンタクト孔１４３内において、ダイオード領域１２１に電気的に接続されている。
　ソース接続部１５９は、ソースパッド１５７およびソース配線１５８を接続している。ソース接続部１５９は、ソースパッド１５７からゲートフィンガー１５４の開放端１５５，１５６を横切り、ソース配線１５８に接続されている。ソース接続部１５９は、アクティブ領域７２からサイドウォール構造１３２を横切って外側領域７３に引き出されている。ソース接続部１５９は、サイドウォール構造１３２を被覆する上層構造の一部を形成している。
　アクティブ領域７２に形成されたＭＩＳＦＥＴは、その構造上、ｎｐｎ型の寄生トランジスタを含む。外側領域７３で生じたアバランシェ電流がアクティブ領域７２に流れ込むと、寄生トランジスタがオン状態となる。この場合、ラッチアップによってＭＩＳＦＥＴの動作が不安定になる。そこで、ＳｉＣ半導体装置６１では、ソース主面電極１５２の構造を利用してアバランシェ電流吸収構造を形成している。
　外側領域７３で生じたアバランシェ電流は、ダイオード領域１２１を介してソース配線１５８によって吸収される。ソース配線１５８によって吸収されたアバランシェ電流は、ソース接続部１５９を介してソースパッド１５７に至る。ソースパッド１５７に導線が電気的に接続されている場合、アバランシェ電流は導線を介して外部に至る。
　これにより、アバランシェ電流に起因する寄生トランジスタの駆動を抑制できる。よって、ラッチアップを抑制できるから、ＭＩＳＦＥＴの安定性を高めることができる。
　図１４および図１５を参照して、第１主面電極１５０（ゲート主面電極１５１およびソース主面電極１５２）は、ＳｉＣチップ６２側からこの順に積層されたバリア層１６０および第１Ａｌ層１６１を含む積層構造を有している。第１Ａｌ層１６１は、比較的小さいヤング率（剛性率）を有するＡｌのクッション性を利用してＳｉＣチップ６２に加えられる外力を第１主面６３側から緩和する第１緩衝層として形成されている。
　バリア層１６０は、Ｔｉ層またはＴｉＮ層を含む単層構造を有していてもよい。バリア層１６０は、ＳｉＣチップ６２側からこの順に積層されたＴｉ層およびＴｉＮ層を含む積層構造を有していてもよい。バリア層１６０の厚さは、０．０１μｍ以上６μｍ以下であってもよい。バリア層１６０の厚さは、０．０１μｍ以上０．１μｍ以下、０．１μｍ以上２μｍ以下、２μｍ以上４μｍ以下、または、４μｍ以上６μｍ以下であってもよい。
　第１Ａｌ層１６１は、バリア層１６０の抵抗値よりも小さい抵抗値を有している。第１Ａｌ層１６１は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層およびＡｌＳｉＣｕ合金層のうちの少なくとも１つを含む。第１Ａｌ層１６１は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層およびＡｌＳｉＣｕ合金層のうちの２つ以上が任意の順序で積層された積層構造を有していてもよい。
　第１Ａｌ層１６１は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層またはＡｌＳｉＣｕ合金層からなる単層構造を有していてもよい。第１Ａｌ層１６１は、ＡｌＳｉ合金層、ＡｌＣｕ合金層またはＡｌＳｉＣｕ合金層からなる単層構造を有していることが好ましい。
　第１Ａｌ層１６１の厚さは、バリア層１６０の厚さを超えている。第１Ａｌ層１６１の厚さは、０．０５μｍ以上１０μｍ以下であってもよい。第１Ａｌ層１６１の厚さは、０．０５μｍ以上０．１μｍ以下、０．１μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上４μｍ以下、４μｍ以上６μｍ以下、６μｍ以上８μｍ以下、または、８μｍ以上１０μｍ以下であってもよい。第１Ａｌ層１６１の厚さは、１μｍ以上８μｍ以下であることが好ましい。
　ＳｉＣ半導体装置６１は、層間絶縁層１４０の上に形成された絶縁層１７０を含む。図９では、絶縁層１７０がハッチングによって示されている。絶縁層１７０の周縁は、側面６５Ａ～６５Ｄから内方に間隔を空けて形成されている。これにより、絶縁層１７０は、平面視においてＳｉＣチップ６２（より具体的には層間絶縁層１４０）の周縁を露出させている。
　絶縁層１７０の周縁は、側面６５Ａ～６５Ｄとの間でダイシングストリートＤＳを区画している。ダイシングストリートＤＳによれば、ＳｉＣウエハからＳｉＣ半導体装置６１を切り出す際に絶縁層１７０を物理的に切断せずに済む。これにより、ＳｉＣウエハからＳｉＣ半導体装置６１を円滑に切り出すことができると同時に、絶縁層１７０の剥離や劣化を抑制できる。その結果、絶縁層１７０によってＳｉＣチップ１０２や第１主面電極１５０等の保護対象物を適切に保護できる。
　ダイシングストリートＤＳの幅は、１μｍ以上２５μｍ以下であってもよい。ダイシングストリートＤＳの幅、ダイシングストリートＤＳが延びる方向に直交する方向の幅である。ダイシングストリートＤＳの幅は、１μｍ以上５μｍ以下、５μｍ以上１０μｍ以下、１０μｍ以上１５μｍ以下、１５μｍ以上２０μｍ以下、または、２０μｍ以上２５μｍ以下であってもよい。
　絶縁層１７０は、ゲート主面電極１５１およびソース主面電極１５２を選択的に被覆している。絶縁層１７０は、パッド開口１７１を含む。パッド開口１７１は、より具体的には、ゲートパッド開口１７２およびソースパッド開口１７３を含む。ゲートパッド開口１７２は、ゲートパッド１５３を露出させている。ソースパッド開口１７３は、ソースパッド１５７を露出させている。ゲートパッド開口１７２の平面形状は、任意である。ソースパッド開口１７３の平面形状は、任意である。
　絶縁層１７０は、この形態では、ＳｉＣチップ６２側からこの順に積層されたパッシベーション層１７４および樹脂層１７５を含む積層構造を有している。
　パッシベーション層１７４は、酸化シリコン層および窒化シリコン層のうちの少なくとも１つを含んでいてもよい。パッシベーション層１７４は、酸化シリコン層および窒化シリコン層を含む積層構造を有していてもよい。パッシベーション層１７４は、酸化シリコン層または窒化シリコン層からなる単層構造を有していてもよい。パッシベーション層１７４は、層間絶縁層１４０とは異なる絶縁材料を含むことが好ましい。パッシベーション層１７４は、この形態では、窒化シリコン層からなる単層構造を有している。
　パッシベーション層１７４は、層間絶縁層１４０に沿って膜状に形成されている。パッシベーション層１７４は、層間絶縁層１４０を挟んでアクティブ領域７２および外側領域７３を被覆している。パッシベーション層１７４は、アクティブ領域７２からサイドウォール構造１３２を横切って外側領域７３に引き出されている。パッシベーション層１７４は、サイドウォール構造１３２を被覆する上層構造の一部を形成している。
　パッシベーション層１７４は、第１ゲート開口１７６および第１ソース開口１７７を有している。第１ゲート開口１７６は、ゲートパッド１５３を露出させている。第１ソース開口１７７は、ソースパッド１５７を露出させている。第１ゲート開口１７６の平面形状は、任意である。第１ソース開口１７７の平面形状は、任意である。
　パッシベーション層１７４の厚さは、０．１μｍ以上２０μｍ以下であってもよい。パッシベーション層１７４の厚さは、０．１μｍ以上１μｍ以下、１μｍ以上５μｍ以下、５μｍ以上１０μｍ以下、１０μｍ以上１５μｍ以下、または、１５μｍ以上２０μｍ以下であってもよい。
　樹脂層１７５は、パッシベーション層１７４の主面に沿って膜状に形成されている。樹脂層１７５は、アクティブ領域７２からサイドウォール構造１３２を横切って外側領域７３に引き出されている。樹脂層１７５は、サイドウォール構造１３２を被覆する上層構造の一部を形成している。
　樹脂層１７５は、感光性樹脂を含んでいてもよい。感光性樹脂は、ネガティブタイプまたはポジティブタイプであってもよい。樹脂層１７５は、ポリイミド、ポリアミドおよびポリベンゾオキサゾールのうちの少なくとも１つを含んでいてもよい。樹脂層１７５は、この形態では、ポリベンゾオキサゾールを含む。
　樹脂層１７５の周縁は、この形態では、パッシベーション層１７４の周縁を露出させている。絶縁層１７０の周縁は、樹脂層１７５の周縁およびパッシベーション層１７４の周縁によって形成されている。樹脂層１７５は、パッシベーション層１７４の周縁を被覆していてもよい。
　樹脂層１７５は、第２ゲート開口１７８および第２ソース開口１７９を有している。第２ゲート開口１７８は、パッシベーション層１７４の第１ゲート開口１７６に連通し、第１ゲート開口１７６との間でゲートパッド開口１７２を形成している。第２ソース開口１７９は、パッシベーション層１７４の第１ソース開口１７７に連通し、第１ソース開口１７７との間でソースパッド開口１７３を形成している。
　第２ゲート開口１７８の内壁は、第１ゲート開口１７６の内壁に面一に形成されていてもよい。第２ゲート開口１７８の内壁は、平面視において第１ゲート開口１７６外に位置していてもよい。第２ゲート開口１７８の内壁は、平面視において第１ゲート開口１７６内に位置していてもよい。つまり、樹脂層１７５は、第１ゲート開口１７６の内壁を被覆していてもよい。
　第２ソース開口１７９の内壁は、第１ソース開口１７７の内壁に面一に形成されていてもよい。第２ソース開口１７９の内壁は、平面視において第１ソース開口１７７外に位置していてもよい。第２ソース開口１７９の内壁は、平面視において第１ソース開口１７７内に位置していてもよい。つまり、樹脂層１７５は、第１ソース開口１７７の内壁を被覆していてもよい。
　樹脂層１７５の厚さは、１μｍ以上５０μｍ以下であってもよい。樹脂層１７５の厚さは、１μｍ以上１０μｍ以下、１０μｍ以上２０μｍ以下、２０μｍ以上３０μｍ以下、３０μｍ以上４０μｍ以下、または、４０μｍ以上５０μｍ以下であってもよい。
　ＳｉＣ半導体装置６１は、外側主面１１２に形成された凹凸構造１８０（Uneven Structure）を含む。凹凸構造１８０は、より具体的には、外側主面１１２を被覆する層間絶縁層１４０を利用して形成された凹凸（Unevenness）を含む。凹凸構造１８０は、さらに具体的には、層間絶縁層１４０に形成されたアンカー孔１８１を含む。
　アンカー孔１８１は、層間絶縁層１４０において外側領域７３を被覆する部分を掘り下げることによって形成されている。アンカー孔１８１は、平面視においてダイオード領域１２１および側面６５Ａ～６５Ｄの間の領域に形成されていてもよい。アンカー孔１８１は、この形態では、平面視においてＦＬ構造１２３および側面６５Ａ～６５Ｄの間の領域に形成されている。
　アンカー孔１８１は、層間絶縁層１４０によって区画されていてもよい。アンカー孔１８１は、この形態では、外側主面１１２を露出させている。アンカー孔１８１は、外側主面１１２を第２主面６４に向けて掘り下げていてもよい。アンカー孔１８１の開口エッジ部は、アンカー孔１８１内に向かう湾曲状に形成されている。
　アンカー孔１８１は、平面視においてアクティブ領域７２に沿って帯状に延びている。アンカー孔１８１は、この形態では、平面視においてアクティブ領域７２を取り囲む環状（より具体的に無端状）に形成されている。アンカー孔１８１の個数は任意である。１つのアンカー孔１８１が層間絶縁層１４０に形成されていてもよいし、複数のアンカー孔１８１が層間絶縁層１４０に形成されていてもよい。
　樹脂層１７５は、アンカー孔１８１に噛合うアンカー部１８２を有している。樹脂層１７５は、この形態では、パッシベーション層１７４を介してアンカー孔１８１に噛合っている。パッシベーション層１７４は、より具体的には、層間絶縁層１４０の上からアンカー孔１８１に入り込んでいる。パッシベーション層１７４は、アンカー孔１８１内において外側主面１１２に接している。パッシベーション層１７４の主面においてアンカー孔１８１を被覆する部分には、アンカー孔１８１に向かって窪んだリセス１８３が形成されている。
　樹脂層１７５の一部は、パッシベーション層１７４のリセス１８３内においてアンカー部１８２を形成している。これにより、第１主面６３に対する樹脂層１７５の接続強度を高めることができるから、樹脂層１７５の剥離を適切に抑制できる。
　図１４および図１５を参照して、ＳｉＣ半導体装置６１は、第１主面電極１５０の上に形成されたパッド電極１９０を含む。パッド電極１９０は、より具体的には、ゲートパッド電極１９１およびソースパッド電極１９２を含む。
　ゲートパッド電極１９１は、ゲート主面電極１５１の上に形成され、ゲート主面電極１５１に電気的に接続されている。ゲートパッド電極１９１は、より具体的には、ゲートパッド開口１７２内においてゲートパッド１５３の上に形成されている。ゲートパッド電極１９１は、導線に外部接続されるゲート端子面１９３を有している。
　ゲート端子面１９３は、絶縁層１７０（樹脂層１７５）の主面に対してゲートパッド１５３側に位置している。ゲート端子面１９３は、絶縁層１７０（樹脂層１７５）の主面よりも上方に突出していてもよい。ゲート端子面１９３は、絶縁層１７０（樹脂層１７５）の主面を被覆するオーバラップ部を有していてもよい。
　ソースパッド電極１９２は、ソース主面電極１５２の上に形成され、ソース主面電極１５２に電気的に接続されている。ソースパッド電極１９２は、より具体的には、ソースパッド開口１７３内においてソースパッド１５７の上に形成されている。ソースパッド電極１９２は、導線に外部接続されるソース端子面１９４を有している。
　ソース端子面１９４は、絶縁層１７０（樹脂層１７５）の主面に対してソースパッド１５７側に位置している。ソース端子面１９４は、絶縁層１７０（樹脂層１７５）の主面よりも上方に突出していてもよい。ソース端子面１９４は、絶縁層１７０（樹脂層１７５）の主面を被覆するオーバラップ部を有していてもよい。
　パッド電極１９０（ゲートパッド電極１９１およびソースパッド電極１９２）は、第１主面電極１５０とは異なる金属材料を含む。パッド電極１９０は、この形態では、第１主面電極１５０側からこの順に積層されたＮｉ層１９５、Ｐｄ層１９６およびＡｕ層１９７を含む積層構造を有している。Ｎｉ、ＰｄおよびＡｕは、Ａｌのヤング率（剛性率）を超えるヤング率（剛性率）をそれぞれ有している。Ｎｉ層１９５、Ｐｄ層１９６およびＡｕ層１９７は、めっき法によって形成されためっき層であってもよい。
　パッド電極１９０は、Ｎｉ層１９５、Ｐｄ層１９６およびＡｕ層１９７のうちの少なくとも１つを含んでいればよい。パッド電極１９０は、Ｎｉ層１９５、Ｐｄ層１９６およびＡｕ層１９７のうちの少なくとも２つを任意の順序で積層した積層構造を有していてもよい。パッド電極１９０は、Ｎｉ層１９５、Ｐｄ層１９６またはＡｕ層１９７からなる単層構造を有していてもよい。
　ゲートパッド電極１９１は、Ａｕ層１９７によって形成されたゲート端子面１９３を有していることが好ましい。ソースパッド電極１９２は、Ａｕ層１９７によって形成されたソース端子面１９４を有していることが好ましい。パッド電極１９０は、少なくとも第１主面電極１５０側からこの順に積層されたＮｉ層１９５およびＡｕ層１９７を含む積層構造を有していることが好ましい。
　Ｎｉ層１９５の厚さは、０．１μｍ以上１０μｍ以下であってもよい。Ｎｉ層１９５の厚さは、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上４μｍ以下、４μｍ以上６μｍ以下、６μｍ以上８μｍ以下、または、８μｍ以上１０μｍ以下であってもよい。
　Ｐｄ層１９６の厚さは、０．１μｍ以上１０μｍ以下であってもよい。Ｐｄ層１９６の厚さは、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上４μｍ以下、４μｍ以上６μｍ以下、６μｍ以上８μｍ以下、または、８μｍ以上１０μｍ以下であってもよい。
　Ａｕ層１９７の厚さは、０．０１μｍ以上３μｍ以下であってもよい。Ａｕ層１９７の厚さは、０．０１μｍ以上０．０５μｍ以下、０．０５μｍ以上０．１μｍ以下、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、または、２μｍ以上３μｍ以下であってもよい。Ａｕ層１９７の厚さは、Ｎｉ層１９５の厚さ未満であることが好ましい。Ａｕ層１９７の厚さは、Ｐｄ層１９６の厚さ未満であることが好ましい。
　ＳｉＣ半導体装置６１は、第２主面６４の上に形成された第２主面電極２００を含む。第２主面電極２００は、ＭＩＳＦＥＴのドレイン電極として形成されている。第２主面電極２００は、この形態では、第２主面６４の全域を被覆している。
　第２主面電極２００は、側面６５Ａ～６５Ｄから内方に間隔を空けて形成され、第２主面６４の周縁部を露出させていてもよい。この場合、ＳｉＣウエハからＳｉＣ半導体装置６１を切り出す際に第２主面電極２００を物理的に切断せずに済む。これにより、ＳｉＣウエハからＳｉＣ半導体装置６１を円滑に切り出すことができると同時に、第２主面電極２００の剥離や劣化を抑制できる。その結果、第２主面電極２００を第２主面６４に適切に接続させることができる。
　このような第２主面電極２００は、一例として、製造工程時において、レジストマスクを介するエッチング法によって第２主面電極２００の不要な部分を除去することによって得ることができる。また、第２主面電極２００は、他の例として、製造工程時において、レジストマスクを用いたリフトオフ法によって第２主面６４を部分的に被覆する第２主面電極２００を形成することによって得ることができる。
　第２主面電極２００は、第２主面６４を被覆する第２Ａｌ層２０１を含む。第２Ａｌ層２０１は、ＳｉＣチップ６２を挟んでゲート主面電極１５１の第１Ａｌ層１６１およびソース主面電極１５２の第１Ａｌ層１６１に対向している。第２Ａｌ層２０１は、比較的小さいヤング率（剛性率）を有するＡｌのクッション性を利用してＳｉＣチップ６２に加えられる外力を第２主面６４側から緩和する第２緩衝層として形成されている。
　第２Ａｌ層２０１は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層およびＡｌＳｉＣｕ合金層のうちの少なくとも１つを含む。第２Ａｌ層２０１は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層およびＡｌＳｉＣｕ合金層のうちの２つ以上が任意の順序で積層された積層構造を有していてもよい。第２Ａｌ層２０１は、スパッタ法および／または蒸着法によって形成されていてもよい。
　第２Ａｌ層２０１は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層またはＡｌＳｉＣｕ合金層からなる単層構造を有していてもよい。第２Ａｌ層２０１のＡｌ系金属材料は、第１Ａｌ層１６１のＡｌ系金属材料とは異なっていてもよい。第２Ａｌ層２０１は、純Ａｌ層からなる単層構造を有していることが好ましい。
　第２Ａｌ層２０１は、第１Ａｌ層１６１の厚さ未満の厚さを有していてもよい。第２Ａｌ層２０１の厚さは、０．０１μｍ以上５μｍ以下であってもよい。第２Ａｌ層２０１の厚さは、０．０１μｍ以上０．１μｍ以下、０．１μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上３μｍ以下、３μｍ以上４μｍ以下、または、４μｍ以上５μｍ以下であってもよい。
　第２主面電極２００は、第２Ａｌ層２０１に加えて、第２Ａｌ層２０１とは異なる金属材料からなる１つまたは複数の電極層をさらに含む。第２主面電極２００は、この形態では、複数の電極層の一例として第２主面６４側からこの順に積層されたＴｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４、Ａｕ層２０５およびＡｇ層２０６を含む。
　Ｔｉ層２０２は、第２主面６４との間でオーミック接触を形成するオーミック電極である。第２Ａｌ層２０１は、Ｔｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４、Ａｕ層２０５およびＡｇ層２０６を挟んで第２主面６４を被覆している。
　Ｔｉ、Ｎｉ、Ｐｄ、ＡｕおよびＡｇは、Ａｌのヤング率（剛性率）を超えるヤング率（剛性率）をそれぞれ有している。Ｔｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４、Ａｕ層２０５およびＡｇ層２０６は、スパッタ法、蒸着法および／またはめっき法によって形成されていてもよい。
　第２主面電極２００は、１つまたは複数の電極層として、Ｔｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４、Ａｕ層２０５およびＡｇ層２０６のうちの少なくとも１つを含んでいればよい。第２Ａｌ層２０１は、少なくともＴｉ層２０２を挟んで第２主面６４を被覆していることが好ましい。
　第２主面電極２００がＮｉ層２０３、Ｐｄ層２０４およびＡｕ層２０５のうちの少なくとも１つを含む場合、Ｎｉ層２０３、Ｐｄ層２０４およびＡｕ層２０５のうちの少なくとも１つは、パッド電極１９０のＮｉ層１９５、Ｐｄ層１９６およびＡｕ層１９７と同時に形成されためっき層であってもよい。
　Ｔｉ層２０２の厚さは、０．０１μｍ以上３μｍ以下であってもよい。Ｔｉ層２０２の厚さは、０．０１μｍ以上０．０５μｍ以下、０．０５μｍ以上０．１μｍ以下、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、または、２μｍ以上３μｍ以下であってもよい。
　Ｎｉ層２０３の厚さは、０．１μｍ以上１０μｍ以下であってもよい。Ｎｉ層２０３の厚さは、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上４μｍ以下、４μｍ以上６μｍ以下、６μｍ以上８μｍ以下、または、８μｍ以上１０μｍ以下であってもよい。Ｎｉ層２０３の厚さは、Ｔｉ層２０２の厚さを超えていることが好ましい。
　Ｐｄ層２０４の厚さは、０．１μｍ以上１０μｍ以下であってもよい。Ｐｄ層２０４の厚さは、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、２μｍ以上４μｍ以下、４μｍ以上６μｍ以下、６μｍ以上８μｍ以下、または、８μｍ以上１０μｍ以下であってもよい。Ｐｄ層２０４の厚さは、Ｔｉ層２０２の厚さを超えていることが好ましい。
　Ａｕ層２０５の厚さは、０．０１μｍ以上３μｍ以下であってもよい。Ａｕ層２０５の厚さは、０．０１μｍ以上０．０５μｍ以下、０．０５μｍ以上０．１μｍ以下、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、または、２μｍ以上３μｍ以下であってもよい。Ａｕ層２０５の厚さは、Ｎｉ層２０３の厚さ未満であることが好ましい。Ａｕ層２０５の厚さは、Ｐｄ層２０４の厚さ未満であることが好ましい。
　Ａｇ層２０６の厚さは、０．０１μｍ以上３μｍ以下であってもよい。Ａｇ層２０６の厚さは、０．０１μｍ以上０．０５μｍ以下、０．０５μｍ以上０．１μｍ以下、０．１μｍ以上０．５μｍ以下、０．５μｍ以上１μｍ以下、１μｍ以上２μｍ以下、または、２μｍ以上３μｍ以下であってもよい。Ａｇ層２０６の厚さは、Ｎｉ層２０３の厚さ未満であることが好ましい。Ａｇ層２０６の厚さは、Ｐｄ層２０４の厚さ未満であることが好ましい。
　第２主面電極２００は、図１７Ａ～図１７Ｉに示される構造を有していてもよい。
　図１７Ａは、第２形態例に係る第２主面電極２００を図解的に示す断面図である。以下では、図６～図１６において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図１７Ａを参照して、第２主面電極２００は、この形態では、第２Ａｌ層２０１、Ｔｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４およびＡｕ層２０５を含む積層構造を有している。Ｔｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４およびＡｕ層２０５は、第２主面６４側からこの順に積層されている。第２Ａｌ層２０１は、Ｔｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４およびＡｕ層２０５を挟んで第２主面６４を被覆している。
　図１７Ｂは、第３形態例に係る第２主面電極２００を図解的に示す断面図である。以下では、図６～図１６において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図１７Ｂを参照して、第２主面電極２００は、この形態では、第２Ａｌ層２０１、Ｔｉ層２０２、Ｎｉ層２０３、Ａｕ層２０５およびＡｇ層２０６を含む積層構造を有している。Ｔｉ層２０２、Ｎｉ層２０３、Ａｕ層２０５およびＡｇ層２０６は、第２主面６４側からこの順に積層されている。第２Ａｌ層２０１は、Ｔｉ層２０２、Ｎｉ層２０３、Ａｕ層２０５およびＡｇ層２０６を挟んで第２主面６４を被覆している。
　図１７Ｃは、第４形態例に係る第２主面電極２００を図解的に示す断面図である。以下では、図６～図１６において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図１７Ｃを参照して、第２主面電極２００は、この形態では、第２Ａｌ層２０１、Ｔｉ層２０２、Ｎｉ層２０３およびＡｕ層２０５を含む積層構造を有している。Ｔｉ層２０２、Ｎｉ層２０３およびＡｕ層２０５は、第２主面６４側からこの順に積層されている。第２Ａｌ層２０１は、Ｔｉ層２０２、Ｎｉ層２０３およびＡｕ層２０５を挟んで第２主面６４を被覆している。
　図１７Ｄは、第５形態例に係る第２主面電極２００を図解的に示す断面図である。以下では、図６～図１６において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図１７Ｄを参照して、第２主面電極２００は、この形態では、第２Ａｌ層２０１およびＴｉ層２０２を含む積層構造を有している。Ｔｉ層２０２は、第２主面６４に接続されている。第２Ａｌ層２０１は、Ｔｉ層２０２を挟んで第２主面６４を被覆している。
　図１７Ｅは、第６形態例に係る第２主面電極２００を図解的に示す断面図である。以下では、図６～図１６において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図１７Ｅを参照して、第２主面電極２００は、この形態では、第２Ａｌ層２０１、Ｔｉ層２０２、Ｎｉ層２０３およびＡｕ層２０５を含む。Ｔｉ層２０２、Ｎｉ層２０３およびＡｕ層２０５は、第２主面６４側からこの順に積層されている。第２Ａｌ層２０１は、Ｔｉ層２０２およびＮｉ層２０３の間に介在し、Ｔｉ層２０２を挟んで第２主面６４を被覆している。
　この場合、パッド電極１９０は、第１主面電極１５０側からこの順に積層されたＮｉ層１９５およびＡｕ層１９７からなる２層構造を有していることが好ましい。第２主面電極２００のＮｉ層２０３およびＡｕ層２０５は、めっき法によって、パッド電極１９０のＮｉ層１９５およびＡｕ層１９７と同時に形成されることができる。
　図１７Ｆは、第７形態例に係る第２主面電極２００を図解的に示す断面図である。以下では、図６～図１６において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図１７Ｆを参照して、第２主面電極２００は、この形態では、第２Ａｌ層２０１、Ｔｉ層２０２、Ｎｉ層２０３、Ａｕ層２０５およびＡｇ層２０６を含む。Ｔｉ層２０２、Ｎｉ層２０３、Ａｕ層２０５およびＡｇ層２０６は、第２主面６４側からこの順に積層されている。第２Ａｌ層２０１は、Ｔｉ層２０２およびＮｉ層２０３の間に介在し、Ｔｉ層２０２を挟んで第２主面６４を被覆している。
　この場合、パッド電極１９０は、第１主面電極１５０側からこの順に積層されたＮｉ層１９５およびＡｕ層１９７からなる２層構造を有していることが好ましい。第２主面電極２００のＮｉ層２０３およびＡｕ層２０５は、めっき法によって、パッド電極１９０のＮｉ層１９５およびＡｕ層１９７と同時に形成されることができる。
　図１７Ｇは、第８形態例に係る第２主面電極２００を図解的に示す断面図である。以下では、図６～図１６において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図１７Ｇを参照して、第２主面電極２００は、この形態では、第２Ａｌ層２０１、Ｔｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４、Ａｕ層２０５およびＡｇ層２０６を含む。Ｔｉ層２０２、Ｎｉ層２０３、Ａｕ層２０５およびＡｇ層２０６は、第２主面６４側からこの順に積層されている。第２Ａｌ層２０１は、Ｔｉ層２０２およびＮｉ層２０３の間に介在し、Ｔｉ層２０２を挟んで第２主面６４を被覆している。
　この場合、パッド電極１９０は、第１主面電極１５０側からこの順に積層されたＮｉ層１９５、Ｐｄ層１９６およびＡｕ層１９７からなる３層構造を有していることが好ましい。第２主面電極２００のＮｉ層２０３、Ｐｄ層２０４およびＡｕ層２０５は、めっき法によって、パッド電極１９０のＮｉ層１９５、Ｐｄ層１９６およびＡｕ層１９７と同時に形成されることができる。
　図１７Ｈは、第９形態例に係る第２主面電極２００を図解的に示す断面図である。以下では、図６～図１６において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図１７Ｈを参照して、第２主面電極２００は、この形態では、第２Ａｌ層２０１、Ｔｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４およびＡｕ層２０５を含む。Ｔｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４およびＡｕ層２０５は、第２主面６４側からこの順に積層されている。第２Ａｌ層２０１は、Ｔｉ層２０２およびＮｉ層２０３の間に介在し、Ｔｉ層２０２を挟んで第２主面６４を被覆している。
　この場合、パッド電極１９０は、第１主面電極１５０側からこの順に積層されたＮｉ層１９５、Ｐｄ層１９６およびＡｕ層１９７からなる３層構造を有していることが好ましい。第２主面電極２００のＮｉ層２０３、Ｐｄ層２０４およびＡｕ層２０５は、めっき法によって、パッド電極１９０のＮｉ層１９５、Ｐｄ層１９６およびＡｕ層１９７と同時に形成されることができる。
　図１７Ｉは、第１０形態例に係る第２主面電極２００を図解的に示す断面図である。以下では、図６～図１６において述べた構造に対応する構造については同一の参照符号を付して、説明を省略する。
　図１７Ｉを参照して、第２主面電極２００は、この形態では、第２Ａｌ層２０１およびシリサイド層２０７を含む。シリサイド層２０７は、第２主面６４に形成されている。シリサイド層２０７は、第２主面６４から露出するＳｉＣを金属材料によってシリサイド化することによって形成されている。シリサイド層２０７は、ＦｅＳｉ２層、ＮｉＳｉ層、ＮｉＳｉ２層、ＣｏＳｉ２層、ＣｒＳｉ２層、ＷＳｉ２層、ＭｏＳｉ２層、ＭｎＳｉ２層、ＮｂＳｉ２層、ＴｉＳｉ２層およびＶＳｉ２層のうちの少なくとも１つを含んでいてもよい。
　第２Ａｌ層２０１は、シリサイド層２０７を挟んで第２主面６４を被覆している。第２主面電極２００は、第２Ａｌ層２０１およびシリサイド層２０７の他、Ｔｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４、Ａｕ層２０５およびＡｇ層２０６のうちの少なくとも１つを含んでいてもよい。第２Ａｌ層２０１、Ｔｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４、Ａｕ層２０５およびＡｇ層２０６の積層順序は任意である。シリサイド層２０７を被覆する構造として、第１～第１０形態例のいずれか１つの積層構造が採用されてもよい。
　図１８は、図６に示すＳｉＣ半導体装置６１が組み込まれた半導体パッケージ２１１を示す図である。図１８では、半導体パッケージ２１１の内部構造が、パッケージ本体２１２を透過して示されている。
　図１８を参照して、半導体パッケージ２１１は、この形態では、３端子型のＴＯ－２２０である。半導体パッケージ２１１は、パッケージ本体２１２、金属プレート２１３、第１端子２１４、第２端子２１５、第３端子２１６、ＳｉＣ半導体装置６１、導電接合材２１７、第１導線２１８および第２導線２１９を含む。
　パッケージ本体２１２は、モールド樹脂からなる。パッケージ本体２１２は、モールド樹脂の一例としてのエポキシ樹脂を含んでいてもよい。パッケージ本体２１２は、直方体形状に形成されている。パッケージ本体２１２は、一方側の第１面２２１および他方側の第２面２２２、ならびに、第１面２２１および第２面２２２を接続する４つの側面２２３Ａ，２２３Ｂ，２２３Ｃ，２２３Ｄを含む。
　４つの側面２２３Ａ～２２３Ｄは、より具体的には、第１側面２２３Ａ、第２側面２２３Ｂ、第３側面２２３Ｃおよび第４側面２２３Ｄを含む。第１側面２２３Ａおよび第２側面２２３Ｂは、互いに対向している。第３側面２２３Ｃおよび第４側面２２３Ｄは、互いに対向している。
　金属プレート２１３は、Ｆｅ、Ａｕ、Ａｇ、ＣｕおよびＡｌのうちの少なくとも１つを含んでいてもよい。金属プレート２１３は、Ｎｉめっき膜、Ａｕめっき膜、Ａｇめっき膜およびＣｕめっき膜のうちの少なくとも１つが形成された外面を有していてもよい。金属プレート２１３の平面形状は任意である。金属プレート２１３は、この形態では、平面視において四角形状（長方形状）に形成されている。
　金属プレート２１３は、より具体的には、パッケージ本体２１２内に位置するパッド部２２４、および、パッケージ本体２１２外に位置するヒートシンク部２２５を一体的に含む。ヒートシンク部２２５は、パッド部２２４から第２側面２２３Ｂを横切ってパッケージ本体２１２外に引き出されている。ヒートシンク部２２５は、貫通孔２２５ａを含む。貫通孔２２５ａは、円形状に形成されている。ヒートシンク部２２５の平面面積は、パッド部２２４の平面面積を超えていてもよい。
　金属プレート２１３は、この形態では、第２面２２２から露出するようにパッケージ本体２１２内に配置されている。金属プレート２１３は、第２面２２２から露出しないようにパッケージ本体２１２内に配置されていてもよい。
　第１端子２１４は、Ｆｅ、Ａｕ、Ａｇ、ＣｕおよびＡｌのうちの少なくとも１つを含んでいてもよい。第１端子２１４は、Ｎｉめっき膜、Ａｕめっき膜、Ａｇめっき膜およびＣｕめっき膜のうちの少なくとも１つが形成された外面を有していてもよい。第１端子２１４は、パッケージ本体２１２内から第１側面２２３Ａを横切ってパッケージ本体２１２外に引き出されている。
　第１端子２１４は、平面視において第１側面２２３Ａの中央部に配置されている。第１端子２１４は、金属プレート２１３の板面に対して第１面２２１側の領域に配置されている。
　第１端子２１４は、第１内端部２２６、第１外端部２２７および第１帯状部２２８を含む。第１内端部２２６は、パッケージ本体２１２内において金属プレート２１３に接続されている。第１外端部２２７は、パッケージ本体２１２外に配置されている。第１帯状部２２８は、第１内端部２２６および第１外端部２２７の間を第１側面２２３Ａに直交する方向に延びている。
　第２端子２１５は、Ｆｅ、Ａｕ、Ａｇ、ＣｕおよびＡｌのうちの少なくとも１つを含んでいてもよい。第２端子２１５は、Ｎｉめっき膜、Ａｕめっき膜、Ａｇめっき膜およびＣｕめっき膜のうちの少なくとも１つが形成された外面を有していてもよい。第２端子２１５は、パッケージ本体２１２内から第１側面２２３Ａを横切ってパッケージ本体２１２外に引き出されている。
　第２端子２１５は、平面視において第１端子２１４から間隔を空けて第３側面２２３Ｃ側の領域に配置されている。第２端子２１５は、金属プレート２１３の板面に対して第１面２２１側の領域に配置されている。
　第２端子２１５は、第２内端部２２９、第２外端部２３０および第２帯状部２３１を含む。第２内端部２２９は、金属プレート２１３から間隔を空けてパッケージ本体２１２内に配置されている。第２外端部２３０は、パッケージ本体２１２外に配置されている。第２帯状部２３１は、第２内端部２２９および第２外端部２３０の間を第１側面２２３Ａに直交する方向に延びている。
　第３端子２１６は、Ｆｅ、Ａｕ、Ａｇ、ＣｕおよびＡｌの少なくとも１つを含んでいてもよい。第３端子２１６は、Ｎｉめっき膜、Ａｕめっき膜、Ａｇめっき膜およびＣｕめっき膜の少なくとも１つが形成された外面を有していてもよい。第３端子２１６は、パッケージ本体２１２内から第１側面２２３Ａを横切ってパッケージ本体２１２外に引き出されている。
　第３端子２１６は、平面視において第１端子２１４から間隔を空けて第４側面２２３Ｄ側の領域に配置されている。第３端子２１６は、金属プレート２１３の板面に対して第１面２２１側の領域に配置されている。
　第３端子２１６は、第３内端部２３２、第３外端部２３３および第３帯状部２３４を含む。第３内端部２３２は、金属プレート２１３から間隔を空けてパッケージ本体２１２内に配置されている。第３外端部２３３は、パッケージ本体２１２外に配置されている。第３帯状部２３４は、第３内端部２３２および第３外端部２３３の間を第１側面２２３Ａに直交する方向に延びている。
　ＳｉＣ半導体装置６１は、パッケージ本体２１２内において金属プレート２１３のパッド部２２４の上に配置されている。導電接合材２１７は、ＳｉＣ半導体装置６１およびパッド部２２４の間に介在し、ＳｉＣ半導体装置６１の第２主面電極２００をパッド部２２４に接合させている。これにより、ＳｉＣ半導体装置６１は、金属プレート２１３を介して第１端子２１４に電気的に接続されている。
　導電接合材２１７は、金属ペーストまたは半田であってもよい。金属ペーストは、Ａｕ、ＡｇおよびＣｕのうちの少なくとも１つを含んでいてもよい。導電接合材２１７は、半田からなることが好ましい。半田は、鉛フリー半田であってもよい。半田は、ＳｎＡｇＣｕ、ＳｎＺｎＢｉ、ＳｎＣｕ、ＳｎＣｕＮｉおよびＳｎＳｂＮｉのうちの少なくとも１つを含んでいてもよい。
　第１導線２１８は、金属ワイヤ（ボンディングワイヤ）または金属クリップからなる。金属ワイヤは、Ａｌワイヤ、Ａｕワイヤ、Ｃｕワイヤまたは半田ワイヤであってもよい。半田ワイヤは、鉛フリー半田ワイヤであってもよい。半田ワイヤは、ＳｎＡｇＣｕ、ＳｎＺｎＢｉ、ＳｎＣｕ、ＳｎＣｕＮｉおよびＳｎＳｂＮｉのうちの少なくとも１つを含んでいてもよい。金属クリップは、Ａｌクリップ、ＡｕクリップまたはＣｕクリップであってもよい。第１導線２１８は、この形態では、半田ワイヤからなる。
　第１導線２１８は、パッケージ本体２１２内において第２端子２１５の第２内端部２２９およびＳｉＣ半導体装置６１のゲートパッド電極１９１に接続されている。これにより、ＳｉＣ半導体装置６１は、第２端子２１５に電気的に接続されている。
　図１８では、１つの第１導線２１８が第２内端部２２９およびゲートパッド電極１９１に接続されている例が示されているが、第１導線２１８の個数は任意である。２つ以上の第１導線２１８が第２内端部２２９およびゲートパッド電極１９１に接続されていてもよい。
　第２導線２１９は、金属ワイヤ（ボンディングワイヤ）または金属クリップからなる。金属ワイヤは、Ａｌワイヤ、Ａｕワイヤ、Ｃｕワイヤまたは半田ワイヤであってもよい。半田ワイヤは、鉛フリー半田ワイヤであってもよい。半田ワイヤは、ＳｎＡｇＣｕ、ＳｎＺｎＢｉ、ＳｎＣｕ、ＳｎＣｕＮｉおよびＳｎＳｂＮｉのうちの少なくとも１つを含んでいてもよい。金属クリップは、Ａｌクリップ、ＡｕクリップまたはＣｕクリップであってもよい。第２導線２１９は、この形態では、半田ワイヤからなる。
　第２導線２１９は、パッケージ本体２１２内において第３端子２１６の第３内端部２３２およびＳｉＣ半導体装置６１のソースパッド電極１９２に接続されている。これにより、ＳｉＣ半導体装置６１は、第３端子２１６に電気的に接続されている。
　図１８では、２つの第２導線２１９が第３内端部２３２およびソースパッド電極１９２に接続されている例が示されているが、第２導線２１９の個数は任意である。１つまたは３つ以上の第２導線２１９が第３内端部２３２およびソースパッド電極１９２に接続されていてもよい。
　半導体パッケージ２１１は、ＴＯ－２２０以外の形態も採り得る。半導体パッケージ２１１は、ＳＯＰ（Small Outline Package）、ＱＦＮ（Quad For Non Lead Package）、ＤＦＰ（Dual Flat Package）、ＤＩＰ（Dual Inline Package）、ＱＦＰ（Quad Flat Package）、ＳＩＰ（Single Inline Package）もしくはＳＯＪ（Small Outline J-leaded Package）、または、これらに類する種々の形態を有していてもよい。
　以上、ＳｉＣ半導体装置６１によれば、第１Ａｌ層１６１が第１主面６３側で外力を緩和する第１緩衝層として形成され、第２Ａｌ層２０１が第２主面６４側で外力を緩和する第２緩衝層として形成されている。これにより、第１主面６３から第２主面６４に向かう方向の外力、および、第２主面６４から第１主面６３に向かう方向の外力を緩和できる。
　一例として、ＳｉＣ半導体装置６１を金属プレート２１３のパッド部２２４に実装する際にＳｉＣチップ６２に加えられる外力を第１Ａｌ層１６１および第２Ａｌ層２０１によって緩和できる。また、ＳｉＣ半導体装置６１のパッド電極１９０に第１導線２１８および第２導線２１９を接合する際にＳｉＣチップ６２に加えられる外力を第１Ａｌ層１６１および第２Ａｌ層２０１によって緩和できる。その結果、ＳｉＣチップ６２のクラックを抑制できる。
　また、ＳｉＣ半導体装置６１は、第１導線２１８および第２導線２１９に外部接合されるパッド電極１９０（ゲートパッド電極１９１およびソースパッド電極１９２）を含む。パッド電極１９０は、Ｎｉ層１９５、Ｐｄ層１９６およびＡｕ層１９７のうちの少なくとも１つを含む。これにより、第１導線２１８および第２導線２１９をパッド電極１９０に適切に接続されることができる。
　一方、Ｎｉ、ＰｄおよびＡｕは、Ａｌのヤング率（剛性率）を超えるヤング率（剛性率）をそれぞれ有している。したがって、パッド電極１９０を備えた構造では、第１導線２１８および第２導線２１９の接合時に加えられる外力を適切に緩和できない。
　そこで、ＳｉＣ半導体装置６１では、ＳｉＣチップ６２およびパッド電極１９０の間にＡｌを含む第１Ａｌ層１６１を介在させている。第１Ａｌ層１６１によれば、比較的小さいヤング率（剛性率）を有するＡｌのクッション性を利用してＳｉＣチップ６２に加えられる外力を第１主面６３側から緩和できる。よって、第１導線２１８および第２導線２１９をパッド電極１９０に適切に接合させることができると同時に、ＳｉＣチップ６２のクラックを抑制できる。
　また、ＳｉＣ半導体装置６１は、第２Ａｌ層２０１に加えて、第２Ａｌ層２０１とは異なる金属材料からなる１つまたは複数の電極層を有する第２主面電極２００を含む。１つまたは複数の電極層は、Ｔｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４、Ａｕ層２０５およびＡｇ層２０６のうちの少なくとも１つを含む。これにより、第２主面電極２００に対する導電接合材２１７の密着力を適切に高めることができる。その結果、ＳｉＣ半導体装置６１を金属プレート２１３のパッド部２２４に適切に実装できる。
　一方、Ｔｉ、Ｎｉ、Ｐｄ、ＡｕおよびＡｇは、Ａｌのヤング率（剛性率）を超えるヤング率（剛性率）をそれぞれ有している。したがって、第２主面電極２００がＴｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４、Ａｕ層２０５およびＡｇ層２０６のうちの少なくとも１つを含む構造では、ＳｉＣ半導体装置６１の実装時や第１導線２１８および第２導線２１９の接合時に加えられる外力を適切に緩和できない。
　そこで、ＳｉＣ半導体装置６１では、Ｔｉ層２０２、Ｎｉ層２０３、Ｐｄ層２０４、Ａｕ層２０５およびＡｇ層２０６のうちの少なくとも１つに加えて、第２Ａｌ層２０１を含む第２主面電極２００を形成している。第２Ａｌ層２０１によれば、比較的小さいヤング率（剛性率）を有するＡｌのクッション性を利用してＳｉＣチップ６２に加えられる外力を第２主面６４側から緩和できる。よって、ＳｉＣ半導体装置６１をパッド部２２４に適切に実装できると同時に、ＳｉＣチップ６２のクラックを抑制できる。
　本発明の実施形態はさらに他の形態で実施することもできる。
　前述の第１実施形態では、絶縁層１７がパッシベーション層１９および樹脂層２０を含む積層構造を有している例について説明した。しかし、絶縁層１７は、パッシベーション層１９または樹脂層２０からなる単層構造を有していてもよい。
　前述の第１実施形態では、ダイオードの一例としてのＳＢＤが形成された例について説明した。しかし、ｎ型のダイオード領域１０に代えてｐ型のダイオード領域１０が形成されてもよい。この場合、ＳＢＤに代えてｐｎ接合ダイオードを提供できる。
　前述の第２実施形態では、絶縁層１７０がパッシベーション層１７４および樹脂層１７５を含む積層構造を有している例について説明した。しかし、絶縁層１７０は、パッシベーション層１７４または樹脂層１７５からなる単層構造を有していてもよい。
　前述の第２実施形態では、ｐ型不純物が添加されたｐ型ポリシリコンを含むゲート電極８０およびゲート配線８５が形成された例について説明した。しかし、ゲート閾値電圧Ｖｔｈの増加を重視しない場合には、ゲート電極８０およびゲート配線８５は、ｐ型ポリシリコンに代えてまたはこれに加えて、ｎ型不純物が添加されたｎ型ポリシリコンを含んでいてもよい。
　この場合、低抵抗層８６は、ゲート電極８０（ｎ型ポリシリコン）において表層部を形成する部分を金属材料によってシリサイド化することによって形成されていてもよい。つまり、低抵抗層８６は、ｎ型ポリサイドを含んでいてもよい。このような構造の場合、ゲート抵抗を低減できる。
　前述の第２実施形態では、絶縁ゲート型トランジスタの一例としてのＭＩＳＦＥＴが形成された例について説明した。しかし、ｎ＋型のドレイン領域６８に代えてｐ＋型のコレクタ領域が採用されてもよい。この構造によれば、ＭＩＳＦＥＴに代えて、ＩＧＢＴ（Insulated Gate Bipolar Transistor）を提供できる。この場合、前述の第２実施形態において、ＭＩＳＦＥＴの「ソース」がＩＧＢＴの「エミッタ」に読み替えられ、ＭＩＳＦＥＴの「ドレイン」がＩＧＢＴの「コレクタ」に読み替えられる。
　前述の各実施形態において、各半導体部分の導電型が反転された構造が採用されてもよい。つまり、ｐ型の部分がｎ型とされ、ｎ型の部分がｐ型とされてもよい。
　以下、この明細書および図面から抽出される特徴の例を示す。
　後工程（アセンブリ工程）では、様々な外力が半導体装置に加えられる。たとえば、半導体装置の実装時には、吸着ノズルを備えた実装機が使用される。半導体装置は、吸着ノズルに吸着保持された状態で接続対象物まで搬送された後、接続対象部に押圧実装される。この時、吸着ノズルから接続対象物に向かう外力、および、接続対象物から吸着ノズルに向かう外力が半導体装置に加えられる。
　また、半導体装置の実装後には、キャピラリによって導線がパッド電極に押圧接合される。この時、キャピラリから接続対象物に向かう外力、および、接続対象物からキャピラリに向かう外力が半導体装置に加えられる。チップの強度を超える外力が半導体装置に加えられると、チップにクラックが発生する。以下では、外力を緩和できる半導体装置を提供する。
　［Ａ１］一方側の第１主面および他方側の第２主面を有するチップと、第１Ａｌ層を含み、前記第１主面の上に形成された第１主面電極と、前記第１主面電極の上に形成され、導線に接続されるパッド電極と、第２Ａｌ層を含み、前記第２主面の上に形成された第２主面電極と、を含む、半導体装置。
　この半導体装置によれば、第１Ａｌ層が第１主面側で外力を緩和する第１緩衝層として形成され、第２Ａｌ層が第２主面側で外力を緩和する第２緩衝層として形成されている。これにより、第１主面から第２主面に向かう方向の外力、および、第２主面から第１主面に向かう方向の外力を緩和できる。
　［Ａ２］前記第１主面の上において前記第１主面電極を被覆し、前記第１主面電極の一部を露出させるパッド開口を有する絶縁層をさらに含み、前記パッド電極は、前記パッド開口内において前記第１主面電極の上に形成されている、Ａ１に記載の半導体装置。
　［Ａ３］前記チップは、前記第１主面および前記第２主面を接続する側面を有し、前記絶縁層は、前記第１主面の上において前記側面から間隔を空けて形成された周縁を有している、Ａ２に記載の半導体装置。
　［Ａ４］前記絶縁層は、樹脂層を含む、Ａ２またはＡ３に記載の半導体装置。
　［Ａ５］前記パッド電極は、前記第１主面電極とは異なる金属材料を含む、Ａ１～Ａ４のいずれか一つに記載の半導体装置。
　［Ａ６］前記パッド電極は、Ｎｉ層、Ｐｄ層およびＡｕ層のうちの少なくとも１つを含む、Ａ１～Ａ５のいずれか一つに記載の半導体装置。
　［Ａ７］前記パッド電極は、前記第１主面電極側からこの順に積層されたＮｉ層およびＡｕ層を含む、Ａ１～Ａ６のいずれか一つに記載の半導体装置。
　［Ａ８］前記パッド電極は、前記第１主面電極側からこの順に積層されたＮｉ層、Ｐｄ層およびＡｕ層を含む、Ａ１～Ａ７のいずれか一つに記載の半導体装置。
　［Ａ９］前記第２主面電極は、前記第２Ａｌ層とは異なる金属材料からなる１つまたは複数の電極層を含み、前記第２Ａｌ層は、１つまたは複数の前記電極層を被覆している、Ａ１～Ａ８のいずれか一つに記載の半導体装置。
　［Ａ１０］１つまたは複数の前記電極層は、Ｔｉ層、Ｎｉ層、Ｐｄ層、Ａｕ層およびＡｇ層のうちの少なくとも１つを含む、Ａ９に記載の半導体装置。
　［Ａ１１］１つまたは複数の前記電極層は、少なくとも前記第２主面との間でオーミック接触を形成するオーミック電極層を含み、前記第２Ａｌ層は、少なくとも前記オーミック電極層を被覆している、Ａ９またはＡ１０に記載の半導体装置。
　［Ａ１２］前記第２Ａｌ層は、前記第１Ａｌ層未満の厚さを有している、Ａ１～Ａ１１のいずれか一つに記載の半導体装置。
　［Ａ１３］前記第２Ａｌ層は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層およびＡｌＳｉＣｕ合金層のうちの少なくとも１つを含む、Ａ１～Ａ１２のいずれか一つに記載の半導体装置。
　［Ａ１４］前記第２Ａｌ層は、純Ａｌ層からなる、Ａ１～Ａ１３のいずれか一つに記載の半導体装置。
　［Ａ１５］前記第１Ａｌ層は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層およびＡｌＳｉＣｕ合金層のうちの少なくとも１つを含む、Ａ１～Ａ１４のいずれか一つに記載の半導体装置。
　［Ａ１６］前記第１主面に形成されたダイオードをさらに含み、前記第１主面電極は、前記ダイオードのアノードに電気的に接続されたアノード電極を形成し、前記第２主面電極は、前記ダイオードのカソードに電気的に接続されたカソード電極を形成している、Ａ１～Ａ１５のいずれか一つに記載の半導体装置。
　［Ａ１７］前記第１主面に形成されたＭＩＳＦＥＴをさらに含み、前記第１主面電極は、前記ＭＩＳＦＥＴのゲートに電気的に接続されたゲート主面電極、および、前記ＭＩＳＦＥＴのソースに電気的に接続されたソース主面電極を含み、前記パッド電極は、前記ゲート主面電極の上に形成されたゲートパッド電極、および、前記ソース主面電極の上に形成されたソースパッド電極を含み、前記第２主面電極は、前記ＭＩＳＦＥＴのドレインに電気的に接続されたドレイン電極を形成している、Ａ１～Ａ１６のいずれか一つに記載の半導体装置。
　［Ａ１８］前記チップは、前記第２主面側から前記第１主面側に向けてこの順に積層された半導体基板およびエピタキシャル層を含む積層構造を有している、Ａ１～Ａ１７のいずれか一つに記載の半導体装置。
　［Ａ１９］前記チップの厚さは、３００μｍ以下である、Ａ１～Ａ１８のいずれか一つに記載の半導体装置。
　［Ａ２０］前記チップは、ＳｉＣ単結晶によって形成されたＳｉＣチップからなる、Ａ１～Ａ１９のいずれか一つに記載の半導体装置。
　この出願は、２０１９年４月１９日に日本国特許庁に提出された特願２０１９－０８０２２７号に対応しており、この出願の全開示はここに引用により組み込まれる。本発明の実施形態について詳細に説明してきたが、これらは本発明の技術的内容を明らかにするために用いられた具体例に過ぎず、本発明はこれらの具体例に限定して解釈されるべきではなく、本発明の範囲は添付の請求の範囲によってのみ限定される。
１　　　ＳｉＣ半導体装置
２　　　ＳｉＣチップ
３　　　第１主面
４　　　第２主面
５Ａ　　第１側面
５Ｂ　　第２側面
５Ｃ　　第３側面
５Ｄ　　第４側面
６　　　ＳｉＣ半導体基板
７　　　ＳｉＣエピタキシャル層
１４　　第１主面電極
１６　　第１Ａｌ層
１７　　絶縁層
１８　　パッド開口
２０　　樹脂層
２３　　パッド電極
２５　　Ｎｉ層
２６　　Ｐｄ層
２７　　Ａｕ層
３１　　第２主面電極
３２　　第２Ａｌ層
３３　　Ｔｉ層
３４　　Ｎｉ層
３５　　Ｐｄ層
３６　　Ａｕ層
３７　　Ａｇ層
６１　　ＳｉＣ半導体装置
６２　　ＳｉＣチップ
６３　　第１主面
６４　　第２主面
６５Ａ　第１側面
６５Ｂ　第２側面
６５Ｃ　第３側面
６５Ｄ　第４側面
６６　　ＳｉＣ半導体基板
６７　　ＳｉＣエピタキシャル層
１５０　第１主面電極
１５１　ゲート主面電極
１５２　ソース主面電極
１６１　第１Ａｌ層
１７０　絶縁層
１７１　パッド開口
１７２　ゲートパッド開口
１７３　ソースパッド開口
１７５　樹脂層
１９０　パッド電極
１９１　ゲートパッド電極
１９２　ソースパッド電極
１９５　Ｎｉ層
１９６　Ｐｄ層
１９７　Ａｕ層
２００　第２主面電極
２０１　第２Ａｌ層
２０２　Ｔｉ層
２０３　Ｎｉ層
２０４　Ｐｄ層
２０５　Ａｕ層
２０６　Ａｇ層

Claims (19)

  1. 　一方側の第１主面および他方側の第２主面を有するＳｉＣチップと、
    　第１Ａｌ層を含み、前記第１主面の上に形成された第１主面電極と、
    　前記第１主面電極の上に形成され、導線に接続されるパッド電極と、
    　第２Ａｌ層を含み、前記第２主面の上に形成された第２主面電極と、を含む、ＳｉＣ半導体装置。
  2. 　前記第１主面の上において前記第１主面電極を被覆し、前記第１主面電極の一部を露出させるパッド開口を有する絶縁層をさらに含み、
    　前記パッド電極は、前記パッド開口内において前記第１主面電極の上に形成されている、請求項１に記載のＳｉＣ半導体装置。
  3. 　前記ＳｉＣチップは、前記第１主面および前記第２主面を接続する側面を有し、
    　前記絶縁層は、前記第１主面の上において前記側面から間隔を空けて形成された周縁を有している、請求項２に記載のＳｉＣ半導体装置。
  4. 　前記絶縁層は、樹脂層を含む、請求項２または３に記載のＳｉＣ半導体装置。
  5. 　前記パッド電極は、前記第１主面電極とは異なる金属材料を含む、請求項１～４のいずれか一項に記載のＳｉＣ半導体装置。
  6. 　前記パッド電極は、Ｎｉ層、Ｐｄ層およびＡｕ層のうちの少なくとも１つを含む、請求項１～５のいずれか一項に記載のＳｉＣ半導体装置。
  7. 　前記パッド電極は、前記第１主面電極側からこの順に積層されたＮｉ層およびＡｕ層を含む、請求項１～６のいずれか一項に記載のＳｉＣ半導体装置。
  8. 　前記パッド電極は、前記第１主面電極側からこの順に積層されたＮｉ層、Ｐｄ層およびＡｕ層を含む、請求項１～７のいずれか一項に記載のＳｉＣ半導体装置。
  9. 　前記第２主面電極は、前記第２Ａｌ層とは異なる金属材料からなる１つまたは複数の電極層を含み、
    　前記第２Ａｌ層は、１つまたは複数の前記電極層を被覆している、請求項１～８のいずれか一項に記載のＳｉＣ半導体装置。
  10. 　１つまたは複数の前記電極層は、Ｔｉ層、Ｎｉ層、Ｐｄ層、Ａｕ層およびＡｇ層のうちの少なくとも１つを含む、請求項９に記載のＳｉＣ半導体装置。
  11. 　１つまたは複数の前記電極層は、少なくとも前記第２主面との間でオーミック接触を形成するオーミック電極層を含み、
    　前記第２Ａｌ層は、少なくとも前記オーミック電極層を被覆している、請求項９または１０に記載のＳｉＣ半導体装置。
  12. 　前記第２Ａｌ層は、前記第１Ａｌ層未満の厚さを有している、請求項１～１１のいずれか一項に記載のＳｉＣ半導体装置。
  13. 　前記第２Ａｌ層は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層およびＡｌＳｉＣｕ合金層のうちの少なくとも１つを含む、請求項１～１２のいずれか一項に記載のＳｉＣ半導体装置。
  14. 　前記第２Ａｌ層は、純Ａｌ層からなる、請求項１～１３のいずれか一項に記載のＳｉＣ半導体装置。
  15. 　前記第１Ａｌ層は、純Ａｌ層、ＡｌＳｉ合金層、ＡｌＣｕ合金層およびＡｌＳｉＣｕ合金層のうちの少なくとも１つを含む、請求項１～１４のいずれか一項に記載のＳｉＣ半導体装置。
  16. 　前記第１主面に形成されたダイオードをさらに含み、
    　前記第１主面電極は、前記ダイオードのアノードに電気的に接続されたアノード電極を形成し、
    　前記第２主面電極は、前記ダイオードのカソードに電気的に接続されたカソード電極を形成している、請求項１～１５のいずれか一項に記載のＳｉＣ半導体装置。
  17. 　前記第１主面に形成されたＭＩＳＦＥＴをさらに含み、
    　前記第１主面電極は、前記ＭＩＳＦＥＴのゲートに電気的に接続されたゲート主面電極、および、前記ＭＩＳＦＥＴのソースに電気的に接続されたソース主面電極を含み、
    　前記パッド電極は、前記ゲート主面電極の上に形成されたゲートパッド電極、および、前記ソース主面電極の上に形成されたソースパッド電極を含み、
    　前記第２主面電極は、前記ＭＩＳＦＥＴのドレインに電気的に接続されたドレイン電極を形成している、請求項１～１６のいずれか一項に記載のＳｉＣ半導体装置。
  18. 　前記ＳｉＣチップは、前記第２主面側から前記第１主面側に向けてこの順に積層されたＳｉＣ半導体基板およびＳｉＣエピタキシャル層を含む積層構造を有している、請求項１～１７のいずれか一項に記載のＳｉＣ半導体装置。
  19. 　前記ＳｉＣチップの厚さは、３００μｍ以下である、請求項１～１８のいずれか一項に記載のＳｉＣ半導体装置。
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