Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
  • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
  • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
  • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
  • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
  • G09G3/3266—Details of drivers for scan electrodes
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0243—Details of the generation of driving signals
  • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

• the present invention relates to the field of display technologies, and in particular, to a shift register, a driving circuit, and a display device. Background technique
• the output characteristics of the conventional shift register are related to the polarity of the TFTs constituting the shift register, that is, the operating range of the N-type TFT shift register outputs the high voltage Vgh; and the operating range of the P-type TFT shift register outputs the low voltage Vgl.
• Existing shift registers cannot provide both low voltage and high voltage outputs.
• the active matrix organic light-emitting diode panel in addition to the startup voltage itself as the startup voltage, a voltage opposite to the startup voltage is required as the startup voltage.
• the P-type TFT compensation type pixel structure shown in FIG. 1 requires five drive signals, and the DATA (data) signal 11 and the VDD (power) signal 14 are directly supplied from the Source IC (drive circuit board), and the other three signals are shifted.
• the bit register is input to the pixel structure, wherein the start voltage of the GATE (gate) signal 12 and the RESET (reset) signal 13 is a low voltage, but the start voltage of the EMISSION signal 15 is a high voltage. Therefore, the existing shift register cannot achieve the purpose of providing both the GATE (gate) and RESET (reset) signals as low voltages and the EMISSION signals as high voltages. Summary of the invention
• Embodiments of the present invention provide a shift register that delays the output of the received start voltage and simultaneously outputs a reverse voltage that is opposite to the start voltage of the delayed output.
• a voltage shifting module a voltage inverting module, a supplemental voltage module, a voltage shifting control module, a first output port, and a second output port;
• the voltage shifting module is configured to receive a voltage in the same direction as the starting voltage under the control of the first starting voltage signal; and to receive the voltage in the same direction as the starting voltage under the control of the second starting voltage signal Said second output port output, and simultaneously output to the voltage inversion module;
• a voltage reversal module connected to the voltage shifting module, configured to reverse the voltage from the starting voltage under the control of the voltage output by the voltage shifting module and the voltage provided by the reverse voltage source
• the first output port outputs and simultaneously outputs to the supplemental voltage module; under the control of the first starting voltage signal and the voltage provided by the starting voltage source, or the third starting voltage signal and the voltage provided by the starting voltage source, a voltage in the same direction is output from the first output port and simultaneously output to the supplemental voltage module;
• a supplemental voltage module connected to the voltage inverting module and the voltage shifting module, for receiving the voltage of the voltage inverting module output and the voltage supplied by the reverse voltage source, when the voltage inverting module outputs When the voltage of the same voltage is started, a voltage reversed from the starting voltage is output from the second output port, and simultaneously output to the voltage inversion module;
• the voltage shift control module is connected to the voltage shifting module for controlling the closing of the voltage shifting module under the control of the voltage provided by the third starting voltage signal and the reverse voltage source.
• Embodiments of the present invention also provide a shift register implemented shift method, the shift register including a voltage shifting module, a voltage inversion module, a supplemental voltage module, a voltage shift control module, a first output port, and a second output port, the method comprising:
• the voltage shifting module receives a voltage in the same direction as the starting voltage under the control of the first starting voltage; and outputs a voltage in the same direction as the starting voltage from the second output port under the control of the second starting voltage;
• the voltage reversing module outputs a voltage reversed from the starting voltage from the first output port under the control of the voltage outputted by the received voltage shifting module; under the control of the first starting voltage and the third starting voltage, a voltage in the same direction as the startup voltage is output from the first output port;
• the supplemental voltage module outputs a voltage reversed from the starting voltage from the second output port when the voltage inverting module outputs a starting voltage under the control of the received voltage of the voltage inverting module output;
• the voltage shift control module controls the voltage shifting module to be turned off when the voltage inverting module outputs the starting voltage under the control of the received third starting voltage.
• Embodiments of the present invention also provide a driving circuit including a first stage shift register, a last stage shift register, and at least one intermediate stage shift register, wherein each shift register is as described above a shift register, wherein the shift register is connected in a cascade manner, and a second output port in the shift register of the upper stage is connected to a voltage shift module of the shift register of the next stage;
• the voltage shifting module of the first stage shift register receives the voltage in the same direction as the starting voltage, outputs the voltage from the second output port to the voltage shifting module of the next stage shift register; and outputs and the second output port from the first output port The voltage at which the output of the output port is reversed;
• the voltage shifting module of each intermediate stage shift register receives the voltage outputted by the second output port of the shift register of the upper stage, and outputs the voltage of the voltage shifting module of the shift register from the second output port to the second stage, and An output port outputs a voltage that is opposite to a second output port output voltage;
• the voltage shifting module of the last stage shift register receives the voltage outputted by the second output port of the shift register of the previous stage, and outputs a voltage reversed from the output voltage of the second output port from the first output port; After the first enable voltage signal of the shift register is turned off, the first start voltage signal for controlling the shift register of the next stage is turned on.
• the shift register of the embodiment of the present invention provides a voltage output reverse to the start voltage while providing a start voltage for the next stage shift register, so that the shift register can not only provide the delay of the shift register of the next stage.
• the same starting voltage also provides a reverse voltage that is opposite to the delayed starting voltage.
• 1 is a P-type TFT compensation type pixel structure
• FIG. 2 is a schematic structural view of a first embodiment of the present invention
• FIG. 3 is a schematic structural diagram of a circuit according to a second embodiment of the present invention.
• FIG. 4 is a schematic circuit diagram of a three-channel N-channel TFT according to a specific embodiment of the present invention
• FIG. 5 is a circuit timing diagram of an N-channel TFT for a third embodiment of the present invention
• FIG. 6 is a schematic diagram showing the circuit structure of a P-channel TFT according to a fourth embodiment of the present invention
• FIG. 7 is a circuit timing diagram of a P-channel TFT for a fourth embodiment of the present invention.
• FIG. 8 is a schematic structural diagram of a driving circuit composed of a plurality of shift registers according to an embodiment of the present invention
• FIG. 9 is a flowchart of a method according to an embodiment of the present invention. detailed description
• the present invention provides a shift with an inverted output. register.
• the shift register with reverse output includes: a voltage shifting module 21, a voltage inverting module 22, a supplemental voltage module 23 and a voltage shifting control module 24, a voltage stabilizing module 25, Voltage regulator control module 26, An output port 39a and a second output port 39b.
• the first enable voltage signal, the second enable voltage signal, and the third enable voltage signal in this embodiment are a first clock signal, a second clock signal, and a third clock signal, respectively.
• the voltage shifting module 21 in this embodiment is configured to receive a voltage signal in the same direction as the starting voltage under the control of the first clock signal; and to receive the voltage signal in the same direction as the starting voltage under the control of the second clock signal
• the second output port outputs and is simultaneously output to the voltage stabilizing module 25.
• the voltage signal received by the voltage shifting module 21 may be an external trigger voltage signal; or a plurality of shift registers connected in a cascade manner may be combined to form a voltage signal output by the shift register of the upper stage when the driving circuit is formed.
• the voltage shifting module 21 can receive the voltage signal; when the second clock signal is controlled, the voltage shifting module 21 outputs the received voltage signal from the second output port 39b.
• the voltage stabilizing module 25 is configured to output a voltage in the same direction and stable to the voltage output from the voltage shifting module 21 from the second output port 39b under the voltage control provided by the starting voltage source.
• the input terminal of the voltage stabilizing module 25 is connected to the output port of the voltage shifting module 21, and the output port of the voltage stabilizing module 25 is connected to the input terminal of the voltage inverting module 22.
• the voltage stabilizing module 25 ensures that the output voltage is a stable voltage in the same direction as the starting voltage. In the actual case, a voltage source in the same direction as the voltage output from the voltage shifting module 21 can be used separately to provide a stable non-inverting voltage.
• the voltage reversing module 22 is connected to the voltage stabilizing module 25 for controlling the voltage signal reversed from the starting voltage from the voltage signal output from the receiving voltage stabilizing module 25 and the voltage voltage provided by the starting voltage source 34.
• An output port 39a is output and simultaneously output to the supplemental voltage module 23 and the voltage stabilizing control module 26; under the voltage provided by the first clock signal and the starting voltage source 34, or the voltage provided by the third clock signal and the starting voltage source 34 The voltage in the same direction as the startup voltage is output from the first output port 39a, and simultaneously output to the supplemental voltage module 23 and the voltage stabilization control module 26.
• the voltage reversal module 22 is coupled to the voltage stabilizing module 25.
• the voltage shifting module 21 outputs a starting voltage input voltage stabilizing module 25, and the voltage output voltage of the voltage stabilizing module 25 is reversed in the module 22.
• the voltage reversing module 22 receives the voltage output from the voltage stabilizing module 25 in the same direction as the starting voltage and the voltage supplied from the starting voltage source 34, and outputs a voltage that is opposite to the starting voltage; the first clock signal and the starting voltage source 34 provide The voltage, or the voltage supplied by the third clock signal and the starting voltage source 34, outputs a voltage in the same direction as the starting voltage from the first output port 39a, and simultaneously outputs to the supplemental voltage module 23 and the voltage stabilizing control module. 26.
• the voltage shifting module 21 and the voltage inverting module 22 can be directly connected. Because, the regulator mode Block 25 is to make the voltage outputted by the voltage shifting module 21 more stable, and a voltage stabilizing module 25 is added between the voltage shifting module 21 and the voltage inverting module. However, without the voltage stabilizing module 25, the functions of the voltage shifting module 21 and the voltage inverting module 22 are not affected. The voltage shifting module 21 can still output the received voltage after shifting, and the voltage inverting module can receive the voltage output by the voltage shifting module 21 and output the reversed voltage.
• the supplemental voltage module 23 is connected to the voltage inverting module 22 for controlling the output of the voltage inverting module 22 and the voltage provided by the reverse voltage source 35, when the voltage inverting module outputs and the starting voltage When the voltage is in the same direction, a voltage that is opposite to the starting voltage is output from the second output port and simultaneously output to the voltage inversion module 22.
• the supplemental voltage module 23 is controlled by the voltage of the output of the voltage inverting module 22, and when the voltage shifting module has no output, the voltage reversed from the starting voltage is output from the second output port 39b.
• the voltage shift control module 24 is coupled to the voltage shifting module 21 for controlling the turning off of the voltage shifting module 21 under the control of the voltage supplied by the third clock signal and the reverse voltage source 35.
• the voltage shift control module 24 is controlled by the third clock signal, and then outputs a control voltage to the voltage shifting module 21, and the voltage shift control module 24 turns off the voltage shift when the voltage inverting module 22 outputs a voltage in the same direction as the starting voltage. Bit module 21.
• the voltage stabilizing control module 26 is configured to, when the voltage reversed module receives the voltage output from the first output port and the voltage provided by the reverse voltage source, when the voltage reversing module outputs the voltage in the same direction as the starting voltage , turn off the voltage regulator module.
• the voltage regulation control module 26 is also not required.
• the second clock signal is turned on; after the second clock signal is turned off, the third clock signal is turned on; after the third clock signal is turned off, the first clock signal is turned on; and so on.
• the voltage shifting module 21 receives the voltage in the same direction as the starting voltage under the control of the first clock signal, and outputs the voltage in the same direction as the starting voltage to the second output port 39b under the control of the second clock signal; The voltage signal is not output under the control of the clock signal and the third clock signal.
• the voltage inverting module 22 outputs a voltage in the same direction as the starting voltage under the control of the first clock signal and the third clock signal, and outputs it from the first output port 39a; under the control of the second clock signal, the voltage is reversed Module 22 then outputs a voltage that is opposite to the startup voltage to first output port 39a.
• the voltage controlled by the first output port 39a controls the supplemental voltage module 23 to output a voltage that is opposite to the voltage output by the first output port 39a and from the second output port. 39b output. So far, the startup voltage output from the second output port 39b is delayed by one clock signal from the startup voltage received by the voltage shifting module 21, and the voltage output from the first output port 39a and the voltage output from the second output port 39b are completely Reverse.
• the shift register performs the purpose of delaying the output of the received voltage signal and simultaneously outputting a voltage signal that is opposite to the voltage signal of the delayed output.
• the shift register in this embodiment delays the output of the received voltage signal and also provides a reverse voltage that is opposite to the voltage signal of the delayed output.
• FIG. 3 it is a schematic diagram of a specific circuit structure of the present invention.
• the enable voltage signal is supplied by CLK1, CLK2, and CLK3, and the start voltage source 34 and the reverse voltage source 35 respectively supply a voltage in the same direction as the start voltage and a voltage opposite to the start voltage.
• CLK1 a voltage shifting module starting voltage of one-third period is generated every one-third period
• CLK2, one-third period of one-third period of voltage shifting module starts every one-third period Voltage, and the occurrence of the starting voltage lags the starting voltage of the first clock signal by one-third of a cycle
• CLK3, every one-third of the cycle occurs a voltage shifting module starting voltage of one-third period, and the starting voltage is delayed
• the startup voltage of the second clock signal CLK2 is one-third of a cycle.
• the voltage shifting module in this embodiment includes: a first switching unit 36a, a first capacitor 37a and a second switching unit 36b.
• the first switching unit 36a performs a switching operation under the control of CLK1, and controls the received voltage output in the same direction as the starting voltage to the first capacitor 37a as the charging voltage and the second switching unit 36b as the control voltage.
• the control terminal of the first switching unit 36a receives CLK1, the input terminal receives the voltage signal, and the output terminal is coupled to the control terminal of the second switching unit 36b.
• the voltage signal received at the input terminal may be an external trigger voltage signal; or a plurality of shift registers connected in a cascade manner may be combined to form a voltage signal outputted by the shift register of the previous stage when the driving circuit is formed.
• the first capacitor 37a is charged to provide a driving control voltage to the second switching unit 36b when the first switching unit 36a is turned on to receive a voltage in the same direction as the starting voltage.
• One end of the first capacitor 37a is connected to the control terminal of the second switching unit 36b, and the other end is connected to the output terminal of the second switching unit 36b.
• the first switching unit 36a When the first switching unit 36a is turned on, the first capacitor 37a starts to be charged, and when the first switching unit 36a is turned off, the first capacitor 37a supplies a voltage to the second switching unit 36b.
• the second switching unit 36b performs a switching operation under the control of the control voltage outputted by the first switching unit 36a, the driving control voltage supplied from the first capacitor 37a, or the control voltage output by the first control unit 38a, thereby controlling the output of the CLK2 to the first
• the three-switch unit 36c serves as a control voltage.
• the control terminal of the second switching unit 36b is connected to the output terminal of the first switching unit 36a, the input terminal receives CLK2, and the output terminal is connected to the control terminal of the third switching unit 36c.
• the voltage inversion module includes: a fourth switching unit 36d, a fifth switching unit 36e, a second capacitor 37b, a sixth switching unit 36f, and a seventh switching unit 36g.
• the fourth switching unit 36d performs a switching operation under the control of the control voltage outputted by the third switching unit 36c, thereby controlling the voltage supplied from the reverse voltage source 35 to be output from the first output port 39a; the reverse voltage source is The shift register initiates a voltage reverse voltage; the first output port 39a can be used for the output of the stage shift register.
• the control terminal of the fourth switching unit 36d is connected to the output terminal of the third switching unit 36c, the input terminal receives the voltage supplied from the reverse voltage source 35, and the output terminal is connected to the first output port 39a.
• Each of the first to fourth switching units is turned on one by one, and not only the starting voltage in the same direction as the starting voltage is outputted to the next-stage shift register as the starting voltage, but also the voltage which is reversed from the starting voltage for the stage.
• the fifth switching unit 36e performs a switching operation under the control of CLK1, and controls the voltage supplied from the startup voltage source 34 to output to the second capacitor 37b as the charging voltage and the sixth switching unit 36f as the control voltage.
• the control terminal of the fifth switching unit 36e receives CLK1
• the input terminal receives the voltage supplied from the startup voltage source 34
• the output terminal is connected to the control terminal of the sixth switching unit 36f.
• the second capacitor 37b receives the voltage supplied from the startup voltage source 34 when the fifth switching unit 36e is turned on, and turns off the sixth switching unit 36f when the fourth switching unit 36d is turned on.
• One end of the second capacitor 37b is connected to the control terminal of the sixth switching unit 36f, and the other end is connected to the output terminal of the sixth switching unit 36f.
• the sixth switching unit 36f performs a switching operation under the control of the control voltage output from the fifth switching unit 36e and the seventh switching unit 36g, thereby controlling the startup voltage source 34 to be output from the first output port 39a.
• the control terminal of the sixth switching unit 36f is connected to the output terminal of the fifth switching unit 36e, the input terminal receives the voltage supplied from the starting voltage source 34, and the output terminal is connected to the first output port 39a.
• the seventh switching unit 36g performs a switching operation under the control of CLK3, thereby controlling the voltage output from the startup voltage source 34 to the sixth switching unit 36f as a control voltage, and outputting the startup voltage.
• the voltage provided by source 34 charges second capacitor 37b.
• the control terminal of the seventh switching unit 36g receives CLK3, the input terminal is connected to the startup voltage source 34, and the output terminal is connected to the control terminal of the sixth switching unit 36f.
• the supplemental voltage module includes: a third control unit 38c.
• the third control unit 38c performs a switching operation under the voltage control outputted by the first output port 39a, thereby controlling the reverse voltage source 35 to output a voltage signal to the fourth switching unit 36d as the off voltage, and outputting the reverse voltage source 35.
• the voltage signal is output from the second output port 39b.
• the control terminal of the third control unit 38c is connected to the first output port 39a, the input terminal receives the voltage signal output from the reverse voltage source 35, and the output terminal is connected to the control terminal of the fourth switching unit 36d.
• the fifth to seventh switching units provide a starting voltage to the first output port to control the outputs of the third switching unit, the fourth switching unit, and the second output port after the second control unit and the third control unit are turned on.
• the voltage shift control module includes: a first control unit 38a.
• the first control unit 38a performs a switching operation under the control of CLK3, thereby controlling the discharge of the first capacitor 37a and the reverse voltage source 35.
• the control terminal of the first control unit 38a receives CLK3, the input terminal is connected to the reverse voltage source 35, and the output terminal is connected to the control terminal of the second switching unit 36b.
• the voltage stabilizing module includes: a third switching unit 36c.
• the third switching unit 36c performs a switching operation under the control of the control voltage outputted by the second switching unit 36b or the control voltage outputted by the second control unit 38b, and controls the startup voltage source 34 to output to the fourth switching unit 36d as a control voltage, and controls
• the startup voltage source is output from the second output port 36b for providing a startup voltage to the next stage shift register; the startup voltage source is the same voltage as the shift register startup voltage.
• the control end of the third switching unit 36c is connected to the output end of the second switching unit 36b, the input terminal receives the starting voltage source 34, and the output terminal is connected to the control terminal of the fourth switching unit 36d.
• the voltage regulation control module includes: a second control unit 38b.
• the output of the second control unit 38b is connected to the control terminal of the third switching unit 36c.
• the second control unit 38b turns off the third switching unit 36c after being turned on.
• the output of the second output port 39b is a voltage signal delayed by the received voltage signal, and the signal can be used as a signal input to the shift register of the next stage in a driving circuit composed of a plurality of shift registers;
• the output port 39a outputs the voltage outputted from the second output port 39b.
• the voltage signal reversed by the signal is used to provide a circuit that requires simultaneous reverse voltage signal drive.
• the first switching unit 36a When CLK1 outputs a voltage in the same direction as the starting voltage, the first switching unit 36a is turned on, and the voltage received by the first switching unit 36a in the same direction as the starting voltage is output to the second switching unit 36b, and is output to the first capacitor 37a for charging. .
• the fifth switching unit 36e is controlled to be turned on when the voltage of the CLK1 is output in the same direction as the starting voltage, and the starting voltage source 34 is input to the sixth switching unit 36f through the fifth switching unit 36e and charges the second capacitor 37b, the sixth switch The unit 36f is turned on under the control of the startup voltage source, and the startup voltage source 34 outputs the startup voltage from the first output port 39a through the sixth switching unit 36f.
• the second control unit 38b and the third control unit 38c are turned on under the control of the startup voltage outputted by the first output port 39a, and the reverse voltage source 35 outputs a voltage signal to the second through the second control unit 38b and the third control unit 38c, respectively.
• the third switching unit 36c and the fourth switching unit 36d turn off the third switching unit 36c and the fourth switching unit 36d; at this time, the second output port 39b outputs a voltage signal supplied from the reverse voltage source 35.
• the voltage output from CLK1 is converted to a voltage opposite to the startup voltage, and the first capacitor 37a outputs the stored voltage to the second switching unit 36b to be turned on.
• the voltage outputted by the CLK2 in the same direction as the startup voltage is output to the third switching unit 36c through the turned-on second switching unit 36b, and the third switching unit 36c is turned on under the control of the startup voltage of the CLK2 output, and the startup voltage is started.
• the source 34 outputs a startup voltage from the second output port 39b via the third switching unit 36c, and the startup voltage source 34 outputs a voltage signal to the fourth switching unit 36d through the third switching unit 36c.
• the reverse voltage source 35 After the fourth switching unit 36d is turned on, the reverse voltage source 35 outputs a voltage signal from the first output port 39a via the fourth switching unit 36d.
• the second capacitor 37b provides a bootstrap action for the sixth switching unit 36f such that the sixth switching unit 36f is turned off.
• the fifth switching unit 36e When CLK1 is a voltage in the same direction as the starting voltage, the fifth switching unit 36e is turned on, and further provides a starting voltage source 34 for the sixth switching unit 36f.
• the fifth switching unit 36e When CLK2 is a voltage in the same direction as the starting voltage, the fifth switching unit 36e is turned off. In order to turn off the sixth switching unit when CLK2 is the starting voltage, it is necessary to connect both ends of the capacitor to the control end and the output end of the sixth switching unit. Because, when CLK1 is a voltage in the same direction as the starting voltage, the voltage in the same direction as the starting voltage is output to the control terminal of the sixth switching unit through the turned-on fifth switching unit.
• the control terminal voltage of the sixth switching unit 36f is converted from the voltage of the starting voltage source to the voltage of the reverse voltage source by the bootstrap action of the second capacitor 37b, so that the sixth switching unit 36f is Turns off the state until the start voltage signal in the next clock signal is received.
• the voltage output from the first output port 39a opposite to the starting voltage also turns off the second control unit 38b and the third control unit 38c.
• CLK3 When the voltage signal output from CLK2 is a voltage opposite to the startup voltage, CLK3 outputs a voltage in the same direction as the startup voltage so that the seventh switching unit 36g and the first control unit 38a are turned on. After the seventh switching unit 36g is turned on, the startup voltage source 34 outputs a voltage signal to the sixth switching unit 36f to turn it on. After the sixth switching unit 36f is turned on, the startup voltage source 34 outputs a voltage signal from the first output port 39a, and the startup voltage source 34 outputs a voltage signal to the second control unit 38b and the third control unit 38c.
• the reverse voltage source 35 is output to the third switching unit 36c, the second output port 39b, and the fourth switching unit 36d.
• the third switching unit 36c and the fourth switching unit 36d are turned off, and the second output port 39b outputs a reverse voltage.
• the shift register provided by the present invention can output a shifted voltage signal from the second output port, and output a signal inverted from the voltage signal outputted by the second output port from the first output port, which can satisfy the voltage that needs to be reversed at the same time. Signal demand. Therefore, the shift register provided by the present invention can output a voltage signal delayed by the received start voltage to the shift register of the next stage, and can output the signal outputted to the shift register of the next stage to the stage. Reverse voltage signal.
• the duration of the startup voltage in CLK1, CLK2, and CLK3 in this embodiment is not limited to one-third of one cycle, wherein the duration of the startup voltage can be adjusted as needed, and only the startup voltages in CLK1, CLK2, and CLK3 are required.
• the start-up cycle occurs in time, that is, when the startup voltage of CLK1 is turned off, the startup voltage of CLK2 is turned on; when the startup voltage of CLK2 is turned off, the startup voltage of CLK3 is turned on; when the startup voltage of CLK3 is turned off, the startup voltage of CLK1 is turned on.
• the switching unit and the control unit in the present invention may be any one or a combination of a field effect transistor, a triode, and a thin film transistor.
• a field effect transistor a triode
• a thin film transistor In this embodiment, an N-channel thin film transistor is used as the opening.
• the components of the off unit and the control unit are shown in Figure 3 and Figure 4.
• This embodiment controls the turning-on and turn-off of components in the shift register by three clock signals, a high voltage power supply and a low voltage power supply. Since the N-channel type thin film transistor is used in this embodiment, the starting voltage source of the present embodiment is a high voltage, and the reverse voltage source is a low voltage.
• the three clock signals include: CLK1, a voltage shifting module starting voltage of one-third period is generated every one-third period; CLK2, one-third length is generated every one-third period
• CLK1 a voltage shifting module starting voltage of one-third period
• CLK2 one-third length is generated every one-third period
• One cycle of voltage shifting module starts voltage, and the start voltage appears one third of the start voltage of CLK1
• CLK3, one third of a cycle of voltage shifting module starts every one third of the cycle
• the voltage, and the occurrence of the startup voltage lags the start voltage of CLK2 by one-third of a cycle; at the same time, the high voltage source Vgh and the low voltage source Vgl respectively supply a voltage in the same direction as the startup voltage and a voltage opposite to the startup voltage.
• the first switching unit 36a includes a thin film transistor M1.
• the thin film transistor includes a gate receiving CLK1; a drain for receiving a voltage in the same direction as the startup voltage; and a source connected to the gate of the thin film transistor M2.
• Ml performs a switching operation under the control of CLK1, and controls the output of the received voltage signal to the first capacitor CI (37a) as the charging voltage and the control M2 is turned on.
• the second switching unit 36b includes a thin film transistor M2.
• the thin film transistor includes a gate connected to the source of the thin film transistor M1; a drain receiving CLK2; and a source connected to the gate of the thin film transistor M3.
• M2 is turned on or off under the control of the control voltage of the M1 output, the drive control voltage supplied from the first capacitor C1, or the control voltage of the output of the thin film transistor M8, thereby controlling the output of the CLK2 to the thin film transistor M3 as the control voltage.
• the first capacitor C1 has one end connected to the gate of M2 and the other end connected to the source of M2.
• the third switching unit 36c includes a thin film transistor M3.
• the thin film transistor includes a gate connected to the source of the thin film transistor M2; a drain receiving Vgh; and a source connected to the gate of the thin film transistor M4 and connected to the second output port 39b.
• the M3 performs a switching operation under the control of the control voltage of the M2 output or the control voltage output from the thin film transistor M9, and controls the Vgh output to the thin film transistor M4 as a control voltage, and simultaneously outputs to the second output port 39b.
• the fourth switching unit 36d includes a thin film transistor M4.
• the thin film transistor includes a gate connected to the source of the thin film transistor M3; a drain connected to the first output port 39b; and a source receiving Vgl.
• M4 performs switching operation under the control of the control voltage of the M3 source output, thereby controlling Vgl from the first Output port 39a outputs; the first output port can be used for the output of the shift register of the stage.
• the drain of the thin film transistor M10 is connected to the gate of M4.
• the received high voltage delay can be output to the next stage shift register by M1-M4 turning on one by one.
• the fifth switching unit 36e includes a thin film transistor M5.
• the thin film transistor includes a gate connected to CLK1; a drain receiving Vgh; and a source connected to the gate of the thin film transistor M6.
• M5 is switched under the control of CLK1, and the Vgh output is controlled to the second capacitor C2 as the charging voltage and the thin film transistor M6 as the control voltage.
• the second capacitor C2 (37b) turns off M6 when M4 turns on and receives Vgl.
• the second capacitor C2 has one end connected to the M6 gate and the other end connected to the M6 source.
• the sixth switching unit 36f includes a thin film transistor M6.
• the thin film transistor includes a gate connected to a source of the thin film transistor M5; a drain receiving Vgh; and a source connected to the first output port 39a.
• the M6 performs a switching operation under the control voltage or control of the output of the thin film transistor M7 of M5, thereby controlling the output of Vgh from the first output port 39a.
• the seventh switching unit 36g includes a thin film transistor M7 including a gate receiving CLK3; a drain receiving Vgh; and a source connected to the gate of the thin film transistor M6.
• the M7 is switched under the control of CLK3 to control the Vgh output to M6 as the control voltage.
• the first control unit 38a includes a thin film transistor M8 including a gate receiving CLK3; a drain connected to the gate of the thin film transistor M2; and a source receiving Vgl. M8 is switched under the control of CLK3 to control the discharge of the first capacitor C1 and Vgl.
• the second control unit 38b includes a thin film transistor M9 including a gate connected to the first output port 39a; a drain connected to the gate of the thin film transistor M3; and a source receiving Vgl.
• the switching operation is performed under the control of the voltage output from the first output port 39a, thereby controlling the Vgl output to M3 as the turn-off voltage.
• the third control unit 38c includes a thin film transistor M10 including a gate connected to the first output port 39a; a drain connected to the M3 source; and a source receiving Vgl.
• the switching operation is performed under the voltage control output from the first output port 39a, thereby controlling the Vgl output to M4 as the off voltage and the Vgl output from the second output port 39b.
• M5 to M7 provide a high voltage to the first output port 39a to control the outputs of M3, M4 and the second output port 39b after M9 and M10 are turned on.
• the second output port 39b outputs a voltage signal delayed by the received voltage signal, and the signal can be input to the signal of the next stage shift register in a driving circuit composed of a plurality of shift registers;
• the output port 39a outputs a voltage signal that is opposite to the voltage signal outputted by the second output port 39b for supplying a circuit that requires simultaneous driving of the reverse voltage signal.
• the workflow of this embodiment is as follows, and the timing chart is as shown in FIG. CLK1, CLK2, CLK3, the start voltage Vgh and the reverse voltage Vgl are input signals, and the first output 39a and the second output 39b are voltage signals outputted by the two output ports of the shift register.
• Ml is turned on under the control of the high voltage signal of CLK1, and outputs the received high voltage to M2 and charges the first capacitor C1.
• M5 turns on under the control of the high voltage signal of CLK1, outputs a high voltage to M6 and charges the second capacitor C2.
• M6 is turned on under the control of the high voltage signal of CLK1, and the high voltage is output from the first output port 39a.
• M9 and M10 are turned on at the high voltage output of the first output port, and the low voltage is output to M3 and M4 to turn off M3 and M4. The low voltage is output from the second output port 39b through the turned-on M10.
• CLK2 outputs a high voltage while CLK1 is reduced to a low voltage.
• M2 is turned on by the charging of the first capacitor C1, and the high voltage of CLK2 is output to M3 through M2. After M3 is turned on, the high voltage is output to the second output ports 39b and M4. M4 is turned on under high voltage control, and a low voltage is output from the first output port 39a through M4.
• CLK2 is the starting voltage
• the voltage at the output of M6 is Vgl.
• the voltage difference between the control terminal and the output terminal of M6 causes M6 to be turned on.
• the high voltage is also output from the first output port 39a. At this time, the first output Port 39a is in a chaotic state.
• CLK3 outputs a high voltage and CLK2 drops to a low voltage.
• M7 is turned on under the control of CLK3, and the high voltage is output to M6. After M6 is turned on, the high voltage is output from the first output port 39a.
• M9 and M10 are turned on under the control of the output voltage of the first output port, and the low voltage is input to M3, the second output port 39b and M4, and M3 and M4 are turned off.
• M8 is turned on under the control of the third clock signal, and the low voltage is supplied to the first capacitor C1 for discharging.
• the duration of the startup voltage in CLK1, CLK2, and CLK3 in this embodiment is not limited to one-third of one cycle, wherein the duration of the startup voltage can be adjusted as needed, and only the startup voltages in CLK1, CLK2, and CLK3 are required.
• the occurrence of the convergence cycle in time that is, when the startup voltage of CLK1 is turned off, the startup voltage of CLK2 is turned on; when the startup voltage of CLK2 is turned off, CLK3 The startup voltage is turned on; when the startup voltage of CLK3 is turned off, the startup voltage of CLK1 is turned on.
• the switching unit and the control unit in the present invention may be any one or a combination of a field effect transistor, a triode, and a thin film transistor.
• a P-channel thin film transistor is used as a component of a switching unit and a control unit, and the circuit structure is as shown in Figs. 3 and 6.
• This embodiment controls the turning-on and turn-off of components in the shift register by three clock signals, a high voltage power supply and a low voltage power supply. Since the P-channel type thin film transistor is used in this embodiment, the starting voltage source of the present embodiment is a low voltage, and the reverse voltage source is a high voltage.
• the three clock signals include: CLK1, a voltage shifting module starting voltage of one-third period is generated every one-third period; CLK2, one-third period occurs every one-third period One-third cycle of the voltage shifting module starts the voltage, and the occurrence of the starting voltage lags the starting voltage of the first clock signal by one-third of a cycle; CLK3, one third of a cycle occurs every one-third of the cycle
• the voltage shifting module starts voltage, and the starting voltage lags the starting voltage of CLK2 by one-third period; at the same time, the high voltage source Vgh and the low voltage source Vgl respectively provide a voltage opposite to the starting voltage and a voltage in the same direction as the starting voltage. .
• the shift register includes:
• the first switching unit 36a includes a thin film transistor M1.
• the thin film transistor includes a gate receiving CLK1; a drain receives a voltage in the same direction as the starting voltage, which is Vgl in this embodiment; and a source is connected to the gate of the thin film transistor M2.
• Ml performs a switching operation under the control of CLK1, and controls the received voltage output to the first capacitor C1 as the charging voltage and the control M2 to be turned on.
• the second switching unit 36b includes a thin film transistor M2.
• the thin film transistor includes a gate connected to the source of the thin film transistor M1; a drain receiving CLK2; and a source connected to the gate of the thin film transistor M3.
• M2 is turned on or off under the control of the control voltage of the M1 output, the drive control voltage supplied from the first capacitor C1, or the control voltage of the output of the thin film transistor M8, thereby controlling the output of the CLK2 to the thin film transistor M3 as the control voltage.
• the first capacitor C1 has one end connected to the gate of M2 and the other end connected to the source of M2.
• the third switching unit 36c includes a thin film transistor M3.
• the thin film transistor includes a gate connected to the source of the thin film transistor M2; a drain receiving Vgl; and a source connected to the gate of the thin film transistor M4 and connected to the second output port 39b.
• M3 control voltage at M2 output or thin film transistor M9 The switching operation is performed under the control of the output control voltage, Vgl to M4 is output to control M4, and Vgl is outputted to the second output port 39b.
• the drain of the thin film transistor M9 is connected to the M3 gate.
• the fourth switching unit 36d includes a thin film transistor M4.
• the thin film transistor includes a gate connected to the source of the thin film transistor M3; a drain connected to the first output port 39b; and a source receiving Vgh.
• M4 performs a switching operation under the control of the control voltage of the M3 source output, thereby controlling Vgh to be output from the first output port 39a.
• the drain of the thin film transistor M10 is connected to the M4 gate.
• the received start-up voltage low voltage delay is output to the next-stage shift register by M1-M4 one by one.
• the fifth switching unit 36e includes a thin film transistor M5.
• the thin film transistor includes a gate receiving CLK1; a drain receiving Vgl; and a source connected to the gate of the thin film transistor M6.
• M5 performs switching operation under the control of CLK1, and controls V gl output to the second capacitor C 2 as the charging voltage and the thin film transistor M6 as the control voltage.
• the second capacitor C2 (37b) turns off M6 when the fourth switching unit 36d is turned on to receive Vgh.
• the second capacitor C2 has one end connected to the M6 gate and the other end connected to the M6 source.
• the sixth switching unit 36f includes a thin film transistor M6.
• the thin film transistor includes a gate connected to a source of the thin film transistor M5; a drain receiving Vgl; and a source connected to the first output port 39a.
• the M6 performs a switching operation under the control voltage or control of the output of the thin film transistor M7 of M5, thereby controlling the output of Vgl from the first output port 39a.
• the seventh switching unit 36g includes a thin film transistor M7.
• the thin film transistor includes a gate receiving CLK3; a drain receiving Vgl; and a source connected to the gate of the thin film transistor M6.
• M7 is switched under the control of CLK3 to control the Vgl output to M6 as the control voltage.
• the first control unit 38a includes a thin film transistor M8.
• the thin film transistor includes a gate receiving CLK3; a drain connected to the gate of the thin film transistor M2; and a source receiving Vgh. M8 is switched under the control of CLK3 to control the discharge of the first capacitor C1 and Vgh.
• the second control unit 38b includes a thin film transistor M9.
• the thin film transistor includes a gate connected to the first output port 39a; a drain connected to the gate of the thin film transistor M3; and a source receiving Vgh. The switching operation is performed under the control of the voltage output from the first output port 39a, thereby controlling the Vgh output to M3 as the turn-off voltage.
• the third control unit 38c includes a thin film transistor M10.
• the thin film transistor includes a gate connected to the first output port 39a; a drain connected to the M3 source; and a source receiving Vgh. At the first output The switching operation is performed under the voltage control of the output of the port 39a, thereby controlling the Vgh output to M4 as the off voltage, and outputting Vgh to the second output port 39b.
• M5 to M7 provide a low voltage to the first output port 39a to cause M9 and M10 to turn on and control M3, M4 to turn off M3, M4, and Vgh from the output of the second output port 39b.
• the second output port 39b outputs a voltage signal delayed by the received voltage signal, and the signal can be input to the signal of the next stage shift register in a driving circuit composed of a plurality of shift registers;
• the output port 39a outputs a voltage signal that is opposite to the voltage signal outputted by the second output port 39b for supplying a circuit that requires simultaneous driving of the reverse voltage signal.
• the workflow of this embodiment is as follows, and the timing chart is as shown in FIG. CLK1, CLK2, CLK3, reverse voltage Vgh and start voltage Vgl are input signals, and the first output 39a and the second output 39b are voltage signals outputted by the two output ports of the shift register.
• Ml is turned on under the control of the low voltage signal of CLK1, and outputs the received voltage in the same direction as the starting voltage to M2 and charges the first capacitor C1.
• M5 turns on under the control of the low voltage signal of CLK1, outputs a low voltage to M6 and charges the second capacitor C2.
• M6 is turned on under the control of the low voltage signal of CLK1, and the low voltage is output from the first output port 39a.
• M9 and M10 are turned on at the low voltage output of the first output port, and the high voltage is output to M3 and M4 to turn off M3 and M4. The high voltage is output from the second output port 39b through the turned-on M10.
• CLK2 outputs a low voltage while CLK1 rises to a high voltage.
• the voltage accumulated on the first capacitor C1 when CLK1 outputs a low voltage is supplied to M2 when CLK2 outputs a low voltage, M2 is turned on by the charging voltage of the first capacitor C1, and the low voltage of CLK2 is output to M3 through M2. After M3 is turned on, the low voltage is output to the second output ports 39b and M4. M4 is turned on under low voltage control, and a high voltage is output from the first output port 39a through M4.
• the output voltage of M6 is Vgh.
• CLK3 outputs a low voltage and CLK2 rises to a high voltage.
• M7 is turned on under the control of the third clock signal, and outputs a low voltage to M6. After M6 is turned on, the low voltage is output from the first output port 39a.
• M9, M10 are turned on under the control of the low voltage output of the first output port, and the high voltage is input to M3, the second Output ports 39b and M4.
• M3 and M4 are turned off.
• M8 is turned on under the control of CLK3, and the high voltage is output to the first capacitor C1 for discharging.
• the duration of the startup voltage in CLK1, CLK2, and CLK3 in this embodiment is not limited to one-third of one cycle, wherein the duration of the startup voltage can be adjusted as needed, and only the startup voltages in CLK1, CLK2, and CLK3 are required.
• the start-up cycle occurs in time, that is, when the startup voltage of CLK1 is turned off, the startup voltage of CLK2 is turned on; when the startup voltage of CLK2 is turned off, the startup voltage of CLK3 is turned on; when the startup voltage of CLK3 is turned off, the startup voltage of CLK1 is turned on.
• the present invention also provides a driving circuit in which a plurality of shift registers are combined.
• the drive circuit of the present invention will now be described with reference to the accompanying drawings.
• the driver circuit is composed of the first stage shift register 81 and the last stage shift register.
• Each shift register uses the shift register described in the above embodiments, and each shift register is connected in a cascade manner.
• Each shift register has two output ports, the voltage signal outputted by the first output port is a voltage signal outputted after the received voltage signal is shifted, and the voltage signal output by the second output port is outputted by the first output port. The voltage signal is reversed.
• the voltage shifting module of each stage of the shift register receives the voltage in the same direction as the start voltage.
• the first stage shift register 81 is configured to receive a voltage in the same direction as the starting voltage, the voltage in the same direction as the starting voltage is from an external trigger, and the voltage is output from the second output port 39b to the voltage shift of the next stage shift register. And outputting a voltage opposite to the voltage output by the second output port 39b from the first output port 39a.
• Each of the intermediate stage shift registers 82 ⁇ 8N-1 is configured to receive the voltage outputted by the second output port 39b of the shift register of the upper stage, and output the voltage shifting module of the shift register from the second output port 39b.
• the voltage, and a voltage inverted from the output voltage of the second output port 39b is output from the first output port 39a.
• the last stage shift register 8N receives the voltage output from the second output port 39b of the shift register of the previous stage, and outputs a voltage inverted from the output voltage of the second output port 39b from the first output port 39a.
• the voltage output from the second output port in the shift register of the upper stage is input to the voltage shifting module of the shift register of the next stage. And, after controlling the first startup voltage signal of the upper shift register to be turned off, controlling the first startup voltage signal of the next-stage shift register to be turned on.
• shift register 81 is the first stage shift register in the driver circuit. Shift The register 82 is the next stage shift register of the shift register 81, the shift register 83 is the next stage shift register of the shift register 82, and so on to 8N as the last stage shift register.
• Each shift register is controlled by CLK1, CLK2, and CLK3. Among them, CLK1 first appears a starting voltage. When the starting voltage of CLK1 is turned off, a starting voltage appears in CLK2. When the starting voltage of CLK2 is turned off, a starting voltage appears in CLK3. After the starting voltage of CLK3 is turned off, the starting voltage appears in CLK1.
• the first enable voltage signal 81a of the shift register 81 is derived from CLK1, the second enable voltage signal 81b is derived from CLK2, and the third enable voltage signal 81c is derived from CLK3.
• the first start voltage signal 82a of the shift register 82 is derived from CLK2
• the second start voltage signal 82b is derived from CLK3
• the third start voltage signal 82c is derived from CLK1, and so on.
• the clock of the first clock signal of the next stage shift register lags behind the clock of the first clock signal of the previous stage shift register by one third of the clock.
• the start voltages of the three clock signals are equal in duration. In practice, there is no limitation on this. Only after the previous start signal is turned off, the latter start signal is turned on, and the three clock signals are sequentially turned on.
• the signal received by the first shift register is from an external trigger
• the signals received by the intermediate stage shift register and the last stage shift register are all from the upper level mobile register connected to itself.
• the voltage output by the second output port At the same time, each stage shift register outputs a voltage reversed from the output voltage of the second output port from the first output port as the output of the stage.
• the drive circuit in this embodiment is constituted by a plurality of shift registers in the present invention.
• Each shift register will delay output from its own received start-up voltage and will also output a voltage that is opposite to the voltage of the delayed output.
• the voltage provided by the present invention can satisfy such a situation when a situation arises in which a positive and negative voltage are simultaneously required in a pixel circuit.
• the embodiment of the display device provided by the present invention is such that each of the display devices is provided with the above-described driving circuit.
• the driver circuit includes at least two shift registers, all of which are connected in a cascade manner.
• the present invention also provides a method for shifting a shift register with an inverted output. An embodiment of the method of the present invention will now be described with reference to FIG.
• Step S901 the voltage shifting module receives the voltage in the same direction as the starting voltage under the control of the first starting voltage; and outputs the electricity in the same direction as the starting voltage from the second output port under the control of the second starting voltage Pressure.
• Step S902 the voltage reversing module outputs a voltage reversed from the starting voltage from the first output port under the control of the voltage output by the received voltage shifting module; at the first starting voltage and the third starting voltage Under the control of the voltage, the voltage of the starting voltage in the same direction is output from the first output port.
• Step S903 the supplemental voltage module outputs a voltage reversed from the starting voltage from the second output port when the voltage inverting module outputs the starting voltage under the control of the voltage output by the received voltage inverting module.
• Step S904 the voltage shift control module controls the voltage shifting module to be turned off when the voltage inverting module outputs the starting voltage under the control of the received third starting voltage.
• the first startup voltage signal, the second startup voltage signal, and the third startup voltage signal are sequentially cyclically generated.
• the spirit and scope of the invention Thus, it is intended that the present invention cover the modifications and variations of the inventions

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• 2012
  • 2012-03-29 CN CN201210089651.3A patent/CN102651239B/zh active Active
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