WO2019227945A1 - 移位寄存器电路及其驱动方法、栅极驱动电路、阵列基板和显示装置 - Google Patents

移位寄存器电路及其驱动方法、栅极驱动电路、阵列基板和显示装置 Download PDF

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Publication number
WO2019227945A1
WO2019227945A1 PCT/CN2019/071649 CN2019071649W WO2019227945A1 WO 2019227945 A1 WO2019227945 A1 WO 2019227945A1 CN 2019071649 W CN2019071649 W CN 2019071649W WO 2019227945 A1 WO2019227945 A1 WO 2019227945A1
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terminal
node
module
signal
input
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PCT/CN2019/071649
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English (en)
French (fr)
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陈凯
陈沫
鲁思颖
李方庆
董文波
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京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Priority to US16/473,968 priority Critical patent/US11308859B2/en
Publication of WO2019227945A1 publication Critical patent/WO2019227945A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation

Definitions

  • Embodiments of the present disclosure relate to a shift register circuit and a driving method thereof, a gate driving circuit, an array substrate, and a display device.
  • a TFT-LCD Thin Film Transistor Liquid Crystal Display
  • a gate scanning signal is output through a gate driving circuit, and each pixel is scanned for progressive scanning.
  • the gate driving circuit is used for generating a gate scanning signal of a pixel.
  • GOA Gate Driver Array
  • Each GOA unit acts as a shift register to scan the gate signal. Pass it to the next GOA unit in turn, turn on the thin film transistor switch of the pixel one by one, and complete the input of the pixel's gate scan signal.
  • An embodiment of the present disclosure provides a shift register circuit including an input sub-circuit and a signal output sub-circuit, wherein:
  • the input subcircuits include:
  • the control module is connected to the input signal terminal and the first voltage terminal, and the control module is configured to output the signal of the first voltage terminal to the voltage division node under the control of the input signal provided by the input signal terminal;
  • An input module the input of the input module is connected to the voltage division node, the output of the input module is connected to the signal output subcircuit, and the input module is configured to output the signal of the voltage division node to the signal output subcircuit under the control of the control module
  • the first end of the voltage dividing module is connected to the control module, the second end of the voltage dividing module is connected to the second voltage terminal, and the resistance of the voltage dividing module is negatively related to the temperature;
  • the signal output sub-circuit is connected to the output terminal of the input module, and the signal output sub-circuit is configured to output the gate scan signal to the output signal terminal under the control of the input module.
  • An embodiment of the present disclosure also provides a gate driving circuit, which includes a plurality of cascaded shift register circuits.
  • the shift register circuit adopts the shift register circuit as described above.
  • An embodiment of the present disclosure also provides an array substrate including the gate driving circuit as described above.
  • An embodiment of the present disclosure also provides a display device including the array substrate as described above.
  • An embodiment of the present disclosure further provides a method for driving the above-mentioned shift register, including:
  • a signal having an effective potential is input to the input signal terminal, and a signal having an invalid potential is input to the first clock signal terminal, so that the control module outputs the effective potential signal from the first voltage terminal to the voltage dividing node, and the input module is in the control module. Output the signal of the voltage-dividing node to the first node under the control to charge the charging and discharging module;
  • Input a signal with a valid potential to the first clock signal terminal, and input a signal with an invalid potential to the input signal terminal to charge the charging and discharging module, and enable the charging and discharging module to output the signal from the output signal terminal under the control of the first node.
  • a signal at the first clock signal terminal at an effective potential;
  • Input a signal with an effective potential to the reset signal terminal and the second clock signal terminal, so that the second node level changing module changes the potential of the second node to an effective potential, and makes the reset module at the second node at the effective potential and at Under the control of the reset signal terminal of the effective potential, an invalid potential signal from the second voltage terminal is output to the output signal terminal.
  • FIG. 1 is a structural diagram of a shift register circuit
  • FIG. 2 is a structural diagram of a shift register circuit in at least one embodiment of the present disclosure
  • FIG. 3 is a structural diagram of a shift register circuit in at least one embodiment of the present disclosure.
  • FIG. 4 is a structural diagram of a shift register circuit in at least one embodiment of the present disclosure.
  • FIG. 5 is a driving timing diagram of a shift register circuit in at least one embodiment of the present disclosure.
  • FIG. 6 is a cascade diagram of the shift register circuit shown in FIG. 4;
  • FIG. 7 is a structural diagram of a shift register circuit in at least one embodiment of the present disclosure.
  • FIG. 8 is a cascade diagram of the shift register circuit shown in FIG. 7;
  • FIG. 9 is a schematic structural diagram of a gate driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a gate driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of an array substrate according to at least one embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a display device according to at least one embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain of the switching transistor are interchangeable. In the embodiments of the present disclosure, the source is referred to as a first terminal and the drain is referred to as a second terminal. However, it should be understood that in other embodiments, the source may be the second terminal and the drain may be the first terminal. In the end, the embodiments of the present disclosure do not limit this.
  • the switching transistor used in the embodiment of the present disclosure may include a P-type switching transistor and an N-type switching transistor.
  • the P-type switching transistor is turned on when a low-level potential is applied to the gate, and when a high-level potential is applied to the gate.
  • the N-type switching transistor turns on when a high-level potential is applied to the gate, and turns off when a low-level potential is applied to the gate.
  • multiple signals in various embodiments of the present disclosure correspond to a high-level potential and a low-level potential, and the effective potential of the signal is a potential that turns on the switching transistor.
  • the low-level potential Is an effective potential.
  • a high-level potential is an effective potential.
  • pulse-up means charging a node or an electrode of a transistor so that the absolute level of the node or the electrode is The value rises to achieve the operation of the corresponding transistor (for example, turn on);
  • pulse-down means to discharge a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced to achieve the corresponding Operation of the transistor (e.g. off).
  • pulse-up means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the corresponding transistor.
  • Operation (such as turning on); “pull-down” means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode increases, thereby realizing the operation of the corresponding transistor (such as turning off) .
  • pulse-up and pulse-down will also be adjusted accordingly according to the specific type of transistor used, as long as the control of the transistor can be achieved to achieve the corresponding switching function.
  • FIG. 1 shows a shift register circuit.
  • the application environment of the shift register circuit is different.
  • the actual operating temperature of the thin film transistor is not fixed, and its threshold voltage will drift with the temperature change.
  • the threshold voltage of the first thin film transistor M1 becomes larger, and the first thin film transistor M1 is turned on later, which will cause an insufficient charge of the capacitor.
  • the insufficient charge of the capacitor will cause the potential of the first node PU to be lower, and the control terminal voltage will rise and fall.
  • the in-plane thin-film transistor charging rate is insufficient, resulting in the screen brightness not reaching the standard.
  • the threshold voltage of the first thin film transistor M1 becomes smaller, the first thin film transistor M1 is turned on earlier, the first node PU is charged in advance, and the shift register circuit is turned on in advance, resulting in simultaneous output with the previous line, and a serial signal appears. Unusual phenomenon.
  • the technical proposal of the present disclosure proposes that the control terminal voltage of the thin-film transistor inputted with the control signal is inputted with different voltage values at different temperatures to achieve temperature compensation of the control-terminal voltage, thereby improving the thin-film transistor of the control signal input Threshold voltage drift caused by insufficient charging of the shift register circuit at low temperatures and abnormal output signals at high temperatures.
  • At least one embodiment of the present disclosure provides a shift register circuit including an input sub-circuit and a signal output sub-circuit.
  • the input sub-circuit includes: a control module, an input module, and a voltage division module.
  • the control module is connected to the input signal terminal and the first voltage terminal.
  • the control module is configured to output the signal of the first voltage terminal to the voltage division node under the control of the input signal.
  • the input end of the input module is connected to the voltage division node, the output end of the input module is connected to the signal output subcircuit, and the input module is configured to output the signal of the voltage division node to the signal output subcircuit under the control of the control module.
  • the first end of the voltage dividing module is connected to the control module, the second end of the voltage dividing module is connected to the second voltage terminal, and the resistance value of the voltage dividing module is negatively related to the temperature.
  • the signal output sub-circuit is connected to the output terminal of the input module, and the signal output sub-circuit is configured to output the gate scan signal to the output signal terminal under the control of the input module.
  • an embodiment of the present disclosure provides a shift register circuit including an input sub-circuit 100 and a signal output sub-circuit 300, wherein the input sub-circuit 100 includes a control module 101, an input module 102, and a voltage dividing module 103;
  • the control module 101 is connected to the input signal terminal Input and the high-level signal terminal V 1.
  • the control module 101 is configured to output the signal of the high-level signal terminal V 1 to the voltage dividing node PR under the control of the input signal; the input module 102 The input terminal is connected to the voltage division node PR, the output of the input module 102 is connected to the signal output subcircuit 300, and the input module 102 is configured to output the signal of the voltage division node PR to the signal output subcircuit under the control of the control module 101 300; the voltage dividing module 103 is connected to the control module 101 and is also connected to the low-level signal terminal V ss .
  • the resistance of the voltage dividing module 103 is negatively related to the temperature; the signal output sub-circuit 300 is connected to the output terminal of the input module 102, and the signal The output sub-circuit 300 is configured to output a gate scan signal to an output signal terminal under the control of the input module 102.
  • the high-level signal terminal V 1 is an example of the aforementioned first voltage terminal, and the low-level signal terminal V ss is an example of the aforementioned second voltage terminal.
  • the first voltage terminal is used to input an effective potential signal capable of turning on the switching transistor, and the second voltage terminal is used to input an invalid potential signal capable of turning off the switching transistor.
  • the input module 102 includes a first thin film transistor M1, a control terminal and a first terminal of the first thin film transistor M1 are connected to a voltage dividing node PR, and a second terminal is connected to the signal output sub-circuit 300.
  • the control module 101 is turned on under the control of the input signal, and outputs a high-level signal to control the first thin film transistor M1 to be turned on.
  • the signal output sub-circuit 300 outputs a gate driving signal under the control of the first thin film transistor M1.
  • the voltage dividing module 103 is configured to divide the first thin film transistor M1. In the low temperature state, the threshold voltage of the control terminal of the first thin film transistor M1 becomes larger due to the influence of the low temperature. By setting the voltage dividing module 103 in the shift register circuit, the resistance of the voltage dividing module 103 is larger at low temperature, and the voltage is larger. When the PR potential of the voltage dividing node rises, the control terminal of the first thin film transistor M1 applies a high voltage to compensate for the drift of the threshold voltage.
  • the control terminal of the first thin film transistor M1 is affected by high temperature and the threshold voltage is reduced.
  • dividing dividing module 103 is reduced, the reduction potential of the voltage division node PR, although the first thin film transistor M1 controls a low voltage, but the high level signal input terminal V 1 higher a high level, even if the first The potential of the control terminal of a thin film transistor M1 is relatively small, which can also meet the needs of capacitor charging, thereby compensating for the drift caused by the threshold voltage.
  • control module includes an input thin film transistor, a control terminal of the input thin film transistor is connected to an input signal terminal, a first end of the input thin film transistor is connected to a first voltage terminal, and a second end of the input thin film transistor is connected to a voltage dividing node.
  • the control module 101 includes an eleventh thin film transistor M11.
  • the eleventh thin film transistor M11 has a control terminal connected to the input signal terminal Input, a first terminal connected to the high-level signal terminal V 1 , and a second terminal connected to the branch terminal. Node PR.
  • the eleventh thin film transistor M11 is an example of the input thin film transistor described above.
  • the high-level signal terminal V 1 is a power-supply voltage signal terminal V gh , and a high-level voltage is connected to the shift register circuit.
  • the level signal value output by the high-level signal terminal V 1 is 27V to 36V.
  • the size of the level signal output from the high-level signal terminal V 1 is determined according to the characteristics of the thin film transistor of different products. For example, 27V, 30V, 36V, etc. can be selected according to the actual use conditions.
  • the voltage dividing module 103 includes a thermistor R, one end of the thermistor R is connected to the voltage dividing node PR, and the other end is connected to the low-level signal terminal V ss .
  • the selection of the thermistor is mainly determined by the off-resistance of the eleventh thin-film transistor M11. Because the shift register is more off, the eleventh thin-film transistor M11 is divided by the thermistor R when it is turned off.
  • the control terminal of a thin film transistor M1 is affected by the bias voltage.
  • a thermistor R with an appropriate resistance value is selected to make the potential of the voltage dividing point close to 0V.
  • the thermistor R can select a negative temperature coefficient thermistor, which is a type of sensor resistance whose resistance value decreases with increasing temperature.
  • the zero-power resistance of the selected negative temperature coefficient thermistor is 210 ⁇ ⁇ 230 ⁇ , and the operating temperature is -25 °C ⁇ 105 °C.
  • the signal output sub-circuit may include a charging and discharging module, a second node holding module, a second node level changing module, a first node noise reduction module, and a reset module.
  • the first input terminal of the charge / discharge module is connected to the output terminal of the input module and the output node of the first node noise reduction module at the first node, and the second input terminal of the charge and discharge module is connected to the first clock signal terminal.
  • the output terminal is connected to the output signal terminal.
  • the charging and discharging module is used to perform the first charging in the first stage under the common effect of the output signal of the first thin film transistor and the first clock signal. In the second stage, the first charging The potential of the node and the first clock signal perform the second charging and output the gate scan signal.
  • the first node of the second node holding module is connected to the second voltage terminal, the second input of the second node holding module is connected to the first node, and the level of the first output of the second node holding module and the second node is changed.
  • the second input of the module is connected.
  • the second output of the second node holding module is connected to the output of the second node level changing module, the third input of the first node noise reduction module and the second input of the reset module.
  • the second node is connected at the second node, and the second node holding module is used to maintain the potential of the second node to an invalid potential under the combined effect of the potential of the first node and the invalid potential signal in the first and second phases.
  • the first input terminal of the second node level changing module is connected to the second clock signal terminal
  • the second input terminal of the second node level changing module is connected to the first output terminal of the second node holding module
  • the second node level is changed.
  • the output end of the module is connected to the second node
  • the second node level changing module is used to change the potential of the second node in the third stage under the common action of the second clock signal and the output signal of the second node holding module.
  • the first input terminal of the first node noise reduction module is connected to the reset signal terminal
  • the second input terminal of the first node noise reduction module is connected to the second voltage terminal
  • the third input terminal of the first node noise reduction module is connected to the second node.
  • the output of the first node noise reduction module is connected to the first node
  • the first node noise reduction module is used to change the third node under the combined action of the reset signal, the invalid potential signal and the potential of the second node in the third stage.
  • the first input terminal of the reset module is connected to the reset signal terminal
  • the second input terminal of the reset module is connected to the second node
  • the third input terminal of the reset module is connected to the second voltage terminal
  • the output terminal of the reset module is connected to the output signal terminal.
  • the reset module is used to reset the potential of the output signal end in the third stage under the common action of the reset signal, the potential of the second node, and the invalid potential signal.
  • the first clock signal and the second clock signal are mutually inverted signals.
  • a driving cycle of the shift register circuit includes a first phase, a second phase, and a third phase in sequence.
  • the signal output sub-circuit 300 includes a charging and discharging module 302 and a second node pull-down module. 304.
  • the first input terminal of the charging and discharging module 302 is connected to the output terminal of the input module 102 and the output terminal of the first node pull-down module 305.
  • the common terminal connected by the three is the first node PU, the second input terminal of the charging and discharging module is connected with the first clock signal terminal CLKA, the output terminal of the charging and discharging module is connected with the output signal terminal Output, and the charging and discharging module 302 is used for In the first stage, the first charging is performed under the common function of the output signal of the input module 102 and the first clock signal CLKA, and in the second stage, the second time is performed under the potential of the first node PU and the first clock signal CLKA.
  • the first input terminal of the second node pull-down module 304 is connected to the low-level signal terminal, and the second input terminal of the second node pull-down module 304 is connected to the first Point PU connection, the first output of the second node pull-down module 304 is connected to the second input of the second node pull-up module 301, the second output of the second node pull-down module 304 is connected to the second node pull-up module 301
  • the output terminal, the third input terminal of the first node pull-down module 305, and the second input terminal of the reset module 303 are connected.
  • the common terminal connected to them is the second node PD, and the second node pull-down module 304 is used for the first stage and the third stage.
  • the potential of the second node PD is kept low by the potential of the first node PU and the low-level signal; the first input terminal of the second node pull-up module 301 and the second clock signal terminal CLKB Connection, the second input end of the second node pull-up module is connected to the first output end of the second node pull-down module 304, the output end of the second node pull-up module is connected to the second node PD, and the second node pull-up module 301 is used
  • the potential of the second node PD is pulled up by the second clock signal and the output signal of the second node pull-down module 304; the first input terminal of the first node pull-down module 305 and the reset signal End Reset U connection, the second input of the first node pull-down module is connected to the low-level signal terminal, the third input of the first node pull-down module is connected to the second node PD, and the output of the first node pull-down module is connected to the first node PU connection
  • the reset module 303 is configured to reset the potential of the output signal terminal Output under the combined action of a reset signal, a second node PD potential, and a low-level signal in the third stage.
  • the second node pull-down module 304 is an example of the above-mentioned second node holding module
  • the second node pull-down module 301 is an example of the above-mentioned second node level changing module
  • the first node pull-down module 305 is the above-mentioned first node Example of a noise reduction module.
  • the low-level signal is an example of the invalid potential signal described above.
  • the first clock signal and the second clock signal are mutually inverted signals.
  • the high-level signal terminal V 1 is connected to a power-supply voltage signal terminal V gh capable of providing a high-level signal, and can also be connected to a clock signal terminal CI.
  • the high-level signal terminal V 1 of the shift register circuit of an odd-numbered row is connected to all
  • the first clock signal terminal CLKA is connected, and the high-level signal terminal of the shift register circuit of the even-numbered row is connected to the second clock signal terminal CLKB; or, the high-level signal terminal of the shift register circuit of the even-numbered row is connected to the second clock signal terminal CLKB.
  • the first clock signal terminal CLKA is connected, and the high-level signal terminals of the shift register circuits in odd rows are connected to the second clock signal terminal CLKB.
  • the high-level signal is an example of the effective potential signal described above.
  • the driving cycle of the above-mentioned shift register circuit includes three phases in sequence.
  • the high-level signal terminal V 1 always inputs a high-level
  • the low-level signal terminal V ss always inputs a low level.
  • the three phases are:
  • the input signal terminal Input and the second clock signal terminal CLKB output a high level
  • the reset signal terminal Reset PU and the first clock signal terminal CLKA output a low level
  • the control module 101 is turned on
  • the voltage dividing module 103 inputs to the input.
  • the module 102 performs voltage division, the first thin film transistor M1 in the input module 102 is turned on, the first node PU voltage is pulled up, the charging and discharging module 302 is turned on, and the first charging is performed.
  • the first node pull-down module 305 and the reset module 303 are turned off, the second node pull-down module 304 and the second node pull-up module 301 are turned on, and the low-level signals output from the reset signal terminal Reset PU and the first clock signal terminal CLKA enable the second node The potential of PD is pulled down.
  • the control terminal of the transistor M1 of the first thin film by a high temperature decreases the threshold voltage
  • dividing partial pressure of a high temperature module 103 is gradually reduced
  • the partial pressure of The potential of the node PR gradually decreases, causing the voltage of the control terminal of the first thin film transistor M1 to be lower, but because the high-level signal terminal V 1 inputs a high level, even though the potential of the control terminal of the first thin film transistor M1 is relatively small at this time, It can also meet the needs of capacitor charging, so as to compensate for the drift caused by the compensation threshold voltage.
  • the first clock signal terminal CLKA outputs a high level
  • the input signal terminal Input the second clock signal terminal CLKB
  • the reset signal terminal Reset PU output a low level
  • the control module 101 is turned off
  • the input module 102 is turned off
  • the charging The discharging module 302 performs the second charging
  • the PU voltage at the first node continues to increase
  • the output signal terminal Output outputs a high-level gate driving signal.
  • the first node pull-down module 305 and the reset module 303 are turned off, the second node pull-down module 304 and the second node pull-up module 301 are turned on, and the low-level signals output from the reset signal terminal Reset PU and the second clock signal terminal CLKB enable the second node
  • the potential of PD is pulled down.
  • the temperature of the input module 102 is gradually reduced after the input module 102 is turned off.
  • the threshold voltage of the first thin film transistor M1 control terminal in the input module 102 is gradually affected by the low temperature.
  • the resistance of the voltage divider module 103 is gradually increased by the low temperature. Then, the divided voltage becomes larger, the potential of the divided node PR increases, and the control terminal of the first thin film transistor M1 is gradually fed with a high voltage to compensate for the drift caused by the threshold voltage.
  • the reset signal terminal Reset PU and the second clock signal terminal CLKB output high level, the input signal terminal Input and the first clock signal terminal CLKA output low level, the control module 101 is turned off, the input module 102 is turned off, The voltage module 103 continues to exert a partial pressure function on the input module 102 at a low temperature.
  • the second node pull-up module 301 is turned on, and the potential of the second node PD is pulled up; the second node pull-down module 304 is turned off, and the first node pull-down module 305 outputs a low-level signal to the first node PU and the potential of the first node PU Pull down to achieve the first node PU noise reduction; the reset module 303 is turned on, outputs a low-level signal to the output signal terminal Output, and resets the potential of the output signal terminal Output.
  • the output signal terminal Output After the first stage t 1 to the third stage t 3 , the output signal terminal Output outputs a high-level pulse signal with a duration of t 2 during the driving time of one gate line in one frame. The output is to a gate line connected to the stage of the shift register circuit, thereby driving the gate line. Repeating the first stage t 1 to the third stage t 3 can complete the driving of the gate line of the next frame.
  • the voltage pressing module 103 divides the voltage of the first thin film transistor M1, and by feeding different voltage values to the control terminal voltage of the first thin film transistor M1 at different temperatures, the temperature compensation of the voltage of the control terminal of the first thin film transistor M1 is realized, thereby improving the first A thin-film transistor M1 threshold voltage drift caused by insufficient charging of the shift register circuit at low temperatures and abnormal output signals at high temperatures improves the stability of the shift register circuit.
  • the charge / discharge module 302 includes a third thin film transistor M3 and a storage capacitor C.
  • the control terminal of the third thin film transistor M3 is connected to the first node PU, the first terminal is connected to the first clock signal terminal CLKA, and the second terminal is connected to the output signal terminal Output; the first terminal of the storage capacitor C is connected to the first node PU, The second terminal is connected to the output signal terminal Output.
  • the second node pull-down module 304 includes a sixth thin film transistor M6 and an eighth thin film transistor M8.
  • the control terminal of the sixth thin film transistor M6 is connected to the first node PU, the first terminal is connected to the low-level signal terminal V ss , and the second terminal is connected to the second node PD; the control terminal of the eighth thin film transistor M8 is connected to the first node PU The first terminal is connected to the low-level signal terminal V ss , and the second terminal is connected to the second node pull-up module 301.
  • the second node pull-up module 301 includes a ninth thin film transistor M9 and a fifth thin film transistor M5.
  • the control terminal and the first terminal of the ninth thin film transistor M9 are both connected to the second clock signal terminal CLKB, and the second terminal is connected to the control terminal of the fifth thin film transistor M5; the control terminal of the fifth thin film transistor M5 is connected to the first terminal of the ninth thin film transistor M9.
  • the two terminals are connected, the first terminal is connected to the low-level signal terminal V ss , and the second terminal is connected to the first node PU.
  • the first node pull-down module 305 includes a second thin film transistor M2 and a tenth thin film transistor M10.
  • the control terminal of the second thin film transistor M2 is connected to the reset signal terminal Reset PU, the first terminal is connected to the low-level signal terminal V ss , and the second terminal is connected to the first node PU; the control terminal of the tenth thin film transistor M10 is connected to the second node PD The first terminal is connected to the low-level signal terminal V ss , and the second terminal is connected to the first node PU.
  • the reset module 303 includes a fourth thin film transistor M4 and a seventh thin film transistor M7.
  • the fourth thin film transistor M4 control terminal is connected to the reset signal terminal Reset PU, the first terminal is connected to the low-level signal terminal V ss , and the second terminal is connected to the output signal terminal Output; the seventh thin film transistor M7 control terminal is connected to the second node PD The first terminal is connected to the low-level signal terminal V ss , and the second terminal is connected to the output signal terminal Output.
  • first to eleventh thin film transistors are all P-type thin film transistors and / or N-type thin film transistors.
  • the first end and the second end of each thin film transistor can be interchanged.
  • the driving process of the shift register circuit with the above specific structure will be described by taking the control terminal as the gate, the first terminal as the source, and the second terminal as the drain as an example.
  • the driving cycle of the shift register circuit in this embodiment includes three phases in sequence.
  • the high-level signal terminal V 1 is connected to the power voltage signal terminal V gh (as shown in FIG. 4), High level is always input, and low level signal terminal V ss is always input low level.
  • the input signal terminal Input and the second clock signal terminal CLKB output a high level
  • the reset signal terminal Reset PU and the first clock signal terminal CLKA output a low level.
  • the eleventh thin film transistor M11 is turned on and outputs a high level.
  • the thermistor R in the voltage dividing module 103 divides the first thin film transistor M1, the first thin film transistor M1 is turned on, and the first node PU voltage is increased, and the storage capacitor C Perform the first charge.
  • the second clock signal terminal CLKB outputs a high level
  • the ninth thin film transistor M9 and the fifth thin film transistor M5 are turned on.
  • the first node PU is pulled up, the sixth thin film transistor M6 and the eighth thin film transistor M8 are turned on, and the low level signal terminal V ss is used to give the low level of the second node PD to pull down the second node PD voltage.
  • the second thin film transistor M2, the tenth thin film transistor M10, the fourth thin film transistor M4, and the seventh thin film transistor M7 are turned off, and the first node pull-down module 305 and the reset module 303 have no signal output.
  • the third thin film transistor M3 is turned on, and the output signal terminal Output outputs a low level.
  • the first clock signal terminal CLKA outputs a high level
  • the input signal terminal Input the second clock signal terminal CLKB, and the reset signal terminal Reset PU output a low level
  • the eleventh thin film transistor M11 is turned off
  • the first thin film The transistor M1 is turned off. Due to the bootstrapping effect of the storage capacitor C, the PU level of the first node continues to rise, the sixth thin film transistor M6 and the eighth thin film transistor M8 are turned on, the second node pull-down module 304 outputs a low level, and the second node PD voltage continues to be maintained Low.
  • the third thin film transistor M3 is turned on, and the output signal terminal Output outputs a high-level signal.
  • the second thin film transistor M2 and the tenth thin film transistor M10 are turned off, and the first node pull-down module 305 has no signal output.
  • the fourth thin film transistor M4 and the seventh thin film transistor M7 are turned off, and no signal is output from the reset module 303.
  • the fifth thin film transistor M5 and the ninth thin film transistor M9 are turned off, and the second node pull-up module 301 has no signal output.
  • the reset signal terminal Reset PU and the second clock signal terminal CLKB output a high level, and the input signal terminal Input and the first clock signal terminal CLKA output a low level.
  • the transistor M1 is turned off.
  • the fifth thin film transistor M5 and the ninth thin film transistor M9 are turned on, and the potential of the second node PD is pulled up.
  • the second thin film transistor M2, the tenth thin film transistor M10 is turned on, the first node PU is pulled down to a low level, and the third thin film transistor M3 is turned off.
  • the sixth thin film transistor M6 and the eighth thin film transistor M8 are turned off, and the second node pull-down module 304 has no signal output.
  • the fourth thin film transistor M4 and the seventh thin film transistor M7 are turned on, and the potential of the output signal terminal Output is reset to a low level.
  • the shift register driving circuit includes a plurality of cascaded shift register circuits, except for the first and last shift register circuits.
  • the input signal terminal Input of each stage of the shift register circuit in the middle is connected to the output signal terminal Output of the previous stage shift register circuit, and the reset signal terminal ResetPU is connected to the output signal terminal Output of the next stage shift register circuit.
  • the output end is connected to one end of a gate line; the input signal end Input of the first shift register circuit receives an initial signal STV (the gate drive circuit shift register "shift" pulse), and the weight of the last shift register circuit
  • the reset signal terminal receives a reset signal Reset.
  • the shift register circuit in this embodiment is the n-th shift register circuit
  • its input signal is the output signal Output (n-1) of the n-1th shift register circuit
  • its reset signal is the first
  • the output signals Output (n + 1) of the n + 1 shift register circuits are Output (n).
  • the high-level signal terminal V 1 is connected to a power-supply voltage signal terminal V gh capable of providing a high-level signal
  • each shift register is connected to the power-supply voltage signal terminals V gh
  • the first clock signal terminal CLKA and the second clock signal terminal CLKB are connected.
  • the high-level signal terminal V 1 in the embodiment of the present disclosure may also be connected to the clock signal terminal CI.
  • the high-level signal terminal V 1 of the shift register circuit of the odd-numbered row is connected to the first clock signal terminal CLKA, and the even-numbered High-level signal terminals of the shift register circuits of the rows are connected to the second clock signal terminal CLKB; or high-level signal terminals of the shift register circuits of the even rows are connected to the first clock signal CLKA terminal, and the odd-numbered
  • the high-level signal terminal of the row shift register circuit is connected to the second clock signal terminal CLKB.
  • the driving principle of the shift register circuit in FIG. 7 in each period is the same as the above embodiment, except that the shift register circuit in FIG.
  • the terminal CI is used as a high-level signal terminal V 1 to provide a high level to the shift register circuit.
  • the clock signal terminal CI is used as the high-level signal terminal V 1 , the high-level signal terminal V 1 needs to be connected.
  • a high-level clock signal terminal CI is output. As shown in FIG.
  • the shift register circuit described in this embodiment is the n-th shift register circuit, the first clock signal terminal CLKA is high when the eleventh thin film transistor M11 is turned on, then the high of the n-th shift register circuit is high.
  • the level signal terminal V 1 is connected to the first clock signal terminal CLKA; in the previous period and the next period when the eleventh thin film transistor M11 of the n-th shift register circuit is turned on, the second clock signal terminal CLKB is a high voltage Level, so the high-level signal terminal V 1 of the n-1th shift register circuit and the n + 1th shift register circuit is connected to the second clock signal terminal CLKB, thereby ensuring that each shift during the circuit driving process
  • the high-level signal terminal V 1 of the register circuit is input to a high level.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including a plurality of cascaded shift register circuits as described above.
  • the gate driving circuit can be directly integrated on the array substrate of the display device by using the same process as the thin film transistor to realize the progressive scanning driving function.
  • FIG. 9 is a schematic structural diagram of a gate driving circuit 20 according to at least one embodiment of the present disclosure.
  • the gate driving circuit 20 includes a plurality of cascaded shift register circuits 10.
  • the shift register unit 10 may adopt any one of the shift register circuits provided in the above embodiments.
  • the input signal terminal Input of each stage of the shift register circuit in the middle is connected to the output signal terminal Output of the previous stage shift register circuit and reset
  • the signal terminal Reset PU is connected to the output signal terminal Output of the next-stage shift register circuit, and the output signal terminal Output is connected to one end of a grid line;
  • the input signal terminal Input of the first-stage shift register circuit receives an initial signal STV (The gate drive circuit shift register "shift" pulse), the reset signal terminal of the last stage shift register circuit receives a reset signal Reset.
  • the gate driving circuit 20 may further include a timing controller 300.
  • the timing controller 300 is configured to provide a power voltage signal terminal V gh , a first clock signal terminal CLKA, a second clock signal terminal CLKB, and a low-level signal terminal V ss .
  • the timing controller 300 may also be configured to provide an initial signal STV and Reset signal Reset.
  • FIG. 10 is a schematic structural diagram of a gate driving circuit 40 according to at least one embodiment of the present disclosure.
  • the gate driving circuit 40 includes a plurality of cascaded shift register circuits 30.
  • the shift register unit 30 may adopt any one of the shift register circuits provided in the above embodiments.
  • the input signal terminal Input of each stage of the shift register circuit in the middle is connected to the output signal terminal Output of the previous stage shift register circuit and reset
  • the signal terminal Reset PU is connected to the output signal terminal Output of the next-stage shift register circuit, and the output signal terminal Output is connected to one end of a grid line;
  • the input signal terminal Input of the first-stage shift register circuit receives an initial signal STV (The gate drive circuit shift register "shift" pulse), the reset signal terminal of the last stage shift register circuit receives a reset signal Reset.
  • the gate driving circuit 20 may further include a timing controller 400.
  • the timing controller 300 is configured to provide a first clock signal terminal CLKA, a second clock signal terminal CLKB, and a low-level signal terminal V ss .
  • the timing controller 300 may be further configured to provide an initial signal STV and a reset signal Reset.
  • the first voltage terminals of two adjacent shift register circuits are respectively connected to the first clock signal terminal CLKA or the second clock signal terminal CLKB.
  • one shift register unit B is a lower stage shift register unit of another shift register unit A.
  • the gate scan signal output by the shift register unit B is late in timing.
  • one shift register unit B is an upper-level shift register unit of another shift register unit A.
  • the gate scan signal output by the shift register unit B is earlier in timing than the gate output by the shift register unit A. Scan signal.
  • At least one embodiment of the present disclosure also provides an array substrate including the gate driving circuit as described above.
  • the shift register circuit in the array substrate has the same advantages as the shift register circuit in the above embodiment, and will not be described again here.
  • an array substrate 1000 includes any gate driving circuit 1100 provided by an embodiment of the present disclosure.
  • the array substrate 1000 includes an array of a plurality of pixel units 1300.
  • the array substrate 1000 may further include a data driving circuit 1200.
  • the data driving circuit 1200 is used to provide a data signal to the pixel array;
  • the gate driving circuit 1100 is used to provide a gate scanning signal to the pixel array.
  • the data driving circuit 1200 is electrically connected to the pixel unit 1300 through the data line 21, and the gate driving circuit 1100 is electrically connected to the pixel unit 1300 through the gate line 11.
  • the high-level signal terminal V 1 of the shift register circuit in the array substrate may be connected to a power supply voltage signal terminal V gh capable of providing a high-level signal, or may be connected to the clock signal terminal CI.
  • the high-level signal terminal V 1 of the shift register circuit of the odd-numbered row is connected to the first clock signal terminal CLKA
  • the high-level signal terminal of the shift register circuit of the even-numbered row is connected to the first clock signal terminal CLKA.
  • the second clock signal terminal CLKB is connected.
  • the high-level signal terminals of the shift register circuits of the even-numbered rows are connected to the first clock signal terminal CLKA, and the high-level signal terminals of the shift register circuits of the odd-numbered rows are connected to the first clock signal terminal CLKA.
  • the two clock signal ends CLKB are connected.
  • At least one embodiment of the present disclosure also provides a display device including any array substrate as described above.
  • a display device 1200 according to at least one embodiment of the present disclosure includes any array substrate 1210 as described above.
  • the display device may be a liquid crystal panel, electronic paper, or OLED (Organic Light-Emitting Diode) panel, and is applied to mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, Any product or component with a display function, such as a navigator.
  • OLED Organic Light-Emitting Diode

Abstract

一种移位寄存器电路及其驱动方法、栅极驱动电路(20，40)、阵列基板(1000)和显示装置(1200)，其中移位寄存器电路包括输入子电路(100)和信号输出子电路(300)，其中，输入子电路(100)包括：控制模块(101)，与输入信号端(Input)和第一电压端(V 1)连接，被配置为在输入信号的控制下将第一电压端(V 1)的信号输出至分压节点(PR)；输入模块(102)，输入模块(102)的输入端与分压节点(PR)连接，输入模块(102)的输出端与信号输出子电路(300)连接，被配置为在控制模块(101)的控制下将分压节点(PR)的信号输出至信号输出子电路(300)；分压模块(103)，分压模块(103)的第一端与控制模块(101)连接，分压模块(103)的第二端第二电压端(Vss)连接，分压模块(103)的阻值与温度负相关；信号输出子电路(300)与输入模块(102)的输出端连接，被配置为在输入模块(102)的控制下将栅极扫描信号输出至输出信号端(Output)。该移位寄存器电路可改善薄膜晶体管阈值电压漂移，提高显示装置不同温度的显示稳定性。

Description

移位寄存器电路及其驱动方法、栅极驱动电路、阵列基板和显示装置
相关申请的交叉引用
本申请要求于2018年6月1日递交的第201810555823.9号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器电路及其驱动方法、栅极驱动电路、阵列基板和显示装置。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)中包括像素矩阵，在显示过程中通过栅极驱动电路输出栅极扫描信号，逐行扫描访问各像素。栅极驱动电路用于产生像素的栅极扫描信号。GOA(Gate Driver on Array，阵列基板行驱动)是一种将栅极驱动电路集成于TFT(Thin Film Transistor，薄膜晶体管)基板上的技术，每个GOA单元作为一个移位寄存器将栅极扫描信号依次传递给下一GOA单元，逐行开启像素的薄膜晶体管开关，完成像素的栅极扫描信号的输入。
发明内容
本公开的实施例提供一种移位寄存器电路，包括输入子电路和信号输出子电路，其中，
输入子电路包括：
控制模块，与输入信号端和第一电压端连接，控制模块被配置为在输入信号端提供的输入信号的控制下将第一电压端的信号输出至分压节点；
输入模块，输入模块的输入端与分压节点连接，输入模块的输出端与信号输出子电路连接，输入模块被配置为在控制模块的控制下将 分压节点的信号输出至信号输出子电路；
分压模块，分压模块的第一端与控制模块相连，分压模块的第二端与第二电压端连接，分压模块的阻值与温度负相关；
信号输出子电路与输入模块的输出端连接，信号输出子电路被配置为在输入模块的控制下将栅极扫描信号输出至输出信号端。
本公开实施例还提供了一种栅极驱动电路，包括多个级联的移位寄存器电路，所述移位寄存器电路采用如上所述的移位寄存器电路。
本公开实施例还提供了一种阵列基板，包括如上所述的栅极驱动电路。
本公开实施例还提供了一种显示装置，包括如上所述的阵列基板。
本公开实施例还提供了一种驱动上述的移位寄存器的方法，包括：
向输入信号端输入具有有效电位的信号，向第一时钟信号端输入具有无效电位的信号，以使得控制模块向分压节点输出来自第一电压端的有效电位信号，并使得输入模块在控制模块的控制下将分压节点的信号输出至第一节点，以对充放电模块进行充电；
向第一时钟信号端输入具有有效电位的信号，向输入信号端输入具有无效电位的信号，以对充放电模块进行充电，并使得充放电模块在第一节点的控制下向输出信号端输出来自第一时钟信号端的、处于有效电位的信号；以及
向复位信号端和第二时钟信号端输入具有有效电位的信号，使得第二节点电平改变模块将第二节点的电位改变为有效电位，并使得复位模块在处于有效电位的第二节点和处于有效电位的复位信号端的控制下向输出信号端输出来自第二电压端的无效电位信号。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种移位寄存器电路的结构图；
图2为本公开至少一个实施例中移位寄存器电路的结构图；
图3为本公开至少一个实施例中移位寄存器电路的结构图；
图4为本公开至少一个实施例中移位寄存器电路的结构图；
图5为本公开至少一个实施例中移位寄存器电路的驱动时序图；
图6为图4所示移位寄存器电路的级联图；
图7为本公开至少一个实施例中移位寄存器电路的结构图；
图8为图7所示移位寄存器电路的级联图；
图9为根据本公开至少一个实施例的栅极驱动电路的结构示意图；
图10为根据本公开至少一个实施例的栅极驱动电路的结构示意图；
图11为根据本公开至少一个实施例的阵列基板的结构示意图；
图12为根据本公开至少一个实施例的显示装置的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一端，漏极称为第二端，然而应理解在其他实施例中，源极还可以是第二端，漏极 还可以是第一端，本公开的实施例对此不作限制。
本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管，其中，P型开关晶体管在栅极施加有低电平电位时导通，在栅极施加有高电平电位时截止，N型开关晶体管在栅极施加有高电平电位时导通，在栅极施加有低电平电位时截止。此外，本公开各个实施例中的多个信号都对应有高电平电位和低电平电位，信号的有效电位为使开关晶体管导通的电位，例如：对于P型开关晶体管，低电平电位为有效电位，对于N型开关晶体管，高电平电位为有效电位。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
并且，术语“上拉”、“下拉”的具体含义也将根据所采用的晶体管的具体类型而相应调整，只要能实现对于晶体管的控制以实现相应的开关功能。
在下文中，将以各电路通过N型晶体管实现为例来描述本公开的各实施例，然而，应理解，本公开并不限于此。
在相关技术中的移位寄存器电路中，控制信号输入的薄膜晶体管器件的控制端在不同温度下工作，会导致该薄膜晶体管阈值电压漂移现象，使移位寄存器电路在面板长时间显示过程中稳定性变差，干扰正常扫描信号的输出。图1示出了一种移位寄存器电路，该移位寄存器电路的应用环境不同，薄膜晶体管的实际工作温度并不固定，其阈值电压会随着温度的变化而产生漂移。低温状态下，第一薄膜晶体管M1阈值电压变大，第一薄膜晶体管M1打开较晚，会导致电容充电不足的现象，电容充电不足会导致第一节点PU电位较低，控制端电压上升及下降时间较长，面内薄膜晶体管充电率不足，导致 屏幕亮度无法达到标准。高温状态下，第一薄膜晶体管M1阈值电压变小，第一薄膜晶体管M1打开较早，第一节点PU提前充电，移位寄存器电路提前打开，导致与上一行同时输出，出现信号串行，画面异常的现象。
基于上述现状，本公开的技术方案提出：通过在不同温度对控制信号输入的薄膜晶体管的控制端电压给入不同电压值，实现对该控制端电压的温度补偿，从而改善控制信号输入的薄膜晶体管阈值电压漂移导致的低温状态下移位寄存器电路充电不足，以及高温状态下输出信号异常的现象。
本公开的至少一个实施例提供了一种移位寄存器电路，包括输入子电路和信号输出子电路。输入子电路包括：控制模块、输入模块以及分压模块。控制模块与输入信号端和第一电压端连接，控制模块被配置为在输入信号的控制下将第一电压端的信号输出至分压节点。输入模块的输入端与分压节点连接，输入模块的输出端与信号输出子电路连接，输入模块被配置为在控制模块的控制下将分压节点的信号输出至信号输出子电路。分压模块的第一端与控制模块相连，分压模块的第二端与第二电压端连接，分压模块的阻值与温度负相关。信号输出子电路与输入模块的输出端连接，信号输出子电路被配置为在输入模块的控制下将栅极扫描信号输出至输出信号端。
如图2所示，本公开实施例提供一种移位寄存器电路，包括输入子电路100和信号输出子电路300，其中，输入子电路100包括控制模块101、输入模块102和分压模块103；控制模块101与输入信号端Input和高电平信号端V 1连接，控制模块101被配置为在输入信号的控制下将高电平信号端V 1的信号输出至分压节点PR；输入模块102的输入端与分压节点PR连接，输入模块102的输出端与信号输出子电路300连接，输入模块102被配置为在控制模块101的控制下将分压节点PR的信号输出至信号输出子电路300；分压模块103与控制模块101相连，还与低电平信号端V ss连接，分压模块103的阻值与温度负相关；信号输出子电路300与输入模块102的输出端连接，信号输出子电路300被配置为在输入模块102的控制下将栅极扫描信号输出至输出信号端。高电平信号端V 1为上述的第一电压端的示例，以及低电平信号端V ss为上述的第二电压端的示例。在本公开的实施例中，第一电压端用于输入能够使开关晶体管导通的有效电位信号，以及第二电压端用于输入能够使开关晶体管截止的无效电位信号。
在一些实施例中，输入模块102包括第一薄膜晶体管M1，第一薄膜晶体管M1的控制端和第一端连接分压节点PR，第二端连接信号输出子电路300。
控制模块101在输入信号的控制下打开，输出高电平信号，从而控制第一薄膜晶体管M1打开，信号输出子电路300在第一薄膜晶体管M1的控制下输出栅极驱动信号。分压模块103用于对第一薄膜晶体管M1进行分压。在低温状态下，第一薄膜晶体管M1控制端受低温影响阈值电压变大，通过在移位寄存器电路中设置分压模块103，低温下分压模块103的阻值较大，进而分压较大，分压节点PR电位升高，第一薄膜晶体管M1控制端给入高电压，补偿阈值电压产生的漂移；在高温状态下，第一薄膜晶体管M1控制端受高温影响阈值电压减小，高温下分压模块103的分压减小，分压节点PR电位降低，虽然第一薄膜晶体管M1控制端电压较低，但是高电平信号端V 1输入一个较高的高电平，即使此时第一薄膜晶体管M1控制端电位较小，也能够满足电容充电的需求，从而补偿阈值电压产生的漂移。
在一些实施例中，控制模块包括输入薄膜晶体管，输入薄膜晶体管的控制端连接输入信号端，输入薄膜晶体管的第一端连接第一电压端，输入薄膜晶体管的第二端连接分压节点。
例如，在一些实施例中，控制模块101包括第十一薄膜晶体管M11，第十一薄膜晶体管M11控制端连接输入信号端Input，第一端连接高电平信号端V 1，第二端连接分压节点PR。第十一薄膜晶体管M11为上述的输入薄膜晶体管的示例。
在一些实施例中，高电平信号端V 1为电源电压信号端V gh，为移位寄存器电路接入高电平电压。高电平信号端V 1输出的电平信号值为27V～36V。高电平信号端V 1输出的电平信号的大小是根据不同产品的薄膜晶体管特性来确定，例如可以根据实际使用条件选用27V、30V、36V等。
在一些实施例中，分压模块103包括热敏电阻R，热敏电阻R一端连接分压节点PR，另一端连接低电平信号端V ss。热敏电阻器的选取主要根据第十一薄膜晶体管M11的关闭阻值决定，由于移位寄存器更多时间处于关闭状态，第十一薄膜晶体管M11关闭时与热敏电阻R分压，为了减少第一薄膜晶体管M1控制端受偏压影响，一般选取阻值合适的热敏电阻R使分压点电 位接近0V。热敏电阻R可以选用负温度系数热敏电阻器，是一类电阻值随温度增大而减小的传感器电阻。选用的负温度系数热敏电阻器的零功率电阻为210Ω～230Ω，工作温度-25℃～105℃。例如，可以选用TPM-S系列TPM1S221N090R型号的热敏电阻器。
在一些实施例中，信号输出子电路可包括充放电模块、第二节点保持模块、第二节点电平改变模块、第一节点降噪模块和复位模块。
充放电模块的第一输入端与输入模块的输出端和第一节点降噪模块的输出端在第一节点处连接，充放电模块的第二输入端与第一时钟信号端连接，充放电模块的输出端与输出信号端连接，充放电模块用于在第一阶段，在第一薄膜晶体管的输出信号及第一时钟信号的共用作用下进行第一次充电，在第二阶段，在第一节点的电位及第一时钟信号的作用下进行第二次充电，并输出栅极扫描信号。
第二节点保持模块的第一输入端与第二电压端连接，第二节点保持模块的第二输入端与第一节点连接，第二节点保持模块的第一输出端与第二节点电平改变模块的第二输入端连接，第二节点保持模块的第二输出端与第二节点电平改变模块的输出端、第一节点降噪模块的第三输入端和复位模块的第二输入端在第二节点处连接，第二节点保持模块用于在第一阶段和第二阶段，在第一节点的电位和无效电位信号的共同作用下，使第二节点的电位保持无效电位。
第二节点电平改变模块的第一输入端与第二时钟信号端连接，第二节点电平改变模块的第二输入端与第二节点保持模块第一输出端连接，第二节点电平改变模块的输出端与第二节点连接，第二节点电平改变模块用于在第三阶段，在第二时钟信号和第二节点保持模块的输出信号的共同作用下，改变第二节点的电位。
第一节点降噪模块的第一输入端与复位信号端连接，第一节点降噪模块的第二输入端与第二电压端连接，第一节点降噪模块的第三输入端与第二节点连接，第一节点降噪模块的输出端与第一节点连接，第一节点降噪模块用于在第三阶段，在复位信号、无效电位信号和第二节点的电位的共同作用下，改变第一节点的电位。
复位模块的第一输入端与复位信号端连接，复位模块的第二输入端与第 二节点连接，复位模块的第三输入端与第二电压端连接，复位模块的输出端与输出信号端连接，复位模块用于在第三阶段，在复位信号、第二节点的电位和无效电位信号的共同作用下，对输出信号端的电位进行复位。
第一时钟信号和第二时钟信号互为反相信号。
在一些实施例中，移位寄存器电路的一个驱动周期依次包括第一阶段、第二阶段和第三阶段，如图3所示，信号输出子电路300包括充放电模块302、第二节点下拉模块304、第二节点上拉模块301、第一节点下拉模块305和复位模块303；其中，充放电模块302的第一输入端与输入模块102的输出端和第一节点下拉模块305的输出端连接，三者连接的公共端为第一节点PU，充放电模块的第二输入端与第一时钟信号端CLKA连接，充放电模块的输出端与输出信号端Output连接，充放电模块302用于在第一阶段在输入模块102的输出信号及第一时钟信号CLKA的共用作用下进行第一次充电，在第二阶段在第一节点PU的电位及第一时钟信号CLKA的作用下进行第二次充电，并输出栅极扫描信号；第二节点下拉模块304的第一输入端与低电平信号端连接，第二节点下拉模块304的第二输入端与第一节点PU连接，第二节点下拉模块304的第一输出端与第二节点上拉模块301的第二输入端连接，第二节点下拉模块304的第二输出端与第二节点上拉模块301的输出端、第一节点下拉模块305的第三输入端和复位模块303的第二输入端连接，它们连接的公共端为第二节点PD，第二节点下拉模块304用于在第一阶段和第二阶段，在第一节点PU的电位和低电平信号的共同作用下，使第二节点PD的电位保持低电位；第二节点上拉模块301的第一输入端与第二时钟信号端CLKB连接，第二节点上拉模块的第二输入端与第二节点下拉模块304第一输出端连接，第二节点上拉模块的输出端与第二节点PD连接，第二节点上拉模块301用于在第三阶段，在第二时钟信号和第二节点下拉模块304的输出信号的共同作用下，将第二节点PD的电位上拉；第一节点下拉模块305的第一输入端与复位信号端Reset PU连接，第一节点下拉模块的第二输入端与低电平信号端连接，第一节点下拉模块的第三输入端与第二节点PD连接，第一节点下拉模块的输出端与第一节点PU连接，第一节点下拉模块305用于在第三阶段，在复位信号、低电平信号、第二节点PD电位的共同作用下，将第一节点PU的电位下拉，实现第一节点PU降噪；复位模块303的第一 输入端与复位信号端Reset PU连接，复位模块的第二输入端与第二节点PD连接，复位模块的第三输入端与低电平信号端连接，复位模块的输出端与输出信号端Output连接，复位模块303用于在第三阶段，在复位信号、第二节点PD电位、低电平信号的共同作用下，对输出信号端Output的电位进行复位。第二节点下拉模块304为上述的第二节点保持模块的示例，第二节点上拉模块301为上述的第二节点电平改变模块的示例，以及第一节点下拉模块305为上述的第一节点降噪模块的示例。此外，低电平信号为上述的无效电位信号的示例。
其中，所述第一时钟信号和所述第二时钟信号互为反相信号。高电平信号端V 1与能够提供高电平信号的电源电压信号端V gh相连，还可以连接时钟信号端CI，例如，奇数行的移位寄存器电路的高电平信号端V 1与所述第一时钟信号端CLKA相连，偶数行的移位寄存器电路的高电平信号端与所述第二时钟信号端CLKB相连；或者，偶数行的移位寄存器电路的高电平信号端与所述第一时钟信号端CLKA相连，奇数行的移位寄存器电路的高电平信号端与所述第二时钟信号端CLKB相连。高电平信号为上述的有效电位信号的示例。
上述移位寄存器电路的驱动周期依次包括三个阶段，在这三个阶段中高电平信号端V 1始终输入高电平，低电平信号端V ss始终输入低电平。三个阶段依次为：
第一阶段t 1，输入信号端Input、第二时钟信号端CLKB输出高电平，复位信号端Reset PU、第一时钟信号端CLKA输出低电平，控制模块101打开，分压模块103对输入模块102进行分压，输入模块102中的第一薄膜晶体管M1打开，拉高第一节点PU电压，充放电模块302打开并进行第一次充电。第一节点下拉模块305和复位模块303关闭，第二节点下拉模块304和第二节点上拉模块301打开，复位信号端Reset PU和第一时钟信号端CLKA输出的低电平信号使第二节点PD的电位下拉。第一阶段t 1中，第一薄膜晶体管M1打开后温度逐渐升高，第一薄膜晶体管M1控制端受高温影响阈值电压逐渐减小，高温下分压模块103的分压逐渐减小，分压节点PR电位逐渐降低，致使第一薄膜晶体管M1控制端电压较低，但由于高电平信号端V 1输入一个较高的高电平，即使此时第一薄膜晶体管M1控制端电位较小，也能够 满足电容充电的需求，从而补偿补偿阈值电压产生的漂移。
第二阶段t 2，第一时钟信号端CLKA输出高电平，输入信号端Input、第二时钟信号端CLKB、复位信号端Reset PU输出低电平，控制模块101关闭，输入模块102关闭，充放电模块302进行第二次充电，第一节点PU电压继续升高，输出信号端Output输出高电平的栅极驱动信号。第一节点下拉模块305和复位模块303关闭，第二节点下拉模块304和第二节点上拉模块301打开，复位信号端Reset PU和第二时钟信号端CLKB输出的低电平信号使第二节点PD的电位下拉。第二阶段t 2中，输入模块102关闭后温度逐渐降低，输入模块102中的第一薄膜晶体管M1控制端受低温影响阈值电压逐渐变大，分压模块103的阻值受低温影响逐渐变大，进而分压变大，分压节点PR电位升高，第一薄膜晶体管M1控制端逐渐给入高电压，补偿阈值电压产生的漂移。
第三阶段t 3，复位信号端Reset PU、第二时钟信号端CLKB输出高电平，输入信号端Input、第一时钟信号端CLKA输出低电平，控制模块101关闭，输入模块102关闭，分压模块103继续发挥低温下对输入模块102的分压作用。第二节点上拉模块301打开，第二节点PD的电位上拉；第二节点下拉模块304关闭，第一节点下拉模块305将低电平信号输出到第一节点PU，第一节点PU的电位下拉，实现第一节点PU降噪；复位模块303打开，将低电平信号输出到输出信号端Output，对输出信号端Output的电位进行复位。
经过第一阶段t 1至第三阶段t 3，在一帧的一条栅线的驱动时间内，输出信号端Output输出一持续时间为t 2的高电平脉冲信号，该高电平脉冲信号被输出至与该级移位寄存器电路相连的栅线，从而完成对该条栅线的驱动。重复第一阶段t 1至第三阶段t3即能够完成下一帧的该条栅线的驱动。
由上述移位寄存电路及其驱动周期中的过程能够得到，利用高电平信号端V 1输入的高电平信号，输入模块102中的第一薄膜晶体管M1在高温和低温环境下工作，分压模块103对第一薄膜晶体管M1进行分压，通过在不同温度对第一薄膜晶体管M1的控制端电压给入不同电压值，实现对第一薄膜晶体管M1控制端电压的温度补偿，从而改善第一薄膜晶体管M1阈值电压漂移导致的低温状态下移位寄存器电路充电不足，以及高温状态下输出信号异常的现象，提高移位寄存器电路的稳定性。
下面对本实施例所提供的移位寄存器电路各功能单元的具体实现结构进行举例说明。如图4或图7所示，充放电模块302包括第三薄膜晶体管M3和存储电容C。第三薄膜晶体管M3控制端与第一节点PU连接，第一端与第一时钟信号端CLKA连接，第二端与输出信号端Output连接；存储电容C的第一端与第一节点PU连接，第二端与输出信号端Output连接。
第二节点下拉模块304包括第六薄膜晶体管M6和第八薄膜晶体管M8。第六薄膜晶体管M6控制端与第一节点PU连接，第一端与低电平信号端V ss连接，第二端与第二节点PD连接；第八薄膜晶体管M8控制端与第一节点PU连接，第一端与低电平信号端V ss连接，第二端与第二节点上拉模块301连接。
第二节点上拉模块301包括第九薄膜晶体管M9和第五薄膜晶体管M5。第九薄膜晶体管M9控制端和第一端均与第二时钟信号端CLKB连接，第二端与第五薄膜晶体管M5的控制端连接；第五薄膜晶体管M5控制端与第九薄膜晶体管M9的第二端连接，第一端与低电平信号端V ss连接，第二端与第一节点PU连接。
第一节点下拉模块305包括第二薄膜晶体管M2和第十薄膜晶体管M10。第二薄膜晶体管M2控制端与复位信号端Reset PU连接，第一端与低电平信号端V ss连接，第二端与第一节点PU连接；第十薄膜晶体管M10控制端与第二节点PD连接，第一端与低电平信号端V ss连接，第二端与第一节点PU连接。
复位模块303包括第四薄膜晶体管M4和第七薄膜晶体管M7。第四薄膜晶体管M4控制端与复位信号端Reset PU连接，第一端与低电平信号端V ss连接，第二端与输出信号端Output连接；第七薄膜晶体管M7控制端与第二节点PD连接，第一端与低电平信号端V ss连接，第二端与输出信号端Output连接。
需要说明的是，上述第一至第十一薄膜晶体管均为P型薄膜晶体管和/或N型薄膜晶体管。上述各薄膜晶体管的第一端和第二端可以互换。在本实施例中以控制端为栅极、第一端为源极、第二端为漏极为例对上述具体结构的移位寄存器电路的驱动过程进行说明。
如图5所示，本实施例中移位寄存器电路的驱动周期依次包括三个阶段， 在这三个阶段中高电平信号端V 1连接电源电压信号端V gh(如图4所示)，始终输入高电平，低电平信号端V ss始终输入低电平。
第一阶段t 1，输入信号端Input、第二时钟信号端CLKB输出高电平，复位信号端Reset PU、第一时钟信号端CLKA输出低电平。第十一薄膜晶体管M11打开，输出高电平，分压模块103中的热敏电阻R对第一薄膜晶体管M1进行分压，第一薄膜晶体管M1打开，拉高第一节点PU电压，存储电容C进行第一次充电。第二时钟信号端CLKB输出高电平，第九薄膜晶体管M9、第五薄膜晶体管M5打开。第一节点PU上拉，第六薄膜晶体管M6、第八薄膜晶体管M8打开，利用低电平信号端V ss给第二节点PD的低电平，使第二节点PD电压下拉。第二薄膜晶体管M2、第十薄膜晶体管M10、第四薄膜晶体管M4、第七薄膜晶体管M7关闭，第一节点下拉模块305和复位模块303无信号输出。第三薄膜晶体管M3打开，输出信号端Output输出低电平。
第二阶段t 2，第一时钟信号端CLKA输出高电平，输入信号端Input、第二时钟信号端CLKB、复位信号端Reset PU输出低电平，第十一薄膜晶体管M11关闭，第一薄膜晶体管M1关闭。由于存储电容C的自举作用，第一节点PU电平继续升高，第六薄膜晶体管M6和第八薄膜晶体管M8打开，第二节点下拉模块304输出低电平，第二节点PD电压继续保持低电平。第三薄膜晶体管M3打开，输出信号端Output输出高电平信号。第二薄膜晶体管M2、第十薄膜晶体管M10关闭，第一节点下拉模块305无信号输出。第四薄膜晶体管M4、第七薄膜晶体管M7关闭，复位模块303无信号输出。第五薄膜晶体管M5、第九薄膜晶体管M9关闭，第二节点上拉模块301无信号输出。
第三阶段t 3，复位信号端Reset PU、第二时钟信号端CLKB输出高电平，输入信号端Input、第一时钟信号端CLKA输出低电平，第十一薄膜晶体管M11关闭，第一薄膜晶体管M1关闭。第五薄膜晶体管M5、第九薄膜晶体管M9打开，第二节点PD的电位上拉。第二薄膜晶体管M2、第十薄膜晶体管M10打开，第一节点PU被下拉到低电平，进而第三薄膜晶体管M3关闭。第六薄膜晶体管M6、第八薄膜晶体管M8关闭，第二节点下拉模块304无信号输出。第四薄膜晶体管M4、第七薄膜晶体管M7打开，对输出信号端 Output的电位复位到低电平。
本实施例提供的移位寄存器电路的级联图如图6所示，在移位寄存器驱动电路中包括多个相互级联的移位寄存器电路，除第一个和最后一个移位寄存器电路外，中间每级移位寄存器电路的输入信号端Input均与上一级移位寄存器电路的输出信号端Output相连，复位信号端Reset PU均与下一级移位寄存器电路的输出信号端Output相连，输出端均与一条栅线的一端相连；第一个移位寄存器电路的输入信号端Input接收一初始信号STV(栅极驱动电路移位寄存器“位移”脉冲)，最后一个移位寄存器电路的重置信号端接收一重置信号Reset。因此，若本实施所述的移位寄存器电路为第n个移位寄存器电路，则其输入信号为第n-1个移位寄存器电路的输出信号Output(n-1)，其复位信号为第n+1个移位寄存器电路的输出信号Output(n+1)，其输出信号为Output(n)。
需说明的是，图6的级联图中，高电平信号端V 1与能够提供高电平信号的电源电压信号端V gh相连，每个移位寄存器都与电源电压信号端V gh、第一时钟信号端CLKA、第二时钟信号端CLKB连接。
本公开实施例中的高电平信号端V 1还可以连接时钟信号端CI，例如，奇数行的移位寄存器电路的高电平信号端V 1与所述第一时钟信号端CLKA相连，偶数行的移位寄存器电路的高电平信号端与所述第二时钟信号端CLKB相连；或者，偶数行的移位寄存器电路的高电平信号端与所述第一时钟信号CLKA端相连，奇数行的移位寄存器电路的高电平信号端与所述第二时钟信号端CLKB相连。如图7所示，图7中的移位寄存器电路在各时段的驱动原理与上述实施例相同，所不同的是，图7中的移位寄存器电路不设置电源电压信号端V gh，时钟信号端CI作为高电平信号端V 1，为移位寄存器电路提供高电平。为了使第十一薄膜晶体管M11导通时高电平信号端V 1的输入信号为高电平，当时钟信号端CI作为高电平信号端V 1时，高电平信号端V 1需要连接到在第十一薄膜晶体管M11导通时输出高电平的时钟信号端CI。如图8所示，由于第一时钟信号端CLKA、第二时钟信号端CLKB提供的信号为反相信号，因此在级联图中可以看出，相邻的两个移位寄存器电路分别连接第一时钟信号端CLKA或第二时钟信号端CLKB。若本实施所述的移位寄存器电路为第n个移位寄存器电路，其第十一薄膜晶体管M11导通时第一 时钟信号端CLKA为高电平，则第n个移位寄存器电路的高电平信号端V 1与第一时钟信号端CLKA连接；在第n个移位寄存器电路的第十一薄膜晶体管M11导通的上一个时段和下一个时段，第二时钟信号端CLKB为高电平，因此第n-1个移位寄存器电路和第n+1个移位寄存器电路的高电平信号端V 1与第二时钟信号端CLKB连接，从而保证在电路驱动过程中每个移位寄存器电路的高电平信号端V 1都输入高电平。
本公开至少一个实施例还提供了一种栅极驱动电路，其包括多个级联的如上所述的任一移位寄存器电路。该栅极驱动电路可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上，实现逐行扫描驱动功能。
例如，图9是根据本公开至少一个实施例的栅极驱动电路20的结构示意图。如图9所示，该栅极驱动电路20包括多个级联的移位寄存器电路10，移位寄存器单元10可以采用上述实施例中提供的任一移位寄存器电路。
例如，如图9所示，除第一个和最后一个移位寄存器电路外，中间每级移位寄存器电路的输入信号端Input均与上一级移位寄存器电路的输出信号端Output相连，复位信号端Reset PU均与下一级移位寄存器电路的输出信号端Output相连，输出信号端Output均与一条栅线的一端相连；第一级移位寄存器电路的输入信号端Input接收一初始信号STV(栅极驱动电路移位寄存器“位移”脉冲)，最后一级移位寄存器电路的重置信号端接收一重置信号Reset。
例如，如图9所示，该栅极驱动电路20还可以包括时序控制器300。时序控制器300被配置提供电源电压信号端V gh、第一时钟信号端CLKA、第二时钟信号端CLKB和低电平信号端V ss，时序控制器300还可以被配置为提供初始信号STV和复位信号Reset。
例如，图10是根据本公开至少一个实施例的栅极驱动电路40的结构示意图。如图10所示，该栅极驱动电路40包括多个级联的移位寄存器电路30，移位寄存器单元30可以采用上述实施例中提供的任一移位寄存器电路。
例如，如图10所示，除第一个和最后一个移位寄存器电路外，中间每级移位寄存器电路的输入信号端Input均与上一级移位寄存器电路的输出信号端Output相连，复位信号端Reset PU均与下一级移位寄存器电路的输出信号端Output相连，输出信号端Output均与一条栅线的一端相连；第一级移 位寄存器电路的输入信号端Input接收一初始信号STV(栅极驱动电路移位寄存器“位移”脉冲)，最后一级移位寄存器电路的重置信号端接收一重置信号Reset。
例如，如图10所示，该栅极驱动电路20还可以包括时序控制器400。时序控制器300被配置提供第一时钟信号端CLKA、第二时钟信号端CLKB和低电平信号端V ss，时序控制器300还可以被配置为提供初始信号STV和复位信号Reset。相邻的两个移位寄存器电路的第一电压端分别连接第一时钟信号端CLKA或第二时钟信号端CLKB。
需要说明的是，在本公开的实施例中，一个移位寄存器单元B是另一个移位寄存器单元A的下级移位寄存器单元表示：移位寄存器单元B输出的栅极扫描信号在时序上晚于移位寄存器单元A输出的栅极扫描信号。相应地，一个移位寄存器单元B是另一个移位寄存器单元A的上级移位寄存器单元表示：移位寄存器单元B输出的栅极扫描信号在时序上早于移位寄存器单元A输出的栅极扫描信号。
本公开至少一个实施例还提供了一种阵列基板，包括如上所述的栅极驱动电路。所述阵列基板中的移位寄存器电路与上述实施例中的移位寄存器电路具有的优势相同，此处不再赘述。
如图11所示，根据本公开至少一个实施例的阵列基板1000包括本公开的实施例提供的任一栅极驱动电路1100。该阵列基板1000包括由多个像素单元1300构成的阵列。例如，该阵列基板1000还可以包括数据驱动电路1200。数据驱动电路1200用于提供数据信号给像素阵列；栅极驱动电路1100用于提供栅极扫描信号给像素阵列。数据驱动电路1200通过数据线21与像素单元1300电连接，栅极驱动电路1100通过栅线11与像素单元1300电连接。
例如，在一些实施例中，阵列基板中移位寄存器电路的高电平信号端V 1可与能够提供高电平信号的电源电压信号端V gh相连，也可以连接至时钟信号端CI。例如，在一些实施例中，奇数行的移位寄存器电路的高电平信号端V 1与所述第一时钟信号端CLKA相连，偶数行的移位寄存器电路的高电平信号端与所述第二时钟信号端CLKB相连。例如，在另一些实施例中，偶数行的移位寄存器电路的高电平信号端与所述第一时钟信号端CLKA相连，奇数 行的移位寄存器电路的高电平信号端与所述第二时钟信号端CLKB相连。
本公开至少一个实施例还提供了一种显示装置，包括如上所述的任一阵列基板。如图12所示，根据本公开至少一个实施例的显示装置1200包括如上所述的任一阵列基板1210。
本公开一些实施例所提供的显示装置可以为液晶面板、电子纸或OLED(Organic Light-Emitting Diode，有机发光二极管)面板，应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (23)

  1. 一种移位寄存器电路，包括输入子电路和信号输出子电路，其中，所述输入子电路包括：
    控制模块，与输入信号端和第一电压端连接，所述控制模块被配置为在所述输入信号端提供的输入信号的控制下将所述第一电压端的信号输出至分压节点；
    输入模块，所述输入模块的输入端与分压节点连接，所述输入模块的输出端与信号输出子电路连接，所述输入模块被配置为在控制模块的控制下将分压节点的信号输出至信号输出子电路；
    分压模块，所述分压模块的第一端与所述控制模块相连，所述分压模块的第二端与第二电压端连接，所述分压模块的阻值与温度负相关；
    所述信号输出子电路与所述输入模块的输出端连接，所述信号输出子电路被配置为在所述输入模块的控制下在输出信号端输出栅极扫描信号。
  2. 根据权利要求1所述的移位寄存器电路，其中，所述控制模块包括输入薄膜晶体管，所述输入薄膜晶体管的控制端连接所述输入信号端，所述输入薄膜晶体管的第一端连接所述第一电压端，所述输入薄膜晶体管的第二端连接所述分压节点。
  3. 根据权利要求1或2所述的移位寄存器电路，其中，所述第一电压端为能够提供有效电位信号的电源电压信号端。
  4. 根据权利要求1至3任一所述的移位寄存器电路，其中，所述输入模块包括第一薄膜晶体管，所述第一薄膜晶体管的控制端和第一端连接所述分压节点，所述第一薄膜晶体管的第二端连接所述信号输出子电路。
  5. 根据权利要求1至4任一所述的移位寄存器电路，其中，所述分压模块包括热敏电阻，所述热敏电阻一端连接所述分压节点，另一端连接所述第二电压端。
  6. 根据权利要求5所述的移位寄存器电路，其中，所述热敏电阻包括负温度系数热敏电阻器。
  7. 根据权利要求6所述的移位寄存器电路，其中，所述负温度系数热敏 电阻器的零功率电阻为210Ω～230Ω，工作温度为-25℃～105℃。
  8. 根据权利要求4所述的移位寄存器电路，其中，所述信号输出子电路包括充放电模块、第二节点保持模块、第二节点电平改变模块、第一节点降噪模块和复位模块；其中，
    所述充放电模块的第一输入端与所述输入模块的输出端和所述第一节点降噪模块的输出端在第一节点处连接，所述充放电模块的第二输入端与第一时钟信号端连接，所述充放电模块的输出端与输出信号端连接，所述充放电模块用于在所述第一薄膜晶体管的输出信号及所述第一时钟信号端提供的第一时钟信号的共用作用下进行第一次充电，以及在所述第一节点的电位及所述第一时钟信号的作用下进行第二次充电，并输出栅极扫描信号；
    所述第二节点保持模块的第一输入端与所述第二电压端连接，所述第二节点保持模块的第二输入端与所述第一节点连接，所述第二节点保持模块的第一输出端与所述第二节点电平改变模块的第二输入端连接，所述第二节点保持模块的第二输出端与所述第二节点电平改变模块的输出端、所述第一节点降噪模块的第三输入端和所述复位模块的第二输入端在第二节点处连接，所述第二节点保持模块用于在所述第一节点的电位和所述第二电压端提供的无效电位信号的共同作用下，使所述第二节点的电位保持无效电位；
    所述第二节点电平改变模块的第一输入端与第二时钟信号端连接，所述第二节点电平改变模块的第二输入端与所述第二节点保持模块第一输出端连接，所述第二节点电平改变模块的输出端与所述第二节点连接，所述第二节点电平改变模块用于在所述第二时钟信号端提供的第二时钟信号和所述第二节点保持模块的输出信号的共同作用下，改变所述第二节点的电位；
    所述第一节点降噪模块的第一输入端与所述复位信号端连接，所述第一节点降噪模块的第二输入端与所述第二电压端连接，所述第一节点降噪模块的第三输入端与所述第二节点连接，所述第一节点降噪模块的输出端与所述第一节点连接，所述第一节点降噪模块用于在所述复位信号端提供的复位信号、所述第二电压端提供的所述无效电位信号和所述第二节点的电位的共同作用下，改变所述第一节点的电位；
    所述复位模块的第一输入端与所述复位信号端连接，所述复位模块的第二输入端与所述第二节点连接，所述复位模块的第三输入端与所述第二电压 端连接，所述复位模块的输出端与所述输出信号端连接，所述复位模块用于在所述复位信号端提供的所述复位信号、所述第二节点的电位和所述第二电压端提供的所述无效电位信号的共同作用下，对所述输出信号端的电位进行复位；
    其中，所述第一时钟信号和所述第二时钟信号互为反相信号。
  9. 根据权利要求8所述的移位寄存器电路，其中，所述第一电压端与能够提供有效电位信号的电源电压信号端相连。
  10. 根据权利要求8或9所述的移位寄存器电路，其中，所述充放电模块包括，
    第三薄膜晶体管，所述第三薄膜晶体管控制端与所述第一节点连接，第一端与所述第一时钟信号端连接，第二端与所述输出信号端连接；
    存储电容，所述存储电容的第一端与所述第一节点连接，第二端与所述输出信号端连接。
  11. 根据权利要求8至10任一所述的移位寄存器电路，其中，所述第二节点保持模块包括，
    第六薄膜晶体管，所述第六薄膜晶体管控制端与所述第一节点连接，第一端与所述第二电压端连接，第二端与所述第二节点连接；
    第八薄膜晶体管，所述第八薄膜晶体管控制端与所述第一节点连接，第一端与所述第二电压端连接，第二端与所述第二节点电平改变模块连接。
  12. 根据权利要求8至11任一所述的移位寄存器电路，其中，所述第二节点电平改变模块包括，
    第九薄膜晶体管，所述第九薄膜晶体管控制端和第一端均与所述第二时钟信号端连接，第二端与第五薄膜晶体管的控制端连接；
    第五薄膜晶体管，所述第五薄膜晶体管控制端与所述第九薄膜晶体管的第二端连接，第一端与所述第二电压端连接，第二端与所述第一节点连接。
  13. 根据权利要求8至12任一所述的移位寄存器电路，其中，所述第一节点降噪模块包括，
    第二薄膜晶体管，所述第二薄膜晶体管控制端与所述复位信号端连接，第一端与所述第二电压端连接，第二端与所述第一节点连接；
    第十薄膜晶体管，所述第十薄膜晶体管控制端与所述第二节点连接，第 一端与所述第二电压端连接，第二端与所述第一节点连接。
  14. 根据权利要求8至13任一所述的移位寄存器电路，其中，所述复位模块包括，
    第四薄膜晶体管，所述第四薄膜晶体管控制端与所述复位信号端连接，第一端与所述第二电压端连接，第二端与所述输出信号端连接；
    第七薄膜晶体管，所述第七薄膜晶体管控制端与所述第二节点连接，第一端与所述第二电压端连接，第二端与所述输出信号端连接。
  15. 根据权利要求2所述的移位寄存器电路，其中，所述输入薄膜晶体管为P型薄膜晶体管或N型薄膜晶体管。
  16. 根据权利要求1至15任一所述的移位寄存器电路，其中，所述输入信号端和所述第一电压端为同一端。
  17. 根据权利要求8所述的移位寄存器电路，其中，所述第一电压端与所述第一时钟信号端相连。
  18. 根据权利要求8所述的移位寄存器电路，其中，所述第一电压端与所述第二时钟信号端相连。
  19. 一种栅极驱动电路，包括多个级联的移位寄存器电路，所述移位寄存器电路为如权利要求1～16任一项所述的移位寄存器电路。
  20. 一种栅极驱动电路，包括多个级联的移位寄存器电路，所述多个级联的移位寄存器电路中两个相邻移位寄存器电路之一为如权利要求17所述的移位寄存器电路，以及所述多个级联的移位寄存器电路中所述两个相邻移位寄存器电路中的另一个为如权利要求18所述的移位寄存器电路。
  21. 一种阵列基板，包括如权利要求19-20任一所述的栅极驱动电路。
  22. 一种显示装置，包括如权利要求21所述的阵列基板。
  23. 一种驱动如权利要求8-14任一所述的移位寄存器电路的方法，包括：
    向所述输入信号端输入具有有效电位的信号，向所述第一时钟信号端输入具有无效电位的信号，以使得所述控制模块向所述分压节点输出来自所述第一电压端的有效电位信号，并使得所述输入模块在所述控制模块的控制下将所述分压节点的信号输出至所述第一节点，以对所述充放电模块进行充电；
    向所述第一时钟信号端输入具有有效电位的信号，向所述输入信号端输入具有无效电位的信号，以对所述充放电模块进行充电，并使得所述充放电 模块在所述第一节点的控制下向所述输出信号端输出来自所述第一时钟信号端的、处于有效电位的信号；以及
    向所述复位信号端和所述第二时钟信号端输入具有有效电位的信号，使得所述第二节点电平改变模块将所述第二节点的电位改变为有效电位，并使得所述复位模块在处于有效电位的所述第二节点和处于有效电位的所述复位信号端的控制下向所述输出信号端输出来自所述第二电压端的无效电位信号。
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