WO2013108733A1 - ヘテロ接合型電界効果トランジスタ用のエピタキシャルウエハ - Google Patents

ヘテロ接合型電界効果トランジスタ用のエピタキシャルウエハ Download PDF

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WO2013108733A1
WO2013108733A1 PCT/JP2013/050519 JP2013050519W WO2013108733A1 WO 2013108733 A1 WO2013108733 A1 WO 2013108733A1 JP 2013050519 W JP2013050519 W JP 2013050519W WO 2013108733 A1 WO2013108733 A1 WO 2013108733A1
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superlattice
layer
buffer layer
layer structure
epitaxial wafer
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French (fr)
Japanese (ja)
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暢行 布袋田
信明 寺口
大輔 本田
伸之 伊藤
雅和 松林
治彦 松笠
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Sharp Corp
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Priority to CN201380005634.XA priority patent/CN104054166A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
    • H10D62/8162—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
    • H10D62/8162—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation
    • H10D62/8164—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation comprising only semiconductor materials 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

  • the present invention relates to an epitaxial wafer for producing a heterojunction field effect transistor including a plurality of nitride-based semiconductor layers capable of generating a two-dimensional electron gas (2DEG), and particularly to reduction of warpage and dislocation density in the wafer.
  • 2DEG two-dimensional electron gas
  • GaN substrates are expensive, and epitaxial crystal growth of those layers on sapphire substrates and Si substrates has been conventionally performed. ing.
  • AlxGa1-xN (0.5) is formed on a silicon substrate for the purpose of forming a nitride semiconductor layer having a smooth surface and containing no cracks on a substrate having greatly different lattice constants and thermal expansion coefficients.
  • ⁇ x ⁇ 1) first superlattice constituent layers and AlyGa1-yN (0.01 ⁇ y ⁇ 0.2) second superlattice constituent layers are alternately and repeatedly stacked to form an AlGaN superlattice buffer layer structure. It is described to form.
  • Patent Document 2 in order to suppress current leakage between electrodes through the buffer layer, an AlN buffer layer on a silicon substrate and a high Al composition ratio H—AlGaN superlayer alternately stacked thereon are formed.
  • a semiconductor device having a lattice structure layer and a superlattice buffer layer structure including an L-AlGaN superlattice structure layer having a low Al composition ratio is described.
  • a composition gradient buffer layer structure in which the Al composition ratio is continuously or stepwise decreased in the thickness direction is formed on an Si substrate or an intermediate layer formed on the Si substrate.
  • a superlattice buffer layer structure including AlGaN superlattice constituent layers with high Al composition ratios and AlGaN superlattice constituent layers with low Al composition ratios, which are alternately stacked, is formed, and a nitride layer serving as a channel layer is formed thereon. ing. It is stated that by using such a laminated structure, a semiconductor element having a nitride semiconductor layer with few cracks and pits and excellent crystallinity can be obtained.
  • the nitride-based semiconductor epitaxial wafer disclosed in Patent Documents 1 to 3 can be used as a wafer for a power device that is an electronic device.
  • semiconductors such as electrode formation, element isolation, surface protection film formation, and internal wiring formation are performed on the wafer through processes such as photolithography and etching. It is necessary to go through a processing process. Therefore, when the wafer is warped, the yield of the device is lowered, and when the warpage is severe, the wafer cannot be processed by the semiconductor manufacturing apparatus.
  • the present invention provides a warp in an epitaxial wafer for a heterojunction FET by adjusting the relationship between a graded compositionally graded buffer layer structure and a superlattice buffer layer structure thereon.
  • the purpose is to reduce the edge dislocation density.
  • an epitaxial wafer for a heterojunction field effect transistor includes an AlN underlayer sequentially laminated on a Si substrate, a graded compositionally graded buffer layer structure, a superlattice buffer layer structure, a GaN channel layer, and a nitridation layer
  • a step-gradient compositionally graded buffer layer structure including a plurality of AlGaN buffer layers stacked so that the Al composition ratio is sequentially reduced, and the uppermost AlGaN buffer layer is an AlxGa1- xN (0 ⁇ x), and within the superlattice buffer layer structure, either an AlyGa1-yN (y ⁇ 1) superlattice constituent layer or an AlzGa1-zN (0 ⁇ z ⁇ y) superlattice constituent layer
  • the superlattice constituent layers are alternately stacked several times from the beginning, and the AlxGa1-xN buffer layer and the AlzGa1-zN superlattice constituent layer are substantially the same Al. It has a composition ratio and sati
  • the lowermost superlattice constituent layer in the superlattice buffer layer structure preferably has an AlN composition.
  • the warpage of the nitride-based semiconductor epitaxial wafer can be greatly reduced, and the edge dislocation density can be reduced. It is also possible to obtain a nitride-based semiconductor epitaxial wafer with reduced resistance.
  • FIG. 6 is a schematic cross-sectional view showing a laminated structure of a nitride semiconductor epitaxial wafer according to Comparative Example 1.
  • FIG. 6 is a schematic cross-sectional view showing a laminated structure of a nitride semiconductor epitaxial wafer according to Comparative Example 2.
  • FIG. The amount of warpage ( ⁇ m) of the epitaxial wafer depending on the Al composition difference (%) of the superlattice constituent layer having a relatively small band gap in the superlattice buffer layer structure with respect to the uppermost layer in the stepwise compositionally graded buffer layer structure. It is a graph to show.
  • FIG. 1 is a schematic cross-sectional view showing a laminated structure of a heterojunction FET epitaxial wafer according to Example 1 of the present invention.
  • a Si substrate 1 having a diameter of 4 inches and a thickness of 625 ⁇ m was used.
  • the surface oxide film of the Si substrate 1 was removed with a hydrofluoric acid-based etchant, and then the substrate was set in an MOCVD (metal organic vapor deposition) apparatus.
  • MOCVD metal organic vapor deposition
  • the substrate was heated to 1100 ° C., and the surface of the substrate was cleaned in a hydrogen atmosphere with a chamber internal pressure of 13.3 kPa. Thereafter, nitriding of the Si substrate surface was performed by flowing ammonia NH3 (12.5 slm) while maintaining the substrate temperature and the pressure in the chamber.
  • TMG trimethylgallium
  • a 1 ⁇ m superlattice (SL) buffer layer structure 7 was formed.
  • Example 1 the single GaN channel layer 8 was deposited. However, in order to improve the withstand voltage of the formed FET, the thickness of 0.3 ⁇ m deposited under a relatively low reaction gas pressure is used. A channel layer having a two-layer structure including a GaN layer having a thickness of 0.7 ⁇ m and deposited under a relatively high reaction gas pressure with the GaN layer may be formed. In this case, when the reaction gas pressure is low, carbon contained in TMG is easily doped into the GaN channel layer, and conversely, when the reaction gas pressure is high, the GaN channel layer is not easily doped with carbon. The withstand voltage is improved.
  • An electron supply layer consisting of (20 nm thick) was deposited.
  • an extremely thin AlN characteristic improving layer (1 nm thickness) is added between the GaN channel layer 8 and the Al0.2Ga0.8N barrier layer 9 to increase the 2DEG concentration in the GaN channel layer.
  • an extremely thin AlN characteristic improving layer (1 nm thickness) is added between the GaN channel layer 8 and the Al0.2Ga0.8N barrier layer 9 to increase the 2DEG concentration in the GaN channel layer.
  • FIG. 2 is a schematic cross-sectional view showing a laminated structure of an epitaxial wafer for a heterojunction FET according to Comparative Example 1.
  • the substrate temperature is set to 1150 ° C., and an AlN superlattice constituting layer having a thickness of 10 nm and a GaN superlattice constituting layer having a thickness of 20 nm are laminated in 70 cycles. It was done.
  • Example 2 Thereafter, as in Example 1, an electron supply layer of GaN channel layer 8 (thickness: 1000 nm) and Al0.2Ga0.8N barrier layer 9 (thickness: 20 nm) was deposited.
  • FIG. 3 is a schematic cross-sectional view showing a laminated structure of an epitaxial wafer for a heterojunction FET according to Comparative Example 2.
  • the layers other than the layer included in the superlattice (SL) buffer layer structure 73 were deposited under the same conditions as in Example 1.
  • the substrate temperature was set to 1150 ° C., and an AlN superlattice constituent layer having a thickness of 10 nm and an Al0.2Ga0.8N superlattice constituent layer having a thickness of 20 nm were formed. 70 cycles were laminated.
  • Example 2 Thereafter, as in Example 1, an electron supply layer of GaN channel layer 8 (thickness: 1000 nm) and Al0.2Ga0.8N barrier layer 9 (thickness: 20 nm) was deposited.
  • Warpage and edge dislocation density were evaluated in the epitaxial wafers according to the examples and comparative examples as described above.
  • the warpage of a wafer having a diameter of 4 inches is measured by adding the amount of warpage of the central portion convex downward.
  • FWHM and edge dislocation density were related by observation by cathodoluminescence (CL).
  • the numerical value “9.0” in the equation (1) is a fitting parameter that relates FWHM and edge dislocation density based on CL observation, and 3.189 ⁇ is the bar gas vector of the edge dislocation in the GaN crystal. Length.
  • the composition of the uppermost layer in the stepwise composition gradient buffer layer structure is AlxGa1-xN (0 ⁇ x)
  • the composition of the superlattice constituent layer having a relatively large band gap in the superlattice buffer layer structure is AlyGa1-
  • yN (y ⁇ 1) and the composition of the superlattice constituent layer having a relatively small band gap is AlzGa1-zN (0 ⁇ z ⁇ y)
  • Example 1 the uppermost layer of 6 in the graded composition graded buffer layer structure for the small band gap Al0.1Ga0.9N superlattice constituent layer in the superlattice buffer layer structure 7.
  • the Al composition difference of the Al0.1Ga0.9N layer 5 was 0%.
  • the amount of warpage of the wafer was 2.0 ⁇ m.
  • the edge dislocation density in the wafer was 2.44 ⁇ 109 cm ⁇ 2.
  • Comparative Example 1 the Al composition difference of the uppermost Al0.1Ga0.9N layer 5 in the stepwise composition gradient buffer layer structure with respect to the GaN superlattice constituent layer with a small band gap in the superlattice buffer layer structure 71 was ⁇ 10%, and in this case, the amount of warpage of the wafer was 44.8 ⁇ m.
  • the edge dislocation density in the wafer was 6.15 ⁇ 10 9 cm ⁇ 2.
  • the uppermost Al0.1Ga0.9N layer 5 in the graded composition graded buffer layer structure for the small band gap Al0.2Ga0.8N superlattice constituent layer in the superlattice buffer layer structure 72 The Al composition difference was + 10%, and in this case, the amount of warpage of the wafer was 67.4 ⁇ m. Further, the edge dislocation density in the wafer was 3.45 ⁇ 109 cm ⁇ 2.
  • the warp of the epitaxial wafer is 20 ⁇ m or less
  • the wafer can be easily handled in the semiconductor manufacturing process, and for example, a GaN-based low on-resistance small power device can be easily manufactured. Therefore, if the composition ratio difference is ⁇ 0.05 ⁇ z ⁇ x ⁇ 0.05, it can be used as a practical epitaxial wafer.
  • the Al0.1Ga0.9N layer 5 was used as the uppermost layer in the composition gradient buffer layer structure 6, but the Al0.2Ga0.8N layer was used as the uppermost layer.
  • the same tendency as in FIG. 4 was confirmed.
  • the AlGaN layer has a lattice constant intermediate between those of the GaN layer and the AlN layer.
  • the Al composition of the superlattice constituent layer with the smaller band gap in the superlattice buffer layer structure substantially the same as the Al composition of the uppermost layer in the graded graded buffer layer, It is considered that the distortion between the inclined buffer layer structure and the warp generated in the wafer can be further minimized.
  • the superlattice buffer layer structure preferably includes an AlN superlattice constituting layer having as large a band gap as possible.
  • the warpage of the nitride-based semiconductor epitaxial wafer can be greatly reduced, and the edge dislocations can be reduced. It is possible to provide a nitride-based semiconductor epitaxial wafer having a reduced density.

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PCT/JP2013/050519 2012-01-16 2013-01-15 ヘテロ接合型電界効果トランジスタ用のエピタキシャルウエハ Ceased WO2013108733A1 (ja)

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GB2519338A (en) * 2013-10-17 2015-04-22 Nanogan Ltd Crack-free gallium nitride materials
WO2016166949A1 (ja) * 2015-04-16 2016-10-20 株式会社デンソー 半導体ウエハ及び半導体装置

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US10109736B2 (en) * 2015-02-12 2018-10-23 Taiwan Semiconductor Manufacturing Co., Ltd. Superlattice buffer structure for gallium nitride transistors
US20160359004A1 (en) * 2015-06-03 2016-12-08 Veeco Instruments, Inc. Stress control for heteroepitaxy
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