WO2012161451A9 - 반도체 박막 구조 및 그 형성 방법 - Google Patents
반도체 박막 구조 및 그 형성 방법 Download PDFInfo
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- WO2012161451A9 WO2012161451A9 PCT/KR2012/003782 KR2012003782W WO2012161451A9 WO 2012161451 A9 WO2012161451 A9 WO 2012161451A9 KR 2012003782 W KR2012003782 W KR 2012003782W WO 2012161451 A9 WO2012161451 A9 WO 2012161451A9
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- thin film
- substrate
- semiconductor thin
- sacrificial layer
- nitride semiconductor
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
Definitions
- the present invention relates to a semiconductor layer of gallium nitride (GaN) or a mixed nitride of gallium and another metal, and a method of forming the same.
- the invention also relates to an electronic or opto-electronic device comprising such a layer and a method of manufacturing the same.
- the technical field of the present invention can be broadly defined as a semiconductor thin film structure for forming a high quality nitride semiconductor thin film on a substrate and a method of forming the same.
- Nitride semiconductors of Group III-V elements on the periodic table already occupy an important position in the field of electronic and optoelectronic devices, which will become more important in the future.
- Applications of nitride semiconductors actually cover a wide range from laser diodes (LDs) to transistors that can operate at high frequencies and temperatures. And an ultraviolet photodetector, a surface acoustic wave device, and a light emitting diode (LED).
- LDs laser diodes
- LED light emitting diode
- gallium nitride is known as a material suitable for the application of blue LEDs or high temperature transistors, but has been widely studied for microelectronic devices, which is not limited thereto.
- gallium nitride may be widely used to include gallium nitride alloys such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN).
- nitride semiconductors such as gallium nitride
- the most frequently used substrates for the growth of nitride semiconductor thin films are "heterogeneous" substrates such as sapphire, silicon carbide (SiC) and silicon.
- SiC silicon carbide
- nitride semiconductor thin films grown on dissimilar substrates have many dislocations, resulting in crack generation and warpage. This is a problem.
- a major technique in the production of gallium nitride optical devices and microelectronic devices is the growth of gallium nitride thin films with low defect density.
- the "two-stage growth method" is mainly used to form a gallium nitride buffer layer at low temperature and to grow a gallium nitride epi layer at high temperature. have.
- the number of through dislocations caused by lattice constant mismatch by the low temperature buffer layer may be reduced to about 10 9 / cm 2 .
- the stress caused by the difference in thermal expansion coefficient between the gallium nitride epi layer and the sapphire substrate and the resulting substrate warpage are still a problem.
- gallium nitride has been actively researched for lighting white LEDs.
- the price of the white LED chip must decrease significantly, and a global scale-up competition has begun.
- the warpage of the substrate is caused by the difference in the coefficient of thermal expansion between the gallium nitride and the heterogeneous substrate, and the larger the thickness of the substrate, the smaller the warpage.
- 1-1.3 mm thickness is considered for 6-inch sapphire substrates.
- the sapphire substrate has a larger coefficient of thermal expansion than gallium nitride
- gallium nitride epitaxial layer is subjected to compressive stress.
- the silicon substrate has a smaller coefficient of thermal expansion than gallium nitride
- a tensile stress is applied to the gallium nitride epi layer. If the stress can be properly reduced, the warpage of the substrate is reduced. In other words, if there is a way to reduce the stress on the nitride thin film it can be reduced by using a substrate of the same size.
- a 500 ⁇ m thick substrate can be used for a 6 inch sapphire substrate.
- the substrate needs to be changed to leave 100 ⁇ m for chip separation after LED fabrication, it is possible to use a thin substrate to obtain a big gain in LED production.
- An object of the present invention is to provide a semiconductor thin film structure and a method of forming the nitride semiconductor thin film which can form a high quality nitride semiconductor thin film by reducing the stress and the dislocation of the nitride semiconductor thin film during growth of the nitride semiconductor thin film.
- a sacrificial layer is formed on the substrate and patterned in various ways.
- the present invention also proposes a method for forming a semiconductor thin film on which an inorganic thin film is formed thereon, and then selectively removing a sacrificial layer to form a cavity defined as a substrate and an inorganic thin film on a substrate, and a semiconductor thin film structure formed by such a method.
- an ELO effect can be obtained because the nitride semiconductor thin film is grown from the surface of the substrate exposed around the empty space by defining an empty space on the substrate. Therefore, a high quality nitride semiconductor thin film having a small defect density can be formed and the internal quantum efficiency can be increased by reducing the density of nitride semiconductor crystal defects.
- the empty space also has the effect of controlling the refractive index in the thin film structure.
- the empty space increases the difference in refractive index with the substrate, thereby allowing the generated photons to escape more efficiently.
- the light extraction effect due to light scattering increases. Accordingly, when the semiconductor thin film structure of the present invention is manufactured by a light emitting device such as an LED, the external quantum efficiency of the LED is increased.
- the thermal expansion coefficient of the substrate when the thermal expansion coefficient of the substrate is larger than that of the nitride semiconductor thin film, the total stress of the nitride semiconductor thin film is reduced as the void space in the nitride semiconductor thin film is compressed in the plane direction.
- the thermal expansion coefficient of the substrate when the thermal expansion coefficient of the substrate is smaller than that of the nitride semiconductor thin film, the total stress of the nitride semiconductor thin film is reduced as the void space in the nitride semiconductor thin film is stretched in the plane direction. Therefore, when a stress is generated in the nitride semiconductor thin film, the void space may be distorted, thereby causing local stress relaxation, thereby reducing substrate warpage. This makes it possible to use a relatively thin substrate even in a large area substrate.
- the empty space can be controlled by adjusting the shape, size, two-dimensional arrangement, etc. of the sacrificial layer pattern, it is possible to control the optical characteristics of the LED manufactured from such a thin film structure, such as an emission pattern.
- the formation of the sacrificial layer pattern is performed by a controlled method such as photolithography or nanoimprint, the empty space is not formed irregularly or randomly, but is formed by the controlled method.
- nitride semiconductor epitaxial layer having excellent physical properties can be grown, an optoelectronic device having high efficiency and high reliability can be realized.
- high-output LD and LED may be implemented according to an increase in light extraction efficiency.
- FIG. 1 is a view illustrating a semiconductor thin film structure and a method of forming the same according to a first embodiment of the present invention.
- FIGS. 2 to 4 are diagrams for describing various methods for forming a sacrificial layer pattern in the method of forming a semiconductor thin film structure according to the present invention.
- FIG. 5 is a view illustrating a semiconductor thin film structure and a method of forming the semiconductor thin film structure according to the second embodiment of the present invention.
- FIG. 6 is a view showing various two-dimensional arrangements of a sacrificial layer pattern in a semiconductor thin film structure and a method of forming the same according to the present invention.
- FIG. 7 is a diagram illustrating a semiconductor thin film structure and a method of forming the semiconductor thin film according to the third embodiment of the present invention.
- FIG. 8 is a diagram illustrating a semiconductor thin film structure and a method of forming the semiconductor thin film according to the fourth embodiment of the present invention.
- FIG. 9 is a view illustrating a semiconductor thin film structure and a method of forming the semiconductor thin film according to the fifth embodiment of the present invention.
- FIG. 10 is a view illustrating a semiconductor thin film structure and a method of forming the semiconductor thin film according to the sixth embodiment of the present invention.
- the semiconductor thin film structure according to the present invention includes a substrate; And an inorganic thin film formed on the substrate such that a plurality of empty spaces separated from each other with the substrate are defined to have a controlled shape, size, and two-dimensional arrangement.
- the semiconductor thin film structure may further include a nitride semiconductor thin film on the substrate.
- the nitride semiconductor thin film may be two or more layers, and such empty space may be defined between the two or more layers.
- the coefficient of thermal expansion of the substrate is larger than that of the nitride semiconductor thin film, the void space is compressed by the nitride semiconductor thin film.
- an inorganic thin film is formed on the sacrificial layer pattern.
- the sacrificial layer pattern is removed from the substrate on which the inorganic thin film is formed so that a plurality of empty spaces separated from each other, which are defined as the substrate and the inorganic thin film, are formed.
- the nitride semiconductor thin film may be further formed on the semiconductor thin film structure.
- the nitride semiconductor thin film is formed by using an epitaxial lateral overgrowth (ELO) method so that the nitride semiconductor thin film is formed using a seed having no empty space on the substrate as a seed.
- ELO epitaxial lateral overgrowth
- the inorganic thin film is a different material from the substrate, patterning the inorganic thin film so as to expose the free space on the substrate between forming the inorganic thin film and removing the sacrificial layer pattern;
- the sacrificial layer pattern may be further removed between the steps of forming the nitride semiconductor thin film.
- the sacrificial layer pattern may be formed by various methods. After coating the photoresist on the substrate may be formed by a photolithography method, or by applying a nanoimprint resin on the substrate may be formed by a nanoimprint method. Instead, it may be formed by pasting organic nanoparticles on the substrate.
- the forming of the inorganic thin film may be performed within a temperature limit at which the sacrificial layer pattern is not deformed.
- the inorganic thin film is silica (SiO 2 ), alumina (Al 2 O 3 ), titania (TiO 2 ), zirconia (ZrO 2 ), yttria (Y 2 O 3 ) -zirconia, copper oxide (CuO, Cu 2 O) And tantalum oxide (Ta 2 O 5 ).
- the empty space is a position where the sacrificial layer pattern is removed. Therefore, the empty space follows the shape and size of the sacrificial layer pattern and the two-dimensional arrangement. Therefore, the shape and size of the sacrificial layer pattern and the two-dimensional arrangement must be determined in order for the empty space to have a controlled shape and size and two-dimensional arrangement.
- the sacrificial layer pattern may be formed and then the shape may be adjusted. For example, a reflow step for modifying the shape of the sacrificial layer pattern is performed.
- the reflow step may change the shape of the sacrificial layer pattern.
- the semiconductor thin film structure according to the present invention it is possible to manufacture ultraviolet photodetectors, surface acoustic wave devices, LEDs, LDs, microelectronic devices, and the like, and to extend them to modules and systems using the devices. Specific details of other embodiments are included in the detailed description and drawings.
- FIG. 1 is a view illustrating a semiconductor thin film structure and a method of forming the same according to a first embodiment of the present invention.
- a sacrificial layer pattern 20 is formed on a substrate 10.
- the thickness d of the sacrificial layer pattern 20 may be 0.01-10 ⁇ m, and the width w of the sacrificial layer pattern 20 may be 0.01-10 ⁇ m.
- the thickness d and the width w of the sacrificial layer pattern 20 may be determined in consideration of the empty space to be finally formed.
- the sacrificial layer pattern 20 is uniformly formed on the entire substrate 10 in the same pattern. However, as will be described later with reference to FIG. 6, the sacrificial layer pattern 20 may be formed in another pattern locally on the substrate 10.
- the sacrificial layer pattern 20 may be formed according to various methods. First, the sacrificial layer pattern 20 may be formed by photo lithography.
- the photoresist film PR is coated on the substrate 10 as shown in FIG.
- the photoresist film PR may be applied to the substrate 10 by selecting among spin coating, dip coating, spray coating, solution dropping, and dispensing. For uniformity of coating, spin coating is recommended.
- the photoresist film PR is exposed using the photomask 12 having the appropriate light shielding pattern 11. Light transmitted through a region other than the light shielding pattern 11 exposes a part of the photosensitive film PR, and an exposed portion EA is formed. Thereafter, when the exposed portion EA is developed and removed, the photoresist pattern PR ′ may be left as shown in FIG. 2C.
- the shape, size, and two-dimensional arrangement of the photoresist pattern PR ′ that can be formed therefrom can be formed.
- the photoresist pattern PR ′ may be used as the sacrificial layer pattern 20. If necessary, an additional reflow step as shown in FIG. 2 (d) may be further performed to form a photoresist pattern PR ′′ in which the angular portion of the photoresist pattern PR ′ is rounded to form a sacrificial layer pattern 20. Can also be used as.
- the sacrificial layer pattern 20 may be formed by a nano-imprint method.
- a nanoimprint resin R is coated on the substrate 10.
- the nanoimprint resin R may also be applied to the substrate 10 by selecting from spin coating, dip coating, spray coating, solution dropping, and dispensing.
- the nanoimprint stamp 14 may be a master mold made of silicon or quartz manufactured by a conventional manufacturing method, or may be an organic mold replicating the master mold.
- the nanoimprint stamp 14 is pressed onto the resin for nanoimprint R as shown in FIG.
- the nanoimprint resin R is filled between the patterns 13 of the nanoimprint stamp 14.
- the nanoimprint resin (R) is cured by heating at the same time as pressurization or by irradiating ultraviolet rays or by irradiating ultraviolet rays at the same time.
- the cured nanoimprint resin R ′ remains on the substrate 10, as shown in FIG. 3C, and may be used as the sacrificial layer pattern 20. Will be.
- the shape and size of the cured nanoimprint resin (R ′) that can be formed therefrom The two-dimensional array can also be adjusted. If necessary, the shape of the cured nanoimprint resin (R ′) may be modified by additional heating or ultraviolet irradiation.
- the sacrificial layer pattern 20 may be formed from organic nanoparticles.
- organic nanoparticles B such as polystyrene or polyimide may be attached onto the substrate 10 and used as the sacrificial layer pattern 20.
- the shape and size of the organic nanoparticles (B) is uniform, and the pre-treatment for the portion to which the organic nanoparticles (B) will be attached to have a regular two-dimensional arrangement on the substrate (10). desirable.
- the substrate 10 is hydrophobic (or has a hydrophobic coating) only a portion to which the organic nanoparticles B are attached is formed to form a hydrophilic film.
- hydrophilic material it is also possible to apply a hydrophilic material to a stamp having a two-dimensional array pattern prepared in advance and to stamp it onto the substrate 10. Then, using the hydrophilic organic nanoparticles (B) or by applying a hydrophilic coating on the surface of the organic nanoparticles (B), or by mixing the organic nanoparticles (B) in a hydrophilic solvent applied to the substrate (10). Then, the organic nanoparticles B are attached only to the hydrophilic portion on the substrate 10.
- the method of attaching the organic nanoparticles B to have a regular two-dimensional arrangement on the substrate 10 may be variously modified, such as using electrostatic attraction.
- the contact area with the substrate 10 is further enlarged while the shape of the organic nanoparticles B 'is modified through additional heat treatment, and the organic nanoparticles B' are dropped. It may further perform the step of preventing.
- the substrate 10 in which the various sacrificial layer patterns 20 are formed may be any heterologous substrate used for growing hetero epitaxial thin films of semiconductor materials such as sapphire, silicon, SiC, and GaAs substrates. In the case of silicon, AlN buffer is grown on it and then used.
- the inorganic thin film 30 is formed on the sacrificial layer pattern 20 with reference to FIG. 1B. The inorganic thin film 30 subsequently defines an empty space with the substrate 10.
- the inorganic thin film 30 is preferably performed within a temperature limit at which the sacrificial layer pattern 20 is not deformed. .
- Processes for forming the inorganic thin film 30 may be various methods such as atomic layer deposition (ALD), wet synthesis, metal deposition and oxidation (metal deposition and oxidation).
- ALD atomic layer deposition
- metal deposition and oxidation metal deposition and oxidation
- a part of the inorganic thin film 30 is in direct contact with the substrate 10 when the inorganic thin film 30 is formed.
- the inorganic thin film 30 includes silica (SiO 2 ), alumina (Al 2 O 3 ), titania (TiO 2 ), zirconia (ZrO 2 ), yttria (Y 2 O 3 ) -zirconia, copper oxide (CuO, Cu 2 0) and tantalum oxide (Ta 2 O 5 ).
- the stress applied to the nitride semiconductor thin film formed on the semiconductor thin film structure using the same may be subsequently adjusted.
- the inorganic thin film 30 may be formed on the entire surface of the substrate 10 while covering the sacrificial layer pattern 20 as illustrated, but may be formed to cover only the sacrificial layer pattern 20 depending on the formation method. This will be described in detail in the following fourth and fifth embodiments.
- the sacrificial layer pattern 20 is selectively removed from the substrate 10 as shown in FIG. Since the sacrificial layer pattern 20 is a polymer such as a photosensitive film, a resin for nanoimprint, or an organic nanoparticle, as described with reference to FIGS. 2 to 4, a method of easily removing the sacrificial layer pattern 20 is heating. And in order to burn more easily by the oxidation method, a chemical reaction with a gas containing oxygen may be added. In some cases, a chemical reaction with a specific solvent may be used. After the sacrificial layer pattern 20 is removed, as shown in FIG. 1C, a semiconductor thin film structure in which a plurality of empty spaces C, which are defined as the substrate 10 and the inorganic thin film 30, are separated from each other is formed. 100 can be obtained.
- the inorganic thin film 30 usually has polycrystals of amorphous or very small particles.
- the sacrificial layer pattern 20 is heat-treated in an oxidizing atmosphere at a temperature T 1 decomposed to remove the sacrificial layer pattern 20, and then heated to a high temperature T 2 to densify the amorphous inorganic thin film 30. You may proceed in two steps.
- the semiconductor thin film structure 100 according to the present invention formed as described above includes the substrate 10 and the inorganic thin film 30 as shown in FIG. Between the substrate 10 and the inorganic thin film 30, a plurality of empty spaces C separated from each other are defined to have a controlled shape and size and a two-dimensional arrangement.
- the empty space C is a position where the sacrificial layer pattern 20 is removed during the formation method. Therefore, the empty space C follows the shape and size of the sacrificial layer pattern 20 and the two-dimensional arrangement. Therefore, in order for the empty space C to have a controlled shape and size and two-dimensional arrangement, the shape and size and two-dimensional arrangement of the sacrificial layer pattern 20 must be determined.
- the empty space C is uniformly defined in the same pattern on the entire substrate 10 according to the design of the sacrificial layer pattern 20.
- the empty space may be defined in a different pattern locally on the substrate, depending on the design of the sacrificial layer pattern.
- Such a semiconductor thin film structure 100 may be used to form a nitride semiconductor thin film thereon in various ways depending on the desired device design.
- the nitride semiconductor thin film includes all nitride semiconductor materials such as GaN, InN, AlN, or a combination thereof, Ga x Al y In z N (0 ⁇ x, y, z ⁇ 1). Since the void space C exists, if there is a difference in thermal expansion coefficient between the substrate 10 and the nitride semiconductor thin film (not shown) formed thereon, the void space C is stretched or compressed, causing local deformation to cause stress energy. Can be consumed. As a result, the thermal stress applied to the nitride semiconductor thin film can be reduced, thereby reducing the substrate warpage phenomenon. This will be described in detail with reference to the following examples.
- FIG. 5 is a view illustrating a semiconductor thin film structure and a method of forming the semiconductor thin film structure according to the second embodiment of the present invention.
- the inorganic thin film 30 is of the same composition as the substrate 10 (eg, the substrate is sapphire, the inorganic thin film is Al 2 O 3 ) during the high temperature (T 2 ) heat treatment. Direct contact with the substrate 10 and the portion of the inorganic thin film 30 will result in solid phase epitaxy and crystallization along the crystal direction of the substrate 10. This part will act as a seed part when the nitride semiconductor epitaxial layer is grown later.
- a sacrificial layer pattern 20a is formed on a substrate 10a and an inorganic thin film 30a is formed thereon.
- the substrate 10a is a sapphire substrate
- the sacrificial layer pattern 20a is formed by a photolithography method using a photosensitive film
- the inorganic thin film 30a is made of alumina.
- Alumina may be formed to have a uniform thickness along the shapes of the substrate 10a and the sacrificial layer pattern 20a by a deposition method such as ALD.
- a wet synthesis method using a wet solution is also possible.
- the wet solution may be uniformly coated along the shapes of the substrate 10a and the sacrificial layer pattern 20a, and then alumina may be synthesized by heating, drying, or chemical reaction.
- an aluminum precursor powder such as aluminum chloride (AlCl 3 ) is mixed with a solvent such as tetrachloroethylene (C 2 Cl 4 ), and then applied to the substrate 10 having the sacrificial layer pattern 20a formed thereon to coat and oxygen atmosphere.
- alumina thin film When heated and reacted at, the alumina thin film can be coated.
- alumina may be formed by depositing a metal Al thin film by sputtering or the like and then performing an oxidation process. Such alumina is formed in a state consisting of polycrystals of amorphous or fine particles.
- the sacrificial layer pattern 20a is removed to form the empty space C.
- the sacrificial layer pattern 20a since the sacrificial layer pattern 20a is formed of a photosensitive film, the sacrificial layer pattern 20a may be removed by a pyrolysis process commonly referred to as ashing when heated to a high temperature in an oxygen atmosphere. For example, it is removed by heating to a temperature of T 1 .
- T 2 It is heated to a higher temperature T 2 in the following.
- T 2 a higher temperature
- the solid phase epitaxy along the crystal direction of the substrate 10a starts at the interface between the substrate 10a and the inorganic thin film 30a of alumina, and the amorphous alumina becomes polycrystalline.
- the fine polycrystal becomes larger in size or, in the most preferred case, is converted into a single crystal such as the substrate 10a.
- a nitride semiconductor thin film 50 is further formed on the semiconductor thin film structure.
- a low temperature buffer 41 such as aluminum gallium nitride (Al x Ga 1-x N) is formed. Although the low temperature buffer 41 is shown to be grown on the substrate 10a between the empty spaces C, the low temperature buffer 41 may be grown on the inorganic thin film 30b above the empty spaces C.
- a nitride semiconductor epitaxial layer 46 including an undoped epitaxial layer 42 such as undoped gallium nitride (GaN) or undoped aluminum gallium nitride (Al x Ga 1-x N) is formed.
- the nitride semiconductor epitaxial layer 46 includes an n-type nitride semiconductor thin film 43, an active layer 44 that may have a structure such as MQW, and a p-type nitride semiconductor thin film 45. To form.
- the nitride semiconductor thin film 50 is grown by the ELO method using a seed having no empty space C on the substrate 10 as a seed, and is grown from above the substrate 10 around the empty space C to form an empty space C. It is formed in a high quality because it is coalesced from the top to form a film.
- the nitride semiconductor device may be manufactured using the structure, and the band gap may be adjusted according to the material of the nitride semiconductor thin film 50 to emit light in the ultraviolet, visible and infrared regions.
- a sufficient thickness at which lattice relaxation can occur perfectly that is, a wide range of 10 nm to 100 nm can be determined.
- CVD chemical vapor deposition
- the temperature range of the surface reaction controlled section may be used to form the low temperature buffer 41. If the GaN layer is grown on the sapphire substrate, the temperature may be 400 ° C to 700 ° C. A range may be used, and the low temperature buffer 41 made of AlN may be formed at a higher temperature range.
- evaporation methods e-beam evaporators, sublimation sources, Knudsen cells
- ion beam deposition methods ion beam deposition methods
- vapor phase epitaxy methods ALE, CVD, APCVD, PECVD, RTCVD, UHVCVD, LPCVD, MOCVD, GSMBE, etc.
- the substrate 10a is first loaded into the reactor.
- the pressure, temperature, and Group 5 precursor: Group 3 precursor ratio of the reactor are then made constant.
- the reactor pressure is 10 to 1000 torr
- the temperature is 300 to 1200 ° C
- the Group 5 precursor: Group 3 precursor ratio can be in the range of 1 to 1000000.
- the Group 5 and Group 3 precursors are injected at a constant rate to grow a layer of nitride on the substrate 10a to obtain the low temperature buffer 41. Injection of the Group 5 and Group 3 precursors is maintained until a low temperature buffer 41 of the desired thickness is obtained.
- the nitride semiconductor thin film 50 is grown on the low temperature buffer 41.
- the growth temperature of the nitride semiconductor thin film such as GaN high temperature epitaxial layer, can be used as the temperature range of the mass transfer controlled section.
- the temperature range of 700 °C to 1200 °C can be used. It is equal to the low temperature buffer 41 growth temperature or made high temperature.
- the formation of the preceding low temperature buffer 41 and the formation of the nitride semiconductor thin film 50 can proceed in one chamber or in two process chambers connected to the transfer chamber without breaking (or in situ) the vacuum. .
- the empty space C may be compressed in the plane direction during the cooling process after forming the nitride semiconductor thin film 50. Therefore, the compressive stress applied to the nitride semiconductor thin film 50 may be relaxed. Therefore, the warpage of the substrate 10a can be reduced.
- an electrode (not shown) is further configured in the structure as shown in FIG. 5D, a semiconductor device and a module or a system including the same may be manufactured.
- an n-type electrode is formed on a surface on which the n-type nitride semiconductor thin film 43 is exposed by mesa etching, and a p-type electrode is formed on the p-type nitride semiconductor thin film 45.
- the semiconductor device uses the semiconductor thin film structure according to the present invention, which may of course be accompanied by appropriate patterning.
- Various devices and modules and systems can be manufactured using the devices.
- the stress applied to the nitride semiconductor thin film 50, the light from the nitride semiconductor thin film 50 The amount of extraction can be adjusted.
- FIG. 6 is a plan view showing a two-dimensional arrangement of the sacrificial layer pattern 20a and shows a portion of a substrate constituting one chip.
- the sacrificial layer pattern 20a formed on the substrate 10a is a line and space type and extends in the y-axis direction or the x-axis direction.
- the LED formed therefrom can control light characteristics in either direction and thus, for example, adjust the polarization direction.
- 6 (c) and 6 (d) show that the sacrificial layer patterns 20a are concentric squares or concentric circles, respectively.
- the sacrificial layer pattern 20a enables to control the light output characteristics according to the emission angle in the LED formed therefrom.
- Examples of the sacrificial layer pattern 20a may be variously modified, and optical properties may be controlled according to various patterns.
- an island pattern such as, for example, FIG. 6E is also possible.
- a uniform pattern is possible with respect to the whole board
- FIG. 7 is a diagram illustrating a semiconductor thin film structure and a method of forming the semiconductor thin film according to the third embodiment of the present invention.
- the semiconductor thin film structure according to the present invention may include two or more nitride semiconductor thin films 50a and 50b over the substrate 10a, and an empty space C ′ is defined between the nitride semiconductor thin films 50a and 50b. You can do that.
- FIG. 8 is a diagram illustrating a semiconductor thin film structure and a method of forming the semiconductor thin film according to the fourth embodiment of the present invention.
- the substrate 10a and the inorganic thin film 30a are made of the same material as sapphire and alumina. If the inorganic thin film is a material different from the substrate (for example, the substrate is sapphire and the inorganic thin film is SiO 2 ), the densification is performed during the high temperature (T 2 ) heat treatment, but it does not act as a seed, so there is no empty space on the substrate. The step of patterning the inorganic thin film must be further performed so that it is exposed.
- a sacrificial layer pattern 20a is formed on a substrate 10a, and an inorganic thin film 30a ′ is formed thereon.
- the substrate 10a is a sapphire substrate
- the sacrificial layer pattern 20a is formed by a photolithography method using a photosensitive film
- the inorganic thin film 30a ' is made of a material different from sapphire, for example, silica.
- the sacrificial layer pattern 20a is removed in FIG. 8B to form the empty space C.
- the sacrificial layer pattern 20a may be removed by heating to a high temperature.
- the inorganic thin film 30a ' is patterned by patterning the inorganic thin film 30a' so that the portion without the empty space C on the substrate 10a is exposed using the photolithography method with reference to FIG. 8 (c).
- the upper surface of the substrate 10a can be exposed.
- the nitride semiconductor thin film 50 may be further formed on the semiconductor thin film structure. Since the nitride semiconductor thin film 50 is grown by the ELO method based on the part where the empty space C on the substrate 10a does not exist, that is, the portion where the upper surface of the substrate 10a is exposed, the nitride semiconductor thin film 50 is grown to a high quality thin film having few crystal defects. do.
- the inorganic thin film 30a ' is patterned after the empty space C is first formed, but the empty space C may be formed after the inorganic thin film 30a' is patterned.
- FIG. 9 is a view illustrating a semiconductor thin film structure and a method of forming the semiconductor thin film according to the fifth embodiment of the present invention.
- the sacrificial layer pattern 20a is formed on the substrate 10a, and the inorganic thin film 30a ′ is formed thereon.
- the substrate 10a is a sapphire substrate
- the sacrificial layer pattern 20a is formed by pasting organic nanoparticles such as polystyrene beads
- the inorganic thin film 30a ' is made of silica.
- the inorganic thin film 30a ′ may be formed to cover only the sacrificial layer pattern 20a. That is, the inorganic thin film 30a 'may be formed without covering the upper surface of the substrate 10a between the sacrificial layer patterns 20a.
- a substrate on which a sacrificial layer pattern 20a of organic nanoparticles such as polystyrene beads is formed after mixing an aluminum precursor powder such as aluminum chloride (AlCl 3 ) with a solvent such as tetrachloroethylene (C 2 Cl 4 ) ( This is because the aluminum precursor powder solution is applied to the sacrificial layer pattern 20a more preferentially than the substrate 10a when applied to 10).
- AlCl 3 aluminum chloride
- C 2 Cl 4 tetrachloroethylene
- the sacrificial layer pattern 20a is also removed from FIG. 9B to form the empty space C. For example, it is removed by heating to a temperature of T 1 .
- T 2 It is heated to a higher temperature T 2 in the following.
- T 2 a higher temperature
- the solid phase epitaxy along the crystal direction of the substrate 10a starts at the interface between the substrate 10a and the inorganic thin film 30a ', and the amorphous silica becomes polycrystalline or fine.
- the polycrystal becomes larger in size and becomes an inorganic thin film 30b '.
- the nitride semiconductor thin film 50 may be further formed on the semiconductor thin film structure. Since the nitride semiconductor thin film 50 is grown by the ELO method using the seed having no empty space C on the substrate 10a as a seed, the nitride semiconductor thin film 50 is grown to a high quality thin film having few crystal defects.
- FIG. 10 is a view illustrating a semiconductor thin film structure and a method of forming the semiconductor thin film according to the sixth embodiment of the present invention.
- a buffer layer 15 such as AlN is formed on the substrate 10b.
- the substrate 10b is a silicon substrate and is formed as a buffer layer 15 by, for example, sputtering AlN to a thickness of 100 GPa or less.
- the sacrificial layer pattern 20a is formed on the substrate 10b, and the inorganic thin film 30a is formed thereon.
- the inorganic thin film 30a is made of alumina or AlN.
- the sacrificial layer pattern 20a is removed to form the empty space C.
- the subsequent steps are the same as in the second embodiment. Since the sacrificial layer pattern 20a is made of a photosensitive film, the sacrificial layer pattern 20a can be removed by pyrolysis when heated to a high temperature. For example, it is removed by heating to a temperature of T 1 .
- T 2 It is heated to a higher temperature T 2 in the following.
- heating to around 1000 ° C. causes a solid phase epitaxy along the crystal direction of the substrate 10b to cause an interface between the inorganic thin film 30b, the buffer layer 15 and the substrate 10b (indicated by dotted lines in the figure).
- the substrate 10b between the empty spaces C may be seeded to grow an epitaxial lateral overgrowth (ELO) method high quality nitride semiconductor thin film.
- ELO epitaxial lateral overgrowth
- the thermal expansion coefficient of the silicon substrate 10b is larger than that of the nitride semiconductor thin film, the nitride semiconductor thin film is formed on the semiconductor thin film structure as shown in FIG.
- the empty space C may be tensioned, and thus the tensile stress applied to the nitride semiconductor thin film may be relaxed. Therefore, the warpage of the substrate 10b can be reduced.
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Abstract
Description
Claims (29)
- 기판; 및상기 기판과의 사이에 서로 분리된 복수개의 빈 공간(cavity)이 제어된 모양과 크기 및 2 차원적인 배열을 갖게 정의되도록 상기 기판 상에 형성된 무기물 박막을 포함하는 반도체 박막 구조.
- 제1항에 있어서, 상기 기판 위로 질화물 반도체 박막을 더 포함하는 것을 특징으로 하는 반도체 박막 구조.
- 제2항에 있어서, 상기 질화물 반도체 박막은 2층 이상의 막인 것을 특징으로 하는 반도체 박막 구조.
- 제3항에 있어서, 상기 2층 이상의 막 사이에 서로 분리된 복수개의 빈 공간이 규칙적으로 제어된 모양과 크기 및 2 차원적인 배열을 갖게 정의되도록 상기 2층 이상의 막 사이에 형성된 다른 무기물 박막을 더 포함하는 것을 특징으로 하는 반도체 박막 구조.
- 제2항에 있어서, 상기 기판의 열팽창계수가 상기 질화물 반도체 박막에 비하여 크고 상기 빈 공간이 상기 질화물 반도체 박막에 의해 면 방향으로 압축된 것을 특징으로 하는 반도체 박막 구조.
- 제2항에 있어서, 상기 기판의 열팽창계수가 상기 질화물 반도체 박막에 비하여 작고 상기 빈 공간이 상기 질화물 반도체 박막에 의해 면 방향으로 인장된 것을 특징으로 하는 반도체 박막 구조.
- 제1항 또는 제2항에 있어서, 상기 빈 공간은 상기 기판 전체에 같은 패턴으로 균일하게 정의되어 있는 것을 특징으로 하는 반도체 박막 구조.
- 제1항 또는 제2항에 있어서, 상기 빈 공간은 상기 기판에 국부적으로 다른 패턴으로 정의되어 있는 것을 특징으로 하는 반도체 박막 구조.
- 기판 상에 희생층 패턴을 형성하는 단계;상기 희생층 패턴 상에 무기물 박막을 형성하는 단계; 및상기 기판과 무기물 박막으로 정의되는 서로 분리된 복수개의 빈 공간(cavity)이 형성되도록, 상기 무기물 박막이 형성된 기판으로부터 상기 희생층 패턴을 제거하는 단계를 포함하는 박막 구조 형성 방법.
- 제9항에 있어서, 상기 기판 위로 질화물 반도체 박막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제10항에 있어서, 상기 질화물 반도체 박막을 형성하는 단계는 상기 기판 상의 상기 빈 공간이 없는 부분을 씨앗으로 삼아 상기 질화물 반도체 박막이 형성되도록 ELO(epitaxial lateral overgrowth) 방법으로 수행하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제11항에 있어서, 상기 무기물 박막은 상기 기판과 다른 물질이며 상기 기판 상의 상기 빈 공간이 없는 부분이 노출되도록 상기 무기물 박막을 패터닝하는 단계를 더 포함하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제10항에 있어서, 상기 기판의 열팽창계수가 상기 질화물 반도체 박막에 비하여 크게 선택하고, 상기 질화물 반도체 박막을 형성하는 단계 이후 냉각시키는 과정에서 상기 질화물 반도체 박막에 의해 상기 빈 공간을 면 방향으로 압축시켜 상기 기판의 휘어짐을 감소하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제10항에 있어서, 상기 기판의 열팽창계수가 상기 질화물 반도체 박막에 비하여 작게 선택하고, 상기 질화물 반도체 박막을 형성하는 단계 이후 냉각시키는 과정에서 상기 질화물 반도체 박막에 의해 상기 빈 공간을 면 방향으로 인장시켜 상기 기판의 휘어짐을 감소하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제10항에 있어서, 상기 질화물 반도체 박막에 걸리는 응력, 상기 질화물 반도체 박막으로부터의 광 추출량 및 방출 패턴 중 적어도 어느 하나를 조절하기 위하여 상기 빈 공간의 모양과 크기 및 2 차원적인 배열 중 적어도 어느 하나를 조절하는 것을 특징으로 하는 박막 구조 형성 방법.
- 제9항에 있어서, 상기 희생층 패턴을 형성하는 단계는 상기 기판 상에 감광막을 도포한 후 사진식각 방법으로 형성하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제9항에 있어서, 상기 희생층 패턴을 형성하는 단계는 상기 기판 상에 나노임프린트용 수지를 도포한 후 나노임프린트 방법으로 형성하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제9항에 있어서, 상기 희생층 패턴을 형성하는 단계는 상기 기판 상에 유기물 나노입자를 붙여서 형성하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제9항에 있어서, 상기 희생층 패턴의 두께는 0.01 ~ 10 ㎛이고 상기 희생층 패턴의 폭은 0.01 ~ 10 ㎛인 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제9항에 있어서, 상기 무기물 박막을 형성하는 단계는 상기 희생층 패턴이 변형되지 않는 온도 한도 내에서 수행하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제9항에 있어서, 상기 무기물 박막은 실리카(SiO2), 알루미나(Al2O3), 티타니아(TiO2), 지르코니아(ZrO2), 이트리아(Y2O3)-지르코니아, 산화구리(CuO, Cu2O) 및 산화탄탈륨(Ta2O5) 중 적어도 어느 하나인 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제10항에 있어서, 상기 질화물 반도체 박막에 걸리는 응력을 조절하기 위하여 상기 무기물 박막의 조성, 강도 및 두께 중 적어도 어느 하나를 조절하는 것을 특징으로 하는 박막 구조 형성 방법.
- 제9항에 있어서, 상기 빈 공간이 제어된 모양과 크기 및 2 차원적인 배열을 갖게 정의되도록 상기 희생층 패턴의 모양과 크기 및 2 차원적인 배열을 정하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제9항에 있어서, 상기 빈 공간의 모양을 조절하기 위하여 상기 희생층 패턴의 모양을 조절하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제9항에 있어서, 상기 희생층 패턴의 모양을 변형시키기 위한 리플로우(reflow) 단계를 더 포함하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제9항에 있어서, 상기 희생층 패턴은 상기 기판 전체에 같은 패턴으로 균일하게 형성하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제9항에 있어서, 상기 희생층 패턴은 상기 기판에 국부적으로 다른 패턴으로 형성하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 제9항에 있어서, 상기 희생층 패턴을 제거하는 단계는 가열, 산소를 포함하는 가스와의 화학 반응, 용매와의 화학 반응 중 적어도 어느 하나를 이용하는 것을 특징으로 하는 반도체 박막 구조 형성 방법.
- 기판;상기 기판과의 사이에 서로 분리된 복수개의 빈 공간(cavity)이 제어된 모양과 크기 및 2 차원적인 배열을 갖게 정의되도록 상기 기판 상에 형성된 무기물 박막; 및상기 기판 위로 형성된 질화물 반도체 박막을 포함하는 반도체 박막 구조를 포함하는 반도체 소자.
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